- 05 9月, 2023 1 次提交
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由 Zifei Zhang 提交于
Add some rolling db: * cpi rolling db * topdown rolling db * ipc-fuType rolling db Others: Add WITH_ROLLINGDB into Makefile, then: make emu WITH_ROLLINGDB=1 to enable rollingdb. Topdown rolling db will add many table into the database. This is something a little ugly. To sovle this: * run emu with --dump-select-db for wanted table, not --dump-db * TODO: enhance the RollingDB with more complicate YAXISPT that contains all the topdown signals
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- 04 9月, 2023 1 次提交
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由 Guokai Chen 提交于
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- 03 9月, 2023 2 次提交
- 02 9月, 2023 1 次提交
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由 Guokai Chen 提交于
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- 01 9月, 2023 2 次提交
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由 sfencevma 提交于
* fix l2l fwd * fix l2l fwd mask * fix s0_l2l_fwd_valid * fix l2l fwd mask and fuOpType logic * fix l2l fwd cancel logic * add fuOpType fast path * remove useless variable * fix s1_addr_misaligned * fix l2l_fwd_out.data
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由 happy-lx 提交于
accuracy: (s2_successfully_forward_channel_D + s2_successfully_forward_mshr + s3_fwd_frm_d_chan) / s2_forward_req
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- 30 8月, 2023 1 次提交
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由 wakafa 提交于
* bump huancun * bump coupledL2 * dcache: pass vaddr to coupledL2 through TL bus * prefetch: support sending pf src towards l2 * bump huancun * bump coupledL2 * bump utility
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- 29 8月, 2023 2 次提交
- 26 8月, 2023 1 次提交
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由 Kunlin You 提交于
Co-authored-by: Nklin <you_kunlin@163.com>
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- 23 8月, 2023 2 次提交
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由 Easton Man 提交于
* FTB: postpone read replacer access this helps with timing * FTB: add comments about replace logic
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由 ssszwic 提交于
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- 22 8月, 2023 2 次提交
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由 Guokai Chen 提交于
high fanout problems Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>
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由 sfencevma 提交于
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- 19 8月, 2023 2 次提交
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由 Xiaokun-Pei 提交于
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由 happy-lx 提交于
* mq: remove usage of raw_data * fix addr width * ci: check verilog of MissEntry * add an extra check to disable using of refill_data_raw in missentry * check it when generating XSTop.v
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- 18 8月, 2023 1 次提交
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由 Guokai Chen 提交于
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- 17 8月, 2023 3 次提交
- 16 8月, 2023 2 次提交
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由 Tang Haojin 提交于
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由 sfencevma 提交于
* fix tl d fwd at s2 * add val s0_remLoadHigherPriorityReplaySelMask * reorder nuke priority * set blocking true when enq * add tlb miss wakeup logic * remove blockByTlbMiss * fix missqueue enq cancel The error scenario is: there are two load instructions, and both wants to enter the missqueue, ldu0's load has highest priority, can enter the missqueue, but it is canceled, so for this cycle, there is no miss request served by missqueue, ldu1's load has the same physical address of ldu0's load, ldu1's load thinks it has also been served by missqueue, becacuse it saw ldu0's load has been served, but without taking cancel signal into consideration. * when considering cancel, use the cancel signal in missqueue instead of io.req.bits.cancel --------- Co-authored-by: Nlixin <1037997956@qq.com>
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- 15 8月, 2023 1 次提交
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由 Chen Xi 提交于
For better performance under L2 Evict@Refill feature
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- 13 8月, 2023 2 次提交
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由 Zifei Zhang 提交于
* bump difftest,utility: support --dump-select-db tableNameList * mk: when WITH_CHISELDB=1, set EnableChiselDB in DebugOptions to true
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由 Chen Xi 提交于
* bump CPL2: for A miss, choose way when refill, then release * bump utility: fix chiselDB * bump CPL2: fix C blocking condition assertion in Monitor of s1/s3 set blocking conflicts with C blocking logic update C blocking modifications in fix-timing * bump CPL2: fix occWays in ReqBuf * bump CPL2: fix multiple bugs * bump CPL2: fix Get/Hint does not read dir and replace at refill * bump CoupledL2: fix C&D firing logic for Get * bump CPL2: fix Get problem * bump CPL2: fix retry * tmp: try modify L3 probeack logic to avoid verilator bug * bump CPL2: fix assertion * Bump CPL2: probe toB should write probeAckData to DS * Bump Utility * Bump HuanCun: use param to fix probeack logic under verilator bug * scripts: add L2 MainPipe-DB parser.sh and helper.py * bump CPL2: update to master with Evict@Refill * bump CPL2: misc - fix connection * bump CPL2 to master * scripts: give l2DB parser scripts more decent filename * bump cpl2
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- 12 8月, 2023 1 次提交
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由 wakafa 提交于
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- 11 8月, 2023 1 次提交
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由 ssszwic 提交于
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- 10 8月, 2023 2 次提交
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由 happy-lx 提交于
* perf: add counter * dcache hit rate = s2_dcache_real_miss_first_issue / s2_in_fire_first_issue * fix: fix compile
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由 wakafa 提交于
* utils: support perf rolling data collection through chiseldb * perf: add ipc rollingperf * script: add rolling plot script * param: disable rollingdb by default * misc: fix typo
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- 09 8月, 2023 2 次提交
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由 YukunXue 提交于
Prefix the port signal name of memblock to indicate the direction and source.
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由 sfencevma 提交于
* fix probe_ttob_check_resp timing * move probe_ttb check to mainpipe s2, get resp in s3 * fix main_pipe_req timing * remove fastarbiter * fix prefetcher timing * remove select invalid way first * MemBlock: fix timing * add redirectCancelCount * correct canAccept * fix loadQueueReplay select timing * rename sleepIndex * rename selectIndexOH --------- Co-authored-by: Nlixin <1037997956@qq.com>
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- 08 8月, 2023 1 次提交
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由 Maxpicca 提交于
Co-authored-by: NYanqin Li <liyanqin@bosc.ac.cn>
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- 05 8月, 2023 1 次提交
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由 Haoyuan Feng 提交于
* PTW: Move PTW to MemBlock Move itlbrepeater to Frontend and MemBlock, dtlbrepeater to MemBlock, L2 TLB (PTW) and ptw_to_l2_buffer to Memblock for better partition. * MMU: Fix sfence delay to synchronize modules
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- 04 8月, 2023 1 次提交
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由 Haoyuan Feng 提交于
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- 03 8月, 2023 1 次提交
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由 sfencevma 提交于
* LQ: wakeup ld by cache miss used TL D channel refill signal * rename sourceId * add Grant ack for tl d channel wakeup * rename refill * tl d channel wakeup when enq
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- 01 8月, 2023 1 次提交
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由 Yinan Xu 提交于
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- 28 7月, 2023 1 次提交
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由 Maxpicca 提交于
Co-authored-by: NbugGenerator <1773908404@qq.com> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: NHaoyuan Feng <fenghaoyuan19@mails.ucas.ac.cn>
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- 25 7月, 2023 1 次提交
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由 happy-lx 提交于
when valid count reaches StoreBufferSize, do eviction * If the way selected by the replacement algorithm cannot be written into dcache, its result is not used * It should remove store stall we observed in lbm. * Add the dynamic prioritization mechanism between load stores. * Detects the number of valid entries in the storeQueue, and if it is larger than ForceWriteUpper, forces the sbuffer to be written down to Dcache until the number of valid entries in the storeQueue is lower than ForceWriteLower. --------- Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local> Co-authored-by: Nsfencevma <35756813+sfencevma@users.noreply.github.com>
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- 24 7月, 2023 1 次提交
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由 Haoyuan Feng 提交于
* Memblock: Add load/store 128 bits datapath --------- Co-authored-by: lulu0521 <majianlu_0521@163.com> * Memblock: fix bug of raw addr match * Memblock, LoadUnit: Fix Vector RAW paddr match --------- Co-authored-by: lulu0521 <majianlu_0521@163.com>
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