未验证 提交 f98e4de8 编写于 作者: L ljw 提交者: GitHub

Merge pull request #258 from RISCVERS/update-mill

build.sc: do not use source of chisel3 and firrtl
[submodule "chisel3"]
path = chisel3
url = https://github.com/ucb-bar/chisel3
[submodule "firrtl"]
path = firrtl
url = https://github.com/ucb-bar/firrtl
[submodule "treadle"]
path = treadle
url = https://github.com/ucb-bar/treadle
[submodule "hardfloat"]
path = hardfloat
url = https://github.com/ucb-bar/berkeley-hardfloat
[submodule "rocket-chip"] [submodule "rocket-chip"]
path = rocket-chip path = rocket-chip
url = https://github.com/chipsalliance/rocket-chip.git url = https://github.com/chipsalliance/rocket-chip.git
......
import os.Path
import mill._ import mill._
import mill.modules.Util import mill.modules.Util
import scalalib._
import $ivy.`com.lihaoyi::mill-contrib-buildinfo:$MILL_VERSION` import $ivy.`com.lihaoyi::mill-contrib-buildinfo:$MILL_VERSION`
import $ivy.`com.lihaoyi::mill-contrib-bsp:$MILL_VERSION` import $ivy.`com.lihaoyi::mill-contrib-bsp:$MILL_VERSION`
import mill.contrib.buildinfo.BuildInfo import mill.contrib.buildinfo.BuildInfo
import $file.chisel3.build import scalalib._
import $file.firrtl.build import coursier.maven.MavenRepository
import $file.treadle.build
import $file.chiseltest.build object CustomZincWorkerModule extends ZincWorkerModule {
import $file.`berkeley-hardfloat`.build def repositories() = super.repositories ++ Seq(
import $file.`rocket-chip`.common MavenRepository("https://maven.aliyun.com/repository/public"),
import $file.`api-config-chipsalliance`.`build-rules`.mill.build MavenRepository("https://maven.aliyun.com/repository/apache-snapshots")
)
val sv = "2.12.12"
object myfirrtl extends firrtl.build.firrtlCrossModule(sv) {
override def millSourcePath = os.pwd / "firrtl"
} }
object mychisel3 extends chisel3.build.chisel3CrossModule(sv) { trait CommonModule extends ScalaModule {
override def millSourcePath = os.pwd / "chisel3" override def scalaVersion = "2.12.10"
def firrtlModule: Option[PublishModule] = Some(myfirrtl) override def scalacOptions = Seq("-Xsource:2.11")
def treadleModule: Option[PublishModule] = Some(mytreadle) override def zincWorker = CustomZincWorkerModule
}
object mytreadle extends treadle.build.treadleCrossModule(sv) { private val macroParadise = ivy"org.scalamacros:::paradise:2.1.0"
override def millSourcePath = os.pwd / "treadle"
def firrtlModule: Option[PublishModule] = Some(myfirrtl) override def compileIvyDeps = Agg(macroParadise)
}
object mychiseltest extends chiseltest.build.chiseltestCrossModule(sv) { override def scalacPluginIvyDeps = Agg(macroParadise)
override def scalaVersion = sv
override def millSourcePath = os.pwd / "chiseltest"
def chisel3Module: Option[PublishModule] = Some(mychisel3)
def treadleModule: Option[PublishModule] = Some(mytreadle)
} }
object myhardfloat extends `berkeley-hardfloat`.build.hardfloat { val chisel = Agg(
override def scalaVersion = sv ivy"edu.berkeley.cs::chisel3:3.4.0"
)
def chisel3Module: Option[PublishModule] = Some(mychisel3) object `api-config-chipsalliance` extends CommonModule {
override def millSourcePath = super.millSourcePath / "design" / "craft"
} }
object myconfig extends `api-config-chipsalliance`.`build-rules`.mill.build.config with PublishModule { object hardfloat extends SbtModule with CommonModule {
override def scalaVersion = sv override def millSourcePath = os.pwd / "berkeley-hardfloat"
override def ivyDeps = super.ivyDeps() ++ chisel
override def millSourcePath = os.pwd / "api-config-chipsalliance" / "design" / "craft"
override def pomSettings = T {
myrocketchip.pomSettings()
}
override def publishVersion = T {
myrocketchip.publishVersion()
}
} }
object myrocketchip extends `rocket-chip`.common.CommonRocketChip { object `rocket-chip` extends SbtModule with CommonModule {
override def scalaVersion = sv
override def millSourcePath = os.pwd / "rocket-chip" override def ivyDeps = super.ivyDeps() ++ Agg(
ivy"${scalaOrganization()}:scala-reflect:${scalaVersion()}",
ivy"org.json4s::json4s-jackson:3.6.1"
) ++ chisel
def chisel3Module: Option[PublishModule] = Some(mychisel3) object macros extends SbtModule with CommonModule
def hardfloatModule: PublishModule = myhardfloat override def moduleDeps = super.moduleDeps ++ Seq(
`api-config-chipsalliance`, macros, hardfloat
)
def configModule: PublishModule = myconfig
} }
object `block-inclusivecache-sifive` extends CommonModule {
override def ivyDeps = super.ivyDeps() ++ chisel
trait CommonModule extends ScalaModule { override def millSourcePath = super.millSourcePath / 'design / 'craft / 'inclusivecache
override def scalaVersion = sv
override def scalacOptions = Seq("-Xsource:2.11")
override def moduleDeps: Seq[ScalaModule] = Seq(mychisel3)
private val macroParadise = ivy"org.scalamacros:::paradise:2.1.1" override def moduleDeps = super.moduleDeps ++ Seq(`rocket-chip`)
override def compileIvyDeps = Agg(macroParadise)
override def scalacPluginIvyDeps = Agg(macroParadise)
} }
object myinclusivecache extends CommonModule { object chiseltest extends CommonModule with SbtModule {
override def millSourcePath = os.pwd / "block-inclusivecache-sifive" / "design" / "craft" / "inclusivecache" override def ivyDeps = super.ivyDeps() ++ Agg(
ivy"edu.berkeley.cs::treadle:1.3.0",
override def moduleDeps = super.moduleDeps ++ Seq(myrocketchip) ivy"org.scalatest::scalatest:3.2.0",
ivy"com.lihaoyi::utest:0.7.4"
) ++ chisel
object test extends Tests {
def ivyDeps = Agg(ivy"org.scalacheck::scalacheck:1.14.3")
def testFrameworks = Seq("org.scalatest.tools.Framework")
}
} }
object myblocks extends CommonModule with SbtModule {
override def moduleDeps = super.moduleDeps ++ Seq(myrocketchip)
}
object XiangShan extends CommonModule with SbtModule { object XiangShan extends CommonModule with SbtModule {
override def millSourcePath = millOuterCtx.millSourcePath override def millSourcePath = millOuterCtx.millSourcePath
override def forkArgs = Seq("-Xmx10G") override def forkArgs = Seq("-Xmx10G")
override def ivyDeps = super.ivyDeps() ++ chisel
override def moduleDeps = super.moduleDeps ++ Seq( override def moduleDeps = super.moduleDeps ++ Seq(
myrocketchip, `rocket-chip`,
myinclusivecache, `block-inclusivecache-sifive`,
chiseltest
) )
object test extends Tests { object test extends Tests {
override def ivyDeps = Agg( override def ivyDeps = super.ivyDeps() ++ Agg(
ivy"org.scalatest::scalatest:3.2.0", ivy"org.scalatest::scalatest:3.2.0"
)
override def moduleDeps = super.moduleDeps ++ Seq(
mychiseltest
) )
def testFrameworks = Seq( def testFrameworks = Seq(
"org.scalatest.tools.Framework" "org.scalatest.tools.Framework"
) )
def testOnly(args: String*) = T.command { def testOnly(args: String*) = T.command {
super.runMain("org.scalatest.tools.Runner", args: _*) super.runMain("org.scalatest.tools.Runner", args: _*)
} }
} }
}
}
\ No newline at end of file
Subproject commit 87916d55490ff04691bc59454086c82ed09646b2
Subproject commit cd845bdbfea0c09e9edbf61e651ede5197d8a084
Subproject commit 0368d83ba472e8fb90057ace0389ff65d96b667a
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