Merge pull request #256 from RISCVERS/wrapCacheWithSRAMTemplate

Wrap cache with sram template

block-inclusivecache-sifive @ 3d6bdf10

-Subproject commit c5619b4cc11858377de2329d74adc2ec148b6367
+Subproject commit 3d6bdf10d7b740588130e3056c8fd29f4175cadb

src/main/scala/xiangshan/cache/L1plusCache.scala

@@ -2,7 +2,7 @@ package xiangshan.cache
 
 import chisel3._
 import chisel3.util._
-import utils.{Code, RandomReplacement, HasTLDump, XSDebug}
+import utils.{Code, RandomReplacement, HasTLDump, XSDebug, SRAMTemplate}
 import xiangshan.{HasXSLog}
 
 import chipsalliance.rocketchip.config.Parameters
@@ -105,24 +105,33 @@ class L1plusCacheDataArray extends L1plusCacheModule {
     val resp  = Output(Vec(nWays, Vec(blockRows, Bits(encRowBits.W))))
   })
 
+  val singlePort = true
+
   // write is always ready
   io.write.ready := true.B
   val waddr = (io.write.bits.addr >> blockOffBits).asUInt()
   val raddr = (io.read.bits.addr >> blockOffBits).asUInt()
-  // raddr === waddr is undefined behavior!
-  // block read in this case
-  io.read.ready := !io.write.valid || raddr =/= waddr
+
+  // for single port SRAM, do not allow read and write in the same cycle
+  // for dual port SRAM, raddr === waddr is undefined behavior
+  val rwhazard = if(singlePort) io.write.valid else io.write.valid && waddr === raddr
+  io.read.ready := !rwhazard
+
   for (w <- 0 until nWays) {
     for (r <- 0 until blockRows) {
-      val array = SyncReadMem(nSets, Bits(encRowBits.W))
+      val array = Module(new SRAMTemplate(Bits(encRowBits.W), set=nSets, way=1,
+        shouldReset=false, holdRead=false, singlePort=singlePort))
       // data write
-      when (io.write.bits.way_en(w) && io.write.bits.wmask(r).asBool && io.write.valid) {
-        val data = io.write.bits.data(r)
-        array.write(waddr, data)
-      }
+      array.io.w.req.valid := io.write.bits.way_en(w) && io.write.bits.wmask(r).asBool && io.write.valid
+      array.io.w.req.bits.apply(
+        setIdx=waddr,
+        data=io.write.bits.data(r),
+        waymask=1.U)
+
       // data read
-      io.resp(w)(r) := RegNext(array.read(raddr, io.read.bits.way_en(w)
-        && io.read.bits.rmask(r) && io.read.valid).asUInt)
+      array.io.r.req.valid := io.read.bits.way_en(w) && io.read.bits.rmask(r) && io.read.valid
+      array.io.r.req.bits.apply(setIdx=raddr)
+      io.resp(w)(r) := RegNext(array.io.r.resp.data(0))
     }
   }
 
@@ -176,7 +185,8 @@ class L1plusCacheMetadataArray extends L1plusCacheModule {
   val rmask = Mux((nWays == 1).B, (-1).asSInt, io.read.bits.way_en.asSInt).asBools
 
   def encTagBits = cacheParams.tagCode.width(tagBits)
-  val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(encTagBits.W)))
+  val tag_array = Module(new SRAMTemplate(UInt(encTagBits.W), set=nSets, way=nWays,
+    shouldReset=false, holdRead=false, singlePort=true))
   val valid_array = Reg(Vec(nSets, UInt(nWays.W)))
   when (reset.toBool || io.flush) {
     for (i <- 0 until nSets) {
@@ -185,24 +195,37 @@ class L1plusCacheMetadataArray extends L1plusCacheModule {
   }
   XSDebug("valid_array:%x   flush:%d\n",valid_array.asUInt,io.flush)
 
+  // tag write
   val wen = io.write.valid && !reset.toBool && !io.flush
+  tag_array.io.w.req.valid := wen
+  tag_array.io.w.req.bits.apply(
+    setIdx=waddr,
+    data=cacheParams.tagCode.encode(wtag),
+    waymask=VecInit(wmask).asUInt)
+
   when (wen) {
-    tag_array.write(waddr, VecInit(Array.fill(nWays)(cacheParams.tagCode.encode(wtag))), wmask)
     when (wvalid) {
       valid_array(waddr) := valid_array(waddr) | io.write.bits.way_en
     } .otherwise {
       valid_array(waddr) := valid_array(waddr) & ~io.write.bits.way_en
     }
   }
-  val rtags = tag_array.read(io.read.bits.idx, io.read.fire()).map(rdata =>
+
+  // tag read
+  tag_array.io.r.req.valid := io.read.fire()
+  tag_array.io.r.req.bits.apply(setIdx=io.read.bits.idx)
+  val rtags = tag_array.io.r.resp.data.map(rdata =>
       cacheParams.tagCode.decode(rdata).corrected)
+
   for (i <- 0 until nWays) {
     io.resp(i).valid := RegNext(valid_array(io.read.bits.idx)(i))
     io.resp(i).tag   := rtags(i)
   }
 
-  io.read.ready  := !io.write.valid && !reset.toBool && !io.flush
-  io.write.ready := !reset.toBool && !io.flush
+  // we use single port SRAM
+  // do not allow read and write in the same cycle
+  io.read.ready  := !io.write.valid && !reset.toBool && !io.flush && tag_array.io.r.req.ready
+  io.write.ready := !reset.toBool && !io.flush && tag_array.io.w.req.ready
 
   def dumpRead() = {
     when (io.read.fire()) {

src/main/scala/xiangshan/cache/dcache.scala

@@ -3,7 +3,7 @@ package xiangshan.cache
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink.{ClientMetadata, TLClientParameters, TLEdgeOut}
-import utils.{Code, RandomReplacement, XSDebug}
+import utils.{Code, RandomReplacement, XSDebug, SRAMTemplate}
 
 import scala.math.max
 
@@ -178,25 +178,40 @@ abstract class AbstractDataArray extends DCacheModule {
 
 class DuplicatedDataArray extends AbstractDataArray
 {
+  val singlePort = true
   // write is always ready
   io.write.ready := true.B
   val waddr = (io.write.bits.addr >> blockOffBits).asUInt()
   for (j <- 0 until LoadPipelineWidth) {
     val raddr = (io.read(j).bits.addr >> blockOffBits).asUInt()
-    // raddr === waddr is undefined behavior!
-    // block read in this case
-    io.read(j).ready := !io.write.valid || raddr =/= waddr
+
+    // for single port SRAM, do not allow read and write in the same cycle
+    // for dual port SRAM, raddr === waddr is undefined behavior
+    val rwhazard = if(singlePort) io.write.valid else io.write.valid && waddr === raddr
+    io.read(j).ready := !rwhazard
+
     for (w <- 0 until nWays) {
       for (r <- 0 until blockRows) {
-        val array = SyncReadMem(nSets, Vec(rowWords, Bits(encWordBits.W)))
-        // data write
-        when (io.write.bits.way_en(w) && io.write.valid) {
-          val data = VecInit((0 until rowWords) map (i => io.write.bits.data(r)(encWordBits*(i+1)-1,encWordBits*i)))
-          array.write(waddr, data, io.write.bits.wmask(r).asBools)
+        val resp = Seq.fill(rowWords)(Wire(Bits(encWordBits.W)))
+        io.resp(j)(w)(r) := Cat((0 until rowWords).reverse map (k => resp(k)))
+
+        for (k <- 0 until rowWords) {
+          val array = Module(new SRAMTemplate(Bits(encWordBits.W), set=nSets, way=1,
+            shouldReset=false, holdRead=false, singlePort=singlePort))
+          // data write
+          val wen = io.write.valid && io.write.bits.way_en(w) && io.write.bits.wmask(r)(k)
+          array.io.w.req.valid := wen
+          array.io.w.req.bits.apply(
+            setIdx=waddr,
+            data=io.write.bits.data(r)(encWordBits*(k+1)-1,encWordBits*k),
+            waymask=1.U)
+
+          // data read
+          val ren = io.read(j).valid && io.read(j).bits.way_en(w) && io.read(j).bits.rmask(r)
+          array.io.r.req.valid := ren
+          array.io.r.req.bits.apply(setIdx=raddr)
+          resp(k) := RegNext(array.io.r.resp.data(0))
         }
-        // data read
-        io.resp(j)(w)(r) := RegNext(array.read(raddr, io.read(j).bits.way_en(w)
-          && io.read(j).bits.rmask(r) && io.read(j).valid).asUInt)
       }
     }
     io.nacks(j) := false.B
@@ -221,12 +236,21 @@ class L1MetadataArray(onReset: () => L1Metadata) extends DCacheModule {
   val metaBits = rstVal.getWidth
   val encMetaBits = cacheParams.tagCode.width(metaBits)
 
-  val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(encMetaBits.W)))
+  val tag_array = Module(new SRAMTemplate(UInt(encMetaBits.W), set=nSets, way=nWays,
+    shouldReset=false, holdRead=false, singlePort=true))
+
+  // tag write
   val wen = rst || io.write.valid
-  when (wen) {
-    tag_array.write(waddr, VecInit(Array.fill(nWays)(cacheParams.tagCode.encode(wdata))), wmask)
-  }
-  io.resp := tag_array.read(io.read.bits.idx, io.read.fire()).map(rdata =>
+  tag_array.io.w.req.valid := wen
+  tag_array.io.w.req.bits.apply(
+    setIdx=waddr,
+    data=cacheParams.tagCode.encode(wdata),
+    waymask=VecInit(wmask).asUInt)
+
+  // tag read
+  tag_array.io.r.req.valid := io.read.fire()
+  tag_array.io.r.req.bits.apply(setIdx=io.read.bits.idx)
+  io.resp := tag_array.io.r.resp.data.map(rdata =>
       cacheParams.tagCode.decode(rdata).corrected.asTypeOf(rstVal))
 
   io.read.ready := !wen