FDivSqrt: fix killReg

6f687286 · Fa_wang · 49444b11 · 6f687286
隐藏空白更改
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src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala +1 -1

未找到文件。
--- a/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala
+++ b/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala
@@ -28,6 +28,7 @@ class FDivSqrt extends FPUSubModule {
      when(divSqrtRawValid){
        when(kill || killReg){
          state := s_idle
+          killReg := false.B
        }.otherwise({
          state := s_finish
        })
@@ -37,7 +38,6 @@ class FDivSqrt extends FPUSubModule {
    }
    is(s_finish){
      state := s_idle
-      killReg := false.B
    }
  }