From 6f6872869ebf048117378e085b9b60367ca16d5d Mon Sep 17 00:00:00 2001
From: Zhangfw <471348957@qq.com>
Date: Tue, 12 Jan 2021 14:25:31 +0800
Subject: [PATCH] FDivSqrt: fix killReg

---
 src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala b/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala
index 7aa56a605..c5774072d 100644
--- a/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala
+++ b/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala
@@ -28,6 +28,7 @@ class FDivSqrt extends FPUSubModule {
       when(divSqrtRawValid){
         when(kill || killReg){
           state := s_idle
+          killReg := false.B
         }.otherwise({
           state := s_finish
         })
@@ -37,7 +38,6 @@ class FDivSqrt extends FPUSubModule {
     }
     is(s_finish){
       state := s_idle
-      killReg := false.B
     }
   }
 
-- 
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