diff --git a/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala b/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala
index 7aa56a605d0488d85c6cea38c0330e920cb7c5c8..c5774072d555d2599044281474d587ce3187fa2d 100644
--- a/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala
+++ b/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala
@@ -28,6 +28,7 @@ class FDivSqrt extends FPUSubModule {
       when(divSqrtRawValid){
         when(kill || killReg){
           state := s_idle
+          killReg := false.B
         }.otherwise({
           state := s_finish
         })
@@ -37,7 +38,6 @@ class FDivSqrt extends FPUSubModule {
     }
     is(s_finish){
       state := s_idle
-      killReg := false.B
     }
   }