diff --git a/src/main/scala/noop/Cache.scala b/src/main/scala/noop/Cache.scala
index 492840e89dd84e7a1336e2aca253b5b6e7372a26..4a2c6172a581d51e623d4d82852093791b767634 100644
--- a/src/main/scala/noop/Cache.scala
+++ b/src/main/scala/noop/Cache.scala
@@ -387,20 +387,17 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
       io.out.bits.rdata := Mux(hit, dataRead, inRdataRegDemand)
       io.out.bits.cmd := req.cmd
     }
-
-    when (req.isBurst()) {
-      io.out.valid := io.in.valid && (Mux(req.isWrite() && (hit || !hit && state === s_wait_resp), true.B, (state === s_memReadResp && io.mem.resp.fire() && req.cmd === SimpleBusCmd.readBurst)) || (respToL1Fire && respToL1Last && state === s_release))
-    }.otherwise {
-      io.out.valid := io.in.valid && Mux(probe, false.B, Mux(hit, true.B, Mux(req.isWrite() || mmio, state === s_wait_resp, afterFirstRead && !alreadyOutFire)))
-    }
-
   } else {
     io.out.bits.rdata := Mux(hit, dataRead, inRdataRegDemand)
     io.out.bits.cmd := DontCare
-    io.out.valid := io.in.valid && Mux(probe, false.B, Mux(hit, true.B, Mux(req.isWrite() || mmio, state === s_wait_resp, afterFirstRead && !alreadyOutFire)))
   }
   io.out.bits.user.zip(req.user).map { case (o,i) => o := i }
 
+  io.out.valid := io.in.valid && Mux(req.isBurst() && (cacheLevel == 2).B,
+    Mux(req.isWrite() && (hit || !hit && state === s_wait_resp), true.B, (state === s_memReadResp && io.mem.resp.fire() && req.cmd === SimpleBusCmd.readBurst)) || (respToL1Fire && respToL1Last && state === s_release),
+    Mux(probe, false.B, Mux(hit, true.B, Mux(req.isWrite() || mmio, state === s_wait_resp, afterFirstRead && !alreadyOutFire)))
+  )
+
   // With critical-word first, the pipeline registers between
   // s2 and s3 can not be overwritten before a missing request
   // is totally handled. We use io.isFinish to indicate when the
diff --git a/src/main/scala/system/SoC.scala b/src/main/scala/system/SoC.scala
index 5bd16c226aad3b760ca4756bef1979efd4a4b350..9623ae1f3ceefe19220eaa4ef69648339219a9b9 100644
--- a/src/main/scala/system/SoC.scala
+++ b/src/main/scala/system/SoC.scala
@@ -43,7 +43,7 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
 
   if (HasL2cache) {
     val l2cacheOut = Wire(new SimpleBusC)
-    if (HasPrefetch) {
+    val l2cacheIn = if (HasPrefetch) {
       val prefetcher = Module(new Prefetcher)
       prefetcher.io.in <> noop.io.prefetchReq
       val l2cacheIn = Wire(new SimpleBusUC)
@@ -52,12 +52,10 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
       l2cacheInReqArb.io.in(1) <> prefetcher.io.out
       l2cacheIn.req <> l2cacheInReqArb.io.out
       xbar.io.out.resp <> l2cacheIn.resp
-      l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(
-        CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
-    } else {
-      l2cacheOut <> Cache(in = xbar.io.out, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(
-        CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
-    }
+      l2cacheIn
+    } else xbar.io.out
+    l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(
+      CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
     io.mem <> l2cacheOut.mem.toAXI4()
     l2cacheOut.coh.resp.ready := true.B
     l2cacheOut.coh.req.valid := false.B