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体验新版 GitCode,发现更多精彩内容 >>
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4a6ab1cd
编写于
2月 02, 2021
作者:
L
LinJiawei
浏览文件
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浏览文件
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差异文件
Merge remote-tracking branch 'origin/master' into opt-jump-unit
上级
31ea8750
b5fcc2d4
变更
7
隐藏空白更改
内联
并排
Showing
7 changed file
with
21 addition
and
17 deletion
+21
-17
.github/workflows/emu.yml
.github/workflows/emu.yml
+9
-5
src/main/scala/xiangshan/XSCore.scala
src/main/scala/xiangshan/XSCore.scala
+1
-1
src/main/scala/xiangshan/backend/fu/Alu.scala
src/main/scala/xiangshan/backend/fu/Alu.scala
+1
-1
src/main/scala/xiangshan/backend/issue/ReservationStation.scala
...in/scala/xiangshan/backend/issue/ReservationStation.scala
+2
-0
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
+2
-4
src/test/csrc/emu.cpp
src/test/csrc/emu.cpp
+3
-3
src/test/scala/top/XSSim.scala
src/test/scala/top/XSSim.scala
+3
-3
未找到文件。
.github/workflows/emu.yml
浏览文件 @
4a6ab1cd
...
@@ -39,7 +39,7 @@ jobs:
...
@@ -39,7 +39,7 @@ jobs:
echo "AM_HOME=/home/ci-runner/xsenv/nexus-am" >> $GITHUB_ENV
echo "AM_HOME=/home/ci-runner/xsenv/nexus-am" >> $GITHUB_ENV
-
name
:
Build EMU
-
name
:
Build EMU
run
:
run
:
make ./build/emu SIM_ARGS=--disable-log NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME B=0 E=0 -j220
make ./build/emu SIM_ARGS=--disable-log NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME B=0 E=0 -j220
EMU_TRACE=1 EMU_THREADS=8
-
name
:
Run cputest
-
name
:
Run cputest
run
:
|
run
:
|
CPU_TEST_DIR=$AM_HOME/tests/cputest
CPU_TEST_DIR=$AM_HOME/tests/cputest
...
@@ -49,7 +49,7 @@ jobs:
...
@@ -49,7 +49,7 @@ jobs:
do
do
t=${test%.c}
t=${test%.c}
echo $t
echo $t
make -C $CPU_TEST_DIR ALL=$t ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run B=0 E=0
| grep "HIT GOOD TRAP"
numactl -m 1 -C 64-71 make -C $CPU_TEST_DIR ALL=$t ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run
| grep "HIT GOOD TRAP"
if [[ $? != 0 ]];
if [[ $? != 0 ]];
then
then
echo $t fail
echo $t fail
...
@@ -59,10 +59,14 @@ jobs:
...
@@ -59,10 +59,14 @@ jobs:
exit $ret
exit $ret
-
name
:
Run riscv-tests
-
name
:
Run riscv-tests
run
:
|
run
:
|
make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua SUITES+=rv64uf SUITES+=rv64ud NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run B=0 E=0
numactl -m 1 -C 64-71 make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua SUITES+=rv64uf SUITES+=rv64ud NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run
-
name
:
Run microbench
-
name
:
Run microbench
run
:
|
run
:
|
make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run B=0 E=0
numactl -m 1 -C 64-71 make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run
-
name
:
Run coremark
-
name
:
Run coremark
run
:
|
run
:
|
make -C $AM_HOME/apps/coremark ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run B=0 E=0
numactl -m 1 -C 64-71 make -C $AM_HOME/apps/coremark ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run
-
name
:
Run Linux
run
:
|
numactl -m 1 -C 64-71 make emu IMAGE=/home/ci-runner/xsenv/workloads/linux-hello/bbl.bin
src/main/scala/xiangshan/XSCore.scala
浏览文件 @
4a6ab1cd
...
@@ -414,7 +414,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
...
@@ -414,7 +414,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
frontend
.
io
.
backend
<>
ctrlBlock
.
io
.
frontend
frontend
.
io
.
backend
<>
ctrlBlock
.
io
.
frontend
frontend
.
io
.
sfence
<>
integerBlock
.
io
.
fenceio
.
sfence
frontend
.
io
.
sfence
<>
integerBlock
.
io
.
fenceio
.
sfence
frontend
.
io
.
tlbCsr
:=
RegNext
(
integerBlock
.
io
.
csrio
.
tlb
)
frontend
.
io
.
tlbCsr
:=
integerBlock
.
io
.
csrio
.
tlb
frontend
.
io
.
icacheMemAcq
<>
l1pluscache
.
io
.
req
frontend
.
io
.
icacheMemAcq
<>
l1pluscache
.
io
.
req
l1pluscache
.
io
.
resp
<>
frontend
.
io
.
icacheMemGrant
l1pluscache
.
io
.
resp
<>
frontend
.
io
.
icacheMemGrant
...
...
src/main/scala/xiangshan/backend/fu/Alu.scala
浏览文件 @
4a6ab1cd
...
@@ -113,7 +113,7 @@ class Alu extends FunctionUnit with HasRedirectOut {
...
@@ -113,7 +113,7 @@ class Alu extends FunctionUnit with HasRedirectOut {
val
slt
=
xorRes
(
XLEN
-
1
)
^
sltu
val
slt
=
xorRes
(
XLEN
-
1
)
^
sltu
val
isW
=
ALUOpType
.
isWordOp
(
func
)
val
isW
=
ALUOpType
.
isWordOp
(
func
)
val
shamt
=
Cat
(
isW
&&
src2
(
5
),
src2
(
4
,
0
))
val
shamt
=
Cat
(
!
isW
&&
src2
(
5
),
src2
(
4
,
0
))
val
leftShiftModule
=
Module
(
new
LeftShiftModule
)
val
leftShiftModule
=
Module
(
new
LeftShiftModule
)
leftShiftModule
.
io
.
sllSrc
:=
src1
leftShiftModule
.
io
.
sllSrc
:=
src1
...
...
src/main/scala/xiangshan/backend/issue/ReservationStation.scala
浏览文件 @
4a6ab1cd
...
@@ -489,6 +489,7 @@ class ReservationStationCtrl
...
@@ -489,6 +489,7 @@ class ReservationStationCtrl
val
asynIdxUop
=
(
0
until
iqSize
).
map
(
i
=>
asynUop
(
io
.
indexVec
(
i
))
)
val
asynIdxUop
=
(
0
until
iqSize
).
map
(
i
=>
asynUop
(
io
.
indexVec
(
i
))
)
val
readyIdxVec
=
(
0
until
iqSize
).
map
(
i
=>
io
.
validVec
(
i
)
&&
Cat
(
srcQueue
(
io
.
indexVec
(
i
))).
andR
)
val
readyIdxVec
=
(
0
until
iqSize
).
map
(
i
=>
io
.
validVec
(
i
)
&&
Cat
(
srcQueue
(
io
.
indexVec
(
i
))).
andR
)
val
fastAsynUop
=
ParallelPriorityMux
(
readyIdxVec
zip
asynIdxUop
)
val
fastAsynUop
=
ParallelPriorityMux
(
readyIdxVec
zip
asynIdxUop
)
val
fastRoqIdx
=
ParallelPriorityMux
(
readyIdxVec
zip
roqIdx
)
val
fastSentUop
=
Wire
(
new
MicroOp
)
val
fastSentUop
=
Wire
(
new
MicroOp
)
fastSentUop
:=
DontCare
fastSentUop
:=
DontCare
fastSentUop
.
pdest
:=
fastAsynUop
.
pdest
fastSentUop
.
pdest
:=
fastAsynUop
.
pdest
...
@@ -502,6 +503,7 @@ class ReservationStationCtrl
...
@@ -502,6 +503,7 @@ class ReservationStationCtrl
val
bpQueue
=
Module
(
new
BypassQueue
(
fixedDelay
))
val
bpQueue
=
Module
(
new
BypassQueue
(
fixedDelay
))
bpQueue
.
io
.
in
.
valid
:=
selValid
bpQueue
.
io
.
in
.
valid
:=
selValid
bpQueue
.
io
.
in
.
bits
:=
fastSentUop
bpQueue
.
io
.
in
.
bits
:=
fastSentUop
bpQueue
.
io
.
in
.
bits
.
roqIdx
:=
fastRoqIdx
bpQueue
.
io
.
redirect
:=
io
.
redirect
bpQueue
.
io
.
redirect
:=
io
.
redirect
bpQueue
.
io
.
flush
:=
io
.
flush
bpQueue
.
io
.
flush
:=
io
.
flush
io
.
fastUopOut
.
valid
:=
bpQueue
.
io
.
out
.
valid
io
.
fastUopOut
.
valid
:=
bpQueue
.
io
.
out
.
valid
...
...
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
浏览文件 @
4a6ab1cd
...
@@ -468,8 +468,7 @@ class LoadQueue extends XSModule
...
@@ -468,8 +468,7 @@ class LoadQueue extends XSModule
val
rollbackGen
=
Wire
(
Valid
(
new
Redirect
))
val
rollbackGen
=
Wire
(
Valid
(
new
Redirect
))
val
rollbackReg
=
Reg
(
Valid
(
new
Redirect
))
val
rollbackReg
=
Reg
(
Valid
(
new
Redirect
))
rollbackGen
.
valid
:=
rollbackSelected
.
valid
&&
rollbackGen
.
valid
:=
rollbackSelected
.
valid
&&
(!
lastCycleRedirect
.
valid
||
!
isAfter
(
rollbackSelected
.
bits
.
roqIdx
,
lastCycleRedirect
.
bits
.
roqIdx
))
&&
!
rollbackSelected
.
bits
.
roqIdx
.
needFlush
(
lastCycleRedirect
,
lastCycleFlush
)
!
lastCycleFlush
rollbackGen
.
bits
.
roqIdx
:=
rollbackSelected
.
bits
.
roqIdx
rollbackGen
.
bits
.
roqIdx
:=
rollbackSelected
.
bits
.
roqIdx
rollbackGen
.
bits
.
ftqIdx
:=
rollbackSelected
.
bits
.
cf
.
ftqPtr
rollbackGen
.
bits
.
ftqIdx
:=
rollbackSelected
.
bits
.
cf
.
ftqPtr
...
@@ -484,8 +483,7 @@ class LoadQueue extends XSModule
...
@@ -484,8 +483,7 @@ class LoadQueue extends XSModule
// S3: fire rollback request
// S3: fire rollback request
io
.
rollback
:=
rollbackReg
io
.
rollback
:=
rollbackReg
io
.
rollback
.
valid
:=
rollbackReg
.
valid
&&
io
.
rollback
.
valid
:=
rollbackReg
.
valid
&&
(!
lastCycleRedirect
.
valid
||
!
isAfter
(
rollbackReg
.
bits
.
roqIdx
,
lastCycleRedirect
.
bits
.
roqIdx
))
&&
!
rollbackReg
.
bits
.
roqIdx
.
needFlush
(
lastCycleRedirect
,
lastCycleFlush
)
!
lastCycleFlush
when
(
io
.
rollback
.
valid
)
{
when
(
io
.
rollback
.
valid
)
{
// XSDebug("Mem rollback: pc %x roqidx %d\n", io.rollback.bits.cfi, io.rollback.bits.roqIdx.asUInt)
// XSDebug("Mem rollback: pc %x roqidx %d\n", io.rollback.bits.cfi, io.rollback.bits.roqIdx.asUInt)
...
...
src/test/csrc/emu.cpp
浏览文件 @
4a6ab1cd
...
@@ -572,7 +572,7 @@ void Emulator::snapshot_load(const char *filename) {
...
@@ -572,7 +572,7 @@ void Emulator::snapshot_load(const char *filename) {
uint64_t
ref_r
[
DIFFTEST_NR_REG
];
uint64_t
ref_r
[
DIFFTEST_NR_REG
];
stream
.
read
(
ref_r
,
sizeof
(
ref_r
));
stream
.
read
(
ref_r
,
sizeof
(
ref_r
));
ref_difftest_setregs
(
&
ref_r
);
ref_difftest_setregs
(
&
ref_r
,
0
);
uint64_t
nemu_this_pc
;
uint64_t
nemu_this_pc
;
stream
.
read
(
&
nemu_this_pc
,
sizeof
(
nemu_this_pc
));
stream
.
read
(
&
nemu_this_pc
,
sizeof
(
nemu_this_pc
));
...
@@ -585,11 +585,11 @@ void Emulator::snapshot_load(const char *filename) {
...
@@ -585,11 +585,11 @@ void Emulator::snapshot_load(const char *filename) {
struct
SyncState
sync_mastate
;
struct
SyncState
sync_mastate
;
stream
.
read
(
&
sync_mastate
,
sizeof
(
struct
SyncState
));
stream
.
read
(
&
sync_mastate
,
sizeof
(
struct
SyncState
));
ref_difftest_set_mastatus
(
&
sync_mastate
);
ref_difftest_set_mastatus
(
&
sync_mastate
,
0
);
uint64_t
csr_buf
[
4096
];
uint64_t
csr_buf
[
4096
];
stream
.
read
(
&
csr_buf
,
sizeof
(
csr_buf
));
stream
.
read
(
&
csr_buf
,
sizeof
(
csr_buf
));
ref_difftest_set_csr
(
csr_buf
);
ref_difftest_set_csr
(
csr_buf
,
0
);
long
sdcard_offset
=
0
;
long
sdcard_offset
=
0
;
stream
.
read
(
&
sdcard_offset
,
sizeof
(
sdcard_offset
));
stream
.
read
(
&
sdcard_offset
,
sizeof
(
sdcard_offset
));
...
...
src/test/scala/top/XSSim.scala
浏览文件 @
4a6ab1cd
...
@@ -6,9 +6,9 @@ import chisel3.util._
...
@@ -6,9 +6,9 @@ import chisel3.util._
import
chipsalliance.rocketchip.config
import
chipsalliance.rocketchip.config
import
chisel3.stage.ChiselGeneratorAnnotation
import
chisel3.stage.ChiselGeneratorAnnotation
import
device._
import
device._
import
freechips.rocketchip.amba.axi4.
{
AXI4
UserYanker
,
AXI4Xbar
,
AXI4IdentityNode
}
import
freechips.rocketchip.amba.axi4.
{
AXI4
IdIndexer
,
AXI4IdentityNode
,
AXI4UserYanker
,
AXI4Xbar
}
import
freechips.rocketchip.diplomacy.
{
AddressSet
,
BufferParams
,
LazyModule
,
LazyModuleImp
}
import
freechips.rocketchip.diplomacy.
{
AddressSet
,
BufferParams
,
LazyModule
,
LazyModuleImp
}
import
freechips.rocketchip.tilelink.
{
TLToAXI4
}
import
freechips.rocketchip.tilelink.
TLToAXI4
import
xiangshan._
import
xiangshan._
import
utils._
import
utils._
import
ExcitingUtils.Debug
import
ExcitingUtils.Debug
...
@@ -100,7 +100,7 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
...
@@ -100,7 +100,7 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
startAddr
=
0x80000000
L
,
startAddr
=
0x80000000
L
,
nOp
=
0
,
nOp
=
0
,
beatBytes
=
L3BusWidth
/
8
))
beatBytes
=
L3BusWidth
/
8
))
soc
.
dma
:=
burst
.
node
soc
.
dma
:=
AXI4IdIndexer
(
16
)
:=
burst
.
node
// AXI MMIO
// AXI MMIO
// -----------------------------------
// -----------------------------------
...
...
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