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31ea8750
编写于
2月 02, 2021
作者:
L
LinJiawei
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
Alu: opt timing
上级
6c954985
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
130 addition
and
31 deletion
+130
-31
src/main/scala/xiangshan/backend/fu/Alu.scala
src/main/scala/xiangshan/backend/fu/Alu.scala
+130
-31
未找到文件。
src/main/scala/xiangshan/backend/fu/Alu.scala
浏览文件 @
31ea8750
...
...
@@ -2,10 +2,91 @@ package xiangshan.backend.fu
import
chisel3._
import
chisel3.util._
import
utils.
{
LookupTree
,
LookupTreeDefault
,
ParallelMux
,
SignExt
,
XSDebug
,
ZeroExt
}
import
utils.
{
LookupTree
,
ParallelMux
,
SignExt
,
ZeroExt
}
import
xiangshan._
import
xiangshan.backend.ALUOpType
class
AddModule
extends
XSModule
{
val
io
=
IO
(
new
Bundle
()
{
val
src1
,
src2
=
Input
(
UInt
(
XLEN
.
W
))
val
out
=
Output
(
UInt
((
XLEN
+
1
).
W
))
})
io
.
out
:=
io
.
src1
+&
io
.
src2
}
class
SubModule
extends
XSModule
{
val
io
=
IO
(
new
Bundle
()
{
val
src1
,
src2
=
Input
(
UInt
(
XLEN
.
W
))
val
out
=
Output
(
UInt
((
XLEN
+
1
).
W
))
})
io
.
out
:=
(
io
.
src1
+&
(~
io
.
src2
).
asUInt
())
+
1.
U
}
class
LeftShiftModule
extends
XSModule
{
val
io
=
IO
(
new
Bundle
()
{
val
shamt
=
Input
(
UInt
(
6.
W
))
val
sllSrc
=
Input
(
UInt
(
XLEN
.
W
))
val
sll
=
Output
(
UInt
(
XLEN
.
W
))
})
io
.
sll
:=
(
io
.
sllSrc
<<
io
.
shamt
)(
XLEN
-
1
,
0
)
}
class
RightShiftModule
extends
XSModule
{
val
io
=
IO
(
new
Bundle
()
{
val
shamt
=
Input
(
UInt
(
6.
W
))
val
srlSrc
,
sraSrc
=
Input
(
UInt
(
XLEN
.
W
))
val
srl
,
sra
=
Output
(
UInt
(
XLEN
.
W
))
})
io
.
srl
:=
io
.
srlSrc
>>
io
.
shamt
io
.
sra
:=
(
io
.
sraSrc
.
asSInt
()
>>
io
.
shamt
).
asUInt
()
}
class
ShiftModule
extends
XSModule
{
val
io
=
IO
(
new
Bundle
()
{
val
shamt
=
Input
(
UInt
(
6.
W
))
val
shsrc1
=
Input
(
UInt
(
XLEN
.
W
))
val
sll
,
srl
,
sra
=
Output
(
UInt
(
XLEN
.
W
))
})
io
.
sll
:=
(
io
.
shsrc1
<<
io
.
shamt
)(
XLEN
-
1
,
0
)
io
.
srl
:=
io
.
shsrc1
>>
io
.
shamt
io
.
sra
:=
(
io
.
shsrc1
.
asSInt
>>
io
.
shamt
).
asUInt
}
class
MiscResultSelect
extends
XSModule
{
val
io
=
IO
(
new
Bundle
()
{
val
func
=
Input
(
UInt
())
val
sll
,
slt
,
sltu
,
xor
,
srl
,
or
,
and
,
sra
=
Input
(
UInt
(
XLEN
.
W
))
val
miscRes
=
Output
(
UInt
(
XLEN
.
W
))
})
io
.
miscRes
:=
ParallelMux
(
List
(
ALUOpType
.
and
->
io
.
and
,
ALUOpType
.
or
->
io
.
or
,
ALUOpType
.
xor
->
io
.
xor
,
ALUOpType
.
slt
->
ZeroExt
(
io
.
slt
,
XLEN
),
ALUOpType
.
sltu
->
ZeroExt
(
io
.
sltu
,
XLEN
),
ALUOpType
.
srl
->
io
.
srl
,
ALUOpType
.
sll
->
io
.
sll
,
ALUOpType
.
sra
->
io
.
sra
).
map
(
x
=>
(
x
.
_1
===
io
.
func
(
3
,
0
),
x
.
_2
)))
}
class
AluResSel
extends
XSModule
{
val
io
=
IO
(
new
Bundle
()
{
val
func
=
Input
(
UInt
())
val
isSub
=
Input
(
Bool
())
val
addRes
,
subRes
,
miscRes
=
Input
(
UInt
(
XLEN
.
W
))
val
aluRes
=
Output
(
UInt
(
XLEN
.
W
))
})
val
isAddSub
=
ALUOpType
.
isAddSub
(
io
.
func
)
val
res
=
Mux
(
ALUOpType
.
isAddSub
(
io
.
func
),
Mux
(
io
.
isSub
,
io
.
subRes
,
io
.
addRes
),
io
.
miscRes
)
val
h32
=
Mux
(
ALUOpType
.
isWordOp
(
io
.
func
),
Fill
(
32
,
res
(
31
)),
res
(
63
,
32
))
io
.
aluRes
:=
Cat
(
h32
,
res
(
31
,
0
))
}
class
Alu
extends
FunctionUnit
with
HasRedirectOut
{
val
(
src1
,
src2
,
func
,
pc
,
uop
)
=
(
...
...
@@ -16,40 +97,63 @@ class Alu extends FunctionUnit with HasRedirectOut {
io
.
in
.
bits
.
uop
)
val
offset
=
src2
val
valid
=
io
.
in
.
valid
val
isAdderSub
=
(
func
=/=
ALUOpType
.
add
)
&&
(
func
=/=
ALUOpType
.
addw
)
val
addRes
=
src1
+&
src2
val
subRes
=
(
src1
+&
(~
src2
).
asUInt
())
+
1.
U
val
addModule
=
Module
(
new
AddModule
)
addModule
.
io
.
src1
:=
src1
addModule
.
io
.
src2
:=
src2
val
subModule
=
Module
(
new
SubModule
)
subModule
.
io
.
src1
:=
src1
subModule
.
io
.
src2
:=
src2
val
addRes
=
addModule
.
io
.
out
val
subRes
=
subModule
.
io
.
out
val
xorRes
=
src1
^
src2
val
sltu
=
!
subRes
(
XLEN
)
val
slt
=
xorRes
(
XLEN
-
1
)
^
sltu
val
shsrc1
=
LookupTreeDefault
(
func
,
src1
,
List
(
ALUOpType
.
srlw
->
ZeroExt
(
src1
(
31
,
0
),
64
),
ALUOpType
.
sraw
->
SignExt
(
src1
(
31
,
0
),
64
)
))
val
shamt
=
Mux
(
ALUOpType
.
isWordOp
(
func
),
src2
(
4
,
0
),
src2
(
5
,
0
))
val
miscRes
=
ParallelMux
(
List
(
ALUOpType
.
sll
->
(
shsrc1
<<
shamt
)(
XLEN
-
1
,
0
),
ALUOpType
.
slt
->
ZeroExt
(
slt
,
XLEN
),
ALUOpType
.
sltu
->
ZeroExt
(
sltu
,
XLEN
),
ALUOpType
.
xor
->
xorRes
,
ALUOpType
.
srl
->
(
shsrc1
>>
shamt
),
ALUOpType
.
or
->
(
src1
|
src2
),
ALUOpType
.
and
->
(
src1
&
src2
),
ALUOpType
.
sra
->
(
shsrc1
.
asSInt
>>
shamt
).
asUInt
).
map
(
x
=>
(
x
.
_1
===
func
(
3
,
0
),
x
.
_2
)))
val
res
=
Mux
(
ALUOpType
.
isAddSub
(
func
),
Mux
(
isAdderSub
,
subRes
,
addRes
),
miscRes
val
isW
=
ALUOpType
.
isWordOp
(
func
)
val
shamt
=
Cat
(
isW
&&
src2
(
5
),
src2
(
4
,
0
))
val
leftShiftModule
=
Module
(
new
LeftShiftModule
)
leftShiftModule
.
io
.
sllSrc
:=
src1
leftShiftModule
.
io
.
shamt
:=
shamt
val
rightShiftModule
=
Module
(
new
RightShiftModule
)
rightShiftModule
.
io
.
shamt
:=
shamt
rightShiftModule
.
io
.
srlSrc
:=
Cat
(
Mux
(
isW
,
0.
U
(
32.
W
),
src1
(
63
,
32
)),
src1
(
31
,
0
)
)
rightShiftModule
.
io
.
sraSrc
:=
Cat
(
Mux
(
isW
,
Fill
(
32
,
src1
(
31
)),
src1
(
63
,
32
)),
src1
(
31
,
0
)
)
val
aluRes
=
Mux
(
ALUOpType
.
isWordOp
(
func
),
SignExt
(
res
(
31
,
0
),
64
),
res
)
val
sll
=
leftShiftModule
.
io
.
sll
val
srl
=
rightShiftModule
.
io
.
srl
val
sra
=
rightShiftModule
.
io
.
sra
val
miscResSel
=
Module
(
new
MiscResultSelect
)
miscResSel
.
io
.
func
:=
func
(
3
,
0
)
miscResSel
.
io
.
sll
:=
sll
miscResSel
.
io
.
slt
:=
ZeroExt
(
slt
,
XLEN
)
miscResSel
.
io
.
sltu
:=
ZeroExt
(
sltu
,
XLEN
)
miscResSel
.
io
.
xor
:=
xorRes
miscResSel
.
io
.
srl
:=
srl
miscResSel
.
io
.
or
:=
(
src1
|
src2
)
miscResSel
.
io
.
and
:=
(
src1
&
src2
)
miscResSel
.
io
.
sra
:=
sra
val
miscRes
=
miscResSel
.
io
.
miscRes
val
aluResSel
=
Module
(
new
AluResSel
)
aluResSel
.
io
.
func
:=
func
aluResSel
.
io
.
isSub
:=
isAdderSub
aluResSel
.
io
.
addRes
:=
addRes
aluResSel
.
io
.
subRes
:=
subRes
aluResSel
.
io
.
miscRes
:=
miscRes
val
aluRes
=
aluResSel
.
io
.
aluRes
val
branchOpTable
=
List
(
ALUOpType
.
getBranchType
(
ALUOpType
.
beq
)
->
!
xorRes
.
orR
,
...
...
@@ -58,14 +162,9 @@ class Alu extends FunctionUnit with HasRedirectOut {
)
val
isBranch
=
ALUOpType
.
isBranch
(
func
)
val
isRVC
=
uop
.
cf
.
pd
.
isRVC
val
taken
=
LookupTree
(
ALUOpType
.
getBranchType
(
func
),
branchOpTable
)
^
ALUOpType
.
isBranchInvert
(
func
)
val
target
=
(
pc
+
offset
)(
VAddrBits
-
1
,
0
)
val
snpc
=
Mux
(
isRVC
,
pc
+
2.
U
,
pc
+
4.
U
)
redirectOutValid
:=
io
.
out
.
valid
&&
isBranch
// Only brTag, level, roqIdx are needed
// other infos are stored in brq
redirectOut
:=
DontCare
redirectOut
.
level
:=
RedirectLevel
.
flushAfter
redirectOut
.
roqIdx
:=
uop
.
roqIdx
...
...
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