diff --git a/.github/workflows/emu.yml b/.github/workflows/emu.yml
index 85c9d8b7fabea9d94bbb4a7316908fde582fc550..fcde0284b8343e6feaa05bd565f8143fab381805 100644
--- a/.github/workflows/emu.yml
+++ b/.github/workflows/emu.yml
@@ -39,7 +39,7 @@ jobs:
           echo "AM_HOME=/home/ci-runner/xsenv/nexus-am" >> $GITHUB_ENV
       - name: Build EMU
         run:
-          make ./build/emu SIM_ARGS=--disable-log NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME B=0 E=0 -j220
+          make ./build/emu SIM_ARGS=--disable-log NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME B=0 E=0 -j220 EMU_TRACE=1 EMU_THREADS=8
       - name: Run cputest
         run: |
           CPU_TEST_DIR=$AM_HOME/tests/cputest
@@ -49,7 +49,7 @@ jobs:
           do
               t=${test%.c}
               echo $t
-              make -C $CPU_TEST_DIR ALL=$t ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run B=0 E=0 | grep "HIT GOOD TRAP"
+              numactl -m 1 -C 64-71 make -C $CPU_TEST_DIR ALL=$t ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run | grep "HIT GOOD TRAP"
               if [[ $? != 0 ]];
               then
                   echo $t fail
@@ -59,10 +59,14 @@ jobs:
           exit $ret
       - name: Run riscv-tests
         run: |
-          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua SUITES+=rv64uf SUITES+=rv64ud NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run B=0 E=0
+          numactl -m 1 -C 64-71 make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua SUITES+=rv64uf SUITES+=rv64ud NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run
       - name: Run microbench
         run: |
-          make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run B=0 E=0
+          numactl -m 1 -C 64-71 make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run
       - name: Run coremark
         run: |
-          make -C $AM_HOME/apps/coremark ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run B=0 E=0
+          numactl -m 1 -C 64-71 make -C $AM_HOME/apps/coremark ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME run
+      - name: Run Linux
+        run: |
+          numactl -m 1 -C 64-71 make emu IMAGE=/home/ci-runner/xsenv/workloads/linux-hello/bbl.bin
+
diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala
index e42f660edf905df6805488d7b05eab139cc0f535..724ad6587f6decb0a7ed055c12c1525888b87070 100644
--- a/src/main/scala/xiangshan/XSCore.scala
+++ b/src/main/scala/xiangshan/XSCore.scala
@@ -414,7 +414,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
 
   frontend.io.backend <> ctrlBlock.io.frontend
   frontend.io.sfence <> integerBlock.io.fenceio.sfence
-  frontend.io.tlbCsr := RegNext(integerBlock.io.csrio.tlb)
+  frontend.io.tlbCsr := integerBlock.io.csrio.tlb
 
   frontend.io.icacheMemAcq <> l1pluscache.io.req
   l1pluscache.io.resp <> frontend.io.icacheMemGrant
diff --git a/src/main/scala/xiangshan/backend/fu/Alu.scala b/src/main/scala/xiangshan/backend/fu/Alu.scala
index 6d2618dc880a63c2f88ce3c485fb9a145cf6f451..6497302709f121fc38a243a32c752a376b0d61f1 100644
--- a/src/main/scala/xiangshan/backend/fu/Alu.scala
+++ b/src/main/scala/xiangshan/backend/fu/Alu.scala
@@ -113,7 +113,7 @@ class Alu extends FunctionUnit with HasRedirectOut {
   val slt = xorRes(XLEN-1) ^ sltu
 
   val isW = ALUOpType.isWordOp(func)
-  val shamt = Cat(isW && src2(5), src2(4, 0))
+  val shamt = Cat(!isW && src2(5), src2(4, 0))
 
   val leftShiftModule = Module(new LeftShiftModule)
   leftShiftModule.io.sllSrc := src1
diff --git a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
index 646861ce36f7a5c3da5228c641cdec6a0f051cd8..00041f1428005061192b5e53e7d04d8b88578d04 100644
--- a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
+++ b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
@@ -489,6 +489,7 @@ class ReservationStationCtrl
     val asynIdxUop = (0 until iqSize).map(i => asynUop(io.indexVec(i)) )
     val readyIdxVec = (0 until iqSize).map(i => io.validVec(i) && Cat(srcQueue(io.indexVec(i))).andR )
     val fastAsynUop = ParallelPriorityMux(readyIdxVec zip asynIdxUop)
+    val fastRoqIdx = ParallelPriorityMux(readyIdxVec zip roqIdx)
     val fastSentUop = Wire(new MicroOp)
     fastSentUop := DontCare
     fastSentUop.pdest := fastAsynUop.pdest
@@ -502,6 +503,7 @@ class ReservationStationCtrl
       val bpQueue = Module(new BypassQueue(fixedDelay))
       bpQueue.io.in.valid := selValid
       bpQueue.io.in.bits  := fastSentUop
+      bpQueue.io.in.bits.roqIdx := fastRoqIdx
       bpQueue.io.redirect := io.redirect
       bpQueue.io.flush    := io.flush
       io.fastUopOut.valid := bpQueue.io.out.valid
diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
index 76f789d72c4f117997d8692d539aade328c7078d..d8789e73d1dc2ac923468e49a3fce5bc8d779d16 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
@@ -468,8 +468,7 @@ class LoadQueue extends XSModule
   val rollbackGen = Wire(Valid(new Redirect))
   val rollbackReg = Reg(Valid(new Redirect))
   rollbackGen.valid := rollbackSelected.valid &&
-    (!lastCycleRedirect.valid || !isAfter(rollbackSelected.bits.roqIdx, lastCycleRedirect.bits.roqIdx)) &&
-    !lastCycleFlush
+    !rollbackSelected.bits.roqIdx.needFlush(lastCycleRedirect, lastCycleFlush)
 
   rollbackGen.bits.roqIdx := rollbackSelected.bits.roqIdx
   rollbackGen.bits.ftqIdx := rollbackSelected.bits.cf.ftqPtr
@@ -484,8 +483,7 @@ class LoadQueue extends XSModule
   // S3: fire rollback request
   io.rollback := rollbackReg
   io.rollback.valid := rollbackReg.valid &&
-    (!lastCycleRedirect.valid || !isAfter(rollbackReg.bits.roqIdx, lastCycleRedirect.bits.roqIdx)) &&
-    !lastCycleFlush
+    !rollbackReg.bits.roqIdx.needFlush(lastCycleRedirect, lastCycleFlush)
 
   when(io.rollback.valid) {
     // XSDebug("Mem rollback: pc %x roqidx %d\n", io.rollback.bits.cfi, io.rollback.bits.roqIdx.asUInt)
diff --git a/src/test/csrc/emu.cpp b/src/test/csrc/emu.cpp
index db5068e538ac4e944acde5f13bb72c9c8b4b33b6..4ba6e05df51b524ca34c7df53dce6d2f60219825 100644
--- a/src/test/csrc/emu.cpp
+++ b/src/test/csrc/emu.cpp
@@ -572,7 +572,7 @@ void Emulator::snapshot_load(const char *filename) {
 
   uint64_t ref_r[DIFFTEST_NR_REG];
   stream.read(ref_r, sizeof(ref_r));
-  ref_difftest_setregs(&ref_r);
+  ref_difftest_setregs(&ref_r, 0);
 
   uint64_t nemu_this_pc;
   stream.read(&nemu_this_pc, sizeof(nemu_this_pc));
@@ -585,11 +585,11 @@ void Emulator::snapshot_load(const char *filename) {
 
   struct SyncState sync_mastate;
   stream.read(&sync_mastate, sizeof(struct SyncState));
-  ref_difftest_set_mastatus(&sync_mastate);
+  ref_difftest_set_mastatus(&sync_mastate, 0);
 
   uint64_t csr_buf[4096];
   stream.read(&csr_buf, sizeof(csr_buf));
-  ref_difftest_set_csr(csr_buf);
+  ref_difftest_set_csr(csr_buf, 0);
 
   long sdcard_offset = 0;
   stream.read(&sdcard_offset, sizeof(sdcard_offset));
diff --git a/src/test/scala/top/XSSim.scala b/src/test/scala/top/XSSim.scala
index 8aa31732085f85214b3b7ac0255eae51c32af657..c57c9371686dc3df772bfe262a813c2c709bddae 100644
--- a/src/test/scala/top/XSSim.scala
+++ b/src/test/scala/top/XSSim.scala
@@ -6,9 +6,9 @@ import chisel3.util._
 import chipsalliance.rocketchip.config
 import chisel3.stage.ChiselGeneratorAnnotation
 import device._
-import freechips.rocketchip.amba.axi4.{AXI4UserYanker, AXI4Xbar, AXI4IdentityNode}
+import freechips.rocketchip.amba.axi4.{AXI4IdIndexer, AXI4IdentityNode, AXI4UserYanker, AXI4Xbar}
 import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, LazyModule, LazyModuleImp}
-import freechips.rocketchip.tilelink.{TLToAXI4}
+import freechips.rocketchip.tilelink.TLToAXI4
 import xiangshan._
 import utils._
 import ExcitingUtils.Debug
@@ -100,7 +100,7 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
     startAddr = 0x80000000L,
     nOp = 0,
     beatBytes = L3BusWidth / 8))
-  soc.dma := burst.node
+  soc.dma := AXI4IdIndexer(16) := burst.node
 
   // AXI MMIO
   // -----------------------------------