build.sc: update chilse to chisel3:3.2.0-RC1

23c18692 · Zihao Yu · d602f6fa · 23c18692 · 23c18692
隐藏空白更改
内联并排

Showing with 1 addition and 3 deletion

build.sc build.sc +1 -2

src/main/scala/top/TopMain.scala src/main/scala/top/TopMain.scala +0 -1

未找到文件。
--- a/build.sc
+++ b/build.sc
@@ -25,8 +25,7 @@ trait HasXsource211 extends ScalaModule {

 trait HasChisel3 extends ScalaModule {
  override def ivyDeps = Agg(
-    //ivy"edu.berkeley.cs::chisel3:3.1.+"
-    ivy"edu.berkeley.cs::chisel3:3.2-SNAPSHOT"
+    ivy"edu.berkeley.cs::chisel3:3.2.0-RC1"
 )
 }


--- a/src/main/scala/top/TopMain.scala
+++ b/src/main/scala/top/TopMain.scala
@@ -6,7 +6,6 @@ import device.{AXI4Timer, AXI4VGA}
 import gpu._

 import chisel3._
-import chisel3.experimental.dontTouch

 class Top extends Module {
  val io = IO(new Bundle{})