pci.c 67.0 KB
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/*
 * Copyright (c) 2005-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/pci.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
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#include <linux/bitops.h>
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#include "core.h"
#include "debug.h"

#include "targaddrs.h"
#include "bmi.h"

#include "hif.h"
#include "htc.h"

#include "ce.h"
#include "pci.h"

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enum ath10k_pci_irq_mode {
	ATH10K_PCI_IRQ_AUTO = 0,
	ATH10K_PCI_IRQ_LEGACY = 1,
	ATH10K_PCI_IRQ_MSI = 2,
};

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enum ath10k_pci_reset_mode {
	ATH10K_PCI_RESET_AUTO = 0,
	ATH10K_PCI_RESET_WARM_ONLY = 1,
};

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static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
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static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
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module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");

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module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");

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/* how long wait to wait for target to initialise, in ms */
#define ATH10K_PCI_TARGET_WAIT 3000
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#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
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#define QCA988X_2_0_DEVICE_ID	(0x003c)
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#define QCA6174_2_1_DEVICE_ID	(0x003e)
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static const struct pci_device_id ath10k_pci_id_table[] = {
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	{ PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
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	{ PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
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	{0}
};

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static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
	/* QCA988X pre 2.0 chips are not supported because they need some nasty
	 * hacks. ath10k doesn't have them and these devices crash horribly
	 * because of that.
	 */
	{ QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
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	{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
	{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
	{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
	{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
	{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
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};

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static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
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static int ath10k_pci_cold_reset(struct ath10k *ar);
static int ath10k_pci_warm_reset(struct ath10k *ar);
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static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
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static int ath10k_pci_init_irq(struct ath10k *ar);
static int ath10k_pci_deinit_irq(struct ath10k *ar);
static int ath10k_pci_request_irq(struct ath10k *ar);
static void ath10k_pci_free_irq(struct ath10k *ar);
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static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
			       struct ath10k_ce_pipe *rx_pipe,
			       struct bmi_xfer *xfer);
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static const struct ce_attr host_ce_config_wlan[] = {
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	/* CE0: host->target HTC control and raw streams */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 16,
		.src_sz_max = 256,
		.dest_nentries = 0,
	},

	/* CE1: target->host HTT + HTC control */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
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		.src_sz_max = 2048,
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		.dest_nentries = 512,
	},

	/* CE2: target->host WMI */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
		.src_sz_max = 2048,
		.dest_nentries = 32,
	},

	/* CE3: host->target WMI */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 32,
		.src_sz_max = 2048,
		.dest_nentries = 0,
	},

	/* CE4: host->target HTT */
	{
		.flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
		.src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
		.src_sz_max = 256,
		.dest_nentries = 0,
	},

	/* CE5: unused */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
		.src_sz_max = 0,
		.dest_nentries = 0,
	},

	/* CE6: target autonomous hif_memcpy */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 0,
		.src_sz_max = 0,
		.dest_nentries = 0,
	},

	/* CE7: ce_diag, the Diagnostic Window */
	{
		.flags = CE_ATTR_FLAGS,
		.src_nentries = 2,
		.src_sz_max = DIAG_TRANSFER_LIMIT,
		.dest_nentries = 2,
	},
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};

/* Target firmware's Copy Engine configuration. */
static const struct ce_pipe_config target_ce_config_wlan[] = {
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	/* CE0: host->target HTC control and raw streams */
	{
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		.pipenum = __cpu_to_le32(0),
		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
		.nentries = __cpu_to_le32(32),
		.nbytes_max = __cpu_to_le32(256),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

	/* CE1: target->host HTT + HTC control */
	{
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		.pipenum = __cpu_to_le32(1),
		.pipedir = __cpu_to_le32(PIPEDIR_IN),
		.nentries = __cpu_to_le32(32),
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		.nbytes_max = __cpu_to_le32(2048),
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		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

	/* CE2: target->host WMI */
	{
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		.pipenum = __cpu_to_le32(2),
		.pipedir = __cpu_to_le32(PIPEDIR_IN),
		.nentries = __cpu_to_le32(32),
		.nbytes_max = __cpu_to_le32(2048),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

	/* CE3: host->target WMI */
	{
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		.pipenum = __cpu_to_le32(3),
		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
		.nentries = __cpu_to_le32(32),
		.nbytes_max = __cpu_to_le32(2048),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

	/* CE4: host->target HTT */
	{
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		.pipenum = __cpu_to_le32(4),
		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
		.nentries = __cpu_to_le32(256),
		.nbytes_max = __cpu_to_le32(256),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

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	/* NB: 50% of src nentries, since tx has 2 frags */
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	/* CE5: unused */
	{
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		.pipenum = __cpu_to_le32(5),
		.pipedir = __cpu_to_le32(PIPEDIR_OUT),
		.nentries = __cpu_to_le32(32),
		.nbytes_max = __cpu_to_le32(2048),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

	/* CE6: Reserved for target autonomous hif_memcpy */
	{
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		.pipenum = __cpu_to_le32(6),
		.pipedir = __cpu_to_le32(PIPEDIR_INOUT),
		.nentries = __cpu_to_le32(32),
		.nbytes_max = __cpu_to_le32(4096),
		.flags = __cpu_to_le32(CE_ATTR_FLAGS),
		.reserved = __cpu_to_le32(0),
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	},

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	/* CE7 used only by Host */
};

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/*
 * Map from service/endpoint to Copy Engine.
 * This table is derived from the CE_PCI TABLE, above.
 * It is passed to the Target at startup for use by firmware.
 */
static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(3),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(2),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(3),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(2),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(3),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(2),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(3),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(2),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(3),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(2),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(0),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(1),
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	},
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	{ /* not used */
		__cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(0),
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	},
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	{ /* not used */
		__cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(1),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
		__cpu_to_le32(PIPEDIR_OUT),	/* out = UL = host -> target */
		__cpu_to_le32(4),
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	},
	{
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		__cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
		__cpu_to_le32(PIPEDIR_IN),	/* in = DL = target -> host */
		__cpu_to_le32(1),
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	},

	/* (Additions here) */

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	{ /* must be last */
		__cpu_to_le32(0),
		__cpu_to_le32(0),
		__cpu_to_le32(0),
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	},
};

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static bool ath10k_pci_irq_pending(struct ath10k *ar)
{
	u32 cause;

	/* Check if the shared legacy irq is for us */
	cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
				  PCIE_INTR_CAUSE_ADDRESS);
	if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
		return true;

	return false;
}

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static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
{
	/* IMPORTANT: INTR_CLR register has to be set after
	 * INTR_ENABLE is set to 0, otherwise interrupt can not be
	 * really cleared. */
	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
			   0);
	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
			   PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);

	/* IMPORTANT: this extra read transaction is required to
	 * flush the posted write buffer. */
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	(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
				PCIE_INTR_ENABLE_ADDRESS);
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}

static void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
{
	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
			   PCIE_INTR_ENABLE_ADDRESS,
			   PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);

	/* IMPORTANT: this extra read transaction is required to
	 * flush the posted write buffer. */
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	(void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
				PCIE_INTR_ENABLE_ADDRESS);
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}

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static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
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{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

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	if (ar_pci->num_msi_intrs > 1)
		return "msi-x";
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	if (ar_pci->num_msi_intrs == 1)
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		return "msi";
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	return "legacy";
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}

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static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
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{
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	struct ath10k *ar = pipe->hif_ce_state;
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	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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	struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
	struct sk_buff *skb;
	dma_addr_t paddr;
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	int ret;

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	lockdep_assert_held(&ar_pci->ce_lock);

	skb = dev_alloc_skb(pipe->buf_sz);
	if (!skb)
		return -ENOMEM;

	WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");

	paddr = dma_map_single(ar->dev, skb->data,
			       skb->len + skb_tailroom(skb),
			       DMA_FROM_DEVICE);
	if (unlikely(dma_mapping_error(ar->dev, paddr))) {
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		ath10k_warn(ar, "failed to dma map pci rx buf\n");
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		dev_kfree_skb_any(skb);
		return -EIO;
	}

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	ATH10K_SKB_RXCB(skb)->paddr = paddr;
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	ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
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	if (ret) {
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		ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
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		dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
				 DMA_FROM_DEVICE);
		dev_kfree_skb_any(skb);
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		return ret;
	}

	return 0;
}

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static void __ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
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{
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	struct ath10k *ar = pipe->hif_ce_state;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
	int ret, num;

	lockdep_assert_held(&ar_pci->ce_lock);

	if (pipe->buf_sz == 0)
		return;

	if (!ce_pipe->dest_ring)
		return;

	num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
	while (num--) {
		ret = __ath10k_pci_rx_post_buf(pipe);
		if (ret) {
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			ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
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			mod_timer(&ar_pci->rx_post_retry, jiffies +
				  ATH10K_PCI_RX_POST_RETRY_MS);
			break;
		}
	}
}

static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
{
	struct ath10k *ar = pipe->hif_ce_state;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	spin_lock_bh(&ar_pci->ce_lock);
	__ath10k_pci_rx_post_pipe(pipe);
	spin_unlock_bh(&ar_pci->ce_lock);
}

static void ath10k_pci_rx_post(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int i;

	spin_lock_bh(&ar_pci->ce_lock);
	for (i = 0; i < CE_COUNT; i++)
		__ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
	spin_unlock_bh(&ar_pci->ce_lock);
}

static void ath10k_pci_rx_replenish_retry(unsigned long ptr)
{
	struct ath10k *ar = (void *)ptr;

	ath10k_pci_rx_post(ar);
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}

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/*
 * Diagnostic read/write access is provided for startup/config/debug usage.
 * Caller must guarantee proper alignment, when applicable, and single user
 * at any moment.
 */
static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
				    int nbytes)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int ret = 0;
	u32 buf;
	unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
	unsigned int id;
	unsigned int flags;
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	struct ath10k_ce_pipe *ce_diag;
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	/* Host buffer address in CE space */
	u32 ce_data;
	dma_addr_t ce_data_base = 0;
	void *data_buf = NULL;
	int i;

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	spin_lock_bh(&ar_pci->ce_lock);

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	ce_diag = ar_pci->ce_diag;

	/*
	 * Allocate a temporary bounce buffer to hold caller's data
	 * to be DMA'ed from Target. This guarantees
	 *   1) 4-byte alignment
	 *   2) Buffer in DMA-able space
	 */
	orig_nbytes = nbytes;
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	data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
						       orig_nbytes,
						       &ce_data_base,
						       GFP_ATOMIC);
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	if (!data_buf) {
		ret = -ENOMEM;
		goto done;
	}
	memset(data_buf, 0, orig_nbytes);

	remaining_bytes = orig_nbytes;
	ce_data = ce_data_base;
	while (remaining_bytes) {
		nbytes = min_t(unsigned int, remaining_bytes,
			       DIAG_TRANSFER_LIMIT);

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		ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data);
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		if (ret != 0)
			goto done;

		/* Request CE to send from Target(!) address to Host buffer */
		/*
		 * The address supplied by the caller is in the
		 * Target CPU virtual address space.
		 *
		 * In order to use this address with the diagnostic CE,
		 * convert it from Target CPU virtual address space
		 * to CE address space
		 */
		address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
						     address);

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		ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
					    0);
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		if (ret)
			goto done;

		i = 0;
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		while (ath10k_ce_completed_send_next_nolock(ce_diag, NULL, &buf,
							    &completed_nbytes,
							    &id) != 0) {
556 557 558 559 560 561 562 563 564 565 566 567
			mdelay(1);
			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
				ret = -EBUSY;
				goto done;
			}
		}

		if (nbytes != completed_nbytes) {
			ret = -EIO;
			goto done;
		}

568
		if (buf != (u32)address) {
569 570 571 572 573
			ret = -EIO;
			goto done;
		}

		i = 0;
K
Kalle Valo 已提交
574 575 576
		while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
							    &completed_nbytes,
							    &id, &flags) != 0) {
577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
			mdelay(1);

			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
				ret = -EBUSY;
				goto done;
			}
		}

		if (nbytes != completed_nbytes) {
			ret = -EIO;
			goto done;
		}

		if (buf != ce_data) {
			ret = -EIO;
			goto done;
		}

		remaining_bytes -= nbytes;
		address += nbytes;
		ce_data += nbytes;
	}

done:
601 602 603
	if (ret == 0)
		memcpy(data, data_buf, orig_nbytes);
	else
604
		ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n",
K
Kalle Valo 已提交
605
			    address, ret);
606 607

	if (data_buf)
608 609
		dma_free_coherent(ar->dev, orig_nbytes, data_buf,
				  ce_data_base);
610

K
Kalle Valo 已提交
611 612
	spin_unlock_bh(&ar_pci->ce_lock);

613 614 615
	return ret;
}

616 617
static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
{
618 619 620 621 622 623 624
	__le32 val = 0;
	int ret;

	ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
	*value = __le32_to_cpu(val);

	return ret;
625 626 627 628 629 630 631 632 633 634 635 636
}

static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
				     u32 src, u32 len)
{
	u32 host_addr, addr;
	int ret;

	host_addr = host_interest_item_address(src);

	ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
	if (ret != 0) {
637
		ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
638 639 640 641 642 643
			    src, ret);
		return ret;
	}

	ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
	if (ret != 0) {
644
		ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
645 646 647 648 649 650 651 652
			    addr, len, ret);
		return ret;
	}

	return 0;
}

#define ath10k_pci_diag_read_hi(ar, dest, src, len)		\
653
	__ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
654

655 656 657 658 659 660 661 662 663
static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
				     const void *data, int nbytes)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int ret = 0;
	u32 buf;
	unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
	unsigned int id;
	unsigned int flags;
664
	struct ath10k_ce_pipe *ce_diag;
665 666 667 668 669
	void *data_buf = NULL;
	u32 ce_data;	/* Host buffer address in CE space */
	dma_addr_t ce_data_base = 0;
	int i;

K
Kalle Valo 已提交
670 671
	spin_lock_bh(&ar_pci->ce_lock);

672 673 674 675 676 677 678 679 680
	ce_diag = ar_pci->ce_diag;

	/*
	 * Allocate a temporary bounce buffer to hold caller's data
	 * to be DMA'ed to Target. This guarantees
	 *   1) 4-byte alignment
	 *   2) Buffer in DMA-able space
	 */
	orig_nbytes = nbytes;
681 682 683 684
	data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
						       orig_nbytes,
						       &ce_data_base,
						       GFP_ATOMIC);
685 686 687 688 689 690
	if (!data_buf) {
		ret = -ENOMEM;
		goto done;
	}

	/* Copy caller's data to allocated DMA buf */
691
	memcpy(data_buf, data, orig_nbytes);
692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711

	/*
	 * The address supplied by the caller is in the
	 * Target CPU virtual address space.
	 *
	 * In order to use this address with the diagnostic CE,
	 * convert it from
	 *    Target CPU virtual address space
	 * to
	 *    CE address space
	 */
	address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);

	remaining_bytes = orig_nbytes;
	ce_data = ce_data_base;
	while (remaining_bytes) {
		/* FIXME: check cast */
		nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);

		/* Set up to receive directly into Target(!) address */
K
Kalle Valo 已提交
712
		ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, address);
713 714 715 716 717 718 719
		if (ret != 0)
			goto done;

		/*
		 * Request CE to send caller-supplied data that
		 * was copied to bounce buffer to Target(!) address.
		 */
K
Kalle Valo 已提交
720 721
		ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data,
					    nbytes, 0, 0);
722 723 724 725
		if (ret != 0)
			goto done;

		i = 0;
K
Kalle Valo 已提交
726 727 728
		while (ath10k_ce_completed_send_next_nolock(ce_diag, NULL, &buf,
							    &completed_nbytes,
							    &id) != 0) {
729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747
			mdelay(1);

			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
				ret = -EBUSY;
				goto done;
			}
		}

		if (nbytes != completed_nbytes) {
			ret = -EIO;
			goto done;
		}

		if (buf != ce_data) {
			ret = -EIO;
			goto done;
		}

		i = 0;
K
Kalle Valo 已提交
748 749 750
		while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
							    &completed_nbytes,
							    &id, &flags) != 0) {
751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775
			mdelay(1);

			if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
				ret = -EBUSY;
				goto done;
			}
		}

		if (nbytes != completed_nbytes) {
			ret = -EIO;
			goto done;
		}

		if (buf != address) {
			ret = -EIO;
			goto done;
		}

		remaining_bytes -= nbytes;
		address += nbytes;
		ce_data += nbytes;
	}

done:
	if (data_buf) {
776 777
		dma_free_coherent(ar->dev, orig_nbytes, data_buf,
				  ce_data_base);
778 779 780
	}

	if (ret != 0)
781
		ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
K
Kalle Valo 已提交
782
			    address, ret);
783

K
Kalle Valo 已提交
784 785
	spin_unlock_bh(&ar_pci->ce_lock);

786 787 788
	return ret;
}

789 790 791 792 793 794 795
static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
{
	__le32 val = __cpu_to_le32(value);

	return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
}

796
static bool ath10k_pci_is_awake(struct ath10k *ar)
797
{
798 799 800
	u32 val = ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS);

	return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
801 802
}

803
static int ath10k_pci_wake_wait(struct ath10k *ar)
804 805 806 807
{
	int tot_delay = 0;
	int curr_delay = 5;

808 809
	while (tot_delay < PCIE_WAKE_TIMEOUT) {
		if (ath10k_pci_is_awake(ar))
810
			return 0;
811 812 813 814 815 816 817

		udelay(curr_delay);
		tot_delay += curr_delay;

		if (curr_delay < 50)
			curr_delay += 5;
	}
818 819

	return -ETIMEDOUT;
820 821
}

822
static int ath10k_pci_wake(struct ath10k *ar)
823
{
824 825 826 827
	ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
			       PCIE_SOC_WAKE_V_MASK);
	return ath10k_pci_wake_wait(ar);
}
828

829 830 831 832
static void ath10k_pci_sleep(struct ath10k *ar)
{
	ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
			       PCIE_SOC_WAKE_RESET);
833 834 835
}

/* Called by lower (CE) layer when a send to Target completes. */
836
static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
837 838 839
{
	struct ath10k *ar = ce_state->ar;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
840
	struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
841 842
	struct sk_buff_head list;
	struct sk_buff *skb;
843 844 845
	u32 ce_data;
	unsigned int nbytes;
	unsigned int transfer_id;
846

847 848 849
	__skb_queue_head_init(&list);
	while (ath10k_ce_completed_send_next(ce_state, (void **)&skb, &ce_data,
					     &nbytes, &transfer_id) == 0) {
850
		/* no need to call tx completion for NULL pointers */
851
		if (skb == NULL)
852 853
			continue;

854
		__skb_queue_tail(&list, skb);
855
	}
856 857 858

	while ((skb = __skb_dequeue(&list)))
		cb->tx_completion(ar, skb);
859 860 861
}

/* Called by lower (CE) layer when data is received from the Target. */
862
static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
863 864 865
{
	struct ath10k *ar = ce_state->ar;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
866
	struct ath10k_pci_pipe *pipe_info =  &ar_pci->pipe_info[ce_state->id];
867
	struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
868
	struct sk_buff *skb;
869
	struct sk_buff_head list;
870 871
	void *transfer_context;
	u32 ce_data;
872
	unsigned int nbytes, max_nbytes;
873 874
	unsigned int transfer_id;
	unsigned int flags;
875

876
	__skb_queue_head_init(&list);
877 878 879
	while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
					     &ce_data, &nbytes, &transfer_id,
					     &flags) == 0) {
880
		skb = transfer_context;
881
		max_nbytes = skb->len + skb_tailroom(skb);
882
		dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
883 884 885
				 max_nbytes, DMA_FROM_DEVICE);

		if (unlikely(max_nbytes < nbytes)) {
886
			ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
887 888 889 890
				    nbytes, max_nbytes);
			dev_kfree_skb_any(skb);
			continue;
		}
891

892
		skb_put(skb, nbytes);
893 894
		__skb_queue_tail(&list, skb);
	}
895

896
	while ((skb = __skb_dequeue(&list))) {
897 898 899 900 901
		ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
			   ce_state->id, skb->len);
		ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
				skb->data, skb->len);

902
		cb->rx_completion(ar, skb);
903
	}
904

905
	ath10k_pci_rx_post_pipe(pipe_info);
906 907
}

908 909
static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
				struct ath10k_hif_sg_item *items, int n_items)
910 911
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
912 913 914
	struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
	struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
	struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
915 916 917
	unsigned int nentries_mask;
	unsigned int sw_index;
	unsigned int write_index;
918
	int err, i = 0;
919

920
	spin_lock_bh(&ar_pci->ce_lock);
921

922 923 924 925
	nentries_mask = src_ring->nentries_mask;
	sw_index = src_ring->sw_index;
	write_index = src_ring->write_index;

926 927 928
	if (unlikely(CE_RING_DELTA(nentries_mask,
				   write_index, sw_index - 1) < n_items)) {
		err = -ENOBUFS;
929
		goto err;
930
	}
931

932
	for (i = 0; i < n_items - 1; i++) {
933
		ath10k_dbg(ar, ATH10K_DBG_PCI,
934 935
			   "pci tx item %d paddr 0x%08x len %d n_items %d\n",
			   i, items[i].paddr, items[i].len, n_items);
936
		ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
937
				items[i].vaddr, items[i].len);
938

939 940 941 942 943 944 945
		err = ath10k_ce_send_nolock(ce_pipe,
					    items[i].transfer_context,
					    items[i].paddr,
					    items[i].len,
					    items[i].transfer_id,
					    CE_SEND_FLAG_GATHER);
		if (err)
946
			goto err;
947 948 949 950
	}

	/* `i` is equal to `n_items -1` after for() */

951
	ath10k_dbg(ar, ATH10K_DBG_PCI,
952 953
		   "pci tx item %d paddr 0x%08x len %d n_items %d\n",
		   i, items[i].paddr, items[i].len, n_items);
954
	ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
955 956 957 958 959 960 961 962 963
			items[i].vaddr, items[i].len);

	err = ath10k_ce_send_nolock(ce_pipe,
				    items[i].transfer_context,
				    items[i].paddr,
				    items[i].len,
				    items[i].transfer_id,
				    0);
	if (err)
964 965 966 967 968 969 970 971
		goto err;

	spin_unlock_bh(&ar_pci->ce_lock);
	return 0;

err:
	for (; i > 0; i--)
		__ath10k_ce_send_revert(ce_pipe);
972 973 974

	spin_unlock_bh(&ar_pci->ce_lock);
	return err;
975 976
}

K
Kalle Valo 已提交
977 978 979 980 981 982
static int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
				    size_t buf_len)
{
	return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
}

983 984 985
static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
K
Kalle Valo 已提交
986

987
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
K
Kalle Valo 已提交
988

M
Michal Kazior 已提交
989
	return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
990 991
}

992 993
static void ath10k_pci_dump_registers(struct ath10k *ar,
				      struct ath10k_fw_crash_data *crash_data)
994
{
995 996
	__le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
	int i, ret;
997

998
	lockdep_assert_held(&ar->data_lock);
999

1000 1001
	ret = ath10k_pci_diag_read_hi(ar, &reg_dump_values[0],
				      hi_failure_state,
1002
				      REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1003
	if (ret) {
1004
		ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1005 1006 1007 1008 1009
		return;
	}

	BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);

1010
	ath10k_err(ar, "firmware register dump:\n");
1011
	for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1012
		ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1013
			   i,
1014 1015 1016 1017
			   __le32_to_cpu(reg_dump_values[i]),
			   __le32_to_cpu(reg_dump_values[i + 1]),
			   __le32_to_cpu(reg_dump_values[i + 2]),
			   __le32_to_cpu(reg_dump_values[i + 3]));
1018

M
Michal Kazior 已提交
1019 1020 1021
	if (!crash_data)
		return;

1022
	for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1023
		crash_data->registers[i] = reg_dump_values[i];
1024 1025
}

1026
static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1027 1028 1029 1030 1031 1032
{
	struct ath10k_fw_crash_data *crash_data;
	char uuid[50];

	spin_lock_bh(&ar->data_lock);

B
Ben Greear 已提交
1033 1034
	ar->stats.fw_crash_counter++;

1035 1036 1037 1038 1039 1040 1041
	crash_data = ath10k_debug_get_new_fw_crash_data(ar);

	if (crash_data)
		scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid);
	else
		scnprintf(uuid, sizeof(uuid), "n/a");

1042
	ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid);
1043
	ath10k_print_driver_info(ar);
1044 1045 1046
	ath10k_pci_dump_registers(ar, crash_data);

	spin_unlock_bh(&ar->data_lock);
1047

1048
	queue_work(ar->workqueue, &ar->restart_work);
1049 1050 1051 1052 1053
}

static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
					       int force)
{
1054
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
K
Kalle Valo 已提交
1055

1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076
	if (!force) {
		int resources;
		/*
		 * Decide whether to actually poll for completions, or just
		 * wait for a later chance.
		 * If there seem to be plenty of resources left, then just wait
		 * since checking involves reading a CE register, which is a
		 * relatively expensive operation.
		 */
		resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);

		/*
		 * If at least 50% of the total resources are still available,
		 * don't bother checking again yet.
		 */
		if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
			return;
	}
	ath10k_ce_per_engine_service(ar, pipe);
}

M
Michal Kazior 已提交
1077 1078
static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
					 struct ath10k_hif_cb *callbacks)
1079 1080 1081
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

1082
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif set callbacks\n");
1083 1084 1085 1086 1087

	memcpy(&ar_pci->msg_callbacks_current, callbacks,
	       sizeof(ar_pci->msg_callbacks_current));
}

1088
static void ath10k_pci_kill_tasklet(struct ath10k *ar)
1089 1090 1091 1092 1093
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int i;

	tasklet_kill(&ar_pci->intr_tq);
1094
	tasklet_kill(&ar_pci->msi_fw_err);
1095 1096 1097

	for (i = 0; i < CE_COUNT; i++)
		tasklet_kill(&ar_pci->pipe_info[i].intr);
1098 1099

	del_timer_sync(&ar_pci->rx_post_retry);
1100 1101
}

1102 1103 1104 1105 1106
static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
					      u16 service_id, u8 *ul_pipe,
					      u8 *dl_pipe, int *ul_is_polled,
					      int *dl_is_polled)
{
1107 1108 1109
	const struct service_to_pipe *entry;
	bool ul_set = false, dl_set = false;
	int i;
1110

1111
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
K
Kalle Valo 已提交
1112

1113 1114 1115
	/* polling for received messages not supported */
	*dl_is_polled = 0;

1116 1117
	for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
		entry = &target_service_to_ce_map_wlan[i];
1118

1119
		if (__le32_to_cpu(entry->service_id) != service_id)
1120
			continue;
1121

1122
		switch (__le32_to_cpu(entry->pipedir)) {
1123 1124 1125 1126
		case PIPEDIR_NONE:
			break;
		case PIPEDIR_IN:
			WARN_ON(dl_set);
1127
			*dl_pipe = __le32_to_cpu(entry->pipenum);
1128 1129 1130 1131
			dl_set = true;
			break;
		case PIPEDIR_OUT:
			WARN_ON(ul_set);
1132
			*ul_pipe = __le32_to_cpu(entry->pipenum);
1133 1134 1135 1136 1137
			ul_set = true;
			break;
		case PIPEDIR_INOUT:
			WARN_ON(dl_set);
			WARN_ON(ul_set);
1138 1139
			*dl_pipe = __le32_to_cpu(entry->pipenum);
			*ul_pipe = __le32_to_cpu(entry->pipenum);
1140 1141 1142 1143
			dl_set = true;
			ul_set = true;
			break;
		}
1144 1145
	}

1146 1147
	if (WARN_ON(!ul_set || !dl_set))
		return -ENOENT;
1148 1149 1150 1151

	*ul_is_polled =
		(host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;

1152
	return 0;
1153 1154 1155
}

static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1156
					    u8 *ul_pipe, u8 *dl_pipe)
1157 1158 1159
{
	int ul_is_polled, dl_is_polled;

1160
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
K
Kalle Valo 已提交
1161

1162 1163 1164 1165 1166 1167 1168 1169
	(void)ath10k_pci_hif_map_service_to_pipe(ar,
						 ATH10K_HTC_SVC_ID_RSVD_CTRL,
						 ul_pipe,
						 dl_pipe,
						 &ul_is_polled,
						 &dl_is_polled);
}

M
Michal Kazior 已提交
1170
static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1171
{
M
Michal Kazior 已提交
1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188
	u32 val;

	val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS);
	val &= ~CORE_CTRL_PCIE_REG_31_MASK;

	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS, val);
}

static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
{
	u32 val;

	val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS);
	val |= CORE_CTRL_PCIE_REG_31_MASK;

	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS, val);
}
1189

M
Michal Kazior 已提交
1190 1191
static void ath10k_pci_irq_disable(struct ath10k *ar)
{
1192
	ath10k_ce_disable_interrupts(ar);
1193
	ath10k_pci_disable_and_clear_legacy_irq(ar);
M
Michal Kazior 已提交
1194 1195 1196 1197 1198 1199 1200
	ath10k_pci_irq_msi_fw_mask(ar);
}

static void ath10k_pci_irq_sync(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int i;
1201

1202 1203
	for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
		synchronize_irq(ar_pci->pdev->irq + i);
1204 1205
}

1206
static void ath10k_pci_irq_enable(struct ath10k *ar)
1207
{
1208
	ath10k_ce_enable_interrupts(ar);
1209
	ath10k_pci_enable_legacy_irq(ar);
M
Michal Kazior 已提交
1210
	ath10k_pci_irq_msi_fw_unmask(ar);
1211 1212 1213 1214
}

static int ath10k_pci_hif_start(struct ath10k *ar)
{
1215
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1216

1217
	ath10k_pci_irq_enable(ar);
1218
	ath10k_pci_rx_post(ar);
K
Kalle Valo 已提交
1219

1220 1221 1222
	return 0;
}

1223
static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1224 1225
{
	struct ath10k *ar;
1226 1227 1228 1229
	struct ath10k_ce_pipe *ce_pipe;
	struct ath10k_ce_ring *ce_ring;
	struct sk_buff *skb;
	int i;
1230

1231 1232 1233
	ar = pci_pipe->hif_ce_state;
	ce_pipe = pci_pipe->ce_hdl;
	ce_ring = ce_pipe->dest_ring;
1234

1235
	if (!ce_ring)
1236 1237
		return;

1238 1239
	if (!pci_pipe->buf_sz)
		return;
1240

1241 1242 1243 1244 1245 1246 1247
	for (i = 0; i < ce_ring->nentries; i++) {
		skb = ce_ring->per_transfer_context[i];
		if (!skb)
			continue;

		ce_ring->per_transfer_context[i] = NULL;

1248
		dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1249
				 skb->len + skb_tailroom(skb),
1250
				 DMA_FROM_DEVICE);
1251
		dev_kfree_skb_any(skb);
1252 1253 1254
	}
}

1255
static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1256 1257 1258
{
	struct ath10k *ar;
	struct ath10k_pci *ar_pci;
1259 1260 1261 1262
	struct ath10k_ce_pipe *ce_pipe;
	struct ath10k_ce_ring *ce_ring;
	struct ce_desc *ce_desc;
	struct sk_buff *skb;
1263
	unsigned int id;
1264
	int i;
1265

1266 1267 1268 1269
	ar = pci_pipe->hif_ce_state;
	ar_pci = ath10k_pci_priv(ar);
	ce_pipe = pci_pipe->ce_hdl;
	ce_ring = ce_pipe->src_ring;
1270

1271
	if (!ce_ring)
1272 1273
		return;

1274 1275
	if (!pci_pipe->buf_sz)
		return;
1276

1277 1278 1279 1280 1281 1282 1283
	ce_desc = ce_ring->shadow_base;
	if (WARN_ON(!ce_desc))
		return;

	for (i = 0; i < ce_ring->nentries; i++) {
		skb = ce_ring->per_transfer_context[i];
		if (!skb)
1284 1285
			continue;

1286 1287 1288 1289
		ce_ring->per_transfer_context[i] = NULL;
		id = MS(__le16_to_cpu(ce_desc[i].flags),
			CE_DESC_FLAGS_META_DATA);

1290
		ar_pci->msg_callbacks_current.tx_completion(ar, skb);
1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306
	}
}

/*
 * Cleanup residual buffers for device shutdown:
 *    buffers that were enqueued for receive
 *    buffers that were to be sent
 * Note: Buffers that had completed but which were
 * not yet processed are on a completion queue. They
 * are handled when the completion thread shuts down.
 */
static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int pipe_num;

M
Michal Kazior 已提交
1307
	for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
1308
		struct ath10k_pci_pipe *pipe_info;
1309 1310 1311 1312 1313 1314 1315 1316 1317

		pipe_info = &ar_pci->pipe_info[pipe_num];
		ath10k_pci_rx_pipe_cleanup(pipe_info);
		ath10k_pci_tx_pipe_cleanup(pipe_info);
	}
}

static void ath10k_pci_ce_deinit(struct ath10k *ar)
{
1318
	int i;
1319

1320 1321
	for (i = 0; i < CE_COUNT; i++)
		ath10k_ce_deinit_pipe(ar, i);
1322 1323
}

1324
static void ath10k_pci_flush(struct ath10k *ar)
1325
{
1326
	ath10k_pci_kill_tasklet(ar);
1327 1328
	ath10k_pci_buffer_cleanup(ar);
}
1329 1330 1331

static void ath10k_pci_hif_stop(struct ath10k *ar)
{
1332
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
1333

1334 1335 1336
	/* Most likely the device has HTT Rx ring configured. The only way to
	 * prevent the device from accessing (and possible corrupting) host
	 * memory is to reset the chip now.
1337 1338 1339 1340 1341 1342 1343
	 *
	 * There's also no known way of masking MSI interrupts on the device.
	 * For ranged MSI the CE-related interrupts can be masked. However
	 * regardless how many MSI interrupts are assigned the first one
	 * is always used for firmware indications (crashes) and cannot be
	 * masked. To prevent the device from asserting the interrupt reset it
	 * before proceeding with cleanup.
1344
	 */
1345
	ath10k_pci_warm_reset(ar);
1346 1347

	ath10k_pci_irq_disable(ar);
M
Michal Kazior 已提交
1348
	ath10k_pci_irq_sync(ar);
1349
	ath10k_pci_flush(ar);
1350 1351 1352 1353 1354 1355 1356
}

static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
					   void *req, u32 req_len,
					   void *resp, u32 *resp_len)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1357 1358 1359 1360
	struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
	struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
	struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
	struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
1361 1362 1363 1364 1365 1366
	dma_addr_t req_paddr = 0;
	dma_addr_t resp_paddr = 0;
	struct bmi_xfer xfer = {};
	void *treq, *tresp = NULL;
	int ret = 0;

1367 1368
	might_sleep();

1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399
	if (resp && !resp_len)
		return -EINVAL;

	if (resp && resp_len && *resp_len == 0)
		return -EINVAL;

	treq = kmemdup(req, req_len, GFP_KERNEL);
	if (!treq)
		return -ENOMEM;

	req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
	ret = dma_mapping_error(ar->dev, req_paddr);
	if (ret)
		goto err_dma;

	if (resp && resp_len) {
		tresp = kzalloc(*resp_len, GFP_KERNEL);
		if (!tresp) {
			ret = -ENOMEM;
			goto err_req;
		}

		resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
					    DMA_FROM_DEVICE);
		ret = dma_mapping_error(ar->dev, resp_paddr);
		if (ret)
			goto err_req;

		xfer.wait_for_resp = true;
		xfer.resp_len = 0;

1400
		ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
1401 1402 1403 1404 1405 1406
	}

	ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
	if (ret)
		goto err_resp;

1407 1408
	ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
	if (ret) {
1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441
		u32 unused_buffer;
		unsigned int unused_nbytes;
		unsigned int unused_id;

		ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
					   &unused_nbytes, &unused_id);
	} else {
		/* non-zero means we did not time out */
		ret = 0;
	}

err_resp:
	if (resp) {
		u32 unused_buffer;

		ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
		dma_unmap_single(ar->dev, resp_paddr,
				 *resp_len, DMA_FROM_DEVICE);
	}
err_req:
	dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);

	if (ret == 0 && resp_len) {
		*resp_len = min(*resp_len, xfer.resp_len);
		memcpy(resp, tresp, xfer.resp_len);
	}
err_dma:
	kfree(treq);
	kfree(tresp);

	return ret;
}

1442
static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
1443
{
1444 1445 1446 1447 1448 1449 1450 1451
	struct bmi_xfer *xfer;
	u32 ce_data;
	unsigned int nbytes;
	unsigned int transfer_id;

	if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
					  &nbytes, &transfer_id))
		return;
1452

1453
	xfer->tx_done = true;
1454 1455
}

1456
static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
1457
{
1458
	struct ath10k *ar = ce_state->ar;
1459 1460 1461 1462 1463 1464 1465 1466 1467
	struct bmi_xfer *xfer;
	u32 ce_data;
	unsigned int nbytes;
	unsigned int transfer_id;
	unsigned int flags;

	if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
					  &nbytes, &transfer_id, &flags))
		return;
1468

M
Michal Kazior 已提交
1469 1470 1471
	if (WARN_ON_ONCE(!xfer))
		return;

1472
	if (!xfer->wait_for_resp) {
1473
		ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
1474 1475 1476 1477
		return;
	}

	xfer->resp_len = nbytes;
1478
	xfer->rx_done = true;
1479 1480
}

1481 1482 1483 1484 1485 1486 1487 1488 1489 1490
static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
			       struct ath10k_ce_pipe *rx_pipe,
			       struct bmi_xfer *xfer)
{
	unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;

	while (time_before_eq(jiffies, timeout)) {
		ath10k_pci_bmi_send_done(tx_pipe);
		ath10k_pci_bmi_recv_data(rx_pipe);

1491
		if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp))
1492 1493 1494 1495
			return 0;

		schedule();
	}
1496

1497 1498
	return -ETIMEDOUT;
}
1499 1500 1501 1502 1503 1504 1505

/*
 * Send an interrupt to the device to wake up the Target CPU
 * so it has an opportunity to notice any changed state.
 */
static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
{
1506
	u32 addr, val;
1507

1508 1509 1510 1511
	addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
	val = ath10k_pci_read32(ar, addr);
	val |= CORE_CTRL_CPU_INTR_MASK;
	ath10k_pci_write32(ar, addr, val);
1512

1513
	return 0;
1514 1515
}

M
Michal Kazior 已提交
1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544
static int ath10k_pci_get_num_banks(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	switch (ar_pci->pdev->device) {
	case QCA988X_2_0_DEVICE_ID:
		return 1;
	case QCA6174_2_1_DEVICE_ID:
		switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
		case QCA6174_HW_1_0_CHIP_ID_REV:
		case QCA6174_HW_1_1_CHIP_ID_REV:
			return 3;
		case QCA6174_HW_1_3_CHIP_ID_REV:
			return 2;
		case QCA6174_HW_2_1_CHIP_ID_REV:
		case QCA6174_HW_2_2_CHIP_ID_REV:
			return 6;
		case QCA6174_HW_3_0_CHIP_ID_REV:
		case QCA6174_HW_3_1_CHIP_ID_REV:
		case QCA6174_HW_3_2_CHIP_ID_REV:
			return 9;
		}
		break;
	}

	ath10k_warn(ar, "unknown number of banks, assuming 1\n");
	return 1;
}

1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562
static int ath10k_pci_init_config(struct ath10k *ar)
{
	u32 interconnect_targ_addr;
	u32 pcie_state_targ_addr = 0;
	u32 pipe_cfg_targ_addr = 0;
	u32 svc_to_pipe_map = 0;
	u32 pcie_config_flags = 0;
	u32 ealloc_value;
	u32 ealloc_targ_addr;
	u32 flag2_value;
	u32 flag2_targ_addr;
	int ret = 0;

	/* Download to Target the CE Config and the service-to-CE map */
	interconnect_targ_addr =
		host_interest_item_address(HI_ITEM(hi_interconnect_state));

	/* Supply Target-side CE configuration */
1563 1564
	ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
				     &pcie_state_targ_addr);
1565
	if (ret != 0) {
1566
		ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
1567 1568 1569 1570 1571
		return ret;
	}

	if (pcie_state_targ_addr == 0) {
		ret = -EIO;
1572
		ath10k_err(ar, "Invalid pcie state addr\n");
1573 1574 1575
		return ret;
	}

1576
	ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1577
					  offsetof(struct pcie_state,
1578 1579
						   pipe_cfg_addr)),
				     &pipe_cfg_targ_addr);
1580
	if (ret != 0) {
1581
		ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
1582 1583 1584 1585 1586
		return ret;
	}

	if (pipe_cfg_targ_addr == 0) {
		ret = -EIO;
1587
		ath10k_err(ar, "Invalid pipe cfg addr\n");
1588 1589 1590 1591
		return ret;
	}

	ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
1592 1593
					target_ce_config_wlan,
					sizeof(target_ce_config_wlan));
1594 1595

	if (ret != 0) {
1596
		ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
1597 1598 1599
		return ret;
	}

1600
	ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1601
					  offsetof(struct pcie_state,
1602 1603
						   svc_to_pipe_map)),
				     &svc_to_pipe_map);
1604
	if (ret != 0) {
1605
		ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
1606 1607 1608 1609 1610
		return ret;
	}

	if (svc_to_pipe_map == 0) {
		ret = -EIO;
1611
		ath10k_err(ar, "Invalid svc_to_pipe map\n");
1612 1613 1614 1615
		return ret;
	}

	ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
1616 1617
					target_service_to_ce_map_wlan,
					sizeof(target_service_to_ce_map_wlan));
1618
	if (ret != 0) {
1619
		ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
1620 1621 1622
		return ret;
	}

1623
	ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
1624
					  offsetof(struct pcie_state,
1625 1626
						   config_flags)),
				     &pcie_config_flags);
1627
	if (ret != 0) {
1628
		ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
1629 1630 1631 1632 1633
		return ret;
	}

	pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;

1634 1635 1636 1637
	ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
					   offsetof(struct pcie_state,
						    config_flags)),
				      pcie_config_flags);
1638
	if (ret != 0) {
1639
		ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
1640 1641 1642 1643 1644 1645
		return ret;
	}

	/* configure early allocation */
	ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));

1646
	ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
1647
	if (ret != 0) {
1648
		ath10k_err(ar, "Faile to get early alloc val: %d\n", ret);
1649 1650 1651 1652 1653 1654
		return ret;
	}

	/* first bank is switched to IRAM */
	ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
			 HI_EARLY_ALLOC_MAGIC_MASK);
M
Michal Kazior 已提交
1655 1656
	ealloc_value |= ((ath10k_pci_get_num_banks(ar) <<
			  HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1657 1658
			 HI_EARLY_ALLOC_IRAM_BANKS_MASK);

1659
	ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
1660
	if (ret != 0) {
1661
		ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
1662 1663 1664 1665 1666 1667
		return ret;
	}

	/* Tell Target to proceed with initialization */
	flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));

1668
	ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
1669
	if (ret != 0) {
1670
		ath10k_err(ar, "Failed to get option val: %d\n", ret);
1671 1672 1673 1674 1675
		return ret;
	}

	flag2_value |= HI_OPTION_EARLY_CFG_DONE;

1676
	ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
1677
	if (ret != 0) {
1678
		ath10k_err(ar, "Failed to set option val: %d\n", ret);
1679 1680 1681 1682 1683 1684
		return ret;
	}

	return 0;
}

1685
static int ath10k_pci_alloc_pipes(struct ath10k *ar)
1686
{
1687 1688
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct ath10k_pci_pipe *pipe;
1689 1690 1691
	int i, ret;

	for (i = 0; i < CE_COUNT; i++) {
1692 1693 1694 1695 1696 1697 1698 1699
		pipe = &ar_pci->pipe_info[i];
		pipe->ce_hdl = &ar_pci->ce_states[i];
		pipe->pipe_num = i;
		pipe->hif_ce_state = ar;

		ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i],
					   ath10k_pci_ce_send_done,
					   ath10k_pci_ce_recv_data);
1700
		if (ret) {
1701
			ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
1702 1703 1704
				   i, ret);
			return ret;
		}
1705 1706 1707 1708 1709 1710 1711 1712

		/* Last CE is Diagnostic Window */
		if (i == CE_COUNT - 1) {
			ar_pci->ce_diag = pipe->ce_hdl;
			continue;
		}

		pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
1713 1714 1715 1716 1717
	}

	return 0;
}

1718
static void ath10k_pci_free_pipes(struct ath10k *ar)
1719 1720
{
	int i;
1721

1722 1723 1724
	for (i = 0; i < CE_COUNT; i++)
		ath10k_ce_free_pipe(ar, i);
}
1725

1726
static int ath10k_pci_init_pipes(struct ath10k *ar)
1727
{
1728
	int i, ret;
1729

1730 1731
	for (i = 0; i < CE_COUNT; i++) {
		ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
1732
		if (ret) {
1733
			ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
1734
				   i, ret);
1735
			return ret;
1736 1737 1738 1739 1740 1741
		}
	}

	return 0;
}

1742
static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
1743
{
1744 1745 1746
	return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
	       FW_IND_EVENT_PENDING;
}
1747

1748 1749 1750
static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
{
	u32 val;
1751

1752 1753 1754
	val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
	val &= ~FW_IND_EVENT_PENDING;
	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
1755 1756
}

1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776
/* this function effectively clears target memory controller assert line */
static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
{
	u32 val;

	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
			       val | SOC_RESET_CONTROL_SI0_RST_MASK);
	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);

	msleep(10);

	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
	ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
			       val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
	val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);

	msleep(10);
}

1777
static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
1778 1779 1780
{
	u32 val;

1781
	ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
1782 1783

	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1784 1785 1786 1787 1788 1789 1790 1791
				SOC_RESET_CONTROL_ADDRESS);
	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
			   val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
}

static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
{
	u32 val;
1792 1793 1794

	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
				SOC_RESET_CONTROL_ADDRESS);
1795

1796 1797 1798 1799 1800
	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
			   val | SOC_RESET_CONTROL_CE_RST_MASK);
	msleep(10);
	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
			   val & ~SOC_RESET_CONTROL_CE_RST_MASK);
1801 1802 1803 1804 1805 1806
}

static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
{
	u32 val;

1807
	val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1808 1809 1810 1811 1812
				SOC_LF_TIMER_CONTROL0_ADDRESS);
	ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
			   SOC_LF_TIMER_CONTROL0_ADDRESS,
			   val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
}
1813

1814 1815 1816 1817 1818
static int ath10k_pci_warm_reset(struct ath10k *ar)
{
	int ret;

	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
1819

1820 1821 1822
	spin_lock_bh(&ar->data_lock);
	ar->stats.fw_warm_reset_counter++;
	spin_unlock_bh(&ar->data_lock);
1823

1824
	ath10k_pci_irq_disable(ar);
1825

1826 1827 1828 1829 1830 1831 1832 1833 1834
	/* Make sure the target CPU is not doing anything dangerous, e.g. if it
	 * were to access copy engine while host performs copy engine reset
	 * then it is possible for the device to confuse pci-e controller to
	 * the point of bringing host system to a complete stop (i.e. hang).
	 */
	ath10k_pci_warm_reset_si0(ar);
	ath10k_pci_warm_reset_cpu(ar);
	ath10k_pci_init_pipes(ar);
	ath10k_pci_wait_for_target_init(ar);
1835

1836 1837 1838 1839
	ath10k_pci_warm_reset_clear_lf(ar);
	ath10k_pci_warm_reset_ce(ar);
	ath10k_pci_warm_reset_cpu(ar);
	ath10k_pci_init_pipes(ar);
1840

1841 1842 1843 1844 1845
	ret = ath10k_pci_wait_for_target_init(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
		return ret;
	}
1846

1847
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
1848

1849
	return 0;
1850 1851
}

M
Michal Kazior 已提交
1852
static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
1853 1854 1855 1856
{
	int i, ret;
	u32 val;

M
Michal Kazior 已提交
1857
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920

	/* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
	 * It is thus preferred to use warm reset which is safer but may not be
	 * able to recover the device from all possible fail scenarios.
	 *
	 * Warm reset doesn't always work on first try so attempt it a few
	 * times before giving up.
	 */
	for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
		ret = ath10k_pci_warm_reset(ar);
		if (ret) {
			ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
				    i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
				    ret);
			continue;
		}

		/* FIXME: Sometimes copy engine doesn't recover after warm
		 * reset. In most cases this needs cold reset. In some of these
		 * cases the device is in such a state that a cold reset may
		 * lock up the host.
		 *
		 * Reading any host interest register via copy engine is
		 * sufficient to verify if device is capable of booting
		 * firmware blob.
		 */
		ret = ath10k_pci_init_pipes(ar);
		if (ret) {
			ath10k_warn(ar, "failed to init copy engine: %d\n",
				    ret);
			continue;
		}

		ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
					     &val);
		if (ret) {
			ath10k_warn(ar, "failed to poke copy engine: %d\n",
				    ret);
			continue;
		}

		ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
		return 0;
	}

	if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
		ath10k_warn(ar, "refusing cold reset as requested\n");
		return -EPERM;
	}

	ret = ath10k_pci_cold_reset(ar);
	if (ret) {
		ath10k_warn(ar, "failed to cold reset: %d\n", ret);
		return ret;
	}

	ret = ath10k_pci_wait_for_target_init(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
			    ret);
		return ret;
	}

M
Michal Kazior 已提交
1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");

	return 0;
}

static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
{
	int ret;

	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");

	/* FIXME: QCA6174 requires cold + warm reset to work. */

	ret = ath10k_pci_cold_reset(ar);
	if (ret) {
		ath10k_warn(ar, "failed to cold reset: %d\n", ret);
		return ret;
	}

	ret = ath10k_pci_wait_for_target_init(ar);
	if (ret) {
		ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
				ret);
		return ret;
	}

	ret = ath10k_pci_warm_reset(ar);
	if (ret) {
		ath10k_warn(ar, "failed to warm reset: %d\n", ret);
		return ret;
	}

	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
1954 1955 1956 1957

	return 0;
}

M
Michal Kazior 已提交
1958 1959 1960 1961 1962 1963 1964 1965 1966 1967
static int ath10k_pci_chip_reset(struct ath10k *ar)
{
	if (QCA_REV_988X(ar))
		return ath10k_pci_qca988x_chip_reset(ar);
	else if (QCA_REV_6174(ar))
		return ath10k_pci_qca6174_chip_reset(ar);
	else
		return -ENOTSUPP;
}

1968
static int ath10k_pci_hif_power_up(struct ath10k *ar)
1969 1970 1971
{
	int ret;

1972 1973
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");

1974 1975 1976 1977 1978 1979
	ret = ath10k_pci_wake(ar);
	if (ret) {
		ath10k_err(ar, "failed to wake up target: %d\n", ret);
		return ret;
	}

1980 1981 1982 1983 1984 1985 1986 1987 1988 1989
	/*
	 * Bring the target up cleanly.
	 *
	 * The target may be in an undefined state with an AUX-powered Target
	 * and a Host in WoW mode. If the Host crashes, loses power, or is
	 * restarted (without unloading the driver) then the Target is left
	 * (aux) powered and running. On a subsequent driver load, the Target
	 * is in an unexpected state. We try to catch that here in order to
	 * reset the Target and retry the probe.
	 */
1990
	ret = ath10k_pci_chip_reset(ar);
1991
	if (ret) {
M
Michal Kazior 已提交
1992 1993 1994 1995 1996 1997
		if (ath10k_pci_has_fw_crashed(ar)) {
			ath10k_warn(ar, "firmware crashed during chip reset\n");
			ath10k_pci_fw_crashed_clear(ar);
			ath10k_pci_fw_crashed_dump(ar);
		}

1998
		ath10k_err(ar, "failed to reset chip: %d\n", ret);
1999
		goto err_sleep;
2000
	}
2001

2002
	ret = ath10k_pci_init_pipes(ar);
2003
	if (ret) {
2004
		ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2005
		goto err_sleep;
2006 2007
	}

M
Michal Kazior 已提交
2008 2009
	ret = ath10k_pci_init_config(ar);
	if (ret) {
2010
		ath10k_err(ar, "failed to setup init config: %d\n", ret);
2011
		goto err_ce;
M
Michal Kazior 已提交
2012
	}
2013 2014 2015

	ret = ath10k_pci_wake_target_cpu(ar);
	if (ret) {
2016
		ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2017
		goto err_ce;
2018 2019 2020 2021 2022 2023
	}

	return 0;

err_ce:
	ath10k_pci_ce_deinit(ar);
2024

2025 2026
err_sleep:
	ath10k_pci_sleep(ar);
2027 2028 2029
	return ret;
}

2030 2031
static void ath10k_pci_hif_power_down(struct ath10k *ar)
{
2032
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
K
Kalle Valo 已提交
2033

2034 2035 2036
	/* Currently hif_power_up performs effectively a reset and hif_stop
	 * resets the chip as well so there's no point in resetting here.
	 */
2037 2038

	ath10k_pci_sleep(ar);
2039 2040
}

M
Michal Kazior 已提交
2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
#ifdef CONFIG_PM

#define ATH10K_PCI_PM_CONTROL 0x44

static int ath10k_pci_hif_suspend(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct pci_dev *pdev = ar_pci->pdev;
	u32 val;

	pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);

	if ((val & 0x000000ff) != 0x3) {
		pci_save_state(pdev);
		pci_disable_device(pdev);
		pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
				       (val & 0xffffff00) | 0x03);
	}

	return 0;
}

static int ath10k_pci_hif_resume(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct pci_dev *pdev = ar_pci->pdev;
	u32 val;

	pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);

	if ((val & 0x000000ff) != 0) {
		pci_restore_state(pdev);
		pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
				       val & 0xffffff00);
		/*
		 * Suspend/Resume resets the PCI configuration space,
		 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
		 * to keep PCI Tx retries from interfering with C3 CPU state
		 */
		pci_read_config_dword(pdev, 0x40, &val);

		if ((val & 0x0000ff00) != 0)
			pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
	}

	return 0;
}
#endif

2090
static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
2091
	.tx_sg			= ath10k_pci_hif_tx_sg,
K
Kalle Valo 已提交
2092
	.diag_read		= ath10k_pci_hif_diag_read,
2093
	.diag_write		= ath10k_pci_diag_write_mem,
2094 2095 2096 2097 2098 2099
	.exchange_bmi_msg	= ath10k_pci_hif_exchange_bmi_msg,
	.start			= ath10k_pci_hif_start,
	.stop			= ath10k_pci_hif_stop,
	.map_service_to_pipe	= ath10k_pci_hif_map_service_to_pipe,
	.get_default_pipe	= ath10k_pci_hif_get_default_pipe,
	.send_complete_check	= ath10k_pci_hif_send_complete_check,
M
Michal Kazior 已提交
2100
	.set_callbacks		= ath10k_pci_hif_set_callbacks,
2101
	.get_free_queue_number	= ath10k_pci_hif_get_free_queue_number,
2102 2103
	.power_up		= ath10k_pci_hif_power_up,
	.power_down		= ath10k_pci_hif_power_down,
2104 2105
	.read32			= ath10k_pci_read32,
	.write32		= ath10k_pci_write32,
M
Michal Kazior 已提交
2106 2107 2108 2109
#ifdef CONFIG_PM
	.suspend		= ath10k_pci_hif_suspend,
	.resume			= ath10k_pci_hif_resume,
#endif
2110 2111 2112 2113
};

static void ath10k_pci_ce_tasklet(unsigned long ptr)
{
2114
	struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
2115 2116 2117 2118 2119 2120 2121 2122 2123
	struct ath10k_pci *ar_pci = pipe->ar_pci;

	ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
}

static void ath10k_msi_err_tasklet(unsigned long data)
{
	struct ath10k *ar = (struct ath10k *)data;

2124
	if (!ath10k_pci_has_fw_crashed(ar)) {
2125
		ath10k_warn(ar, "received unsolicited fw crash interrupt\n");
2126 2127 2128
		return;
	}

2129
	ath10k_pci_irq_disable(ar);
2130 2131
	ath10k_pci_fw_crashed_clear(ar);
	ath10k_pci_fw_crashed_dump(ar);
2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143
}

/*
 * Handler for a per-engine interrupt on a PARTICULAR CE.
 * This is used in cases where each CE has a private MSI interrupt.
 */
static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
{
	struct ath10k *ar = arg;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;

D
Dan Carpenter 已提交
2144
	if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
2145 2146
		ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
			    ce_id);
2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181
		return IRQ_HANDLED;
	}

	/*
	 * NOTE: We are able to derive ce_id from irq because we
	 * use a one-to-one mapping for CE's 0..5.
	 * CE's 6 & 7 do not use interrupts at all.
	 *
	 * This mapping must be kept in sync with the mapping
	 * used by firmware.
	 */
	tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
	return IRQ_HANDLED;
}

static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
{
	struct ath10k *ar = arg;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	tasklet_schedule(&ar_pci->msi_fw_err);
	return IRQ_HANDLED;
}

/*
 * Top-level interrupt handler for all PCI interrupts from a Target.
 * When a block of MSI interrupts is allocated, this top-level handler
 * is not used; instead, we directly call the correct sub-handler.
 */
static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
{
	struct ath10k *ar = arg;
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	if (ar_pci->num_msi_intrs == 0) {
2182 2183 2184
		if (!ath10k_pci_irq_pending(ar))
			return IRQ_NONE;

2185
		ath10k_pci_disable_and_clear_legacy_irq(ar);
2186 2187 2188 2189 2190 2191 2192
	}

	tasklet_schedule(&ar_pci->intr_tq);

	return IRQ_HANDLED;
}

2193
static void ath10k_pci_tasklet(unsigned long data)
2194 2195
{
	struct ath10k *ar = (struct ath10k *)data;
2196
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2197

2198
	if (ath10k_pci_has_fw_crashed(ar)) {
2199
		ath10k_pci_irq_disable(ar);
2200
		ath10k_pci_fw_crashed_clear(ar);
2201
		ath10k_pci_fw_crashed_dump(ar);
2202 2203 2204
		return;
	}

2205 2206
	ath10k_ce_per_engine_service_any(ar);

2207 2208 2209
	/* Re-enable legacy irq that was disabled in the irq handler */
	if (ar_pci->num_msi_intrs == 0)
		ath10k_pci_enable_legacy_irq(ar);
2210 2211
}

M
Michal Kazior 已提交
2212
static int ath10k_pci_request_irq_msix(struct ath10k *ar)
2213 2214
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
M
Michal Kazior 已提交
2215
	int ret, i;
2216 2217 2218 2219

	ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
			  ath10k_pci_msi_fw_handler,
			  IRQF_SHARED, "ath10k_pci", ar);
2220
	if (ret) {
2221
		ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n",
2222
			    ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
2223
		return ret;
2224
	}
2225 2226 2227 2228 2229 2230

	for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
		ret = request_irq(ar_pci->pdev->irq + i,
				  ath10k_pci_per_engine_handler,
				  IRQF_SHARED, "ath10k_pci", ar);
		if (ret) {
2231
			ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n",
2232 2233
				    ar_pci->pdev->irq + i, ret);

M
Michal Kazior 已提交
2234 2235
			for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
				free_irq(ar_pci->pdev->irq + i, ar);
2236

M
Michal Kazior 已提交
2237
			free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
2238 2239 2240 2241 2242 2243 2244
			return ret;
		}
	}

	return 0;
}

M
Michal Kazior 已提交
2245
static int ath10k_pci_request_irq_msi(struct ath10k *ar)
2246 2247 2248 2249 2250 2251 2252
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int ret;

	ret = request_irq(ar_pci->pdev->irq,
			  ath10k_pci_interrupt_handler,
			  IRQF_SHARED, "ath10k_pci", ar);
M
Michal Kazior 已提交
2253
	if (ret) {
2254
		ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
M
Michal Kazior 已提交
2255
			    ar_pci->pdev->irq, ret);
2256 2257 2258 2259 2260 2261
		return ret;
	}

	return 0;
}

M
Michal Kazior 已提交
2262
static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
2263 2264 2265 2266 2267 2268 2269
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int ret;

	ret = request_irq(ar_pci->pdev->irq,
			  ath10k_pci_interrupt_handler,
			  IRQF_SHARED, "ath10k_pci", ar);
2270
	if (ret) {
2271
		ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
M
Michal Kazior 已提交
2272
			    ar_pci->pdev->irq, ret);
2273
		return ret;
2274
	}
2275 2276 2277 2278

	return 0;
}

M
Michal Kazior 已提交
2279 2280 2281
static int ath10k_pci_request_irq(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2282

M
Michal Kazior 已提交
2283 2284 2285 2286 2287 2288 2289 2290
	switch (ar_pci->num_msi_intrs) {
	case 0:
		return ath10k_pci_request_irq_legacy(ar);
	case 1:
		return ath10k_pci_request_irq_msi(ar);
	case MSI_NUM_REQUEST:
		return ath10k_pci_request_irq_msix(ar);
	}
2291

2292
	ath10k_warn(ar, "unknown irq configuration upon request\n");
M
Michal Kazior 已提交
2293
	return -EINVAL;
2294 2295
}

M
Michal Kazior 已提交
2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307
static void ath10k_pci_free_irq(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int i;

	/* There's at least one interrupt irregardless whether its legacy INTR
	 * or MSI or MSI-X */
	for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
		free_irq(ar_pci->pdev->irq + i, ar);
}

static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2308 2309 2310 2311
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int i;

M
Michal Kazior 已提交
2312
	tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
2313
	tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
M
Michal Kazior 已提交
2314
		     (unsigned long)ar);
2315 2316 2317

	for (i = 0; i < CE_COUNT; i++) {
		ar_pci->pipe_info[i].ar_pci = ar_pci;
M
Michal Kazior 已提交
2318
		tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
2319 2320
			     (unsigned long)&ar_pci->pipe_info[i]);
	}
M
Michal Kazior 已提交
2321 2322 2323 2324 2325 2326
}

static int ath10k_pci_init_irq(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	int ret;
2327

M
Michal Kazior 已提交
2328
	ath10k_pci_init_irq_tasklets(ar);
2329

2330
	if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
2331 2332
		ath10k_info(ar, "limiting irq mode to: %d\n",
			    ath10k_pci_irq_mode);
2333

M
Michal Kazior 已提交
2334
	/* Try MSI-X */
M
Michal Kazior 已提交
2335
	if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) {
2336
		ar_pci->num_msi_intrs = MSI_NUM_REQUEST;
2337
		ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
2338
					   ar_pci->num_msi_intrs);
2339
		if (ret > 0)
2340
			return 0;
2341

2342
		/* fall-through */
2343 2344
	}

M
Michal Kazior 已提交
2345
	/* Try MSI */
2346 2347 2348
	if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
		ar_pci->num_msi_intrs = 1;
		ret = pci_enable_msi(ar_pci->pdev);
2349
		if (ret == 0)
2350
			return 0;
2351

2352
		/* fall-through */
2353 2354
	}

M
Michal Kazior 已提交
2355 2356 2357 2358 2359 2360 2361 2362 2363
	/* Try legacy irq
	 *
	 * A potential race occurs here: The CORE_BASE write
	 * depends on target correctly decoding AXI address but
	 * host won't know when target writes BAR to CORE_CTRL.
	 * This write might get lost if target has NOT written BAR.
	 * For now, fix the race by repeating the write in below
	 * synchronization checking. */
	ar_pci->num_msi_intrs = 0;
2364

M
Michal Kazior 已提交
2365 2366 2367 2368
	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
			   PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);

	return 0;
2369 2370
}

2371
static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
2372
{
M
Michal Kazior 已提交
2373 2374
	ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
			   0);
2375 2376
}

M
Michal Kazior 已提交
2377
static int ath10k_pci_deinit_irq(struct ath10k *ar)
2378 2379 2380
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

M
Michal Kazior 已提交
2381 2382
	switch (ar_pci->num_msi_intrs) {
	case 0:
2383 2384
		ath10k_pci_deinit_irq_legacy(ar);
		return 0;
M
Michal Kazior 已提交
2385 2386 2387
	case 1:
		/* fall-through */
	case MSI_NUM_REQUEST:
2388
		pci_disable_msi(ar_pci->pdev);
M
Michal Kazior 已提交
2389
		return 0;
2390 2391
	default:
		pci_disable_msi(ar_pci->pdev);
M
Michal Kazior 已提交
2392 2393
	}

2394
	ath10k_warn(ar, "unknown irq configuration upon deinit\n");
M
Michal Kazior 已提交
2395
	return -EINVAL;
2396 2397
}

2398
static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
2399 2400
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2401 2402
	unsigned long timeout;
	u32 val;
2403

2404
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
2405

2406 2407 2408 2409 2410
	timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);

	do {
		val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);

2411 2412
		ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
			   val);
K
Kalle Valo 已提交
2413

2414 2415 2416 2417
		/* target should never return this */
		if (val == 0xffffffff)
			continue;

2418 2419 2420 2421
		/* the device has crashed so don't bother trying anymore */
		if (val & FW_IND_EVENT_PENDING)
			break;

2422 2423 2424
		if (val & FW_IND_INITIALIZED)
			break;

2425 2426
		if (ar_pci->num_msi_intrs == 0)
			/* Fix potential race by repeating CORE_BASE writes */
2427
			ath10k_pci_enable_legacy_irq(ar);
2428

2429
		mdelay(10);
2430
	} while (time_before(jiffies, timeout));
2431

2432
	ath10k_pci_disable_and_clear_legacy_irq(ar);
M
Michal Kazior 已提交
2433
	ath10k_pci_irq_msi_fw_mask(ar);
2434

2435
	if (val == 0xffffffff) {
2436
		ath10k_err(ar, "failed to read device register, device is gone\n");
2437
		return -EIO;
2438 2439
	}

2440
	if (val & FW_IND_EVENT_PENDING) {
2441
		ath10k_warn(ar, "device has crashed during init\n");
2442
		return -ECOMM;
2443 2444
	}

2445
	if (!(val & FW_IND_INITIALIZED)) {
2446
		ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
2447
			   val);
2448
		return -ETIMEDOUT;
2449 2450
	}

2451
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
2452
	return 0;
2453 2454
}

2455
static int ath10k_pci_cold_reset(struct ath10k *ar)
2456
{
2457
	int i;
2458 2459
	u32 val;

2460
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
2461

B
Ben Greear 已提交
2462 2463 2464 2465 2466 2467
	spin_lock_bh(&ar->data_lock);

	ar->stats.fw_cold_reset_counter++;

	spin_unlock_bh(&ar->data_lock);

2468
	/* Put Target, including PCIe, into RESET. */
2469
	val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
2470
	val |= 1;
2471
	ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2472 2473

	for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2474
		if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2475 2476 2477 2478 2479 2480 2481
					  RTC_STATE_COLD_RESET_MASK)
			break;
		msleep(1);
	}

	/* Pull Target, including PCIe, out of RESET. */
	val &= ~1;
2482
	ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
2483 2484

	for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
2485
		if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
2486 2487 2488 2489 2490
					    RTC_STATE_COLD_RESET_MASK))
			break;
		msleep(1);
	}

2491
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
K
Kalle Valo 已提交
2492

2493
	return 0;
2494 2495
}

2496
static int ath10k_pci_claim(struct ath10k *ar)
2497
{
2498 2499 2500 2501
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct pci_dev *pdev = ar_pci->pdev;
	u32 lcr_val;
	int ret;
2502 2503 2504 2505 2506

	pci_set_drvdata(pdev, ar);

	ret = pci_enable_device(pdev);
	if (ret) {
2507
		ath10k_err(ar, "failed to enable pci device: %d\n", ret);
2508
		return ret;
2509 2510 2511 2512
	}

	ret = pci_request_region(pdev, BAR_NUM, "ath");
	if (ret) {
2513
		ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
2514
			   ret);
2515 2516 2517
		goto err_device;
	}

2518
	/* Target expects 32 bit DMA. Enforce it. */
2519 2520
	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
2521
		ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
2522 2523 2524 2525 2526
		goto err_region;
	}

	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
2527
		ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
2528
			   ret);
2529 2530 2531 2532 2533
		goto err_region;
	}

	pci_set_master(pdev);

2534
	/* Workaround: Disable ASPM */
2535 2536 2537 2538
	pci_read_config_dword(pdev, 0x80, &lcr_val);
	pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));

	/* Arrange for access to Target SoC registers. */
2539 2540
	ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
	if (!ar_pci->mem) {
2541
		ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
2542 2543 2544 2545
		ret = -EIO;
		goto err_master;
	}

2546
	ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571
	return 0;

err_master:
	pci_clear_master(pdev);

err_region:
	pci_release_region(pdev, BAR_NUM);

err_device:
	pci_disable_device(pdev);

	return ret;
}

static void ath10k_pci_release(struct ath10k *ar)
{
	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
	struct pci_dev *pdev = ar_pci->pdev;

	pci_iounmap(pdev, ar_pci->mem);
	pci_release_region(pdev, BAR_NUM);
	pci_clear_master(pdev);
	pci_disable_device(pdev);
}

2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588
static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
{
	const struct ath10k_pci_supp_chip *supp_chip;
	int i;
	u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);

	for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
		supp_chip = &ath10k_pci_supp_chips[i];

		if (supp_chip->dev_id == dev_id &&
		    supp_chip->rev_id == rev_id)
			return true;
	}

	return false;
}

2589 2590 2591 2592 2593 2594
static int ath10k_pci_probe(struct pci_dev *pdev,
			    const struct pci_device_id *pci_dev)
{
	int ret = 0;
	struct ath10k *ar;
	struct ath10k_pci *ar_pci;
M
Michal Kazior 已提交
2595
	enum ath10k_hw_rev hw_rev;
2596 2597
	u32 chip_id;

M
Michal Kazior 已提交
2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611
	switch (pci_dev->device) {
	case QCA988X_2_0_DEVICE_ID:
		hw_rev = ATH10K_HW_QCA988X;
		break;
	case QCA6174_2_1_DEVICE_ID:
		hw_rev = ATH10K_HW_QCA6174;
		break;
	default:
		WARN_ON(1);
		return -ENOTSUPP;
	}

	ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
				hw_rev, &ath10k_pci_hif_ops);
2612
	if (!ar) {
2613
		dev_err(&pdev->dev, "failed to allocate core\n");
2614 2615 2616
		return -ENOMEM;
	}

2617 2618
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci probe\n");

2619 2620 2621 2622
	ar_pci = ath10k_pci_priv(ar);
	ar_pci->pdev = pdev;
	ar_pci->dev = &pdev->dev;
	ar_pci->ar = ar;
2623 2624

	spin_lock_init(&ar_pci->ce_lock);
2625 2626
	setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
		    (unsigned long)ar);
2627

2628
	ret = ath10k_pci_claim(ar);
2629
	if (ret) {
2630
		ath10k_err(ar, "failed to claim device: %d\n", ret);
2631
		goto err_core_destroy;
2632 2633
	}

2634
	ret = ath10k_pci_wake(ar);
2635
	if (ret) {
2636
		ath10k_err(ar, "failed to wake up: %d\n", ret);
2637
		goto err_release;
2638 2639
	}

2640
	ret = ath10k_pci_alloc_pipes(ar);
2641
	if (ret) {
2642 2643
		ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
			   ret);
2644
		goto err_sleep;
2645 2646
	}

2647
	ath10k_pci_ce_deinit(ar);
M
Michal Kazior 已提交
2648
	ath10k_pci_irq_disable(ar);
2649

2650
	ret = ath10k_pci_init_irq(ar);
2651
	if (ret) {
2652
		ath10k_err(ar, "failed to init irqs: %d\n", ret);
2653
		goto err_free_pipes;
2654 2655
	}

2656
	ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n",
2657 2658 2659
		    ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs,
		    ath10k_pci_irq_mode, ath10k_pci_reset_mode);

2660 2661
	ret = ath10k_pci_request_irq(ar);
	if (ret) {
2662
		ath10k_warn(ar, "failed to request irqs: %d\n", ret);
2663 2664 2665
		goto err_deinit_irq;
	}

2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683
	ret = ath10k_pci_chip_reset(ar);
	if (ret) {
		ath10k_err(ar, "failed to reset chip: %d\n", ret);
		goto err_free_irq;
	}

	chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
	if (chip_id == 0xffffffff) {
		ath10k_err(ar, "failed to get chip id\n");
		goto err_free_irq;
	}

	if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
		ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
			   pdev->device, chip_id);
		goto err_sleep;
	}

2684 2685
	ath10k_pci_sleep(ar);

2686
	ret = ath10k_core_register(ar, chip_id);
2687
	if (ret) {
2688
		ath10k_err(ar, "failed to register driver core: %d\n", ret);
2689
		goto err_free_irq;
2690 2691 2692 2693
	}

	return 0;

2694 2695
err_free_irq:
	ath10k_pci_free_irq(ar);
2696
	ath10k_pci_kill_tasklet(ar);
2697

2698 2699 2700
err_deinit_irq:
	ath10k_pci_deinit_irq(ar);

2701 2702
err_free_pipes:
	ath10k_pci_free_pipes(ar);
2703

2704 2705
err_sleep:
	ath10k_pci_sleep(ar);
2706 2707 2708 2709

err_release:
	ath10k_pci_release(ar);

M
Michal Kazior 已提交
2710
err_core_destroy:
2711 2712 2713 2714 2715 2716 2717 2718 2719 2720
	ath10k_core_destroy(ar);

	return ret;
}

static void ath10k_pci_remove(struct pci_dev *pdev)
{
	struct ath10k *ar = pci_get_drvdata(pdev);
	struct ath10k_pci *ar_pci;

2721
	ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
2722 2723 2724 2725 2726 2727 2728 2729 2730 2731

	if (!ar)
		return;

	ar_pci = ath10k_pci_priv(ar);

	if (!ar_pci)
		return;

	ath10k_core_unregister(ar);
2732
	ath10k_pci_free_irq(ar);
2733
	ath10k_pci_kill_tasklet(ar);
2734 2735
	ath10k_pci_deinit_irq(ar);
	ath10k_pci_ce_deinit(ar);
2736
	ath10k_pci_free_pipes(ar);
2737
	ath10k_pci_release(ar);
2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755
	ath10k_core_destroy(ar);
}

MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);

static struct pci_driver ath10k_pci_driver = {
	.name = "ath10k_pci",
	.id_table = ath10k_pci_id_table,
	.probe = ath10k_pci_probe,
	.remove = ath10k_pci_remove,
};

static int __init ath10k_pci_init(void)
{
	int ret;

	ret = pci_register_driver(&ath10k_pci_driver);
	if (ret)
2756 2757
		printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
		       ret);
2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772

	return ret;
}
module_init(ath10k_pci_init);

static void __exit ath10k_pci_exit(void)
{
	pci_unregister_driver(&ath10k_pci_driver);
}

module_exit(ath10k_pci_exit);

MODULE_AUTHOR("Qualcomm Atheros");
MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
MODULE_LICENSE("Dual BSD/GPL");
2773 2774 2775
MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
2776
MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);