- warning: implicit declaration of function ‘serial_initialize’
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.
Signed-off-by: NAndre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: NAndy Fleming <afleming@freescale.com>
Acked-by: NBen Warren <biggerbadderben@gmail.com>
--

 drivers/net/tsec.c |    6 ++++++
 drivers/net/tsec.h |    3 +++
 2 files changed, 9 insertions(+), 0 deletions(-)

start.S:183:1: warning: "ICMR" redefined
In file included from start.S:33:
include/asm/arch/pxa-regs.h:935:1: warning: this is the location of the previous definition
start.S:187:1: warning: "RCSR" redefined
...
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NWolfgang Denk <wd@denx.de>

Make the flags use -Os like all other boards
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch fixes a problem with the month being read and written
incorrectly (offset by one). This only gets visible by also using
the Linux driver (rtc-m41t80).

Tested on AMCC Canyonlands.
Signed-off-by: NStefan Roese <sr@denx.de>

Onenand needs a version of memcpy() which performs 16 bit accesses
only; make sure the name does not conflict with the standard
function.
Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Some 86xx chips use CCB as the base clock for the I2C, and others used CCB/2.
There is no pattern that can be used to determine which chips use which
frequency, so the only way to determine is to look up the actual SOC
designation and use the right value for that SOC.
Signed-off-by: NTimur Tabi <timur@freescale.com>

The ethernet hang is caused by receiving buffer in DRAM is not
yet ready due to access cycles require longer time in DRAM.
Relocate DMA buffer descriptors from DRAM to internal SRAM.
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NLuigi Comio Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: NKurt Mahan <kmahan@freescale.com>
Signed-off-by: NTsiChung Liew <Tsi-Chung.Liew@freescale.com>

Fix warnings

nv_nand.c: In function 'saveenv':
env_nand.c:200: warning: passing argument 3 of 'nand_write' from incompatible pointer type
env_nand.c: In function 'env_relocate_spec':
env_nand.c:275: warning: passing argument 3 of 'nand_read' from incompatible pointer type

if compiled for davinci_schmoogie_config.
Signed-off-by: NDirk Behme <dirk.behme@gmail.com>
Ack by: Sergey Kubushyn <ksi@koi8.net>

MPC8610HPCD board adds -O2 gcc option to PLATFORM_CPPFLAGS
causing overriding default -Os option. New gcc (ver. 4.2.2)
produces warnings while compiling net/net.c file with -O2
option. The patch is an attempt to fix this.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>

Signed-off-by: NSascha Laue <sascha.laue@liebherr.com>
Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NSascha Laue <sascha.laue@liebherr.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

This problem shows up with parallel builds only; it results in
somewhat cryptic error messages like

	$ JOBS=-j6 MAKEALL netstar
	Configuring for netstar board...
	arm-linux-ld: cannot find -lgeneric
	make[1]: *** [eeprom.srec] Error 1

A few boards (like netstar and voiceblue) need some libraries for
building; however, the board Makefile does not contain any such
dependencies which may cause problems with parallel builds. Adding
such dependencies is difficult as we would also have to provide build
rules, which already exist in the respective library Makefiles.

To solve this, we make sure that all libraries get built before the
board code.
Signed-off-by: NWolfgang Denk <wd@denx.de>

This patch changes the Canyonlands/Glacier fixed DDR2 controller setup
used for NAND booting to match the values needed for the new 512MB
DIMM modules shipped with the productions boards:

Crucial: CT6464AC667.8FB
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes a problem with DIMMs that have 8 banks. Now the
MCIF0_MBxCF register will be setup correctly for this setup too.

This was noticed with the 512MB DIMM on Canyonlands/Glacier.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Newer gcc's might be configured to enable autovectorization by default.
If we happen to build with one of those compilers we will get SPE
instructions in random code.

-mno-spe disables the compiler for automatically generating SPE
instructions without our knowledge.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

All the 85xx and 86xx UM describe the register as timing_cfg_3
not as ext_refrec.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Rename init_addr and init_ext_addr to match the docs between
85xx and 86xx.  Both now use 'init_addr' and 'init_ext_addr'.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* adjust __spin_table alignment to match ePAPR v0.94 spec
* loop over all cpus when determing who is up.  This fixes an issue if
  the "boot cpu" isn't core0.  The "boot cpu" will already be in the
  cpu_up_mask so there is no harm
* Added some protection in the code to ensure proper behavior.  These
  changes are explicitly needed but don't hurt:
  - Added eieio to ensure the "hot word" of the table is written after
    all other table updates have occurred.
  - Added isync to ensure we don't prefetch loading of table entries
    until we a released

These issues we raised by Dave Liu.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

LWMON5 DSPIC POST uses the watch-dog scratch register. So, make
the CFG_DSPIC_TEST_ADDR definition more readable.
Signed-off-by: NYuri Tikhonov <yur@emcraft.com>

Signed-off-by: NStefan Roese <sr@denx.de>

Some boards (e.g. lwmon5) need rather a frequent watch-dog
kicking. Since the time it takes for the flush_cache() function
to complete its job depends on the size of data being flushed, one
may encounter watch-dog resets on such boards when, for example,
download big files over ethernet.
Signed-off-by: NYuri Tikhonov <yur@emcraft.com>