85xx: Additional fixes and cleanup of MP code

* adjust __spin_table alignment to match ePAPR v0.94 spec
* loop over all cpus when determing who is up.  This fixes an issue if
  the "boot cpu" isn't core0.  The "boot cpu" will already be in the
  cpu_up_mask so there is no harm
* Added some protection in the code to ensure proper behavior.  These
  changes are explicitly needed but don't hurt:
  - Added eieio to ensure the "hot word" of the table is written after
    all other table updates have occurred.
  - Added isync to ensure we don't prefetch loading of table entries
    until we a released

These issues we raised by Dave Liu.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

cpu/mpc85xx/mp.c

@@ -103,6 +103,10 @@ int cpu_release(int nr, int argc, char *argv[])
 	}
 
 	table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
+
+	/* ensure all table updates complete before final address write */
+	eieio();
+
 	table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
 
 	return 0;
@@ -153,7 +157,7 @@ static void pq3_mp_up(unsigned long bootpg)
 	/* wait for everyone */
 	while (timeout) {
 		int i;
-		for (i = 1; i < CONFIG_NR_CPUS; i++) {
+		for (i = 0; i < CONFIG_NR_CPUS; i++) {
 			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
 				cpu_up_mask |= (1 << i);
 		};

cpu/mpc85xx/release.S

@@ -114,6 +114,7 @@ __secondary_start_page:
 	lwz	r4,ENTRY_ADDR_LOWER(r10)
 	andi.	r11,r4,1
 	bne	2b
+	isync
 
 	/* get the upper bits of the addr */
 	lwz	r11,ENTRY_ADDR_UPPER(r10)
@@ -169,7 +170,7 @@ __secondary_start_page:
 	mtspr	SPRN_SRR1,r13
 	rfi
 
-	.align 3
+	.align L1_CACHE_SHIFT
 	.globl __spin_table
 __spin_table:
 	.space CONFIG_NR_CPUS*ENTRY_SIZE