Freescale (NXP) boards have lots of defconfig files per board.
I used "imply PANIC_HANG" for them.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

And use 'imply' liberally.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>

Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC
phase using esbc_validate command.

Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment

Add header address for PPA to be validated during ESBC phase for
LS1088A platform based on LAyerscape Chasis 3.

Moves sec_init prior to ppa_init as for validation of PPA sec must
be initialised before the PPA is initialised.
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: NVinitha Pillai-B57223 <vinitha.pillai@nxp.com>
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This is suplement for patch which handle below errata:
A-009007, A-009008, A-008997, A-009798
Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NAmrita Kumari <amrita.kumari@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Use Kconfig to select QE-HDLC and USB pin-mux.
Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Rx Compliance tests may fail intermittently at high jitter
frequencies using default register values.

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.
Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values.

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NSuresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter
settings

Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NSuresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: NYork Sun <york.sun@nxp.com>

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NSuresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: NYork Sun <york.sun@nxp.com>

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch adds support for RGMII protocol

NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAmrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
platform that supports the LS1088A family SoCs. This patch add basic
support of the platform.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRaghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com>
[YS: Disabled NAND in board header file]
Reviewed-by: NYork Sun <york.sun@nxp.com>

WIP: disable NAND for LS1088ARDB

LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRaghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

LS2080 family has CCN-504 cache coherent interconnet. Other SoCs
in LSCH3 family may have differnt interconnect.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Adds header address for PPA to be validated during ESBC phase for
ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It
must be initialized before the PPA.
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
[YS: revised commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Tested-by: NVinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: NYork Sun <york.sun@nxp.com>

With SPL_LDSCRIPT moved to Kconfig (and this being a 'string' config
node), all the lingering definitions in header files will cause
warnings/errors due to the redefinition of the configuration item.

As we don't want to pollute the defconfig files (and values should
usually be identical for entire architectures), the defaults are moved
into Kconfig.  Kconfig will always pick the first default that
matches, so please keep these values at the end of each file (to allow
any board-specific Kconfig, which will be included earlier) to
override with an unconditional default setting.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This converts the following to Kconfig:
   CONFIG_CMD_PCI
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

It is derived from Platform clock instead of Platform PLL frequency.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This converts the following to Kconfig:
   CONFIG_SCSI
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Loading PPA in SPL puts the rest of U-Boot (including RAM version
loaded later) in EL2 with MMU and cache enabled. Once PPA is loaded,
PSCI is available.
Signed-off-by: NYork Sun <york.sun@nxp.com>

This patch adjusts memory map for images on LS2080ARDB and
LS2080AQDS NOR flash as below

Image				Flash Offset
RCW+PBI				0x00000000
Boot firmware (U-Boot)		0x00100000
Boot firmware Environment	0x00300000
PPA firmware			0x00400000
PHY firmware			0x00980000
DPAA2 MC			0x00A00000
DPAA2 DPL			0x00D00000
DPAA2 DPC			0x00E00000
Kernel.itb			0x01000000
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch is to adjust the memory mapping for FLash/SD card on
LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN
firmware load address, QE firmware load address, U-Boot start address
on serial flash and environment address.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is not enabled.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: NSuresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Add Kconfig option to support loading PPA header from eMMC/SD and
NAND Flash.
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Tested-by: NVinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Number of TZASC instances may vary across NXP SoCs.
So put TZASC configuration under instance specific defines.
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Define bootscript and its header addresses for QSPI target
Also add PPA header address in Kconfig
Signed-off-by: NVinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Define bootscript and its header addresses for QSPI target. Also
define PPA header address to enable PPA validation.
Signed-off-by: NVinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>

The header address of PPA defined in Kconfig.
Signed-off-by: NVinitha Pillai <vinitha.pillai@nxp.com>
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Enable PPA on LS2080A, LS2088A boards:
-LS2080ARDB, LS2080AQDS
-LS2088ARDB, LS2088AQDS
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Signed-off-by: NAbhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This i2c errata only applies to LS2080A and its variants, namely
LS2080A, LS2085A and LS2088A.
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Use Kconfig option instead of config macro in header file.
Signed-off-by: NYork Sun <york.sun@nxp.com>

Use Kconfig option instead of config macro in header file.
Clean up existing usage.
Signed-off-by: NYork Sun <york.sun@nxp.com>

Use gd->arch.resv_ram to track reserved memory allocation.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This moves all of the current ARM errata from various header files and in to
Kconfig.  This allows for a minor amount of cleanup as we had some instances
where both a general common header file was enabling errata as well as the
board config.  We now just select these once at the higher level in Kconfig
Signed-off-by: NTom Rini <trini@konsulko.com>

Erratum A-008336 applies to LS1046A per latest SoC document.
Signed-off-by: NYork Sun <york.sun@nxp.com>
CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>