- 14 1月, 2011 1 次提交
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由 Kumar Gala 提交于
We set the L1 dache register with a bogus register value. Need to be using 'r3' instead of 'r0'. Reported-by: NJohn Traill <john.traill@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 15 11月, 2010 1 次提交
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由 Joakim Tjernlund 提交于
The fixup procedure just stored a constant value in the fixup table rather than just adjusting the table. Although that doesn't seem to do any harm, it prevents relocation more that once. Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
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- 11 11月, 2010 1 次提交
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由 Haiying Wang 提交于
Use CONFIG_SYS_MONITOR_BASE instead of CONFIG_SYS_TEXT_BASE in early init code so we can share the same code with NAND or NOR boot and not have additional ifdefs in here. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 27 10月, 2010 1 次提交
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由 Wolfgang Denk 提交于
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: NWolfgang Denk <wd@denx.de> Acked-by: NKumar Gala <galak@kernel.crashing.org>
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- 19 10月, 2010 2 次提交
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由 Joakim Tjernlund 提交于
The fixup routine must not fixup NULL pointers. Problem can be seen by char *testfun(void) __attribute__((weak)); char *(*myfun)(void) = testfun; Then add printf("myfun:%p, &myfun:%p\n", myfun, &myfun); before relocation and after relocation. myfun should be NULL in both cases but it is not. Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
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由 Wolfgang Denk 提交于
The change is currently needed to be able to remove the board configuration scripting from the top level Makefile and replace it by a simple, table driven script. Moving this configuration setting into the "CONFIG_*" name space is also desirable because it is needed if we ever should move forward to a Kconfig driven configuration system. Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 13 10月, 2010 1 次提交
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由 Peter Tyser 提交于
No boards utilize the warm reset entry point, so remove it. Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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- 27 7月, 2010 1 次提交
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由 york 提交于
If 36-bit physical address is used, move the INIT_RAM_ADDR to higher address. This frees the low 4GB address space for better use. Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 22 4月, 2010 1 次提交
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由 Stefan Roese 提交于
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NWolfgang Denk <wd@denx.de> Acked-by: NDetlev Zundel <dzu@denx.de> Acked-by: NKim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
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- 13 4月, 2010 1 次提交
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由 Peter Tyser 提交于
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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- 07 4月, 2010 2 次提交
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由 Sandeep Gopalpet 提交于
The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize the performance of mbar/eieio instructions. Signed-off-by: NSandeep Gopalpet <sandeep.kumar@freescale.com>
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由 Kumar Gala 提交于
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 30 3月, 2010 1 次提交
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由 Kumar Gala 提交于
Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 27 1月, 2010 2 次提交
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由 Joakim Tjernlund 提交于
r14 is not supposed to be clobbered by functions. Switch to r12 and call GET_GOT when needed. This will allow u-boot to loose the -ffixed-r14 gcc option. Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
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由 Joakim Tjernlund 提交于
Using the GOT in IRQ handlers requires r14 to be -ffixed-r14. Avoid this by relocatate transfer_to_handler too. This will allow to free up r14 later on. Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
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- 06 1月, 2010 1 次提交
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由 Kumar Gala 提交于
The e500mc core supports the ability to stash into the L1 or L2 cache, however we need to uniquely identify the caches with an id. We use the following equation to set the various stash-ids: 32 + coreID*2 + 0(L1) or 1(L2) The 0 (for L1) or 1 (for L2) matches the CT field used be various cache control instructions. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 08 10月, 2009 1 次提交
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由 Joakim Tjernlund 提交于
NULL is an absolute value and should not be relocated. After this correction code like: void weak_fun(void) __attribute__((weak)); printf("weak_fun:%p\n", weak_fun); will still print null after relocation. Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
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- 03 10月, 2009 5 次提交
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由 Mingkai Hu 提交于
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Factor out the code we use to actually write a tlb entry. set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Scott Wood 提交于
Its reset value is random, and we sometimes read uninitialized TLB arrays. Make sure that we don't retain MAS8 from reading such an entry if the VF bit in MAS8 is set, attempts to use the mapping will trap. Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Scott Wood 提交于
We cannot handle any exceptions while running in AS1, as the exceptions will transition back to AS0 without a valid mapping. Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Kumar Gala 提交于
In future Book-E implementations IVORs will most likely go away and be replaced with fixed offsets. The IVPR will continue to exist to allow for relocation of the interrupt vectors. This code adds support to setup the IVORs as their fixed offset values per the ISA 2.06 spec when we transition from u-boot to another OS either via 'bootm' or a cpu release. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 16 9月, 2009 4 次提交
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由 Mingkai Hu 提交于
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Factor out the code we use to actually write a tlb entry. set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Scott Wood 提交于
Its reset value is random, and we sometimes read uninitialized TLB arrays. Make sure that we don't retain MAS8 from reading such an entry if the VF bit in MAS8 is set, attempts to use the mapping will trap. Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Scott Wood 提交于
We cannot handle any exceptions while running in AS1, as the exceptions will transition back to AS0 without a valid mapping. Signed-off-by: NScott Wood <scottwood@freescale.com>
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- 08 9月, 2009 1 次提交
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由 Kumar Gala 提交于
In future Book-E implementations IVORs will most likely go away and be replaced with fixed offsets. The IVPR will continue to exist to allow for relocation of the interrupt vectors. This code adds support to setup the IVORs as their fixed offset values per the ISA 2.06 spec when we transition from u-boot to another OS either via 'bootm' or a cpu release. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 31 3月, 2009 2 次提交
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由 Haiying Wang 提交于
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then invalidate it after LBCR bit 13 is set. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
* Enable backside L2 * e500mc no longer has timebase enable in HID (moved to CCSR register) Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 20 12月, 2008 1 次提交
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由 Dave Liu 提交于
If one custom board is using the 8MB flash, it is set as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. The current start.S code will be broken at switch_as. It is because the TLB1[15] is set as 16MB page size, EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. For the 8MB flash case, the EPN = 0xefxxxxxx, RPN = 0xffxxxxxx. Assume the virt address of switch_as is 0xef7ff18c, the real address of the instruction at switch_as should be 0xff7ff18c. the 0xff7ff18c is out of the range of the default 8MB boot LAW window 0xff800000 - 0xffffffff. So when we switch to AS1 address space at switch_as, the core can't fetch the instruction at switch_as any more. It will cause broken issue. Signed-off-by: NDave Liu <daveliu@freescale.com>
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- 07 12月, 2008 1 次提交
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由 Peter Tyser 提交于
Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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- 25 10月, 2008 2 次提交
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由 Kumar Gala 提交于
Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle e500mc's 64-byte cacheline properly when it gets added. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 19 10月, 2008 2 次提交
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由 Kumar Gala 提交于
Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 15 7月, 2008 1 次提交
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由 Andrew Klossner 提交于
With a page size of BOOKE_PAGESZ_16M, both the real and effective addresses must be multiples of 16MB. The hardware silently truncates them so the code happens to work. This patch clarifies the situation by establishing addresses that the hardware doesn't need to truncate. Signed-off-by: NAndrew Klossner <andrew@cesa.opbu.xerox.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 21 5月, 2008 1 次提交
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由 Wolfgang Denk 提交于
This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 28 2月, 2008 2 次提交
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由 Kumar Gala 提交于
There is no reason to icbi when invalidating the temporary stack in the d-cache. Its impossible on e500 to have the i-cache contain any addresses in the temp stack and it can be problematic in generating transactions on the bus to non-valid addresses. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Andy Fleming 提交于
Commit 0db37dc2... (and some others) changed the INIT_RAM TLB mappings to be unguarded. This collided with an existing "bug" where the mappings for the INIT_RAM were being kept around. This meant that speculative loads to those addresses were succeeding in the TLB, and going out to the bus, where they were causing an exception (there's nothing at that address). The Flash code was coincidentally causing such a speculative load. Rather than go back to mapping the INIT RAM as guarded, we fix it so that the entries for the INIT_RAM are invalidated. Thus the speculative loads will fail in the TLB, and have no effect. Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 15 2月, 2008 1 次提交
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由 Rafal Jaworowski 提交于
Signed-off-by: NRafal Jaworowski <raj@semihalf.com>
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