powerpc/85xx: Fix bug in dcache_disable

We set the L1 dache register with a bogus register value.  Need to be
using 'r3' instead of 'r0'.
Reported-by: NJohn Traill <john.traill@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

arch/powerpc/cpu/mpc85xx/start.S

 /*
- * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
  * Copyright (C) 2003  Motorola,Inc.
  *
  * See file CREDITS for list of people who contributed to this
@@ -753,7 +753,7 @@ dcache_disable:
 	lis	r4,0
 	ori	r4,r4,L1CSR0_DCE
 	andc	r3,r3,r4
-	mtspr	L1CSR0,r0
+	mtspr	L1CSR0,r3
 	isync
 	blr