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  1. 18 11月, 2011 3 次提交
  3. 14 6月, 2011 1 次提交
    • P
      serial: sh-sci: Abstract register maps. · 61a6976b
      由 Paul Mundt 提交于 
      This takes a bit of a sledgehammer to the horribly CPU subtype
ifdef-ridden header and abstracts all of the different register layouts
in to distinct types which in turn can be overriden on a per-port basis,
or permitted to default to the map matching the port type at probe time.

In the process this ultimately fixes up inumerable bugs with mismatches
on various CPU types (particularly the legacy ones that were obviously
broken years ago and no one noticed) and provides a more tightly coupled
and consolidated platform for extending and implementing generic
features.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      61a6976b
  5. 02 10月, 2010 1 次提交
  7. 01 10月, 2010 1 次提交
  9. 05 1月, 2010 1 次提交
    • P
      sh: Abstracted SH-4A UBC support on hw-breakpoint core. · 4352fc1b
      由 Paul Mundt 提交于 
      This is the next big chunk of hw_breakpoint support. This decouples
the SH-4A support from the core and moves it out in to its own stub,
following many of the conventions established with the perf events
layering.

In addition to extending SH-4A support to encapsulate the remainder
of the UBC channels, clock framework support for handling the UBC
interface clock is added as well, allowing for dynamic clock gating.

This also fixes up a regression introduced by the SIGTRAP handling that
broke the ksym_tracer, to the extent that the current support works well
with all of the ksym_tracer/ptrace/kgdb. The kprobes singlestep code will
follow in turn.

With this in place, the remaining UBC variants (SH-2A and SH-4) can now
be trivially plugged in.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      4352fc1b
  11. 28 10月, 2009 1 次提交
    • P
      sh: perf events: Add preliminary support for SH-4A counters. · ac44e669
      由 Paul Mundt 提交于 
      This adds in preliminary support for the SH-4A performance counters.
Presently only the first 2 counters are supported, as these are the ones
of the most interest to the perf tool and end users. Counter chaining is
not presently handled, so these are simply implemented as 32-bit
counters.

This also establishes a perf event support framework for other hardware
counters, which the existing SH-4 oprofile code will migrate over to as
the SH-4A support evolves.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      ac44e669
  13. 21 8月, 2009 1 次提交
  15. 04 8月, 2009 1 次提交
  17. 20 7月, 2009 1 次提交
  19. 04 7月, 2009 1 次提交
    • M
      sh: hwblk for sh7722 · a61c1a63
      由 Magnus Damm 提交于 
      This patch contains the sh7722 specific hwblk implementation.

Hwblk ids are added to the processor specific header file,
module stop bits and areas are kept track of as hwblks,
clocks are converted to make use of the shared hwblk code.
Code to determine allowed sleep modes is also added.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      a61c1a63
  21. 23 6月, 2009 1 次提交
    • P
      sh: SH7786 SMP support. · 2eb2a436
      由 Paul Mundt 提交于 
      SH7786 is roughly identical to SH-X3 proto SMP, though there are only 2
CPUs. This just wraps in to the existing SH-X3 SMP code with some minor
changes for SH7786, including wiring up the IPIs properly, enabling
IRQ_PER_CPU, and so forth.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      2eb2a436
  23. 11 6月, 2009 4 次提交
  25. 16 4月, 2009 1 次提交
  27. 16 3月, 2009 2 次提交
  29. 03 3月, 2009 1 次提交
  31. 23 10月, 2008 1 次提交
  33. 20 10月, 2008 2 次提交
  35. 28 7月, 2008 1 次提交
  37. 19 4月, 2008 1 次提交
  39. 14 2月, 2008 1 次提交
  41. 28 1月, 2008 1 次提交
  43. 21 9月, 2007 1 次提交
  45. 25 7月, 2007 1 次提交
  47. 20 6月, 2007 1 次提交
  49. 07 5月, 2007 2 次提交
  51. 12 12月, 2006 1 次提交