apic_64.c 31.8 KB
Newer Older
L
Linus Torvalds 已提交
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
/*
 *	Local APIC handling, local APIC timers
 *
 *	(c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
26
#include <linux/ioport.h>
27
#include <linux/clockchips.h>
28
#include <linux/acpi_pmtmr.h>
H
Hiroshi Shimamoto 已提交
29
#include <linux/module.h>
L
Linus Torvalds 已提交
30 31 32 33 34

#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/mtrr.h>
#include <asm/mpspec.h>
H
Hiroshi Shimamoto 已提交
35
#include <asm/hpet.h>
L
Linus Torvalds 已提交
36 37
#include <asm/pgalloc.h>
#include <asm/mach_apic.h>
38
#include <asm/nmi.h>
A
Andi Kleen 已提交
39
#include <asm/idle.h>
40 41
#include <asm/proto.h>
#include <asm/timex.h>
42
#include <asm/apic.h>
L
Linus Torvalds 已提交
43

44
int disable_apic_timer __cpuinitdata;
45
static int apic_calibrate_pmtmr __initdata;
46
int disable_apic;
L
Linus Torvalds 已提交
47

H
Hiroshi Shimamoto 已提交
48
/* Local APIC timer works in C2 */
49 50 51
int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

H
Hiroshi Shimamoto 已提交
52 53 54 55 56
/*
 * Debug level, exported for io_apic.c
 */
int apic_verbosity;

57 58 59 60 61
static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

62 63
static unsigned int calibration_result;

64 65 66 67 68
static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt);
static void lapic_timer_setup(enum clock_event_mode mode,
			      struct clock_event_device *evt);
static void lapic_timer_broadcast(cpumask_t mask);
69
static void apic_pm_activate(void);
70 71 72 73 74 75 76 77 78 79 80 81 82 83

static struct clock_event_device lapic_clockevent = {
	.name		= "lapic",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
			| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
	.shift		= 32,
	.set_mode	= lapic_timer_setup,
	.set_next_event	= lapic_next_event,
	.broadcast	= lapic_timer_broadcast,
	.rating		= 100,
	.irq		= -1,
};
static DEFINE_PER_CPU(struct clock_event_device, lapic_events);

84 85
static unsigned long apic_phys;

86 87 88 89
/*
 * Get the LAPIC version
 */
static inline int lapic_get_version(void)
90
{
91
	return GET_APIC_VERSION(apic_read(APIC_LVR));
92 93
}

94 95 96 97
/*
 * Check, if the APIC is integrated or a seperate chip
 */
static inline int lapic_is_integrated(void)
98
{
99
	return 1;
100 101 102
}

/*
103
 * Check, whether this is a modern or a first generation APIC
104
 */
105
static int modern_apic(void)
106
{
107 108 109 110 111
	/* AMD systems use old APIC versions, so check the CPU */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	    boot_cpu_data.x86 >= 0xf)
		return 1;
	return lapic_get_version() >= 0x14;
112 113
}

114 115 116 117 118 119
void apic_wait_icr_idle(void)
{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

120
u32 safe_apic_wait_icr_idle(void)
121
{
122
	u32 send_status;
123 124 125 126 127 128 129 130 131 132 133 134 135
	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

136 137 138
/**
 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
 */
139
void __cpuinit enable_NMI_through_LVT0(void)
L
Linus Torvalds 已提交
140
{
141
	unsigned int v;
142 143 144

	/* unmask and set to NMI */
	v = APIC_DM_NMI;
145
	apic_write(APIC_LVT0, v);
L
Linus Torvalds 已提交
146 147
}

148 149 150
/**
 * lapic_get_maxlvt - get the maximum number of local vector table entries
 */
151
int lapic_get_maxlvt(void)
L
Linus Torvalds 已提交
152
{
153
	unsigned int v, maxlvt;
L
Linus Torvalds 已提交
154 155 156 157 158 159

	v = apic_read(APIC_LVR);
	maxlvt = GET_APIC_MAXLVT(v);
	return maxlvt;
}

160 161 162 163 164 165 166 167 168 169 170 171
/*
 * This function sets up the local APIC timer, with a timeout of
 * 'clocks' APIC bus clock. During calibration we actually call
 * this function twice on the boot CPU, once with a bogus timeout
 * value, second time for real. The other (noncalibrating) CPUs
 * call this function only once, with the real, calibrated value.
 *
 * We do reads before writes even if unnecessary, to get around the
 * P5 APIC double write bug.
 */

static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
L
Linus Torvalds 已提交
172
{
173
	unsigned int lvtt_value, tmp_value;
L
Linus Torvalds 已提交
174

175 176 177 178 179
	lvtt_value = LOCAL_TIMER_VECTOR;
	if (!oneshot)
		lvtt_value |= APIC_LVT_TIMER_PERIODIC;
	if (!irqen)
		lvtt_value |= APIC_LVT_MASKED;
L
Linus Torvalds 已提交
180

181
	apic_write(APIC_LVTT, lvtt_value);
L
Linus Torvalds 已提交
182 183

	/*
184
	 * Divide PICLK by 16
L
Linus Torvalds 已提交
185
	 */
186 187 188 189 190 191 192
	tmp_value = apic_read(APIC_TDCR);
	apic_write(APIC_TDCR, (tmp_value
				& ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
				| APIC_TDR_DIV_16);

	if (!oneshot)
		apic_write(APIC_TMICT, clocks);
L
Linus Torvalds 已提交
193 194
}

195
/*
196 197 198 199
 * Setup extended LVT, AMD specific (K8, family 10h)
 *
 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
 * MCE interrupts are supported. Thus MCE offset must be set to 0.
200
 */
201 202 203 204 205

#define APIC_EILVT_LVTOFF_MCE 0
#define APIC_EILVT_LVTOFF_IBS 1

static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
L
Linus Torvalds 已提交
206
{
207
	unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
208
	unsigned int  v   = (mask << 16) | (msg_type << 8) | vector;
A
Andi Kleen 已提交
209

210
	apic_write(reg, v);
L
Linus Torvalds 已提交
211 212
}

213 214 215 216 217 218 219 220 221 222 223 224
u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
{
	setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
	return APIC_EILVT_LVTOFF_MCE;
}

u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
{
	setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
	return APIC_EILVT_LVTOFF_IBS;
}

225 226 227 228 229
/*
 * Program the next event, relative to now
 */
static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt)
L
Linus Torvalds 已提交
230
{
231 232
	apic_write(APIC_TMICT, delta);
	return 0;
L
Linus Torvalds 已提交
233 234
}

235 236 237 238 239
/*
 * Setup the lapic timer in periodic or oneshot mode
 */
static void lapic_timer_setup(enum clock_event_mode mode,
			      struct clock_event_device *evt)
240 241
{
	unsigned long flags;
242
	unsigned int v;
243

244 245
	/* Lapic used as dummy for broadcast ? */
	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
246 247 248 249
		return;

	local_irq_save(flags);

250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
		__setup_APIC_LVTT(calibration_result,
				  mode != CLOCK_EVT_MODE_PERIODIC, 1);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		v = apic_read(APIC_LVTT);
		v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, v);
		break;
	case CLOCK_EVT_MODE_RESUME:
		/* Nothing to do here */
		break;
	}
266 267 268 269

	local_irq_restore(flags);
}

L
Linus Torvalds 已提交
270
/*
271
 * Local APIC timer broadcast function
L
Linus Torvalds 已提交
272
 */
273
static void lapic_timer_broadcast(cpumask_t mask)
L
Linus Torvalds 已提交
274
{
275 276 277 278
#ifdef CONFIG_SMP
	send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
#endif
}
L
Linus Torvalds 已提交
279

280 281 282 283 284 285 286
/*
 * Setup the local APIC timer for this CPU. Copy the initilized values
 * of the boot CPU and register the clock event in the framework.
 */
static void setup_APIC_timer(void)
{
	struct clock_event_device *levt = &__get_cpu_var(lapic_events);
L
Linus Torvalds 已提交
287

288 289
	memcpy(levt, &lapic_clockevent, sizeof(*levt));
	levt->cpumask = cpumask_of_cpu(smp_processor_id());
L
Linus Torvalds 已提交
290

291 292
	clockevents_register_device(levt);
}
L
Linus Torvalds 已提交
293

294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363
/*
 * In this function we calibrate APIC bus clocks to the external
 * timer. Unfortunately we cannot use jiffies and the timer irq
 * to calibrate, since some later bootup code depends on getting
 * the first irq? Ugh.
 *
 * We want to do the calibration only once since we
 * want to have local timer irqs syncron. CPUs connected
 * by the same APIC bus have the very same bus frequency.
 * And we want to have irqs off anyways, no accidental
 * APIC irq that way.
 */

#define TICK_COUNT 100000000

static void __init calibrate_APIC_clock(void)
{
	unsigned apic, apic_start;
	unsigned long tsc, tsc_start;
	int result;

	local_irq_disable();

	/*
	 * Put whatever arbitrary (but long enough) timeout
	 * value into the APIC clock, we just want to get the
	 * counter running for calibration.
	 *
	 * No interrupt enable !
	 */
	__setup_APIC_LVTT(250000000, 0, 0);

	apic_start = apic_read(APIC_TMCCT);
#ifdef CONFIG_X86_PM_TIMER
	if (apic_calibrate_pmtmr && pmtmr_ioport) {
		pmtimer_wait(5000);  /* 5ms wait */
		apic = apic_read(APIC_TMCCT);
		result = (apic_start - apic) * 1000L / 5;
	} else
#endif
	{
		rdtscll(tsc_start);

		do {
			apic = apic_read(APIC_TMCCT);
			rdtscll(tsc);
		} while ((tsc - tsc_start) < TICK_COUNT &&
				(apic_start - apic) < TICK_COUNT);

		result = (apic_start - apic) * 1000L * tsc_khz /
					(tsc - tsc_start);
	}

	local_irq_enable();

	printk(KERN_DEBUG "APIC timer calibration result %d\n", result);

	printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
		result / 1000 / 1000, result / 1000 % 1000);

	/* Calculate the scaled math multiplication factor */
	lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32);
	lapic_clockevent.max_delta_ns =
		clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
	lapic_clockevent.min_delta_ns =
		clockevent_delta2ns(0xF, &lapic_clockevent);

	calibration_result = result / HZ;
}

H
Hiroshi Shimamoto 已提交
364 365 366 367 368
/*
 * Setup the boot APIC
 *
 * Calibrate and verify the result.
 */
369 370 371 372 373 374 375 376 377 378 379
void __init setup_boot_APIC_clock(void)
{
	/*
	 * The local apic timer can be disabled via the kernel commandline.
	 * Register the lapic timer as a dummy clock event source on SMP
	 * systems, so the broadcast mechanism is used. On UP systems simply
	 * ignore it.
	 */
	if (disable_apic_timer) {
		printk(KERN_INFO "Disabling APIC timer\n");
		/* No broadcast on UP ! */
380 381
		if (num_possible_cpus() > 1) {
			lapic_clockevent.mult = 1;
382
			setup_APIC_timer();
383
		}
384 385 386 387 388 389
		return;
	}

	printk(KERN_INFO "Using local APIC timer interrupts.\n");
	calibrate_APIC_clock();

390 391 392 393 394 395 396 397 398 399 400 401
	/*
	 * Do a sanity check on the APIC calibration result
	 */
	if (calibration_result < (1000000 / HZ)) {
		printk(KERN_WARNING
		       "APIC frequency too slow, disabling apic timer\n");
		/* No broadcast on UP ! */
		if (num_possible_cpus() > 1)
			setup_APIC_timer();
		return;
	}

402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433
	/*
	 * If nmi_watchdog is set to IO_APIC, we need the
	 * PIT/HPET going.  Otherwise register lapic as a dummy
	 * device.
	 */
	if (nmi_watchdog != NMI_IO_APIC)
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
	else
		printk(KERN_WARNING "APIC timer registered as dummy,"
		       " due to nmi_watchdog=1!\n");

	setup_APIC_timer();
}

/*
 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
 * C1E flag only in the secondary CPU, so when we detect the wreckage
 * we already have enabled the boot CPU local apic timer. Check, if
 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
 * set the DUMMY flag again and force the broadcast mode in the
 * clockevents layer.
 */
void __cpuinit check_boot_apic_timer_broadcast(void)
{
	if (!disable_apic_timer ||
	    (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
		return;

	printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
	lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;

	local_irq_enable();
434 435
	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
			   &boot_cpu_physical_apicid);
436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530
	local_irq_disable();
}

void __cpuinit setup_secondary_APIC_clock(void)
{
	check_boot_apic_timer_broadcast();
	setup_APIC_timer();
}

/*
 * The guts of the apic timer interrupt
 */
static void local_apic_timer_interrupt(void)
{
	int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(lapic_events, cpu);

	/*
	 * Normally we should not be here till LAPIC has been initialized but
	 * in some cases like kdump, its possible that there is a pending LAPIC
	 * timer interrupt from previous kernel's context and is delivered in
	 * new kernel the moment interrupts are enabled.
	 *
	 * Interrupts are enabled early and LAPIC is setup much later, hence
	 * its possible that when we get here evt->event_handler is NULL.
	 * Check for event_handler being NULL and discard the interrupt as
	 * spurious.
	 */
	if (!evt->event_handler) {
		printk(KERN_WARNING
		       "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
		/* Switch it off */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
		return;
	}

	/*
	 * the NMI deadlock-detector uses this.
	 */
	add_pda(apic_timer_irqs, 1);

	evt->event_handler(evt);
}

/*
 * Local APIC timer interrupt. This is the most natural way for doing
 * local interrupts, but local timer interrupts can be emulated by
 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
 *
 * [ if a single-CPU system runs an SMP kernel then we call the local
 *   interrupt as well. Thus we cannot inline the local irq ... ]
 */
void smp_apic_timer_interrupt(struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	/*
	 * NOTE! We'd better ACK the irq immediately,
	 * because timer handling can be slow.
	 */
	ack_APIC_irq();
	/*
	 * update_process_times() expects us to have done irq_enter().
	 * Besides, if we don't timer interrupts ignore the global
	 * interrupt lock, which is the WrongThing (tm) to do.
	 */
	exit_idle();
	irq_enter();
	local_apic_timer_interrupt();
	irq_exit();
	set_irq_regs(old_regs);
}

int setup_profiling_timer(unsigned int multiplier)
{
	return -EINVAL;
}


/*
 * Local APIC start and shutdown
 */

/**
 * clear_local_APIC - shutdown the local APIC
 *
 * This is called, when a CPU is disabled and before rebooting, so the state of
 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
 * leftovers during boot.
 */
void clear_local_APIC(void)
{
	int maxlvt = lapic_get_maxlvt();
	u32 v;

531 532 533 534 535
	/* APIC hasn't been mapped yet */
	if (!apic_phys)
		return;

	maxlvt = lapic_get_maxlvt();
536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653
	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
}

/**
 * disable_local_APIC - clear and disable the local APIC
 */
void disable_local_APIC(void)
{
	unsigned int value;

	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
}

void lapic_shutdown(void)
{
	unsigned long flags;

	if (!cpu_has_apic)
		return;

	local_irq_save(flags);

	disable_local_APIC();

	local_irq_restore(flags);
}

/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
{
	unsigned int reg0, reg1;

	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
		return 0;

	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = lapic_get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;

	/*
	 * The ID register is read/write in a real APIC.
	 */
	reg0 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	reg1 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
	if (reg1 != (reg0 ^ APIC_ID_MASK))
		return 0;

	/*
L
Linus Torvalds 已提交
654 655 656 657 658
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
659
	apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
L
Linus Torvalds 已提交
660 661 662 663 664 665
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
}

666 667 668
/**
 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
 */
L
Linus Torvalds 已提交
669 670 671
void __init sync_Arb_IDs(void)
{
	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
672
	if (modern_apic())
L
Linus Torvalds 已提交
673 674 675 676 677 678 679 680
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
681
	apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
L
Linus Torvalds 已提交
682 683 684 685 686 687 688 689
				| APIC_DM_INIT);
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
690
	unsigned int value;
L
Linus Torvalds 已提交
691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	value = apic_read(APIC_LVR);

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= APIC_SPIV_FOCUS_DISABLED;
	value |= SPURIOUS_APIC_VECTOR;
714
	apic_write(APIC_SPIV, value);
L
Linus Torvalds 已提交
715 716 717 718

	/*
	 * Set up the virtual wire mode.
	 */
719
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
L
Linus Torvalds 已提交
720
	value = APIC_DM_NMI;
721
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
722 723
}

724 725 726 727
/**
 * setup_local_APIC - setup the local APIC
 */
void __cpuinit setup_local_APIC(void)
L
Linus Torvalds 已提交
728
{
729
	unsigned int value;
730
	int i, j;
L
Linus Torvalds 已提交
731 732 733

	value = apic_read(APIC_LVR);

734
	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
L
Linus Torvalds 已提交
735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755

	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
	if (!apic_id_registered())
		BUG();

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
	init_apic_ldr();

	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
756
	apic_write(APIC_TASKPRI, value);
L
Linus Torvalds 已提交
757

758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776
	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
		value = apic_read(APIC_ISR + i*0x10);
		for (j = 31; j >= 0; j--) {
			if (value & (1<<j))
				ack_APIC_irq();
		}
	}

L
Linus Torvalds 已提交
777 778 779 780 781 782 783 784 785 786
	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

787 788
	/* We always use processor focus */

L
Linus Torvalds 已提交
789 790 791 792
	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
793
	apic_write(APIC_SPIV, value);
L
Linus Torvalds 已提交
794 795 796 797 798 799 800 801 802 803 804 805

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
A
Andi Kleen 已提交
806
	if (!smp_processor_id() && !value) {
L
Linus Torvalds 已提交
807
		value = APIC_DM_EXTINT;
808 809
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
			    smp_processor_id());
L
Linus Torvalds 已提交
810 811
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
812 813
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
			    smp_processor_id());
L
Linus Torvalds 已提交
814
	}
815
	apic_write(APIC_LVT0, value);
L
Linus Torvalds 已提交
816 817 818 819 820 821 822 823

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
	if (!smp_processor_id())
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
824
	apic_write(APIC_LVT1, value);
825
}
L
Linus Torvalds 已提交
826

827 828 829 830 831
void __cpuinit lapic_setup_esr(void)
{
	unsigned maxlvt = lapic_get_maxlvt();

	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
832
	/*
833
	 * spec says clear errors after enabling vector.
834
	 */
835 836 837
	if (maxlvt > 3)
		apic_write(APIC_ESR, 0);
}
L
Linus Torvalds 已提交
838

839 840 841
void __cpuinit end_local_APIC_setup(void)
{
	lapic_setup_esr();
L
Linus Torvalds 已提交
842
	nmi_watchdog_default();
843
	setup_apic_nmi_watchdog(NULL);
844
	apic_pm_activate();
L
Linus Torvalds 已提交
845 846 847 848 849 850
}

/*
 * Detect and enable local APICs on non-SMP boards.
 * Original code written by Keir Fraser.
 * On AMD64 we trust the BIOS - if it says no APIC it is likely
851
 * not correctly set up (usually the APIC timer won't work etc.)
L
Linus Torvalds 已提交
852
 */
853
static int __init detect_init_APIC(void)
L
Linus Torvalds 已提交
854 855 856 857 858 859 860
{
	if (!cpu_has_apic) {
		printk(KERN_INFO "No local APIC present\n");
		return -1;
	}

	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
861
	boot_cpu_physical_apicid = 0;
L
Linus Torvalds 已提交
862 863 864
	return 0;
}

865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885
void __init early_init_lapic_mapping(void)
{
	unsigned long apic_phys;

	/*
	 * If no local APIC can be found then go out
	 * : it means there is no mpatable and MADT
	 */
	if (!smp_found_config)
		return;

	apic_phys = mp_lapic_addr;

	set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
	apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
				 APIC_BASE, apic_phys);

	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
886
	boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
887 888
}

889 890 891
/**
 * init_apic_mappings - initialize APIC mappings
 */
L
Linus Torvalds 已提交
892 893 894 895 896 897 898 899 900 901 902 903 904 905
void __init init_apic_mappings(void)
{
	/*
	 * If no local APIC can be found then set up a fake all
	 * zeroes page to simulate the local APIC and another
	 * one for the IO-APIC.
	 */
	if (!smp_found_config && detect_init_APIC()) {
		apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
		apic_phys = __pa(apic_phys);
	} else
		apic_phys = mp_lapic_addr;

	set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
Y
Yinghai Lu 已提交
906 907
	apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
				APIC_BASE, apic_phys);
L
Linus Torvalds 已提交
908 909 910 911 912

	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
913
	boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
L
Linus Torvalds 已提交
914 915 916
}

/*
917 918
 * This initializes the IO-APIC and APIC hardware if this is
 * a UP kernel.
L
Linus Torvalds 已提交
919
 */
920
int __init APIC_init_uniprocessor(void)
L
Linus Torvalds 已提交
921
{
922 923 924 925 926 927 928 929 930
	if (disable_apic) {
		printk(KERN_INFO "Apic disabled\n");
		return -1;
	}
	if (!cpu_has_apic) {
		disable_apic = 1;
		printk(KERN_INFO "Apic disabled by BIOS\n");
		return -1;
	}
L
Linus Torvalds 已提交
931

932
	verify_local_APIC();
L
Linus Torvalds 已提交
933

934 935
	phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
	apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
L
Linus Torvalds 已提交
936

937
	setup_local_APIC();
L
Linus Torvalds 已提交
938

939 940 941 942 943 944 945 946 947
	/*
	 * Now enable IO-APICs, actually call clear_IO_APIC
	 * We need clear_IO_APIC before enabling vector on BP
	 */
	if (!skip_ioapic_setup && nr_ioapics)
		enable_IO_APIC();

	end_local_APIC_setup();

948 949 950 951 952 953 954
	if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
		setup_IO_APIC();
	else
		nr_ioapics = 0;
	setup_boot_APIC_clock();
	check_nmi_watchdog();
	return 0;
L
Linus Torvalds 已提交
955 956 957
}

/*
958
 * Local APIC interrupts
L
Linus Torvalds 已提交
959 960
 */

961 962 963 964
/*
 * This interrupt should _never_ happen with our APIC/SMP architecture
 */
asmlinkage void smp_spurious_interrupt(void)
L
Linus Torvalds 已提交
965
{
966 967 968
	unsigned int v;
	exit_idle();
	irq_enter();
L
Linus Torvalds 已提交
969
	/*
970 971 972
	 * Check if this really is a spurious interrupt and ACK it
	 * if it is a vectored one.  Just in case...
	 * Spurious interrupts should not be ACKed.
L
Linus Torvalds 已提交
973
	 */
974 975 976
	v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
	if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
		ack_APIC_irq();
977

978 979 980
	add_pda(irq_spurious_count, 1);
	irq_exit();
}
L
Linus Torvalds 已提交
981

982 983 984 985 986 987
/*
 * This interrupt should never happen with our APIC/SMP architecture
 */
asmlinkage void smp_error_interrupt(void)
{
	unsigned int v, v1;
L
Linus Torvalds 已提交
988

989 990 991 992 993 994 995 996
	exit_idle();
	irq_enter();
	/* First tickle the hardware, only then report what went on. -- REW */
	v = apic_read(APIC_ESR);
	apic_write(APIC_ESR, 0);
	v1 = apic_read(APIC_ESR);
	ack_APIC_irq();
	atomic_inc(&irq_err_count);
997

998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010
	/* Here is what the APIC error bits mean:
	   0: Send CS error
	   1: Receive CS error
	   2: Send accept error
	   3: Receive accept error
	   4: Reserved
	   5: Send illegal vector
	   6: Received illegal vector
	   7: Illegal register address
	*/
	printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
		smp_processor_id(), v , v1);
	irq_exit();
L
Linus Torvalds 已提交
1011 1012
}

1013
void disconnect_bsp_APIC(int virt_wire_setup)
L
Linus Torvalds 已提交
1014
{
1015 1016
	/* Go back to Virtual Wire compatibility mode */
	unsigned long value;
L
Linus Torvalds 已提交
1017

1018 1019 1020 1021 1022 1023
	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);
T
Thomas Gleixner 已提交
1024

1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040
	if (!virt_wire_setup) {
		/*
		 * For LVT0 make it edge triggered, active high,
		 * external and enabled
		 */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}
T
Thomas Gleixner 已提交
1041

1042 1043 1044 1045 1046 1047 1048 1049
	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
1050 1051
}

1052
/*
1053
 * Power management
1054
 */
1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081
#ifdef CONFIG_PM

static struct {
	/* 'active' is true if the local APIC was enabled by us and
	   not the BIOS; this signifies that we are also responsible
	   for disabling it before entering apm/acpi suspend */
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

static int lapic_suspend(struct sys_device *dev, pm_message_t state)
{
	unsigned long flags;
	int maxlvt;
1082

1083 1084
	if (!apic_pm_state.active)
		return 0;
1085

1086
	maxlvt = lapic_get_maxlvt();
1087

1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108
	apic_pm_state.apic_id = apic_read(APIC_ID);
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
	local_irq_save(flags);
	disable_local_APIC();
	local_irq_restore(flags);
	return 0;
L
Linus Torvalds 已提交
1109 1110
}

1111
static int lapic_resume(struct sys_device *dev)
L
Linus Torvalds 已提交
1112
{
1113 1114 1115
	unsigned int l, h;
	unsigned long flags;
	int maxlvt;
L
Linus Torvalds 已提交
1116

1117 1118
	if (!apic_pm_state.active)
		return 0;
1119

1120
	maxlvt = lapic_get_maxlvt();
L
Linus Torvalds 已提交
1121

1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151
	local_irq_save(flags);
	rdmsr(MSR_IA32_APICBASE, l, h);
	l &= ~MSR_IA32_APICBASE_BASE;
	l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
	wrmsr(MSR_IA32_APICBASE, l, h);
	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
	apic_write(APIC_ID, apic_pm_state.apic_id);
	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 5)
		apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
#endif
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
	local_irq_restore(flags);
	return 0;
}
T
Thomas Gleixner 已提交
1152

1153 1154 1155 1156 1157
static struct sysdev_class lapic_sysclass = {
	.name		= "lapic",
	.resume		= lapic_resume,
	.suspend	= lapic_suspend,
};
T
Thomas Gleixner 已提交
1158

1159
static struct sys_device device_lapic = {
H
Hiroshi Shimamoto 已提交
1160 1161
	.id	= 0,
	.cls	= &lapic_sysclass,
1162
};
T
Thomas Gleixner 已提交
1163

1164 1165 1166
static void __cpuinit apic_pm_activate(void)
{
	apic_pm_state.active = 1;
L
Linus Torvalds 已提交
1167 1168
}

1169
static int __init init_lapic_sysfs(void)
L
Linus Torvalds 已提交
1170
{
1171
	int error;
H
Hiroshi Shimamoto 已提交
1172

1173 1174 1175
	if (!cpu_has_apic)
		return 0;
	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
H
Hiroshi Shimamoto 已提交
1176

1177 1178 1179 1180
	error = sysdev_class_register(&lapic_sysclass);
	if (!error)
		error = sysdev_register(&device_lapic);
	return error;
L
Linus Torvalds 已提交
1181
}
1182 1183 1184 1185 1186 1187 1188
device_initcall(init_lapic_sysfs);

#else	/* CONFIG_PM */

static void apic_pm_activate(void) { }

#endif	/* CONFIG_PM */
L
Linus Torvalds 已提交
1189 1190

/*
1191
 * apic_is_clustered_box() -- Check if we can expect good TSC
L
Linus Torvalds 已提交
1192 1193 1194
 *
 * Thus far, the major user of this is IBM's Summit2 series:
 *
1195
 * Clustered boxes may have unsynced TSC problems if they are
L
Linus Torvalds 已提交
1196 1197 1198
 * multi-chassis. Use available data to take a good guess.
 * If in doubt, go HPET.
 */
1199
__cpuinit int apic_is_clustered_box(void)
L
Linus Torvalds 已提交
1200 1201 1202
{
	int i, clusters, zeros;
	unsigned id;
1203
	u16 *bios_cpu_apicid;
L
Linus Torvalds 已提交
1204 1205
	DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);

1206 1207 1208 1209
	/*
	 * there is not this kind of box with AMD CPU yet.
	 * Some AMD box with quadcore cpu and 8 sockets apicid
	 * will be [4, 0x23] or [8, 0x27] could be thought to
Y
Yinghai Lu 已提交
1210
	 * vsmp box still need checking...
1211
	 */
Y
Yinghai Lu 已提交
1212
	if (!is_vsmp_box() && (boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
1213 1214 1215
		return 0;

	bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
1216
	bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
L
Linus Torvalds 已提交
1217 1218

	for (i = 0; i < NR_CPUS; i++) {
1219
		/* are we being called early in kernel startup? */
1220 1221
		if (bios_cpu_apicid) {
			id = bios_cpu_apicid[i];
1222 1223 1224 1225 1226 1227 1228 1229 1230 1231
		}
		else if (i < nr_cpu_ids) {
			if (cpu_present(i))
				id = per_cpu(x86_bios_cpu_apicid, i);
			else
				continue;
		}
		else
			break;

L
Linus Torvalds 已提交
1232 1233 1234 1235 1236 1237
		if (id != BAD_APICID)
			__set_bit(APIC_CLUSTERID(id), clustermap);
	}

	/* Problem:  Partially populated chassis may not have CPUs in some of
	 * the APIC clusters they have been allocated.  Only present CPUs have
1238 1239 1240
	 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
	 * Since clusters are allocated sequentially, count zeros only if
	 * they are bounded by ones.
L
Linus Torvalds 已提交
1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252
	 */
	clusters = 0;
	zeros = 0;
	for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
		if (test_bit(i, clustermap)) {
			clusters += 1 + zeros;
			zeros = 0;
		} else
			++zeros;
	}

	/*
1253
	 * If clusters > 2, then should be multi-chassis.
L
Linus Torvalds 已提交
1254 1255 1256 1257 1258 1259 1260
	 * May have to revisit this when multi-core + hyperthreaded CPUs come
	 * out, but AFAIK this will work even for them.
	 */
	return (clusters > 2);
}

/*
1261
 * APIC command line parameters
L
Linus Torvalds 已提交
1262
 */
1263
static int __init apic_set_verbosity(char *str)
L
Linus Torvalds 已提交
1264
{
1265 1266 1267 1268
	if (str == NULL)  {
		skip_ioapic_setup = 0;
		ioapic_force = 1;
		return 0;
L
Linus Torvalds 已提交
1269
	}
1270 1271 1272 1273 1274 1275 1276 1277
	if (strcmp("debug", str) == 0)
		apic_verbosity = APIC_DEBUG;
	else if (strcmp("verbose", str) == 0)
		apic_verbosity = APIC_VERBOSE;
	else {
		printk(KERN_WARNING "APIC Verbosity level %s not recognised"
				" use apic=verbose or apic=debug\n", str);
		return -EINVAL;
L
Linus Torvalds 已提交
1278 1279 1280 1281
	}

	return 0;
}
1282
early_param("apic", apic_set_verbosity);
L
Linus Torvalds 已提交
1283

1284 1285
static __init int setup_disableapic(char *str)
{
L
Linus Torvalds 已提交
1286
	disable_apic = 1;
1287
	clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1288 1289 1290
	return 0;
}
early_param("disableapic", setup_disableapic);
L
Linus Torvalds 已提交
1291

1292
/* same as disableapic, for compatibility */
1293 1294
static __init int setup_nolapic(char *str)
{
1295
	return setup_disableapic(str);
1296
}
1297
early_param("nolapic", setup_nolapic);
L
Linus Torvalds 已提交
1298

1299 1300 1301 1302 1303 1304 1305
static int __init parse_lapic_timer_c2_ok(char *arg)
{
	local_apic_timer_c2_ok = 1;
	return 0;
}
early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);

1306 1307
static __init int setup_noapictimer(char *str)
{
1308
	if (str[0] != ' ' && str[0] != 0)
1309
		return 0;
L
Linus Torvalds 已提交
1310
	disable_apic_timer = 1;
1311
	return 1;
1312
}
T
Thomas Gleixner 已提交
1313
__setup("noapictimer", setup_noapictimer);
1314

1315 1316 1317
static __init int setup_apicpmtimer(char *s)
{
	apic_calibrate_pmtmr = 1;
1318
	notsc_setup(NULL);
T
Thomas Gleixner 已提交
1319
	return 0;
1320 1321 1322
}
__setup("apicpmtimer", setup_apicpmtimer);

1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340
static int __init lapic_insert_resource(void)
{
	if (!apic_phys)
		return -1;

	/* Put local APIC into the resource map. */
	lapic_resource.start = apic_phys;
	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
	insert_resource(&iomem_resource, &lapic_resource);

	return 0;
}

/*
 * need call insert after e820_reserve_resources()
 * that is using request_resource
 */
late_initcall(lapic_insert_resource);