bnx2.c 200.9 KB
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/* bnx2.c: Broadcom NX2 network driver.
 *
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 * Copyright (c) 2004-2009 Broadcom Corporation
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation.
 *
 * Written by: Michael Chan  (mchan@broadcom.com)
 */

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#include <linux/module.h>
#include <linux/moduleparam.h>

#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/dma-mapping.h>
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#include <linux/bitops.h>
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#include <asm/io.h>
#include <asm/irq.h>
#include <linux/delay.h>
#include <asm/byteorder.h>
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#include <asm/page.h>
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#include <linux/time.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
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#define BCM_VLAN 1
#endif
#include <net/ip.h>
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#include <net/tcp.h>
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#include <net/checksum.h>
#include <linux/workqueue.h>
#include <linux/crc32.h>
#include <linux/prefetch.h>
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#include <linux/cache.h>
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#include <linux/firmware.h>
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#include <linux/log2.h>
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#include <linux/list.h>
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#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
#define BCM_CNIC 1
#include "cnic_if.h"
#endif
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#include "bnx2.h"
#include "bnx2_fw.h"
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#define DRV_MODULE_NAME		"bnx2"
#define PFX DRV_MODULE_NAME	": "
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#define DRV_MODULE_VERSION	"2.0.2"
#define DRV_MODULE_RELDATE	"Aug 21, 2009"
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#define FW_MIPS_FILE_06		"bnx2/bnx2-mips-06-5.0.0.j3.fw"
#define FW_RV2P_FILE_06		"bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
#define FW_MIPS_FILE_09		"bnx2/bnx2-mips-09-5.0.0.j3.fw"
#define FW_RV2P_FILE_09_Ax	"bnx2/bnx2-rv2p-09ax-5.0.0.j3.fw"
#define FW_RV2P_FILE_09		"bnx2/bnx2-rv2p-09-5.0.0.j3.fw"
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#define RUN_AT(x) (jiffies + (x))

/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT  (5*HZ)

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static char version[] __devinitdata =
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	"Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";

MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
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MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_MODULE_VERSION);
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MODULE_FIRMWARE(FW_MIPS_FILE_06);
MODULE_FIRMWARE(FW_RV2P_FILE_06);
MODULE_FIRMWARE(FW_MIPS_FILE_09);
MODULE_FIRMWARE(FW_RV2P_FILE_09);
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MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
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static int disable_msi = 0;

module_param(disable_msi, int, 0);
MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");

typedef enum {
	BCM5706 = 0,
	NC370T,
	NC370I,
	BCM5706S,
	NC370F,
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	BCM5708,
	BCM5708S,
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	BCM5709,
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	BCM5709S,
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	BCM5716,
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	BCM5716S,
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} board_t;

/* indexed by board_t, above */
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static struct {
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	char *name;
} board_info[] __devinitdata = {
	{ "Broadcom NetXtreme II BCM5706 1000Base-T" },
	{ "HP NC370T Multifunction Gigabit Server Adapter" },
	{ "HP NC370i Multifunction Gigabit Server Adapter" },
	{ "Broadcom NetXtreme II BCM5706 1000Base-SX" },
	{ "HP NC370F Multifunction Gigabit Server Adapter" },
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	{ "Broadcom NetXtreme II BCM5708 1000Base-T" },
	{ "Broadcom NetXtreme II BCM5708 1000Base-SX" },
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	{ "Broadcom NetXtreme II BCM5709 1000Base-T" },
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	{ "Broadcom NetXtreme II BCM5709 1000Base-SX" },
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	{ "Broadcom NetXtreme II BCM5716 1000Base-T" },
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	{ "Broadcom NetXtreme II BCM5716 1000Base-SX" },
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	};

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static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
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	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
	  PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
	  PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
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	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
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	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
	  PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
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	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
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	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
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	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
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	{ PCI_VENDOR_ID_BROADCOM, 0x163b,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
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	{ PCI_VENDOR_ID_BROADCOM, 0x163c,
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	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
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	{ 0, }
};

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static const struct flash_spec flash_table[] =
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{
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#define BUFFERED_FLAGS		(BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
#define NONBUFFERED_FLAGS	(BNX2_NV_WREN)
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	/* Slow EEPROM */
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	{0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
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	 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
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	 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
	 "EEPROM - slow"},
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	/* Expansion entry 0001 */
	{0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 0001"},
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	/* Saifun SA25F010 (non-buffered flash) */
	/* strap, cfg1, & write1 need updates */
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	{0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
	 "Non-buffered flash (128kB)"},
	/* Saifun SA25F020 (non-buffered flash) */
	/* strap, cfg1, & write1 need updates */
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	{0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
	 "Non-buffered flash (256kB)"},
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	/* Expansion entry 0100 */
	{0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 0100"},
	/* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
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	{0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
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	 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
	 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
	/* Entry 0110: ST M45PE20 (non-buffered flash)*/
	{0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
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	 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
	 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
	/* Saifun SA25F005 (non-buffered flash) */
	/* strap, cfg1, & write1 need updates */
	{0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
	 "Non-buffered flash (64kB)"},
	/* Fast EEPROM */
	{0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
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	 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
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	 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
	 "EEPROM - fast"},
	/* Expansion entry 1001 */
	{0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1001"},
	/* Expansion entry 1010 */
	{0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1010"},
	/* ATMEL AT45DB011B (buffered flash) */
	{0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
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	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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	 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
	 "Buffered flash (128kB)"},
	/* Expansion entry 1100 */
	{0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1100"},
	/* Expansion entry 1101 */
	{0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
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	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
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	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1101"},
	/* Ateml Expansion entry 1110 */
	{0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
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	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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	 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1110 (Atmel)"},
	/* ATMEL AT45DB021B (buffered flash) */
	{0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
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	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
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	 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
	 "Buffered flash (256kB)"},
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};

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static const struct flash_spec flash_5709 = {
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	.flags		= BNX2_NV_BUFFERED,
	.page_bits	= BCM5709_FLASH_PAGE_BITS,
	.page_size	= BCM5709_FLASH_PAGE_SIZE,
	.addr_mask	= BCM5709_FLASH_BYTE_ADDR_MASK,
	.total_size	= BUFFERED_FLASH_TOTAL_SIZE*2,
	.name		= "5709 Buffered flash (256kB)",
};

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MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);

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static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
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{
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	u32 diff;
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	smp_mb();
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	/* The ring uses 256 indices for 255 entries, one of them
	 * needs to be skipped.
	 */
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	diff = txr->tx_prod - txr->tx_cons;
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	if (unlikely(diff >= TX_DESC_CNT)) {
		diff &= 0xffff;
		if (diff == TX_DESC_CNT)
			diff = MAX_TX_DESC_CNT;
	}
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	return (bp->tx_ring_size - diff);
}

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static u32
bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
{
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	u32 val;

	spin_lock_bh(&bp->indirect_lock);
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	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
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	val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
	spin_unlock_bh(&bp->indirect_lock);
	return val;
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}

static void
bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
{
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	spin_lock_bh(&bp->indirect_lock);
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	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
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	spin_unlock_bh(&bp->indirect_lock);
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}

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static void
bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
{
	bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
}

static u32
bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
{
	return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
}

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static void
bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
{
	offset += cid_addr;
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	spin_lock_bh(&bp->indirect_lock);
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	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		int i;

		REG_WR(bp, BNX2_CTX_CTX_DATA, val);
		REG_WR(bp, BNX2_CTX_CTX_CTRL,
		       offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
		for (i = 0; i < 5; i++) {
			val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
			if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
				break;
			udelay(5);
		}
	} else {
		REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
		REG_WR(bp, BNX2_CTX_DATA, val);
	}
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	spin_unlock_bh(&bp->indirect_lock);
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}

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#ifdef BCM_CNIC
static int
bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
{
	struct bnx2 *bp = netdev_priv(dev);
	struct drv_ctl_io *io = &info->data.io;

	switch (info->cmd) {
	case DRV_CTL_IO_WR_CMD:
		bnx2_reg_wr_ind(bp, io->offset, io->data);
		break;
	case DRV_CTL_IO_RD_CMD:
		io->data = bnx2_reg_rd_ind(bp, io->offset);
		break;
	case DRV_CTL_CTX_WR_CMD:
		bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
{
	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
	int sb_id;

	if (bp->flags & BNX2_FLAG_USING_MSIX) {
		cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
		bnapi->cnic_present = 0;
		sb_id = bp->irq_nvecs;
		cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
	} else {
		cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
		bnapi->cnic_tag = bnapi->last_status_idx;
		bnapi->cnic_present = 1;
		sb_id = 0;
		cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
	}

	cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
	cp->irq_arr[0].status_blk = (void *)
		((unsigned long) bnapi->status_blk.msi +
		(BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
	cp->irq_arr[0].status_blk_num = sb_id;
	cp->num_irq = 1;
}

static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
			      void *data)
{
	struct bnx2 *bp = netdev_priv(dev);
	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;

	if (ops == NULL)
		return -EINVAL;

	if (cp->drv_state & CNIC_DRV_STATE_REGD)
		return -EBUSY;

	bp->cnic_data = data;
	rcu_assign_pointer(bp->cnic_ops, ops);

	cp->num_irq = 0;
	cp->drv_state = CNIC_DRV_STATE_REGD;

	bnx2_setup_cnic_irq_info(bp);

	return 0;
}

static int bnx2_unregister_cnic(struct net_device *dev)
{
	struct bnx2 *bp = netdev_priv(dev);
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;

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	mutex_lock(&bp->cnic_lock);
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	cp->drv_state = 0;
	bnapi->cnic_present = 0;
	rcu_assign_pointer(bp->cnic_ops, NULL);
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	mutex_unlock(&bp->cnic_lock);
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	synchronize_rcu();
	return 0;
}

struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
{
	struct bnx2 *bp = netdev_priv(dev);
	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;

	cp->drv_owner = THIS_MODULE;
	cp->chip_id = bp->chip_id;
	cp->pdev = bp->pdev;
	cp->io_base = bp->regview;
	cp->drv_ctl = bnx2_drv_ctl;
	cp->drv_register_cnic = bnx2_register_cnic;
	cp->drv_unregister_cnic = bnx2_unregister_cnic;

	return cp;
}
EXPORT_SYMBOL(bnx2_cnic_probe);

static void
bnx2_cnic_stop(struct bnx2 *bp)
{
	struct cnic_ops *c_ops;
	struct cnic_ctl_info info;

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	mutex_lock(&bp->cnic_lock);
	c_ops = bp->cnic_ops;
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	if (c_ops) {
		info.cmd = CNIC_CTL_STOP_CMD;
		c_ops->cnic_ctl(bp->cnic_data, &info);
	}
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	mutex_unlock(&bp->cnic_lock);
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}

static void
bnx2_cnic_start(struct bnx2 *bp)
{
	struct cnic_ops *c_ops;
	struct cnic_ctl_info info;

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	mutex_lock(&bp->cnic_lock);
	c_ops = bp->cnic_ops;
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	if (c_ops) {
		if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
			struct bnx2_napi *bnapi = &bp->bnx2_napi[0];

			bnapi->cnic_tag = bnapi->last_status_idx;
		}
		info.cmd = CNIC_CTL_START_CMD;
		c_ops->cnic_ctl(bp->cnic_data, &info);
	}
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	mutex_unlock(&bp->cnic_lock);
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}

#else

static void
bnx2_cnic_stop(struct bnx2 *bp)
{
}

static void
bnx2_cnic_start(struct bnx2 *bp)
{
}

#endif

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static int
bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
{
	u32 val1;
	int i, ret;

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	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
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		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	val1 = (bp->phy_addr << 21) | (reg << 16) |
		BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
		BNX2_EMAC_MDIO_COMM_START_BUSY;
	REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);

	for (i = 0; i < 50; i++) {
		udelay(10);

		val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
		if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
			udelay(5);

			val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
			val1 &= BNX2_EMAC_MDIO_COMM_DATA;

			break;
		}
	}

	if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
		*val = 0x0;
		ret = -EBUSY;
	}
	else {
		*val = val1;
		ret = 0;
	}

523
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	return ret;
}

static int
bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
{
	u32 val1;
	int i, ret;

542
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
543 544 545 546 547 548 549 550 551 552 553 554 555
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	val1 = (bp->phy_addr << 21) | (reg << 16) | val |
		BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
		BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
	REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
556

557 558 559 560 561 562 563 564 565 566 567 568 569 570 571
	for (i = 0; i < 50; i++) {
		udelay(10);

		val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
		if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
			udelay(5);
			break;
		}
	}

	if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
        	ret = -EBUSY;
	else
		ret = 0;

572
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
573 574 575 576 577 578 579 580 581 582 583 584 585 586 587
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	return ret;
}

static void
bnx2_disable_int(struct bnx2 *bp)
{
588 589 590 591 592 593 594 595
	int i;
	struct bnx2_napi *bnapi;

	for (i = 0; i < bp->irq_nvecs; i++) {
		bnapi = &bp->bnx2_napi[i];
		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
		       BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
	}
596 597 598 599 600 601
	REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
}

static void
bnx2_enable_int(struct bnx2 *bp)
{
602 603
	int i;
	struct bnx2_napi *bnapi;
604

605 606
	for (i = 0; i < bp->irq_nvecs; i++) {
		bnapi = &bp->bnx2_napi[i];
607

608 609 610 611
		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
		       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
		       BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
		       bnapi->last_status_idx);
612

613 614 615 616
		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
		       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
		       bnapi->last_status_idx);
	}
617
	REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
618 619 620 621 622
}

static void
bnx2_disable_int_sync(struct bnx2 *bp)
{
623 624
	int i;

625
	atomic_inc(&bp->intr_sem);
626 627 628
	if (!netif_running(bp->dev))
		return;

629
	bnx2_disable_int(bp);
630 631
	for (i = 0; i < bp->irq_nvecs; i++)
		synchronize_irq(bp->irq_tbl[i].vector);
632 633
}

634 635 636
static void
bnx2_napi_disable(struct bnx2 *bp)
{
637 638 639 640
	int i;

	for (i = 0; i < bp->irq_nvecs; i++)
		napi_disable(&bp->bnx2_napi[i].napi);
641 642 643 644 645
}

static void
bnx2_napi_enable(struct bnx2 *bp)
{
646 647 648 649
	int i;

	for (i = 0; i < bp->irq_nvecs; i++)
		napi_enable(&bp->bnx2_napi[i].napi);
650 651
}

652 653 654
static void
bnx2_netif_stop(struct bnx2 *bp)
{
655
	bnx2_cnic_stop(bp);
656 657
	bnx2_disable_int_sync(bp);
	if (netif_running(bp->dev)) {
658
		bnx2_napi_disable(bp);
659 660 661 662 663 664 665 666 667 668
		netif_tx_disable(bp->dev);
		bp->dev->trans_start = jiffies;	/* prevent tx timeout */
	}
}

static void
bnx2_netif_start(struct bnx2 *bp)
{
	if (atomic_dec_and_test(&bp->intr_sem)) {
		if (netif_running(bp->dev)) {
669
			netif_tx_wake_all_queues(bp->dev);
670
			bnx2_napi_enable(bp);
671
			bnx2_enable_int(bp);
672
			bnx2_cnic_start(bp);
673 674 675 676
		}
	}
}

677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696
static void
bnx2_free_tx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_tx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;

		if (txr->tx_desc_ring) {
			pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
					    txr->tx_desc_ring,
					    txr->tx_desc_mapping);
			txr->tx_desc_ring = NULL;
		}
		kfree(txr->tx_buf_ring);
		txr->tx_buf_ring = NULL;
	}
}

697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713
static void
bnx2_free_rx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_rx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
		int j;

		for (j = 0; j < bp->rx_max_ring; j++) {
			if (rxr->rx_desc_ring[j])
				pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
						    rxr->rx_desc_ring[j],
						    rxr->rx_desc_mapping[j]);
			rxr->rx_desc_ring[j] = NULL;
		}
714
		vfree(rxr->rx_buf_ring);
715 716 717 718 719
		rxr->rx_buf_ring = NULL;

		for (j = 0; j < bp->rx_max_pg_ring; j++) {
			if (rxr->rx_pg_desc_ring[j])
				pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
720 721 722
						    rxr->rx_pg_desc_ring[j],
						    rxr->rx_pg_desc_mapping[j]);
			rxr->rx_pg_desc_ring[j] = NULL;
723
		}
724
		vfree(rxr->rx_pg_ring);
725 726 727 728
		rxr->rx_pg_ring = NULL;
	}
}

729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750
static int
bnx2_alloc_tx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_tx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;

		txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
		if (txr->tx_buf_ring == NULL)
			return -ENOMEM;

		txr->tx_desc_ring =
			pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
					     &txr->tx_desc_mapping);
		if (txr->tx_desc_ring == NULL)
			return -ENOMEM;
	}
	return 0;
}

751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799
static int
bnx2_alloc_rx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_rx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
		int j;

		rxr->rx_buf_ring =
			vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
		if (rxr->rx_buf_ring == NULL)
			return -ENOMEM;

		memset(rxr->rx_buf_ring, 0,
		       SW_RXBD_RING_SIZE * bp->rx_max_ring);

		for (j = 0; j < bp->rx_max_ring; j++) {
			rxr->rx_desc_ring[j] =
				pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
						     &rxr->rx_desc_mapping[j]);
			if (rxr->rx_desc_ring[j] == NULL)
				return -ENOMEM;

		}

		if (bp->rx_pg_ring_size) {
			rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
						  bp->rx_max_pg_ring);
			if (rxr->rx_pg_ring == NULL)
				return -ENOMEM;

			memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
			       bp->rx_max_pg_ring);
		}

		for (j = 0; j < bp->rx_max_pg_ring; j++) {
			rxr->rx_pg_desc_ring[j] =
				pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
						&rxr->rx_pg_desc_mapping[j]);
			if (rxr->rx_pg_desc_ring[j] == NULL)
				return -ENOMEM;

		}
	}
	return 0;
}

800 801 802
static void
bnx2_free_mem(struct bnx2 *bp)
{
803
	int i;
804
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
805

806
	bnx2_free_tx_mem(bp);
807
	bnx2_free_rx_mem(bp);
808

809 810 811 812 813 814 815 816
	for (i = 0; i < bp->ctx_pages; i++) {
		if (bp->ctx_blk[i]) {
			pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
					    bp->ctx_blk[i],
					    bp->ctx_blk_mapping[i]);
			bp->ctx_blk[i] = NULL;
		}
	}
817
	if (bnapi->status_blk.msi) {
818
		pci_free_consistent(bp->pdev, bp->status_stats_size,
819 820 821
				    bnapi->status_blk.msi,
				    bp->status_blk_mapping);
		bnapi->status_blk.msi = NULL;
822
		bp->stats_blk = NULL;
823 824 825 826 827 828
	}
}

static int
bnx2_alloc_mem(struct bnx2 *bp)
{
829
	int i, status_blk_size, err;
830 831
	struct bnx2_napi *bnapi;
	void *status_blk;
832

833 834
	/* Combine status and statistics blocks into one allocation. */
	status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
835
	if (bp->flags & BNX2_FLAG_MSIX_CAP)
836 837
		status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
						 BNX2_SBLK_MSIX_ALIGN_SIZE);
838 839 840
	bp->status_stats_size = status_blk_size +
				sizeof(struct statistics_block);

841 842 843
	status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
					  &bp->status_blk_mapping);
	if (status_blk == NULL)
844 845
		goto alloc_mem_err;

846
	memset(status_blk, 0, bp->status_stats_size);
847

848 849 850 851 852 853
	bnapi = &bp->bnx2_napi[0];
	bnapi->status_blk.msi = status_blk;
	bnapi->hw_tx_cons_ptr =
		&bnapi->status_blk.msi->status_tx_quick_consumer_index0;
	bnapi->hw_rx_cons_ptr =
		&bnapi->status_blk.msi->status_rx_quick_consumer_index0;
854
	if (bp->flags & BNX2_FLAG_MSIX_CAP) {
855
		for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
856 857 858
			struct status_block_msix *sblk;

			bnapi = &bp->bnx2_napi[i];
859

860 861 862 863 864 865 866
			sblk = (void *) (status_blk +
					 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
			bnapi->status_blk.msix = sblk;
			bnapi->hw_tx_cons_ptr =
				&sblk->status_tx_quick_consumer_index;
			bnapi->hw_rx_cons_ptr =
				&sblk->status_rx_quick_consumer_index;
867 868 869
			bnapi->int_num = i << 24;
		}
	}
870

871
	bp->stats_blk = status_blk + status_blk_size;
872

873
	bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
874

875 876 877 878 879 880 881 882 883 884 885 886
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
		if (bp->ctx_pages == 0)
			bp->ctx_pages = 1;
		for (i = 0; i < bp->ctx_pages; i++) {
			bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
						BCM_PAGE_SIZE,
						&bp->ctx_blk_mapping[i]);
			if (bp->ctx_blk[i] == NULL)
				goto alloc_mem_err;
		}
	}
887

888 889 890 891
	err = bnx2_alloc_rx_mem(bp);
	if (err)
		goto alloc_mem_err;

892 893 894 895
	err = bnx2_alloc_tx_mem(bp);
	if (err)
		goto alloc_mem_err;

896 897 898 899 900 901 902
	return 0;

alloc_mem_err:
	bnx2_free_mem(bp);
	return -ENOMEM;
}

903 904 905 906 907
static void
bnx2_report_fw_link(struct bnx2 *bp)
{
	u32 fw_link_status = 0;

908
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
909 910
		return;

911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945
	if (bp->link_up) {
		u32 bmsr;

		switch (bp->line_speed) {
		case SPEED_10:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_10HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_10FULL;
			break;
		case SPEED_100:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_100HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_100FULL;
			break;
		case SPEED_1000:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_1000HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_1000FULL;
			break;
		case SPEED_2500:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_2500HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_2500FULL;
			break;
		}

		fw_link_status |= BNX2_LINK_STATUS_LINK_UP;

		if (bp->autoneg) {
			fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;

946 947
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
948 949

			if (!(bmsr & BMSR_ANEGCOMPLETE) ||
950
			    bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
951 952 953 954 955 956 957 958
				fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
			else
				fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
		}
	}
	else
		fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;

959
	bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
960 961
}

962 963 964 965
static char *
bnx2_xceiver_str(struct bnx2 *bp)
{
	return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
966
		((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
967 968 969
		 "Copper"));
}

970 971 972 973 974
static void
bnx2_report_link(struct bnx2 *bp)
{
	if (bp->link_up) {
		netif_carrier_on(bp->dev);
975 976
		printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
		       bnx2_xceiver_str(bp));
977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999

		printk("%d Mbps ", bp->line_speed);

		if (bp->duplex == DUPLEX_FULL)
			printk("full duplex");
		else
			printk("half duplex");

		if (bp->flow_ctrl) {
			if (bp->flow_ctrl & FLOW_CTRL_RX) {
				printk(", receive ");
				if (bp->flow_ctrl & FLOW_CTRL_TX)
					printk("& transmit ");
			}
			else {
				printk(", transmit ");
			}
			printk("flow control ON");
		}
		printk("\n");
	}
	else {
		netif_carrier_off(bp->dev);
1000 1001
		printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
		       bnx2_xceiver_str(bp));
1002
	}
1003 1004

	bnx2_report_fw_link(bp);
1005 1006 1007 1008 1009 1010 1011 1012
}

static void
bnx2_resolve_flow_ctrl(struct bnx2 *bp)
{
	u32 local_adv, remote_adv;

	bp->flow_ctrl = 0;
1013
	if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025
		(AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {

		if (bp->duplex == DUPLEX_FULL) {
			bp->flow_ctrl = bp->req_flow_ctrl;
		}
		return;
	}

	if (bp->duplex != DUPLEX_FULL) {
		return;
	}

1026
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037
	    (CHIP_NUM(bp) == CHIP_NUM_5708)) {
		u32 val;

		bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
		if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
			bp->flow_ctrl |= FLOW_CTRL_TX;
		if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
			bp->flow_ctrl |= FLOW_CTRL_RX;
		return;
	}

1038 1039
	bnx2_read_phy(bp, bp->mii_adv, &local_adv);
	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1040

1041
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082
		u32 new_local_adv = 0;
		u32 new_remote_adv = 0;

		if (local_adv & ADVERTISE_1000XPAUSE)
			new_local_adv |= ADVERTISE_PAUSE_CAP;
		if (local_adv & ADVERTISE_1000XPSE_ASYM)
			new_local_adv |= ADVERTISE_PAUSE_ASYM;
		if (remote_adv & ADVERTISE_1000XPAUSE)
			new_remote_adv |= ADVERTISE_PAUSE_CAP;
		if (remote_adv & ADVERTISE_1000XPSE_ASYM)
			new_remote_adv |= ADVERTISE_PAUSE_ASYM;

		local_adv = new_local_adv;
		remote_adv = new_remote_adv;
	}

	/* See Table 28B-3 of 802.3ab-1999 spec. */
	if (local_adv & ADVERTISE_PAUSE_CAP) {
		if(local_adv & ADVERTISE_PAUSE_ASYM) {
	                if (remote_adv & ADVERTISE_PAUSE_CAP) {
				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
			}
			else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
				bp->flow_ctrl = FLOW_CTRL_RX;
			}
		}
		else {
			if (remote_adv & ADVERTISE_PAUSE_CAP) {
				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
			}
		}
	}
	else if (local_adv & ADVERTISE_PAUSE_ASYM) {
		if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
			(remote_adv & ADVERTISE_PAUSE_ASYM)) {

			bp->flow_ctrl = FLOW_CTRL_TX;
		}
	}
}

1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121
static int
bnx2_5709s_linkup(struct bnx2 *bp)
{
	u32 val, speed;

	bp->link_up = 1;

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
	bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

	if ((bp->autoneg & AUTONEG_SPEED) == 0) {
		bp->line_speed = bp->req_line_speed;
		bp->duplex = bp->req_duplex;
		return 0;
	}
	speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
	switch (speed) {
		case MII_BNX2_GP_TOP_AN_SPEED_10:
			bp->line_speed = SPEED_10;
			break;
		case MII_BNX2_GP_TOP_AN_SPEED_100:
			bp->line_speed = SPEED_100;
			break;
		case MII_BNX2_GP_TOP_AN_SPEED_1G:
		case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
			bp->line_speed = SPEED_1000;
			break;
		case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
			bp->line_speed = SPEED_2500;
			break;
	}
	if (val & MII_BNX2_GP_TOP_AN_FD)
		bp->duplex = DUPLEX_FULL;
	else
		bp->duplex = DUPLEX_HALF;
	return 0;
}

1122
static int
1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152
bnx2_5708s_linkup(struct bnx2 *bp)
{
	u32 val;

	bp->link_up = 1;
	bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
	switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
		case BCM5708S_1000X_STAT1_SPEED_10:
			bp->line_speed = SPEED_10;
			break;
		case BCM5708S_1000X_STAT1_SPEED_100:
			bp->line_speed = SPEED_100;
			break;
		case BCM5708S_1000X_STAT1_SPEED_1G:
			bp->line_speed = SPEED_1000;
			break;
		case BCM5708S_1000X_STAT1_SPEED_2G5:
			bp->line_speed = SPEED_2500;
			break;
	}
	if (val & BCM5708S_1000X_STAT1_FD)
		bp->duplex = DUPLEX_FULL;
	else
		bp->duplex = DUPLEX_HALF;

	return 0;
}

static int
bnx2_5706s_linkup(struct bnx2 *bp)
1153 1154 1155 1156 1157 1158
{
	u32 bmcr, local_adv, remote_adv, common;

	bp->link_up = 1;
	bp->line_speed = SPEED_1000;

1159
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
	if (bmcr & BMCR_FULLDPLX) {
		bp->duplex = DUPLEX_FULL;
	}
	else {
		bp->duplex = DUPLEX_HALF;
	}

	if (!(bmcr & BMCR_ANENABLE)) {
		return 0;
	}

1171 1172
	bnx2_read_phy(bp, bp->mii_adv, &local_adv);
	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192

	common = local_adv & remote_adv;
	if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {

		if (common & ADVERTISE_1000XFULL) {
			bp->duplex = DUPLEX_FULL;
		}
		else {
			bp->duplex = DUPLEX_HALF;
		}
	}

	return 0;
}

static int
bnx2_copper_linkup(struct bnx2 *bp)
{
	u32 bmcr;

1193
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
	if (bmcr & BMCR_ANENABLE) {
		u32 local_adv, remote_adv, common;

		bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
		bnx2_read_phy(bp, MII_STAT1000, &remote_adv);

		common = local_adv & (remote_adv >> 2);
		if (common & ADVERTISE_1000FULL) {
			bp->line_speed = SPEED_1000;
			bp->duplex = DUPLEX_FULL;
		}
		else if (common & ADVERTISE_1000HALF) {
			bp->line_speed = SPEED_1000;
			bp->duplex = DUPLEX_HALF;
		}
		else {
1210 1211
			bnx2_read_phy(bp, bp->mii_adv, &local_adv);
			bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253

			common = local_adv & remote_adv;
			if (common & ADVERTISE_100FULL) {
				bp->line_speed = SPEED_100;
				bp->duplex = DUPLEX_FULL;
			}
			else if (common & ADVERTISE_100HALF) {
				bp->line_speed = SPEED_100;
				bp->duplex = DUPLEX_HALF;
			}
			else if (common & ADVERTISE_10FULL) {
				bp->line_speed = SPEED_10;
				bp->duplex = DUPLEX_FULL;
			}
			else if (common & ADVERTISE_10HALF) {
				bp->line_speed = SPEED_10;
				bp->duplex = DUPLEX_HALF;
			}
			else {
				bp->line_speed = 0;
				bp->link_up = 0;
			}
		}
	}
	else {
		if (bmcr & BMCR_SPEED100) {
			bp->line_speed = SPEED_100;
		}
		else {
			bp->line_speed = SPEED_10;
		}
		if (bmcr & BMCR_FULLDPLX) {
			bp->duplex = DUPLEX_FULL;
		}
		else {
			bp->duplex = DUPLEX_HALF;
		}
	}

	return 0;
}

1254
static void
1255
bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1256
{
1257
	u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289

	val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
	val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
	val |= 0x02 << 8;

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		u32 lo_water, hi_water;

		if (bp->flow_ctrl & FLOW_CTRL_TX)
			lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
		else
			lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
		if (lo_water >= bp->rx_ring_size)
			lo_water = 0;

		hi_water = bp->rx_ring_size / 4;

		if (hi_water <= lo_water)
			lo_water = 0;

		hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
		lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;

		if (hi_water > 0xf)
			hi_water = 0xf;
		else if (hi_water == 0)
			lo_water = 0;
		val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
	}
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
}

1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302
static void
bnx2_init_all_rx_contexts(struct bnx2 *bp)
{
	int i;
	u32 cid;

	for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
		if (i == 1)
			cid = RX_RSS_CID;
		bnx2_init_rx_context(bp, cid);
	}
}

1303
static void
1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317
bnx2_set_mac_link(struct bnx2 *bp)
{
	u32 val;

	REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
	if (bp->link_up && (bp->line_speed == SPEED_1000) &&
		(bp->duplex == DUPLEX_HALF)) {
		REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
	}

	/* Configure the EMAC mode register. */
	val = REG_RD(bp, BNX2_EMAC_MODE);

	val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1318
		BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1319
		BNX2_EMAC_MODE_25G_MODE);
1320 1321

	if (bp->link_up) {
1322 1323
		switch (bp->line_speed) {
			case SPEED_10:
1324 1325
				if (CHIP_NUM(bp) != CHIP_NUM_5706) {
					val |= BNX2_EMAC_MODE_PORT_MII_10M;
1326 1327 1328 1329 1330 1331 1332
					break;
				}
				/* fall through */
			case SPEED_100:
				val |= BNX2_EMAC_MODE_PORT_MII;
				break;
			case SPEED_2500:
1333
				val |= BNX2_EMAC_MODE_25G_MODE;
1334 1335 1336 1337 1338
				/* fall through */
			case SPEED_1000:
				val |= BNX2_EMAC_MODE_PORT_GMII;
				break;
		}
1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366
	}
	else {
		val |= BNX2_EMAC_MODE_PORT_GMII;
	}

	/* Set the MAC to operate in the appropriate duplex mode. */
	if (bp->duplex == DUPLEX_HALF)
		val |= BNX2_EMAC_MODE_HALF_DUPLEX;
	REG_WR(bp, BNX2_EMAC_MODE, val);

	/* Enable/disable rx PAUSE. */
	bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;

	if (bp->flow_ctrl & FLOW_CTRL_RX)
		bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
	REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);

	/* Enable/disable tx PAUSE. */
	val = REG_RD(bp, BNX2_EMAC_TX_MODE);
	val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;

	if (bp->flow_ctrl & FLOW_CTRL_TX)
		val |= BNX2_EMAC_TX_MODE_FLOW_EN;
	REG_WR(bp, BNX2_EMAC_TX_MODE, val);

	/* Acknowledge the interrupt. */
	REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);

1367
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
1368
		bnx2_init_all_rx_contexts(bp);
1369 1370
}

1371 1372 1373
static void
bnx2_enable_bmsr1(struct bnx2 *bp)
{
1374
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1375 1376 1377 1378 1379 1380 1381 1382
	    (CHIP_NUM(bp) == CHIP_NUM_5709))
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_GP_STATUS);
}

static void
bnx2_disable_bmsr1(struct bnx2 *bp)
{
1383
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1384 1385 1386 1387 1388
	    (CHIP_NUM(bp) == CHIP_NUM_5709))
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
}

1389 1390 1391 1392 1393 1394
static int
bnx2_test_and_enable_2g5(struct bnx2 *bp)
{
	u32 up1;
	int ret = 1;

1395
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1396 1397 1398 1399 1400
		return 0;

	if (bp->autoneg & AUTONEG_SPEED)
		bp->advertising |= ADVERTISED_2500baseX_Full;

1401 1402 1403
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);

1404 1405 1406 1407 1408 1409 1410
	bnx2_read_phy(bp, bp->mii_up1, &up1);
	if (!(up1 & BCM5708S_UP1_2G5)) {
		up1 |= BCM5708S_UP1_2G5;
		bnx2_write_phy(bp, bp->mii_up1, up1);
		ret = 0;
	}

1411 1412 1413 1414
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

1415 1416 1417 1418 1419 1420 1421 1422 1423
	return ret;
}

static int
bnx2_test_and_disable_2g5(struct bnx2 *bp)
{
	u32 up1;
	int ret = 0;

1424
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1425 1426
		return 0;

1427 1428 1429
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);

1430 1431 1432 1433 1434 1435 1436
	bnx2_read_phy(bp, bp->mii_up1, &up1);
	if (up1 & BCM5708S_UP1_2G5) {
		up1 &= ~BCM5708S_UP1_2G5;
		bnx2_write_phy(bp, bp->mii_up1, up1);
		ret = 1;
	}

1437 1438 1439 1440
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

1441 1442 1443 1444 1445 1446 1447 1448
	return ret;
}

static void
bnx2_enable_forced_2g5(struct bnx2 *bp)
{
	u32 bmcr;

1449
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1450 1451
		return;

1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		u32 val;

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_SERDES_DIG);
		bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
		val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
		val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
		bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);

	} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
		bmcr |= BCM5708S_BMCR_FORCE_2500;
	}

	if (bp->autoneg & AUTONEG_SPEED) {
		bmcr &= ~BMCR_ANENABLE;
		if (bp->req_duplex == DUPLEX_FULL)
			bmcr |= BMCR_FULLDPLX;
	}
	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
}

static void
bnx2_disable_forced_2g5(struct bnx2 *bp)
{
	u32 bmcr;

1484
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1485 1486
		return;

1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		u32 val;

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_SERDES_DIG);
		bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
		val &= ~MII_BNX2_SD_MISC1_FORCE;
		bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);

	} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1501 1502 1503 1504 1505 1506 1507 1508 1509
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
		bmcr &= ~BCM5708S_BMCR_FORCE_2500;
	}

	if (bp->autoneg & AUTONEG_SPEED)
		bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
}

1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522
static void
bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
{
	u32 val;

	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
	if (start)
		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
	else
		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
}

1523 1524 1525 1526 1527 1528
static int
bnx2_set_link(struct bnx2 *bp)
{
	u32 bmsr;
	u8 link_up;

1529
	if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1530 1531 1532 1533
		bp->link_up = 1;
		return 0;
	}

1534
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1535 1536
		return 0;

1537 1538
	link_up = bp->link_up;

1539 1540 1541 1542
	bnx2_enable_bmsr1(bp);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_disable_bmsr1(bp);
1543

1544
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1545
	    (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1546
		u32 val, an_dbg;
1547

1548
		if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1549
			bnx2_5706s_force_link_dn(bp, 0);
1550
			bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1551
		}
1552
		val = REG_RD(bp, BNX2_EMAC_STATUS);
1553 1554 1555 1556 1557 1558 1559

		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);

		if ((val & BNX2_EMAC_STATUS_LINK) &&
		    !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1560 1561 1562 1563 1564 1565 1566 1567
			bmsr |= BMSR_LSTATUS;
		else
			bmsr &= ~BMSR_LSTATUS;
	}

	if (bmsr & BMSR_LSTATUS) {
		bp->link_up = 1;

1568
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1569 1570 1571 1572
			if (CHIP_NUM(bp) == CHIP_NUM_5706)
				bnx2_5706s_linkup(bp);
			else if (CHIP_NUM(bp) == CHIP_NUM_5708)
				bnx2_5708s_linkup(bp);
1573 1574
			else if (CHIP_NUM(bp) == CHIP_NUM_5709)
				bnx2_5709s_linkup(bp);
1575 1576 1577 1578 1579 1580 1581
		}
		else {
			bnx2_copper_linkup(bp);
		}
		bnx2_resolve_flow_ctrl(bp);
	}
	else {
1582
		if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1583 1584
		    (bp->autoneg & AUTONEG_SPEED))
			bnx2_disable_forced_2g5(bp);
1585

1586
		if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1587 1588 1589 1590 1591 1592
			u32 bmcr;

			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
			bmcr |= BMCR_ANENABLE;
			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);

1593
			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1594
		}
1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612
		bp->link_up = 0;
	}

	if (bp->link_up != link_up) {
		bnx2_report_link(bp);
	}

	bnx2_set_mac_link(bp);

	return 0;
}

static int
bnx2_reset_phy(struct bnx2 *bp)
{
	int i;
	u32 reg;

1613
        bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1614 1615 1616 1617 1618

#define PHY_RESET_MAX_WAIT 100
	for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
		udelay(10);

1619
		bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638
		if (!(reg & BMCR_RESET)) {
			udelay(20);
			break;
		}
	}
	if (i == PHY_RESET_MAX_WAIT) {
		return -EBUSY;
	}
	return 0;
}

static u32
bnx2_phy_get_pause_adv(struct bnx2 *bp)
{
	u32 adv = 0;

	if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
		(FLOW_CTRL_RX | FLOW_CTRL_TX)) {

1639
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1640 1641 1642 1643 1644 1645 1646
			adv = ADVERTISE_1000XPAUSE;
		}
		else {
			adv = ADVERTISE_PAUSE_CAP;
		}
	}
	else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1647
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1648 1649 1650 1651 1652 1653 1654
			adv = ADVERTISE_1000XPSE_ASYM;
		}
		else {
			adv = ADVERTISE_PAUSE_ASYM;
		}
	}
	else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1655
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1656 1657 1658 1659 1660 1661 1662 1663 1664
			adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
		}
		else {
			adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
		}
	}
	return adv;
}

1665
static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1666

1667
static int
1668
bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1669 1670
__releases(&bp->phy_lock)
__acquires(&bp->phy_lock)
1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709
{
	u32 speed_arg = 0, pause_adv;

	pause_adv = bnx2_phy_get_pause_adv(bp);

	if (bp->autoneg & AUTONEG_SPEED) {
		speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
		if (bp->advertising & ADVERTISED_10baseT_Half)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
		if (bp->advertising & ADVERTISED_10baseT_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
		if (bp->advertising & ADVERTISED_100baseT_Half)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
		if (bp->advertising & ADVERTISED_100baseT_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
		if (bp->advertising & ADVERTISED_1000baseT_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
		if (bp->advertising & ADVERTISED_2500baseX_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
	} else {
		if (bp->req_line_speed == SPEED_2500)
			speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
		else if (bp->req_line_speed == SPEED_1000)
			speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
		else if (bp->req_line_speed == SPEED_100) {
			if (bp->req_duplex == DUPLEX_FULL)
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
			else
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
		} else if (bp->req_line_speed == SPEED_10) {
			if (bp->req_duplex == DUPLEX_FULL)
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
			else
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
		}
	}

	if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
		speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1710
	if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1711 1712 1713 1714 1715 1716
		speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;

	if (port == PORT_TP)
		speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
			     BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;

1717
	bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1718 1719

	spin_unlock_bh(&bp->phy_lock);
1720
	bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1721 1722 1723 1724 1725 1726 1727
	spin_lock_bh(&bp->phy_lock);

	return 0;
}

static int
bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1728 1729
__releases(&bp->phy_lock)
__acquires(&bp->phy_lock)
1730
{
1731
	u32 adv, bmcr;
1732 1733
	u32 new_adv = 0;

1734
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1735 1736
		return (bnx2_setup_remote_phy(bp, port));

1737 1738
	if (!(bp->autoneg & AUTONEG_SPEED)) {
		u32 new_bmcr;
1739 1740
		int force_link_down = 0;

1741 1742 1743 1744 1745 1746 1747
		if (bp->req_line_speed == SPEED_2500) {
			if (!bnx2_test_and_enable_2g5(bp))
				force_link_down = 1;
		} else if (bp->req_line_speed == SPEED_1000) {
			if (bnx2_test_and_disable_2g5(bp))
				force_link_down = 1;
		}
1748
		bnx2_read_phy(bp, bp->mii_adv, &adv);
1749 1750
		adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);

1751
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1752
		new_bmcr = bmcr & ~BMCR_ANENABLE;
1753
		new_bmcr |= BMCR_SPEED1000;
1754

1755 1756 1757 1758 1759 1760 1761 1762 1763
		if (CHIP_NUM(bp) == CHIP_NUM_5709) {
			if (bp->req_line_speed == SPEED_2500)
				bnx2_enable_forced_2g5(bp);
			else if (bp->req_line_speed == SPEED_1000) {
				bnx2_disable_forced_2g5(bp);
				new_bmcr &= ~0x2000;
			}

		} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1764 1765 1766 1767
			if (bp->req_line_speed == SPEED_2500)
				new_bmcr |= BCM5708S_BMCR_FORCE_2500;
			else
				new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1768 1769
		}

1770
		if (bp->req_duplex == DUPLEX_FULL) {
1771
			adv |= ADVERTISE_1000XFULL;
1772 1773 1774
			new_bmcr |= BMCR_FULLDPLX;
		}
		else {
1775
			adv |= ADVERTISE_1000XHALF;
1776 1777
			new_bmcr &= ~BMCR_FULLDPLX;
		}
1778
		if ((new_bmcr != bmcr) || (force_link_down)) {
1779 1780
			/* Force a link down visible on the other side */
			if (bp->link_up) {
1781
				bnx2_write_phy(bp, bp->mii_adv, adv &
1782 1783
					       ~(ADVERTISE_1000XFULL |
						 ADVERTISE_1000XHALF));
1784
				bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1785 1786 1787 1788
					BMCR_ANRESTART | BMCR_ANENABLE);

				bp->link_up = 0;
				netif_carrier_off(bp->dev);
1789
				bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1790
				bnx2_report_link(bp);
1791
			}
1792 1793
			bnx2_write_phy(bp, bp->mii_adv, adv);
			bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1794 1795 1796
		} else {
			bnx2_resolve_flow_ctrl(bp);
			bnx2_set_mac_link(bp);
1797 1798 1799 1800
		}
		return 0;
	}

1801
	bnx2_test_and_enable_2g5(bp);
1802

1803 1804 1805 1806 1807
	if (bp->advertising & ADVERTISED_1000baseT_Full)
		new_adv |= ADVERTISE_1000XFULL;

	new_adv |= bnx2_phy_get_pause_adv(bp);

1808 1809
	bnx2_read_phy(bp, bp->mii_adv, &adv);
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1810 1811 1812 1813 1814

	bp->serdes_an_pending = 0;
	if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
		/* Force a link down visible on the other side */
		if (bp->link_up) {
1815
			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1816 1817 1818
			spin_unlock_bh(&bp->phy_lock);
			msleep(20);
			spin_lock_bh(&bp->phy_lock);
1819 1820
		}

1821 1822
		bnx2_write_phy(bp, bp->mii_adv, new_adv);
		bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1823
			BMCR_ANENABLE);
1824 1825 1826 1827 1828 1829 1830 1831
		/* Speed up link-up time when the link partner
		 * does not autonegotiate which is very common
		 * in blade servers. Some blade servers use
		 * IPMI for kerboard input and it's important
		 * to minimize link disruptions. Autoneg. involves
		 * exchanging base pages plus 3 next pages and
		 * normally completes in about 120 msec.
		 */
1832
		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1833 1834
		bp->serdes_an_pending = 1;
		mod_timer(&bp->timer, jiffies + bp->current_interval);
1835 1836 1837
	} else {
		bnx2_resolve_flow_ctrl(bp);
		bnx2_set_mac_link(bp);
1838 1839 1840 1841 1842 1843
	}

	return 0;
}

#define ETHTOOL_ALL_FIBRE_SPEED						\
1844
	(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?			\
1845 1846
		(ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
		(ADVERTISED_1000baseT_Full)
1847 1848 1849 1850 1851 1852 1853 1854

#define ETHTOOL_ALL_COPPER_SPEED					\
	(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |		\
	ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |		\
	ADVERTISED_1000baseT_Full)

#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
	ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1855

1856 1857
#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)

1858 1859 1860 1861 1862 1863
static void
bnx2_set_default_remote_link(struct bnx2 *bp)
{
	u32 link;

	if (bp->phy_port == PORT_TP)
1864
		link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1865
	else
1866
		link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904

	if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
		bp->req_line_speed = 0;
		bp->autoneg |= AUTONEG_SPEED;
		bp->advertising = ADVERTISED_Autoneg;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
			bp->advertising |= ADVERTISED_10baseT_Half;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
			bp->advertising |= ADVERTISED_10baseT_Full;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
			bp->advertising |= ADVERTISED_100baseT_Half;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
			bp->advertising |= ADVERTISED_100baseT_Full;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
			bp->advertising |= ADVERTISED_1000baseT_Full;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
			bp->advertising |= ADVERTISED_2500baseX_Full;
	} else {
		bp->autoneg = 0;
		bp->advertising = 0;
		bp->req_duplex = DUPLEX_FULL;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
			bp->req_line_speed = SPEED_10;
			if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
				bp->req_duplex = DUPLEX_HALF;
		}
		if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
			bp->req_line_speed = SPEED_100;
			if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
				bp->req_duplex = DUPLEX_HALF;
		}
		if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
			bp->req_line_speed = SPEED_1000;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
			bp->req_line_speed = SPEED_2500;
	}
}

1905 1906 1907
static void
bnx2_set_default_link(struct bnx2 *bp)
{
1908 1909 1910 1911
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
		bnx2_set_default_remote_link(bp);
		return;
	}
1912

1913 1914
	bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
	bp->req_line_speed = 0;
1915
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1916 1917 1918 1919
		u32 reg;

		bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;

1920
		reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1921 1922 1923 1924 1925 1926 1927 1928 1929 1930
		reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
		if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
			bp->autoneg = 0;
			bp->req_line_speed = bp->line_speed = SPEED_1000;
			bp->req_duplex = DUPLEX_FULL;
		}
	} else
		bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
}

1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944
static void
bnx2_send_heart_beat(struct bnx2 *bp)
{
	u32 msg;
	u32 addr;

	spin_lock(&bp->indirect_lock);
	msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
	addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
	spin_unlock(&bp->indirect_lock);
}

1945 1946 1947 1948 1949 1950 1951
static void
bnx2_remote_phy_event(struct bnx2 *bp)
{
	u32 msg;
	u8 link_up = bp->link_up;
	u8 old_port;

1952
	msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1953

1954 1955 1956 1957 1958
	if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
		bnx2_send_heart_beat(bp);

	msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;

1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026
	if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
		bp->link_up = 0;
	else {
		u32 speed;

		bp->link_up = 1;
		speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
		bp->duplex = DUPLEX_FULL;
		switch (speed) {
			case BNX2_LINK_STATUS_10HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_10FULL:
				bp->line_speed = SPEED_10;
				break;
			case BNX2_LINK_STATUS_100HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_100BASE_T4:
			case BNX2_LINK_STATUS_100FULL:
				bp->line_speed = SPEED_100;
				break;
			case BNX2_LINK_STATUS_1000HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_1000FULL:
				bp->line_speed = SPEED_1000;
				break;
			case BNX2_LINK_STATUS_2500HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_2500FULL:
				bp->line_speed = SPEED_2500;
				break;
			default:
				bp->line_speed = 0;
				break;
		}

		bp->flow_ctrl = 0;
		if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
		    (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
			if (bp->duplex == DUPLEX_FULL)
				bp->flow_ctrl = bp->req_flow_ctrl;
		} else {
			if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
				bp->flow_ctrl |= FLOW_CTRL_TX;
			if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
				bp->flow_ctrl |= FLOW_CTRL_RX;
		}

		old_port = bp->phy_port;
		if (msg & BNX2_LINK_STATUS_SERDES_LINK)
			bp->phy_port = PORT_FIBRE;
		else
			bp->phy_port = PORT_TP;

		if (old_port != bp->phy_port)
			bnx2_set_default_link(bp);

	}
	if (bp->link_up != link_up)
		bnx2_report_link(bp);

	bnx2_set_mac_link(bp);
}

static int
bnx2_set_remote_link(struct bnx2 *bp)
{
	u32 evt_code;

2027
	evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2028 2029 2030 2031 2032 2033
	switch (evt_code) {
		case BNX2_FW_EVT_CODE_LINK_EVENT:
			bnx2_remote_phy_event(bp);
			break;
		case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
		default:
2034
			bnx2_send_heart_beat(bp);
2035 2036 2037 2038 2039
			break;
	}
	return 0;
}

2040 2041
static int
bnx2_setup_copper_phy(struct bnx2 *bp)
2042 2043
__releases(&bp->phy_lock)
__acquires(&bp->phy_lock)
2044 2045 2046 2047
{
	u32 bmcr;
	u32 new_bmcr;

2048
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2049 2050 2051 2052 2053 2054

	if (bp->autoneg & AUTONEG_SPEED) {
		u32 adv_reg, adv1000_reg;
		u32 new_adv_reg = 0;
		u32 new_adv1000_reg = 0;

2055
		bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071
		adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
			ADVERTISE_PAUSE_ASYM);

		bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
		adv1000_reg &= PHY_ALL_1000_SPEED;

		if (bp->advertising & ADVERTISED_10baseT_Half)
			new_adv_reg |= ADVERTISE_10HALF;
		if (bp->advertising & ADVERTISED_10baseT_Full)
			new_adv_reg |= ADVERTISE_10FULL;
		if (bp->advertising & ADVERTISED_100baseT_Half)
			new_adv_reg |= ADVERTISE_100HALF;
		if (bp->advertising & ADVERTISED_100baseT_Full)
			new_adv_reg |= ADVERTISE_100FULL;
		if (bp->advertising & ADVERTISED_1000baseT_Full)
			new_adv1000_reg |= ADVERTISE_1000FULL;
2072

2073 2074 2075 2076 2077 2078 2079 2080
		new_adv_reg |= ADVERTISE_CSMA;

		new_adv_reg |= bnx2_phy_get_pause_adv(bp);

		if ((adv1000_reg != new_adv1000_reg) ||
			(adv_reg != new_adv_reg) ||
			((bmcr & BMCR_ANENABLE) == 0)) {

2081
			bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2082
			bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2083
			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105
				BMCR_ANENABLE);
		}
		else if (bp->link_up) {
			/* Flow ctrl may have changed from auto to forced */
			/* or vice-versa. */

			bnx2_resolve_flow_ctrl(bp);
			bnx2_set_mac_link(bp);
		}
		return 0;
	}

	new_bmcr = 0;
	if (bp->req_line_speed == SPEED_100) {
		new_bmcr |= BMCR_SPEED100;
	}
	if (bp->req_duplex == DUPLEX_FULL) {
		new_bmcr |= BMCR_FULLDPLX;
	}
	if (new_bmcr != bmcr) {
		u32 bmsr;

2106 2107
		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2108

2109 2110
		if (bmsr & BMSR_LSTATUS) {
			/* Force link down */
2111
			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2112 2113 2114 2115
			spin_unlock_bh(&bp->phy_lock);
			msleep(50);
			spin_lock_bh(&bp->phy_lock);

2116 2117
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2118 2119
		}

2120
		bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131

		/* Normally, the new speed is setup after the link has
		 * gone down and up again. In some cases, link will not go
		 * down so we need to set up the new speed here.
		 */
		if (bmsr & BMSR_LSTATUS) {
			bp->line_speed = bp->req_line_speed;
			bp->duplex = bp->req_duplex;
			bnx2_resolve_flow_ctrl(bp);
			bnx2_set_mac_link(bp);
		}
2132 2133 2134
	} else {
		bnx2_resolve_flow_ctrl(bp);
		bnx2_set_mac_link(bp);
2135 2136 2137 2138 2139
	}
	return 0;
}

static int
2140
bnx2_setup_phy(struct bnx2 *bp, u8 port)
2141 2142
__releases(&bp->phy_lock)
__acquires(&bp->phy_lock)
2143 2144 2145 2146
{
	if (bp->loopback == MAC_LOOPBACK)
		return 0;

2147
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2148
		return (bnx2_setup_serdes_phy(bp, port));
2149 2150 2151 2152 2153 2154
	}
	else {
		return (bnx2_setup_copper_phy(bp));
	}
}

2155
static int
2156
bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170
{
	u32 val;

	bp->mii_bmcr = MII_BMCR + 0x10;
	bp->mii_bmsr = MII_BMSR + 0x10;
	bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
	bp->mii_adv = MII_ADVERTISE + 0x10;
	bp->mii_lpa = MII_LPA + 0x10;
	bp->mii_up1 = MII_BNX2_OVER1G_UP1;

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
	bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2171 2172
	if (reset_phy)
		bnx2_reset_phy(bp);
2173 2174 2175 2176 2177 2178 2179 2180 2181 2182

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);

	bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
	val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
	val |= MII_BNX2_SD_1000XCTL1_FIBER;
	bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
	bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2183
	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204
		val |= BCM5708S_UP1_2G5;
	else
		val &= ~BCM5708S_UP1_2G5;
	bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
	bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
	val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
	bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);

	val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
	      MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
	bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

	return 0;
}

2205
static int
2206
bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2207 2208 2209
{
	u32 val;

2210 2211
	if (reset_phy)
		bnx2_reset_phy(bp);
2212 2213 2214

	bp->mii_up1 = BCM5708S_UP1;

2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226
	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
	bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);

	bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
	val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
	bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);

	bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
	val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
	bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);

2227
	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2228 2229 2230 2231 2232 2233
		bnx2_read_phy(bp, BCM5708S_UP1, &val);
		val |= BCM5708S_UP1_2G5;
		bnx2_write_phy(bp, BCM5708S_UP1, val);
	}

	if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
M
Michael Chan 已提交
2234 2235
	    (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2236 2237 2238 2239 2240 2241 2242 2243 2244
		/* increase tx signal amplitude */
		bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
			       BCM5708S_BLK_ADDR_TX_MISC);
		bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
		val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
		bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
		bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
	}

2245
	val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2246 2247 2248 2249 2250
	      BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;

	if (val) {
		u32 is_backplane;

2251
		is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263
		if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
				       BCM5708S_BLK_ADDR_TX_MISC);
			bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
				       BCM5708S_BLK_ADDR_DIG);
		}
	}
	return 0;
}

static int
2264
bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2265
{
2266 2267
	if (reset_phy)
		bnx2_reset_phy(bp);
2268

2269
	bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2270

2271 2272
	if (CHIP_NUM(bp) == CHIP_NUM_5706)
        	REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301

	if (bp->dev->mtu > 1500) {
		u32 val;

		/* Set extended packet length bit */
		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);

		bnx2_write_phy(bp, 0x1c, 0x6c00);
		bnx2_read_phy(bp, 0x1c, &val);
		bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
	}
	else {
		u32 val;

		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, val & ~0x4007);

		bnx2_write_phy(bp, 0x1c, 0x6c00);
		bnx2_read_phy(bp, 0x1c, &val);
		bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
	}

	return 0;
}

static int
2302
bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2303
{
2304 2305
	u32 val;

2306 2307
	if (reset_phy)
		bnx2_reset_phy(bp);
2308

2309
	if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2310 2311 2312 2313 2314 2315 2316 2317 2318 2319
		bnx2_write_phy(bp, 0x18, 0x0c00);
		bnx2_write_phy(bp, 0x17, 0x000a);
		bnx2_write_phy(bp, 0x15, 0x310b);
		bnx2_write_phy(bp, 0x17, 0x201f);
		bnx2_write_phy(bp, 0x15, 0x9506);
		bnx2_write_phy(bp, 0x17, 0x401f);
		bnx2_write_phy(bp, 0x15, 0x14e2);
		bnx2_write_phy(bp, 0x18, 0x0400);
	}

2320
	if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2321 2322 2323 2324 2325 2326 2327
		bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
			       MII_BNX2_DSP_EXPAND_REG | 0x8);
		bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
		val &= ~(1 << 8);
		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
	}

2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345
	if (bp->dev->mtu > 1500) {
		/* Set extended packet length bit */
		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, val | 0x4000);

		bnx2_read_phy(bp, 0x10, &val);
		bnx2_write_phy(bp, 0x10, val | 0x1);
	}
	else {
		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, val & ~0x4007);

		bnx2_read_phy(bp, 0x10, &val);
		bnx2_write_phy(bp, 0x10, val & ~0x1);
	}

2346 2347 2348 2349
	/* ethernet@wirespeed */
	bnx2_write_phy(bp, 0x18, 0x7007);
	bnx2_read_phy(bp, 0x18, &val);
	bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2350 2351 2352 2353 2354
	return 0;
}


static int
2355
bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2356 2357
__releases(&bp->phy_lock)
__acquires(&bp->phy_lock)
2358 2359 2360 2361
{
	u32 val;
	int rc = 0;

2362 2363
	bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
	bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2364

2365 2366
	bp->mii_bmcr = MII_BMCR;
	bp->mii_bmsr = MII_BMSR;
2367
	bp->mii_bmsr1 = MII_BMSR;
2368 2369 2370
	bp->mii_adv = MII_ADVERTISE;
	bp->mii_lpa = MII_LPA;

2371 2372
        REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);

2373
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2374 2375
		goto setup_phy;

2376 2377 2378 2379 2380
	bnx2_read_phy(bp, MII_PHYSID1, &val);
	bp->phy_id = val << 16;
	bnx2_read_phy(bp, MII_PHYSID2, &val);
	bp->phy_id |= val & 0xffff;

2381
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2382
		if (CHIP_NUM(bp) == CHIP_NUM_5706)
2383
			rc = bnx2_init_5706s_phy(bp, reset_phy);
2384
		else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2385
			rc = bnx2_init_5708s_phy(bp, reset_phy);
2386
		else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2387
			rc = bnx2_init_5709s_phy(bp, reset_phy);
2388 2389
	}
	else {
2390
		rc = bnx2_init_copper_phy(bp, reset_phy);
2391 2392
	}

2393 2394 2395
setup_phy:
	if (!rc)
		rc = bnx2_setup_phy(bp, bp->phy_port);
2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412

	return rc;
}

static int
bnx2_set_mac_loopback(struct bnx2 *bp)
{
	u32 mac_mode;

	mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
	mac_mode &= ~BNX2_EMAC_MODE_PORT;
	mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
	REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
	bp->link_up = 1;
	return 0;
}

2413 2414 2415 2416 2417 2418 2419 2420 2421
static int bnx2_test_link(struct bnx2 *);

static int
bnx2_set_phy_loopback(struct bnx2 *bp)
{
	u32 mac_mode;
	int rc, i;

	spin_lock_bh(&bp->phy_lock);
2422
	rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2423 2424 2425 2426 2427 2428 2429 2430
			    BMCR_SPEED1000);
	spin_unlock_bh(&bp->phy_lock);
	if (rc)
		return rc;

	for (i = 0; i < 10; i++) {
		if (bnx2_test_link(bp) == 0)
			break;
2431
		msleep(100);
2432 2433 2434 2435 2436
	}

	mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
	mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
		      BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2437
		      BNX2_EMAC_MODE_25G_MODE);
2438 2439 2440 2441 2442 2443 2444

	mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
	REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
	bp->link_up = 1;
	return 0;
}

2445
static int
2446
bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2447 2448 2449 2450 2451 2452 2453
{
	int i;
	u32 val;

	bp->fw_wr_seq++;
	msg_data |= bp->fw_wr_seq;

2454
	bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2455

2456 2457 2458
	if (!ack)
		return 0;

2459
	/* wait for an acknowledgement. */
2460
	for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2461
		msleep(10);
2462

2463
		val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2464 2465 2466 2467

		if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
			break;
	}
2468 2469
	if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
		return 0;
2470 2471

	/* If we timed out, inform the firmware that this is the case. */
2472 2473 2474 2475
	if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
		if (!silent)
			printk(KERN_ERR PFX "fw sync timeout, reset code = "
					    "%x\n", msg_data);
2476 2477 2478 2479

		msg_data &= ~BNX2_DRV_MSG_CODE;
		msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;

2480
		bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2481 2482 2483 2484

		return -EBUSY;
	}

2485 2486 2487
	if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
		return -EIO;

2488 2489 2490
	return 0;
}

2491 2492 2493 2494 2495 2496 2497 2498 2499
static int
bnx2_init_5709_context(struct bnx2 *bp)
{
	int i, ret = 0;
	u32 val;

	val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
	val |= (BCM_PAGE_BITS - 8) << 16;
	REG_WR(bp, BNX2_CTX_COMMAND, val);
2500 2501 2502 2503 2504 2505 2506 2507 2508
	for (i = 0; i < 10; i++) {
		val = REG_RD(bp, BNX2_CTX_COMMAND);
		if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
			break;
		udelay(2);
	}
	if (val & BNX2_CTX_COMMAND_MEM_INIT)
		return -EBUSY;

2509 2510 2511
	for (i = 0; i < bp->ctx_pages; i++) {
		int j;

2512 2513 2514 2515 2516
		if (bp->ctx_blk[i])
			memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
		else
			return -ENOMEM;

2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538
		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
		       (bp->ctx_blk_mapping[i] & 0xffffffff) |
		       BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
		       (u64) bp->ctx_blk_mapping[i] >> 32);
		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
		       BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
		for (j = 0; j < 10; j++) {

			val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
			if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
				break;
			udelay(5);
		}
		if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
			ret = -EBUSY;
			break;
		}
	}
	return ret;
}

2539 2540 2541 2542 2543 2544 2545 2546
static void
bnx2_init_context(struct bnx2 *bp)
{
	u32 vcid;

	vcid = 96;
	while (vcid) {
		u32 vcid_addr, pcid_addr, offset;
2547
		int i;
2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567

		vcid--;

		if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
			u32 new_vcid;

			vcid_addr = GET_PCID_ADDR(vcid);
			if (vcid & 0x8) {
				new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
			}
			else {
				new_vcid = vcid;
			}
			pcid_addr = GET_PCID_ADDR(new_vcid);
		}
		else {
	    		vcid_addr = GET_CID_ADDR(vcid);
			pcid_addr = vcid_addr;
		}

2568 2569 2570
		for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
			vcid_addr += (i << PHY_CTX_SHIFT);
			pcid_addr += (i << PHY_CTX_SHIFT);
2571

2572
			REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2573
			REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2574

2575 2576
			/* Zero out the context. */
			for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2577
				bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2578
		}
2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601
	}
}

static int
bnx2_alloc_bad_rbuf(struct bnx2 *bp)
{
	u16 *good_mbuf;
	u32 good_mbuf_cnt;
	u32 val;

	good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
	if (good_mbuf == NULL) {
		printk(KERN_ERR PFX "Failed to allocate memory in "
				    "bnx2_alloc_bad_rbuf\n");
		return -ENOMEM;
	}

	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
		BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);

	good_mbuf_cnt = 0;

	/* Allocate a bunch of mbufs and save the good ones in an array. */
2602
	val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2603
	while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2604 2605
		bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
				BNX2_RBUF_COMMAND_ALLOC_REQ);
2606

2607
		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2608 2609 2610 2611 2612 2613 2614 2615 2616

		val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;

		/* The addresses with Bit 9 set are bad memory blocks. */
		if (!(val & (1 << 9))) {
			good_mbuf[good_mbuf_cnt] = (u16) val;
			good_mbuf_cnt++;
		}

2617
		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2618 2619 2620 2621 2622 2623 2624 2625 2626 2627
	}

	/* Free the good ones back to the mbuf pool thus discarding
	 * all the bad ones. */
	while (good_mbuf_cnt) {
		good_mbuf_cnt--;

		val = good_mbuf[good_mbuf_cnt];
		val = (val << 9) | val | 1;

2628
		bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2629 2630 2631 2632 2633 2634
	}
	kfree(good_mbuf);
	return 0;
}

static void
2635
bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2636 2637 2638 2639 2640
{
	u32 val;

	val = (mac_addr[0] << 8) | mac_addr[1];

2641
	REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2642

2643
	val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2644 2645
		(mac_addr[4] << 8) | mac_addr[5];

2646
	REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2647 2648
}

2649
static inline int
2650
bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2651 2652
{
	dma_addr_t mapping;
2653
	struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2654
	struct rx_bd *rxbd =
2655
		&rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2656 2657 2658 2659 2660 2661
	struct page *page = alloc_page(GFP_ATOMIC);

	if (!page)
		return -ENOMEM;
	mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
			       PCI_DMA_FROMDEVICE);
2662 2663 2664 2665 2666
	if (pci_dma_mapping_error(bp->pdev, mapping)) {
		__free_page(page);
		return -EIO;
	}

2667 2668 2669 2670 2671 2672 2673 2674
	rx_pg->page = page;
	pci_unmap_addr_set(rx_pg, mapping, mapping);
	rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
	rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
	return 0;
}

static void
2675
bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2676
{
2677
	struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689
	struct page *page = rx_pg->page;

	if (!page)
		return;

	pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
		       PCI_DMA_FROMDEVICE);

	__free_page(page);
	rx_pg->page = NULL;
}

2690
static inline int
2691
bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2692 2693
{
	struct sk_buff *skb;
2694
	struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2695
	dma_addr_t mapping;
2696
	struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2697 2698
	unsigned long align;

2699
	skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2700 2701 2702 2703
	if (skb == NULL) {
		return -ENOMEM;
	}

2704 2705
	if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
		skb_reserve(skb, BNX2_RX_ALIGN - align);
2706 2707 2708

	mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
		PCI_DMA_FROMDEVICE);
2709 2710 2711 2712
	if (pci_dma_mapping_error(bp->pdev, mapping)) {
		dev_kfree_skb(skb);
		return -EIO;
	}
2713 2714 2715 2716 2717 2718 2719

	rx_buf->skb = skb;
	pci_unmap_addr_set(rx_buf, mapping, mapping);

	rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
	rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;

2720
	rxr->rx_prod_bseq += bp->rx_buf_use_size;
2721 2722 2723 2724

	return 0;
}

2725
static int
2726
bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2727
{
2728
	struct status_block *sblk = bnapi->status_blk.msi;
2729
	u32 new_link_state, old_link_state;
2730
	int is_set = 1;
2731

2732 2733
	new_link_state = sblk->status_attn_bits & event;
	old_link_state = sblk->status_attn_bits_ack & event;
2734
	if (new_link_state != old_link_state) {
2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745
		if (new_link_state)
			REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
		else
			REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
	} else
		is_set = 0;

	return is_set;
}

static void
2746
bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2747
{
2748 2749 2750
	spin_lock(&bp->phy_lock);

	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2751
		bnx2_set_link(bp);
2752
	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2753 2754
		bnx2_set_remote_link(bp);

2755 2756
	spin_unlock(&bp->phy_lock);

2757 2758
}

2759
static inline u16
2760
bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2761 2762 2763
{
	u16 cons;

2764 2765 2766
	/* Tell compiler that status block fields can change. */
	barrier();
	cons = *bnapi->hw_tx_cons_ptr;
2767
	barrier();
2768 2769 2770 2771 2772
	if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
		cons++;
	return cons;
}

2773 2774
static int
bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2775
{
2776
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2777
	u16 hw_cons, sw_cons, sw_ring_cons;
2778 2779 2780 2781 2782
	int tx_pkt = 0, index;
	struct netdev_queue *txq;

	index = (bnapi - bp->bnx2_napi);
	txq = netdev_get_tx_queue(bp->dev, index);
2783

2784
	hw_cons = bnx2_get_hw_tx_cons(bnapi);
2785
	sw_cons = txr->tx_cons;
2786 2787

	while (sw_cons != hw_cons) {
2788
		struct sw_tx_bd *tx_buf;
2789 2790 2791 2792 2793
		struct sk_buff *skb;
		int i, last;

		sw_ring_cons = TX_RING_IDX(sw_cons);

2794
		tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2795
		skb = tx_buf->skb;
2796

2797 2798 2799
		/* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
		prefetch(&skb->end);

2800
		/* partial BD completions possible with TSO packets */
2801
		if (tx_buf->is_gso) {
2802 2803
			u16 last_idx, last_ring_idx;

2804 2805
			last_idx = sw_cons + tx_buf->nr_frags + 1;
			last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2806 2807 2808 2809 2810 2811 2812
			if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
				last_idx++;
			}
			if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
				break;
			}
		}
2813

2814
		skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
2815 2816

		tx_buf->skb = NULL;
2817
		last = tx_buf->nr_frags;
2818 2819 2820 2821 2822 2823 2824

		for (i = 0; i < last; i++) {
			sw_cons = NEXT_TX_BD(sw_cons);
		}

		sw_cons = NEXT_TX_BD(sw_cons);

2825
		dev_kfree_skb(skb);
2826 2827 2828
		tx_pkt++;
		if (tx_pkt == budget)
			break;
2829

2830 2831
		if (hw_cons == sw_cons)
			hw_cons = bnx2_get_hw_tx_cons(bnapi);
2832 2833
	}

2834 2835
	txr->hw_tx_cons = hw_cons;
	txr->tx_cons = sw_cons;
2836

2837
	/* Need to make the tx_cons update visible to bnx2_start_xmit()
2838
	 * before checking for netif_tx_queue_stopped().  Without the
2839 2840 2841 2842
	 * memory barrier, there is a small possibility that bnx2_start_xmit()
	 * will miss it and cause the queue to be stopped forever.
	 */
	smp_mb();
2843

2844
	if (unlikely(netif_tx_queue_stopped(txq)) &&
2845
		     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2846 2847
		__netif_tx_lock(txq, smp_processor_id());
		if ((netif_tx_queue_stopped(txq)) &&
2848
		    (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2849 2850
			netif_tx_wake_queue(txq);
		__netif_tx_unlock(txq);
2851
	}
2852

2853
	return tx_pkt;
2854 2855
}

2856
static void
2857
bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2858
			struct sk_buff *skb, int count)
2859 2860 2861 2862
{
	struct sw_pg *cons_rx_pg, *prod_rx_pg;
	struct rx_bd *cons_bd, *prod_bd;
	int i;
2863
	u16 hw_prod, prod;
2864
	u16 cons = rxr->rx_pg_cons;
2865

2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886
	cons_rx_pg = &rxr->rx_pg_ring[cons];

	/* The caller was unable to allocate a new page to replace the
	 * last one in the frags array, so we need to recycle that page
	 * and then free the skb.
	 */
	if (skb) {
		struct page *page;
		struct skb_shared_info *shinfo;

		shinfo = skb_shinfo(skb);
		shinfo->nr_frags--;
		page = shinfo->frags[shinfo->nr_frags].page;
		shinfo->frags[shinfo->nr_frags].page = NULL;

		cons_rx_pg->page = page;
		dev_kfree_skb(skb);
	}

	hw_prod = rxr->rx_pg_prod;

2887 2888 2889
	for (i = 0; i < count; i++) {
		prod = RX_PG_RING_IDX(hw_prod);

2890 2891 2892 2893
		prod_rx_pg = &rxr->rx_pg_ring[prod];
		cons_rx_pg = &rxr->rx_pg_ring[cons];
		cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
		prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907

		if (prod != cons) {
			prod_rx_pg->page = cons_rx_pg->page;
			cons_rx_pg->page = NULL;
			pci_unmap_addr_set(prod_rx_pg, mapping,
				pci_unmap_addr(cons_rx_pg, mapping));

			prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
			prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;

		}
		cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
		hw_prod = NEXT_RX_BD(hw_prod);
	}
2908 2909
	rxr->rx_pg_prod = hw_prod;
	rxr->rx_pg_cons = cons;
2910 2911
}

2912
static inline void
2913 2914
bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
		  struct sk_buff *skb, u16 cons, u16 prod)
2915
{
2916 2917 2918
	struct sw_bd *cons_rx_buf, *prod_rx_buf;
	struct rx_bd *cons_bd, *prod_bd;

2919 2920
	cons_rx_buf = &rxr->rx_buf_ring[cons];
	prod_rx_buf = &rxr->rx_buf_ring[prod];
2921 2922 2923

	pci_dma_sync_single_for_device(bp->pdev,
		pci_unmap_addr(cons_rx_buf, mapping),
2924
		BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2925

2926
	rxr->rx_prod_bseq += bp->rx_buf_use_size;
2927

2928
	prod_rx_buf->skb = skb;
2929

2930 2931
	if (cons == prod)
		return;
2932

2933 2934 2935
	pci_unmap_addr_set(prod_rx_buf, mapping,
			pci_unmap_addr(cons_rx_buf, mapping));

2936 2937
	cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
	prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2938 2939
	prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
	prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2940 2941
}

2942
static int
2943
bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2944 2945
	    unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
	    u32 ring_idx)
2946 2947 2948 2949
{
	int err;
	u16 prod = ring_idx & 0xffff;

2950
	err = bnx2_alloc_rx_skb(bp, rxr, prod);
2951
	if (unlikely(err)) {
2952
		bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2953 2954 2955 2956
		if (hdr_len) {
			unsigned int raw_len = len + 4;
			int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;

2957
			bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2958
		}
2959 2960 2961
		return err;
	}

2962
	skb_reserve(skb, BNX2_RX_OFFSET);
2963 2964 2965
	pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
			 PCI_DMA_FROMDEVICE);

2966 2967 2968 2969 2970 2971
	if (hdr_len == 0) {
		skb_put(skb, len);
		return 0;
	} else {
		unsigned int i, frag_len, frag_size, pages;
		struct sw_pg *rx_pg;
2972 2973
		u16 pg_cons = rxr->rx_pg_cons;
		u16 pg_prod = rxr->rx_pg_prod;
2974 2975 2976 2977 2978 2979

		frag_size = len + 4 - hdr_len;
		pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
		skb_put(skb, hdr_len);

		for (i = 0; i < pages; i++) {
2980 2981
			dma_addr_t mapping_old;

2982 2983 2984 2985
			frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
			if (unlikely(frag_len <= 4)) {
				unsigned int tail = 4 - frag_len;

2986 2987 2988
				rxr->rx_pg_cons = pg_cons;
				rxr->rx_pg_prod = pg_prod;
				bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2989
							pages - i);
2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001
				skb->len -= tail;
				if (i == 0) {
					skb->tail -= tail;
				} else {
					skb_frag_t *frag =
						&skb_shinfo(skb)->frags[i - 1];
					frag->size -= tail;
					skb->data_len -= tail;
					skb->truesize -= tail;
				}
				return 0;
			}
3002
			rx_pg = &rxr->rx_pg_ring[pg_cons];
3003

3004 3005 3006 3007
			/* Don't unmap yet.  If we're unable to allocate a new
			 * page, we need to recycle the page and the DMA addr.
			 */
			mapping_old = pci_unmap_addr(rx_pg, mapping);
3008 3009 3010 3011 3012 3013
			if (i == pages - 1)
				frag_len -= 4;

			skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
			rx_pg->page = NULL;

3014 3015
			err = bnx2_alloc_rx_page(bp, rxr,
						 RX_PG_RING_IDX(pg_prod));
3016
			if (unlikely(err)) {
3017 3018 3019
				rxr->rx_pg_cons = pg_cons;
				rxr->rx_pg_prod = pg_prod;
				bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3020
							pages - i);
3021 3022 3023
				return err;
			}

3024 3025 3026
			pci_unmap_page(bp->pdev, mapping_old,
				       PAGE_SIZE, PCI_DMA_FROMDEVICE);

3027 3028 3029 3030 3031 3032 3033 3034
			frag_size -= frag_len;
			skb->data_len += frag_len;
			skb->truesize += frag_len;
			skb->len += frag_len;

			pg_prod = NEXT_RX_BD(pg_prod);
			pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
		}
3035 3036
		rxr->rx_pg_prod = pg_prod;
		rxr->rx_pg_cons = pg_cons;
3037
	}
3038 3039 3040
	return 0;
}

M
Michael Chan 已提交
3041
static inline u16
3042
bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
M
Michael Chan 已提交
3043
{
3044 3045
	u16 cons;

3046 3047 3048
	/* Tell compiler that status block fields can change. */
	barrier();
	cons = *bnapi->hw_rx_cons_ptr;
3049
	barrier();
M
Michael Chan 已提交
3050 3051 3052 3053 3054
	if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
		cons++;
	return cons;
}

3055
static int
3056
bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3057
{
3058
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3059 3060
	u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
	struct l2_fhdr *rx_hdr;
3061
	int rx_pkt = 0, pg_ring_used = 0;
3062

3063
	hw_cons = bnx2_get_hw_rx_cons(bnapi);
3064 3065
	sw_cons = rxr->rx_cons;
	sw_prod = rxr->rx_prod;
3066 3067 3068 3069 3070 3071

	/* Memory barrier necessary as speculative reads of the rx
	 * buffer can be ahead of the index in the status block
	 */
	rmb();
	while (sw_cons != hw_cons) {
3072
		unsigned int len, hdr_len;
3073
		u32 status;
3074 3075
		struct sw_bd *rx_buf;
		struct sk_buff *skb;
3076
		dma_addr_t dma_addr;
3077 3078
		u16 vtag = 0;
		int hw_vlan __maybe_unused = 0;
3079 3080 3081 3082

		sw_ring_cons = RX_RING_IDX(sw_cons);
		sw_ring_prod = RX_RING_IDX(sw_prod);

3083
		rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3084
		skb = rx_buf->skb;
3085 3086 3087 3088 3089 3090

		rx_buf->skb = NULL;

		dma_addr = pci_unmap_addr(rx_buf, mapping);

		pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3091 3092
			BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
			PCI_DMA_FROMDEVICE);
3093 3094

		rx_hdr = (struct l2_fhdr *) skb->data;
3095
		len = rx_hdr->l2_fhdr_pkt_len;
3096
		status = rx_hdr->l2_fhdr_status;
3097

3098 3099 3100 3101 3102 3103 3104 3105 3106
		hdr_len = 0;
		if (status & L2_FHDR_STATUS_SPLIT) {
			hdr_len = rx_hdr->l2_fhdr_ip_xsum;
			pg_ring_used = 1;
		} else if (len > bp->rx_jumbo_thresh) {
			hdr_len = bp->rx_jumbo_thresh;
			pg_ring_used = 1;
		}

3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124
		if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
				       L2_FHDR_ERRORS_PHY_DECODE |
				       L2_FHDR_ERRORS_ALIGNMENT |
				       L2_FHDR_ERRORS_TOO_SHORT |
				       L2_FHDR_ERRORS_GIANT_FRAME))) {

			bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
					  sw_ring_prod);
			if (pg_ring_used) {
				int pages;

				pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;

				bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
			}
			goto next_rx;
		}

3125
		len -= 4;
3126

3127
		if (len <= bp->rx_copy_thresh) {
3128 3129
			struct sk_buff *new_skb;

3130
			new_skb = netdev_alloc_skb(bp->dev, len + 6);
3131
			if (new_skb == NULL) {
3132
				bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3133 3134 3135
						  sw_ring_prod);
				goto next_rx;
			}
3136 3137

			/* aligned copy */
3138
			skb_copy_from_linear_data_offset(skb,
3139 3140 3141
							 BNX2_RX_OFFSET - 6,
				      new_skb->data, len + 6);
			skb_reserve(new_skb, 6);
3142 3143
			skb_put(new_skb, len);

3144
			bnx2_reuse_rx_skb(bp, rxr, skb,
3145 3146 3147
				sw_ring_cons, sw_ring_prod);

			skb = new_skb;
3148
		} else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3149
			   dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3150 3151
			goto next_rx;

3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170
		if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
		    !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
			vtag = rx_hdr->l2_fhdr_vlan_tag;
#ifdef BCM_VLAN
			if (bp->vlgrp)
				hw_vlan = 1;
			else
#endif
			{
				struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
					__skb_push(skb, 4);

				memmove(ve, skb->data + 4, ETH_ALEN * 2);
				ve->h_vlan_proto = htons(ETH_P_8021Q);
				ve->h_vlan_TCI = htons(vtag);
				len += 4;
			}
		}

3171 3172 3173
		skb->protocol = eth_type_trans(skb, bp->dev);

		if ((len > (bp->dev->mtu + ETH_HLEN)) &&
A
Alexey Dobriyan 已提交
3174
			(ntohs(skb->protocol) != 0x8100)) {
3175

3176
			dev_kfree_skb(skb);
3177 3178 3179 3180 3181 3182 3183 3184 3185
			goto next_rx;

		}

		skb->ip_summed = CHECKSUM_NONE;
		if (bp->rx_csum &&
			(status & (L2_FHDR_STATUS_TCP_SEGMENT |
			L2_FHDR_STATUS_UDP_DATAGRAM))) {

3186 3187
			if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
					      L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3188 3189 3190
				skb->ip_summed = CHECKSUM_UNNECESSARY;
		}

3191 3192
		skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);

3193
#ifdef BCM_VLAN
3194 3195
		if (hw_vlan)
			vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207
		else
#endif
			netif_receive_skb(skb);

		rx_pkt++;

next_rx:
		sw_cons = NEXT_RX_BD(sw_cons);
		sw_prod = NEXT_RX_BD(sw_prod);

		if ((rx_pkt == budget))
			break;
3208 3209 3210

		/* Refresh hw_cons to see if there is new work */
		if (sw_cons == hw_cons) {
3211
			hw_cons = bnx2_get_hw_rx_cons(bnapi);
3212 3213
			rmb();
		}
3214
	}
3215 3216
	rxr->rx_cons = sw_cons;
	rxr->rx_prod = sw_prod;
3217

3218
	if (pg_ring_used)
3219
		REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3220

3221
	REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3222

3223
	REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234

	mmiowb();

	return rx_pkt;

}

/* MSI ISR - The only difference between this and the INTx ISR
 * is that the MSI interrupt is always serviced.
 */
static irqreturn_t
3235
bnx2_msi(int irq, void *dev_instance)
3236
{
3237 3238
	struct bnx2_napi *bnapi = dev_instance;
	struct bnx2 *bp = bnapi->bp;
3239

3240
	prefetch(bnapi->status_blk.msi);
3241 3242 3243 3244 3245
	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
		BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
		BNX2_PCICFG_INT_ACK_CMD_MASK_INT);

	/* Return here if interrupt is disabled. */
3246 3247
	if (unlikely(atomic_read(&bp->intr_sem) != 0))
		return IRQ_HANDLED;
3248

3249
	napi_schedule(&bnapi->napi);
3250

3251
	return IRQ_HANDLED;
3252 3253
}

3254 3255 3256
static irqreturn_t
bnx2_msi_1shot(int irq, void *dev_instance)
{
3257 3258
	struct bnx2_napi *bnapi = dev_instance;
	struct bnx2 *bp = bnapi->bp;
3259

3260
	prefetch(bnapi->status_blk.msi);
3261 3262 3263 3264 3265

	/* Return here if interrupt is disabled. */
	if (unlikely(atomic_read(&bp->intr_sem) != 0))
		return IRQ_HANDLED;

3266
	napi_schedule(&bnapi->napi);
3267 3268 3269 3270

	return IRQ_HANDLED;
}

3271
static irqreturn_t
3272
bnx2_interrupt(int irq, void *dev_instance)
3273
{
3274 3275
	struct bnx2_napi *bnapi = dev_instance;
	struct bnx2 *bp = bnapi->bp;
3276
	struct status_block *sblk = bnapi->status_blk.msi;
3277 3278 3279 3280 3281 3282 3283

	/* When using INTx, it is possible for the interrupt to arrive
	 * at the CPU before the status block posted prior to the
	 * interrupt. Reading a register will flush the status block.
	 * When using MSI, the MSI message will always complete after
	 * the status block write.
	 */
3284
	if ((sblk->status_idx == bnapi->last_status_idx) &&
3285 3286
	    (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
	     BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3287
		return IRQ_NONE;
3288 3289 3290 3291 3292

	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
		BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
		BNX2_PCICFG_INT_ACK_CMD_MASK_INT);

3293 3294 3295 3296 3297
	/* Read back to deassert IRQ immediately to avoid too many
	 * spurious interrupts.
	 */
	REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);

3298
	/* Return here if interrupt is shared and is disabled. */
3299 3300
	if (unlikely(atomic_read(&bp->intr_sem) != 0))
		return IRQ_HANDLED;
3301

3302
	if (napi_schedule_prep(&bnapi->napi)) {
3303
		bnapi->last_status_idx = sblk->status_idx;
3304
		__napi_schedule(&bnapi->napi);
3305
	}
3306

3307
	return IRQ_HANDLED;
3308 3309
}

3310
static inline int
3311
bnx2_has_fast_work(struct bnx2_napi *bnapi)
3312
{
3313
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3314
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3315

3316
	if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3317
	    (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3318
		return 1;
3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331
	return 0;
}

#define STATUS_ATTN_EVENTS	(STATUS_ATTN_BITS_LINK_STATE | \
				 STATUS_ATTN_BITS_TIMER_ABORT)

static inline int
bnx2_has_work(struct bnx2_napi *bnapi)
{
	struct status_block *sblk = bnapi->status_blk.msi;

	if (bnx2_has_fast_work(bnapi))
		return 1;
3332

3333 3334 3335 3336 3337
#ifdef BCM_CNIC
	if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
		return 1;
#endif

3338 3339
	if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
	    (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3340 3341 3342 3343 3344
		return 1;

	return 0;
}

3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366
static void
bnx2_chk_missed_msi(struct bnx2 *bp)
{
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
	u32 msi_ctrl;

	if (bnx2_has_work(bnapi)) {
		msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
		if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
			return;

		if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
			REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
			       ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
			REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
			bnx2_msi(bp->irq_tbl[0].vector, bnapi);
		}
	}

	bp->idle_chk_status_idx = bnapi->last_status_idx;
}

3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383
#ifdef BCM_CNIC
static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
{
	struct cnic_ops *c_ops;

	if (!bnapi->cnic_present)
		return;

	rcu_read_lock();
	c_ops = rcu_dereference(bp->cnic_ops);
	if (c_ops)
		bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
						      bnapi->status_blk.msi);
	rcu_read_unlock();
}
#endif

3384
static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3385
{
3386
	struct status_block *sblk = bnapi->status_blk.msi;
3387 3388
	u32 status_attn_bits = sblk->status_attn_bits;
	u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3389

3390 3391
	if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
	    (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3392

3393
		bnx2_phy_int(bp, bnapi);
3394 3395 3396 3397 3398 3399 3400

		/* This is needed to take care of transient status
		 * during link changes.
		 */
		REG_WR(bp, BNX2_HC_COMMAND,
		       bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
		REG_RD(bp, BNX2_HC_COMMAND);
3401
	}
3402 3403 3404 3405 3406 3407 3408
}

static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
			  int work_done, int budget)
{
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3409

3410
	if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3411
		bnx2_tx_int(bp, bnapi, 0);
3412

3413
	if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3414
		work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3415

3416 3417 3418
	return work_done;
}

3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435
static int bnx2_poll_msix(struct napi_struct *napi, int budget)
{
	struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
	struct bnx2 *bp = bnapi->bp;
	int work_done = 0;
	struct status_block_msix *sblk = bnapi->status_blk.msix;

	while (1) {
		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
		if (unlikely(work_done >= budget))
			break;

		bnapi->last_status_idx = sblk->status_idx;
		/* status idx must be read before checking for more work. */
		rmb();
		if (likely(!bnx2_has_fast_work(bnapi))) {

3436
			napi_complete(napi);
3437 3438 3439 3440 3441 3442 3443 3444 3445
			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
			       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
			       bnapi->last_status_idx);
			break;
		}
	}
	return work_done;
}

3446 3447
static int bnx2_poll(struct napi_struct *napi, int budget)
{
3448 3449
	struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
	struct bnx2 *bp = bnapi->bp;
3450
	int work_done = 0;
3451
	struct status_block *sblk = bnapi->status_blk.msi;
3452 3453

	while (1) {
3454 3455
		bnx2_poll_link(bp, bnapi);

3456
		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3457

3458 3459 3460 3461
#ifdef BCM_CNIC
		bnx2_poll_cnic(bp, bnapi);
#endif

3462
		/* bnapi->last_status_idx is used below to tell the hw how
3463 3464 3465
		 * much work has been processed, so we must read it before
		 * checking for more work.
		 */
3466
		bnapi->last_status_idx = sblk->status_idx;
3467 3468 3469 3470

		if (unlikely(work_done >= budget))
			break;

3471
		rmb();
3472
		if (likely(!bnx2_has_work(bnapi))) {
3473
			napi_complete(napi);
3474
			if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3475 3476
				REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
				       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3477
				       bnapi->last_status_idx);
3478
				break;
3479
			}
3480 3481
			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
			       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3482
			       BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3483
			       bnapi->last_status_idx);
3484

3485 3486
			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
			       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3487
			       bnapi->last_status_idx);
3488 3489
			break;
		}
3490 3491
	}

3492
	return work_done;
3493 3494
}

H
Herbert Xu 已提交
3495
/* Called with rtnl_lock from vlan functions and also netif_tx_lock
3496 3497 3498 3499 3500
 * from set_multicast.
 */
static void
bnx2_set_rx_mode(struct net_device *dev)
{
M
Michael Chan 已提交
3501
	struct bnx2 *bp = netdev_priv(dev);
3502
	u32 rx_mode, sort_mode;
3503
	struct netdev_hw_addr *ha;
3504 3505
	int i;

3506 3507 3508
	if (!netif_running(dev))
		return;

3509
	spin_lock_bh(&bp->phy_lock);
3510 3511 3512 3513 3514

	rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
				  BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
	sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
#ifdef BCM_VLAN
3515
	if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3516 3517
		rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
#else
3518
	if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
M
Michael Chan 已提交
3519
		rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3520 3521 3522 3523
#endif
	if (dev->flags & IFF_PROMISC) {
		/* Promiscuous mode. */
		rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
M
Michael Chan 已提交
3524 3525
		sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
			     BNX2_RPM_SORT_USER0_PROM_VLAN;
3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561
	}
	else if (dev->flags & IFF_ALLMULTI) {
		for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
			REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
			       0xffffffff);
        	}
		sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
	}
	else {
		/* Accept one or more multicast(s). */
		struct dev_mc_list *mclist;
		u32 mc_filter[NUM_MC_HASH_REGISTERS];
		u32 regidx;
		u32 bit;
		u32 crc;

		memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);

		for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
		     i++, mclist = mclist->next) {

			crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
			bit = crc & 0xff;
			regidx = (bit & 0xe0) >> 5;
			bit &= 0x1f;
			mc_filter[regidx] |= (1 << bit);
		}

		for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
			REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
			       mc_filter[i]);
		}

		sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
	}

3562
	if (dev->uc.count > BNX2_MAX_UNICAST_ADDRESSES) {
3563 3564 3565 3566 3567
		rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
		sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
			     BNX2_RPM_SORT_USER0_PROM_VLAN;
	} else if (!(dev->flags & IFF_PROMISC)) {
		/* Add all entries into to the match filter list */
3568
		i = 0;
3569
		list_for_each_entry(ha, &dev->uc.list, list) {
3570
			bnx2_set_mac_addr(bp, ha->addr,
3571 3572 3573
					  i + BNX2_START_UNICAST_ADDRESS_INDEX);
			sort_mode |= (1 <<
				      (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3574
			i++;
3575 3576 3577 3578
		}

	}

3579 3580 3581 3582 3583 3584 3585 3586 3587
	if (rx_mode != bp->rx_mode) {
		bp->rx_mode = rx_mode;
		REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
	}

	REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
	REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
	REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);

3588
	spin_unlock_bh(&bp->phy_lock);
3589 3590
}

3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619
static int __devinit
check_fw_section(const struct firmware *fw,
		 const struct bnx2_fw_file_section *section,
		 u32 alignment, bool non_empty)
{
	u32 offset = be32_to_cpu(section->offset);
	u32 len = be32_to_cpu(section->len);

	if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
		return -EINVAL;
	if ((non_empty && len == 0) || len > fw->size - offset ||
	    len & (alignment - 1))
		return -EINVAL;
	return 0;
}

static int __devinit
check_mips_fw_entry(const struct firmware *fw,
		    const struct bnx2_mips_fw_file_entry *entry)
{
	if (check_fw_section(fw, &entry->text, 4, true) ||
	    check_fw_section(fw, &entry->data, 4, false) ||
	    check_fw_section(fw, &entry->rodata, 4, false))
		return -EINVAL;
	return 0;
}

static int __devinit
bnx2_request_firmware(struct bnx2 *bp)
3620
{
3621
	const char *mips_fw_file, *rv2p_fw_file;
3622 3623
	const struct bnx2_mips_fw_file *mips_fw;
	const struct bnx2_rv2p_fw_file *rv2p_fw;
3624 3625 3626 3627
	int rc;

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		mips_fw_file = FW_MIPS_FILE_09;
3628 3629 3630 3631 3632
		if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
		    (CHIP_ID(bp) == CHIP_ID_5709_A1))
			rv2p_fw_file = FW_RV2P_FILE_09_Ax;
		else
			rv2p_fw_file = FW_RV2P_FILE_09;
3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650
	} else {
		mips_fw_file = FW_MIPS_FILE_06;
		rv2p_fw_file = FW_RV2P_FILE_06;
	}

	rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
	if (rc) {
		printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
		       mips_fw_file);
		return rc;
	}

	rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
	if (rc) {
		printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
		       rv2p_fw_file);
		return rc;
	}
3651 3652 3653 3654 3655 3656 3657 3658
	mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
	rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
	if (bp->mips_firmware->size < sizeof(*mips_fw) ||
	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3659 3660 3661 3662
		printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
		       mips_fw_file);
		return -EINVAL;
	}
3663 3664 3665
	if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691
		printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
		       rv2p_fw_file);
		return -EINVAL;
	}

	return 0;
}

static u32
rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
{
	switch (idx) {
	case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
		rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
		rv2p_code |= RV2P_BD_PAGE_SIZE;
		break;
	}
	return rv2p_code;
}

static int
load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
	     const struct bnx2_rv2p_fw_file_entry *fw_entry)
{
	u32 rv2p_code_len, file_offset;
	__be32 *rv2p_code;
3692
	int i;
3693 3694 3695 3696 3697 3698
	u32 val, cmd, addr;

	rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
	file_offset = be32_to_cpu(fw_entry->rv2p.offset);

	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3699

3700 3701 3702 3703 3704 3705
	if (rv2p_proc == RV2P_PROC1) {
		cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
		addr = BNX2_RV2P_PROC1_ADDR_CMD;
	} else {
		cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
		addr = BNX2_RV2P_PROC2_ADDR_CMD;
3706
	}
3707 3708

	for (i = 0; i < rv2p_code_len; i += 8) {
3709
		REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3710
		rv2p_code++;
3711
		REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3712 3713
		rv2p_code++;

3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731
		val = (i / 8) | cmd;
		REG_WR(bp, addr, val);
	}

	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
	for (i = 0; i < 8; i++) {
		u32 loc, code;

		loc = be32_to_cpu(fw_entry->fixup[i]);
		if (loc && ((loc * 4) < rv2p_code_len)) {
			code = be32_to_cpu(*(rv2p_code + loc - 1));
			REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
			code = be32_to_cpu(*(rv2p_code + loc));
			code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
			REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);

			val = (loc / 2) | cmd;
			REG_WR(bp, addr, val);
3732 3733 3734 3735 3736 3737 3738 3739 3740 3741
		}
	}

	/* Reset the processor, un-stall is done later. */
	if (rv2p_proc == RV2P_PROC1) {
		REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
	}
	else {
		REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
	}
3742 3743

	return 0;
3744 3745
}

3746
static int
3747 3748
load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
	    const struct bnx2_mips_fw_file_entry *fw_entry)
3749
{
3750 3751
	u32 addr, len, file_offset;
	__be32 *data;
3752 3753 3754 3755
	u32 offset;
	u32 val;

	/* Halt the CPU. */
3756
	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3757
	val |= cpu_reg->mode_value_halt;
3758 3759
	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3760 3761

	/* Load the Text area. */
3762 3763 3764 3765
	addr = be32_to_cpu(fw_entry->text.addr);
	len = be32_to_cpu(fw_entry->text.len);
	file_offset = be32_to_cpu(fw_entry->text.offset);
	data = (__be32 *)(bp->mips_firmware->data + file_offset);
3766

3767 3768
	offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
	if (len) {
3769 3770
		int j;

3771 3772
		for (j = 0; j < (len / 4); j++, offset += 4)
			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3773 3774
	}

3775 3776 3777 3778 3779
	/* Load the Data area. */
	addr = be32_to_cpu(fw_entry->data.addr);
	len = be32_to_cpu(fw_entry->data.len);
	file_offset = be32_to_cpu(fw_entry->data.offset);
	data = (__be32 *)(bp->mips_firmware->data + file_offset);
3780

3781 3782
	offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
	if (len) {
3783 3784
		int j;

3785 3786
		for (j = 0; j < (len / 4); j++, offset += 4)
			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3787 3788 3789
	}

	/* Load the Read-Only area. */
3790 3791 3792 3793 3794 3795 3796
	addr = be32_to_cpu(fw_entry->rodata.addr);
	len = be32_to_cpu(fw_entry->rodata.len);
	file_offset = be32_to_cpu(fw_entry->rodata.offset);
	data = (__be32 *)(bp->mips_firmware->data + file_offset);

	offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
	if (len) {
3797 3798
		int j;

3799 3800
		for (j = 0; j < (len / 4); j++, offset += 4)
			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3801 3802 3803
	}

	/* Clear the pre-fetch instruction. */
3804
	bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3805 3806 3807

	val = be32_to_cpu(fw_entry->start_addr);
	bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3808 3809

	/* Start the CPU. */
3810
	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3811
	val &= ~cpu_reg->mode_value_halt;
3812 3813
	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3814 3815

	return 0;
3816 3817
}

3818
static int
3819 3820
bnx2_init_cpus(struct bnx2 *bp)
{
3821 3822 3823 3824 3825
	const struct bnx2_mips_fw_file *mips_fw =
		(const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
	const struct bnx2_rv2p_fw_file *rv2p_fw =
		(const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
	int rc;
3826 3827

	/* Initialize the RV2P processor. */
3828 3829
	load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
	load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3830 3831

	/* Initialize the RX Processor. */
3832
	rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3833 3834 3835
	if (rc)
		goto init_cpu_err;

3836
	/* Initialize the TX Processor. */
3837
	rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3838 3839 3840
	if (rc)
		goto init_cpu_err;

3841
	/* Initialize the TX Patch-up Processor. */
3842
	rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3843 3844 3845
	if (rc)
		goto init_cpu_err;

3846
	/* Initialize the Completion Processor. */
3847
	rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3848 3849 3850
	if (rc)
		goto init_cpu_err;

3851
	/* Initialize the Command Processor. */
3852
	rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3853

3854 3855
init_cpu_err:
	return rc;
3856 3857 3858
}

static int
3859
bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3860 3861 3862 3863 3864 3865
{
	u16 pmcsr;

	pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);

	switch (state) {
3866
	case PCI_D0: {
3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886
		u32 val;

		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
			(pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
			PCI_PM_CTRL_PME_STATUS);

		if (pmcsr & PCI_PM_CTRL_STATE_MASK)
			/* delay required during transition out of D3hot */
			msleep(20);

		val = REG_RD(bp, BNX2_EMAC_MODE);
		val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
		val &= ~BNX2_EMAC_MODE_MPKT;
		REG_WR(bp, BNX2_EMAC_MODE, val);

		val = REG_RD(bp, BNX2_RPM_CONFIG);
		val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
		REG_WR(bp, BNX2_RPM_CONFIG, val);
		break;
	}
3887
	case PCI_D3hot: {
3888 3889 3890 3891 3892 3893 3894 3895 3896 3897
		int i;
		u32 val, wol_msg;

		if (bp->wol) {
			u32 advertising;
			u8 autoneg;

			autoneg = bp->autoneg;
			advertising = bp->advertising;

3898 3899 3900 3901 3902 3903 3904 3905
			if (bp->phy_port == PORT_TP) {
				bp->autoneg = AUTONEG_SPEED;
				bp->advertising = ADVERTISED_10baseT_Half |
					ADVERTISED_10baseT_Full |
					ADVERTISED_100baseT_Half |
					ADVERTISED_100baseT_Full |
					ADVERTISED_Autoneg;
			}
3906

3907 3908 3909
			spin_lock_bh(&bp->phy_lock);
			bnx2_setup_phy(bp, bp->phy_port);
			spin_unlock_bh(&bp->phy_lock);
3910 3911 3912 3913

			bp->autoneg = autoneg;
			bp->advertising = advertising;

3914
			bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3915 3916 3917 3918 3919

			val = REG_RD(bp, BNX2_EMAC_MODE);

			/* Enable port mode. */
			val &= ~BNX2_EMAC_MODE_PORT;
3920
			val |= BNX2_EMAC_MODE_MPKT_RCVD |
3921 3922
			       BNX2_EMAC_MODE_ACPI_RCVD |
			       BNX2_EMAC_MODE_MPKT;
3923 3924 3925 3926 3927 3928 3929
			if (bp->phy_port == PORT_TP)
				val |= BNX2_EMAC_MODE_PORT_MII;
			else {
				val |= BNX2_EMAC_MODE_PORT_GMII;
				if (bp->line_speed == SPEED_2500)
					val |= BNX2_EMAC_MODE_25G_MODE;
			}
3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963

			REG_WR(bp, BNX2_EMAC_MODE, val);

			/* receive all multicast */
			for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
				REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
				       0xffffffff);
			}
			REG_WR(bp, BNX2_EMAC_RX_MODE,
			       BNX2_EMAC_RX_MODE_SORT_MODE);

			val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
			      BNX2_RPM_SORT_USER0_MC_EN;
			REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
			REG_WR(bp, BNX2_RPM_SORT_USER0, val);
			REG_WR(bp, BNX2_RPM_SORT_USER0, val |
			       BNX2_RPM_SORT_USER0_ENA);

			/* Need to enable EMAC and RPM for WOL. */
			REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
			       BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
			       BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
			       BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);

			val = REG_RD(bp, BNX2_RPM_CONFIG);
			val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
			REG_WR(bp, BNX2_RPM_CONFIG, val);

			wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
		}
		else {
			wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
		}

3964
		if (!(bp->flags & BNX2_FLAG_NO_WOL))
3965 3966
			bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
				     1, 0);
3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049

		pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
		if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
		    (CHIP_ID(bp) == CHIP_ID_5706_A1)) {

			if (bp->wol)
				pmcsr |= 3;
		}
		else {
			pmcsr |= 3;
		}
		if (bp->wol) {
			pmcsr |= PCI_PM_CTRL_PME_ENABLE;
		}
		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
				      pmcsr);

		/* No more memory access after this point until
		 * device is brought back to D0.
		 */
		udelay(50);
		break;
	}
	default:
		return -EINVAL;
	}
	return 0;
}

static int
bnx2_acquire_nvram_lock(struct bnx2 *bp)
{
	u32 val;
	int j;

	/* Request access to the flash interface. */
	REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		val = REG_RD(bp, BNX2_NVM_SW_ARB);
		if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
			break;

		udelay(5);
	}

	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}

static int
bnx2_release_nvram_lock(struct bnx2 *bp)
{
	int j;
	u32 val;

	/* Relinquish nvram interface. */
	REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);

	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		val = REG_RD(bp, BNX2_NVM_SW_ARB);
		if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
			break;

		udelay(5);
	}

	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}


static int
bnx2_enable_nvram_write(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_MISC_CFG);
	REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);

4050
	if (bp->flash_info->flags & BNX2_NV_WREN) {
4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087
		int j;

		REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
		REG_WR(bp, BNX2_NVM_COMMAND,
		       BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);

		for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
			udelay(5);

			val = REG_RD(bp, BNX2_NVM_COMMAND);
			if (val & BNX2_NVM_COMMAND_DONE)
				break;
		}

		if (j >= NVRAM_TIMEOUT_COUNT)
			return -EBUSY;
	}
	return 0;
}

static void
bnx2_disable_nvram_write(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_MISC_CFG);
	REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
}


static void
bnx2_enable_nvram_access(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
	/* Enable both bits, even on read. */
4088
	REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4089 4090 4091 4092 4093 4094 4095 4096 4097 4098
	       val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
}

static void
bnx2_disable_nvram_access(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
	/* Disable both bits, even after read. */
4099
	REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4100 4101 4102 4103 4104 4105 4106 4107 4108 4109
		val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
			BNX2_NVM_ACCESS_ENABLE_WR_EN));
}

static int
bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
{
	u32 cmd;
	int j;

4110
	if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152
		/* Buffered flash, no erase needed */
		return 0;

	/* Build an erase command */
	cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
	      BNX2_NVM_COMMAND_DOIT;

	/* Need to clear DONE bit separately. */
	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);

	/* Address of the NVRAM to read from. */
	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);

	/* Issue an erase command. */
	REG_WR(bp, BNX2_NVM_COMMAND, cmd);

	/* Wait for completion. */
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		u32 val;

		udelay(5);

		val = REG_RD(bp, BNX2_NVM_COMMAND);
		if (val & BNX2_NVM_COMMAND_DONE)
			break;
	}

	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}

static int
bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
{
	u32 cmd;
	int j;

	/* Build the command word. */
	cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;

4153 4154
	/* Calculate an offset of a buffered flash, not needed for 5709. */
	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176
		offset = ((offset / bp->flash_info->page_size) <<
			   bp->flash_info->page_bits) +
			  (offset % bp->flash_info->page_size);
	}

	/* Need to clear DONE bit separately. */
	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);

	/* Address of the NVRAM to read from. */
	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);

	/* Issue a read command. */
	REG_WR(bp, BNX2_NVM_COMMAND, cmd);

	/* Wait for completion. */
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		u32 val;

		udelay(5);

		val = REG_RD(bp, BNX2_NVM_COMMAND);
		if (val & BNX2_NVM_COMMAND_DONE) {
A
Al Viro 已提交
4177 4178
			__be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
			memcpy(ret_val, &v, 4);
4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191
			break;
		}
	}
	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}


static int
bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
{
A
Al Viro 已提交
4192 4193
	u32 cmd;
	__be32 val32;
4194 4195 4196 4197 4198
	int j;

	/* Build the command word. */
	cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;

4199 4200
	/* Calculate an offset of a buffered flash, not needed for 5709. */
	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211
		offset = ((offset / bp->flash_info->page_size) <<
			  bp->flash_info->page_bits) +
			 (offset % bp->flash_info->page_size);
	}

	/* Need to clear DONE bit separately. */
	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);

	memcpy(&val32, val, 4);

	/* Write the data. */
A
Al Viro 已提交
4212
	REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236

	/* Address of the NVRAM to write to. */
	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);

	/* Issue the write command. */
	REG_WR(bp, BNX2_NVM_COMMAND, cmd);

	/* Wait for completion. */
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		udelay(5);

		if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
			break;
	}
	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}

static int
bnx2_init_nvram(struct bnx2 *bp)
{
	u32 val;
4237
	int j, entry_count, rc = 0;
4238
	const struct flash_spec *flash;
4239

4240 4241 4242 4243 4244
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		bp->flash_info = &flash_5709;
		goto get_flash_size;
	}

4245 4246 4247
	/* Determine the selected interface. */
	val = REG_RD(bp, BNX2_NVM_CFG1);

4248
	entry_count = ARRAY_SIZE(flash_table);
4249 4250 4251 4252 4253

	if (val & 0x40000000) {

		/* Flash interface has been reconfigured */
		for (j = 0, flash = &flash_table[0]; j < entry_count;
4254 4255 4256
		     j++, flash++) {
			if ((val & FLASH_BACKUP_STRAP_MASK) ==
			    (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4257 4258 4259 4260 4261 4262
				bp->flash_info = flash;
				break;
			}
		}
	}
	else {
4263
		u32 mask;
4264 4265
		/* Not yet been reconfigured */

4266 4267 4268 4269 4270
		if (val & (1 << 23))
			mask = FLASH_BACKUP_STRAP_MASK;
		else
			mask = FLASH_STRAP_MASK;

4271 4272 4273
		for (j = 0, flash = &flash_table[0]; j < entry_count;
			j++, flash++) {

4274
			if ((val & mask) == (flash->strapping & mask)) {
4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300
				bp->flash_info = flash;

				/* Request access to the flash interface. */
				if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
					return rc;

				/* Enable access to flash interface */
				bnx2_enable_nvram_access(bp);

				/* Reconfigure the flash interface */
				REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
				REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
				REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
				REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);

				/* Disable access to flash interface */
				bnx2_disable_nvram_access(bp);
				bnx2_release_nvram_lock(bp);

				break;
			}
		}
	} /* if (val & 0x40000000) */

	if (j == entry_count) {
		bp->flash_info = NULL;
4301
		printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
M
Michael Chan 已提交
4302
		return -ENODEV;
4303 4304
	}

4305
get_flash_size:
4306
	val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
M
Michael Chan 已提交
4307 4308 4309 4310 4311 4312
	val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
	if (val)
		bp->flash_size = val;
	else
		bp->flash_size = bp->flash_info->total_size;

4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430
	return rc;
}

static int
bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
		int buf_size)
{
	int rc = 0;
	u32 cmd_flags, offset32, len32, extra;

	if (buf_size == 0)
		return 0;

	/* Request access to the flash interface. */
	if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
		return rc;

	/* Enable access to flash interface */
	bnx2_enable_nvram_access(bp);

	len32 = buf_size;
	offset32 = offset;
	extra = 0;

	cmd_flags = 0;

	if (offset32 & 3) {
		u8 buf[4];
		u32 pre_len;

		offset32 &= ~3;
		pre_len = 4 - (offset & 3);

		if (pre_len >= len32) {
			pre_len = len32;
			cmd_flags = BNX2_NVM_COMMAND_FIRST |
				    BNX2_NVM_COMMAND_LAST;
		}
		else {
			cmd_flags = BNX2_NVM_COMMAND_FIRST;
		}

		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);

		if (rc)
			return rc;

		memcpy(ret_buf, buf + (offset & 3), pre_len);

		offset32 += 4;
		ret_buf += pre_len;
		len32 -= pre_len;
	}
	if (len32 & 3) {
		extra = 4 - (len32 & 3);
		len32 = (len32 + 4) & ~3;
	}

	if (len32 == 4) {
		u8 buf[4];

		if (cmd_flags)
			cmd_flags = BNX2_NVM_COMMAND_LAST;
		else
			cmd_flags = BNX2_NVM_COMMAND_FIRST |
				    BNX2_NVM_COMMAND_LAST;

		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);

		memcpy(ret_buf, buf, 4 - extra);
	}
	else if (len32 > 0) {
		u8 buf[4];

		/* Read the first word. */
		if (cmd_flags)
			cmd_flags = 0;
		else
			cmd_flags = BNX2_NVM_COMMAND_FIRST;

		rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);

		/* Advance to the next dword. */
		offset32 += 4;
		ret_buf += 4;
		len32 -= 4;

		while (len32 > 4 && rc == 0) {
			rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);

			/* Advance to the next dword. */
			offset32 += 4;
			ret_buf += 4;
			len32 -= 4;
		}

		if (rc)
			return rc;

		cmd_flags = BNX2_NVM_COMMAND_LAST;
		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);

		memcpy(ret_buf, buf, 4 - extra);
	}

	/* Disable access to flash interface */
	bnx2_disable_nvram_access(bp);

	bnx2_release_nvram_lock(bp);

	return rc;
}

static int
bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
		int buf_size)
{
	u32 written, offset32, len32;
4431
	u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4432 4433 4434 4435 4436 4437 4438 4439 4440 4441
	int rc = 0;
	int align_start, align_end;

	buf = data_buf;
	offset32 = offset;
	len32 = buf_size;
	align_start = align_end = 0;

	if ((align_start = (offset32 & 3))) {
		offset32 &= ~3;
4442 4443 4444
		len32 += align_start;
		if (len32 < 4)
			len32 = 4;
4445 4446 4447 4448 4449
		if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
			return rc;
	}

	if (len32 & 3) {
4450 4451 4452 4453
		align_end = 4 - (len32 & 3);
		len32 += align_end;
		if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
			return rc;
4454 4455 4456
	}

	if (align_start || align_end) {
4457 4458
		align_buf = kmalloc(len32, GFP_KERNEL);
		if (align_buf == NULL)
4459 4460
			return -ENOMEM;
		if (align_start) {
4461
			memcpy(align_buf, start, 4);
4462 4463
		}
		if (align_end) {
4464
			memcpy(align_buf + len32 - 4, end, 4);
4465
		}
4466 4467
		memcpy(align_buf + align_start, data_buf, buf_size);
		buf = align_buf;
4468 4469
	}

4470
	if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4471 4472 4473 4474 4475 4476 4477
		flash_buffer = kmalloc(264, GFP_KERNEL);
		if (flash_buffer == NULL) {
			rc = -ENOMEM;
			goto nvram_write_end;
		}
	}

4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491
	written = 0;
	while ((written < len32) && (rc == 0)) {
		u32 page_start, page_end, data_start, data_end;
		u32 addr, cmd_flags;
		int i;

	        /* Find the page_start addr */
		page_start = offset32 + written;
		page_start -= (page_start % bp->flash_info->page_size);
		/* Find the page_end addr */
		page_end = page_start + bp->flash_info->page_size;
		/* Find the data_start addr */
		data_start = (written == 0) ? offset32 : page_start;
		/* Find the data_end addr */
4492
		data_end = (page_end > offset32 + len32) ?
4493 4494 4495 4496 4497 4498 4499 4500 4501 4502
			(offset32 + len32) : page_end;

		/* Request access to the flash interface. */
		if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
			goto nvram_write_end;

		/* Enable access to flash interface */
		bnx2_enable_nvram_access(bp);

		cmd_flags = BNX2_NVM_COMMAND_FIRST;
4503
		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4504 4505 4506 4507 4508 4509 4510 4511 4512
			int j;

			/* Read the whole page into the buffer
			 * (non-buffer flash only) */
			for (j = 0; j < bp->flash_info->page_size; j += 4) {
				if (j == (bp->flash_info->page_size - 4)) {
					cmd_flags |= BNX2_NVM_COMMAND_LAST;
				}
				rc = bnx2_nvram_read_dword(bp,
4513 4514
					page_start + j,
					&flash_buffer[j],
4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530
					cmd_flags);

				if (rc)
					goto nvram_write_end;

				cmd_flags = 0;
			}
		}

		/* Enable writes to flash interface (unlock write-protect) */
		if ((rc = bnx2_enable_nvram_write(bp)) != 0)
			goto nvram_write_end;

		/* Loop to write back the buffer data from page_start to
		 * data_start */
		i = 0;
4531
		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4532 4533 4534 4535 4536 4537 4538
			/* Erase the page */
			if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
				goto nvram_write_end;

			/* Re-enable the write again for the actual write */
			bnx2_enable_nvram_write(bp);

4539 4540
			for (addr = page_start; addr < data_start;
				addr += 4, i += 4) {
4541

4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552
				rc = bnx2_nvram_write_dword(bp, addr,
					&flash_buffer[i], cmd_flags);

				if (rc != 0)
					goto nvram_write_end;

				cmd_flags = 0;
			}
		}

		/* Loop to write the new data from data_start to data_end */
4553
		for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4554
			if ((addr == page_end - 4) ||
4555
				((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571
				 (addr == data_end - 4))) {

				cmd_flags |= BNX2_NVM_COMMAND_LAST;
			}
			rc = bnx2_nvram_write_dword(bp, addr, buf,
				cmd_flags);

			if (rc != 0)
				goto nvram_write_end;

			cmd_flags = 0;
			buf += 4;
		}

		/* Loop to write back the buffer data from data_end
		 * to page_end */
4572
		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4573 4574
			for (addr = data_end; addr < page_end;
				addr += 4, i += 4) {
4575

4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600
				if (addr == page_end-4) {
					cmd_flags = BNX2_NVM_COMMAND_LAST;
                		}
				rc = bnx2_nvram_write_dword(bp, addr,
					&flash_buffer[i], cmd_flags);

				if (rc != 0)
					goto nvram_write_end;

				cmd_flags = 0;
			}
		}

		/* Disable writes to flash interface (lock write-protect) */
		bnx2_disable_nvram_write(bp);

		/* Disable access to flash interface */
		bnx2_disable_nvram_access(bp);
		bnx2_release_nvram_lock(bp);

		/* Increment written */
		written += data_end - data_start;
	}

nvram_write_end:
4601 4602
	kfree(flash_buffer);
	kfree(align_buf);
4603 4604 4605
	return rc;
}

4606
static void
4607
bnx2_init_fw_cap(struct bnx2 *bp)
4608
{
4609
	u32 val, sig = 0;
4610

4611
	bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4612 4613 4614 4615
	bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;

	if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4616

4617
	val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4618 4619 4620
	if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
		return;

4621 4622 4623 4624 4625 4626 4627 4628 4629
	if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
		sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
	}

	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
	    (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
		u32 link;

4630
		bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4631

4632 4633
		link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
		if (link & BNX2_LINK_STATUS_SERDES_LINK)
4634 4635 4636
			bp->phy_port = PORT_FIBRE;
		else
			bp->phy_port = PORT_TP;
4637

4638 4639
		sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
		       BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4640
	}
4641 4642 4643

	if (netif_running(bp->dev) && sig)
		bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4644 4645
}

4646 4647 4648 4649 4650 4651 4652 4653 4654
static void
bnx2_setup_msix_tbl(struct bnx2 *bp)
{
	REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);

	REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
	REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
}

4655 4656 4657 4658 4659
static int
bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
{
	u32 val;
	int i, rc = 0;
4660
	u8 old_port;
4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671

	/* Wait for the current PCI transaction to complete before
	 * issuing a reset. */
	REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
	       BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
	       BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
	       BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
	       BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
	val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
	udelay(5);

4672
	/* Wait for the firmware to tell us it is ok to issue a reset. */
4673
	bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4674

4675 4676
	/* Deposit a driver reset signature so the firmware knows that
	 * this is a soft reset. */
4677 4678
	bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
		      BNX2_DRV_RESET_SIGNATURE_MAGIC);
4679 4680 4681 4682 4683

	/* Do a dummy read to force the chip to complete all current transaction
	 * before we issue a reset. */
	val = REG_RD(bp, BNX2_MISC_ID);

4684 4685 4686 4687
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
		REG_RD(bp, BNX2_MISC_COMMAND);
		udelay(5);
4688

4689 4690
		val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
		      BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4691

4692
		pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4693

4694 4695 4696 4697 4698 4699 4700 4701
	} else {
		val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
		      BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
		      BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;

		/* Chip reset. */
		REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);

4702 4703 4704 4705
		/* Reading back any register after chip reset will hang the
		 * bus on 5706 A0 and A1.  The msleep below provides plenty
		 * of margin for write posting.
		 */
4706
		if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
A
Arjan van de Ven 已提交
4707 4708
		    (CHIP_ID(bp) == CHIP_ID_5706_A1))
			msleep(20);
4709

4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723
		/* Reset takes approximate 30 usec */
		for (i = 0; i < 10; i++) {
			val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
			if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
				    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
				break;
			udelay(10);
		}

		if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
			   BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
			printk(KERN_ERR PFX "Chip reset did not complete\n");
			return -EBUSY;
		}
4724 4725 4726 4727 4728 4729 4730 4731 4732 4733
	}

	/* Make sure byte swapping is properly configured. */
	val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
	if (val != 0x01020304) {
		printk(KERN_ERR PFX "Chip not in correct endian mode\n");
		return -ENODEV;
	}

	/* Wait for the firmware to finish its initialization. */
4734
	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4735 4736
	if (rc)
		return rc;
4737

4738
	spin_lock_bh(&bp->phy_lock);
4739
	old_port = bp->phy_port;
4740
	bnx2_init_fw_cap(bp);
4741 4742
	if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
	    old_port != bp->phy_port)
4743 4744 4745
		bnx2_set_default_remote_link(bp);
	spin_unlock_bh(&bp->phy_lock);

4746 4747 4748 4749 4750 4751 4752 4753 4754
	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		/* Adjust the voltage regular to two steps lower.  The default
		 * of this register is 0x0000000e. */
		REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);

		/* Remove bad rbuf memory from the free pool. */
		rc = bnx2_alloc_bad_rbuf(bp);
	}

4755
	if (bp->flags & BNX2_FLAG_USING_MSIX)
4756 4757
		bnx2_setup_msix_tbl(bp);

4758 4759 4760 4761 4762 4763
	return rc;
}

static int
bnx2_init_chip(struct bnx2 *bp)
{
4764
	u32 val, mtu;
4765
	int rc, i;
4766 4767 4768 4769 4770 4771 4772

	/* Make sure the interrupt is not active. */
	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);

	val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
	      BNX2_DMA_CONFIG_DATA_WORD_SWAP |
#ifdef __BIG_ENDIAN
4773
	      BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4774
#endif
4775
	      BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4776 4777 4778 4779 4780
	      DMA_READ_CHANS << 12 |
	      DMA_WRITE_CHANS << 16;

	val |= (0x2 << 20) | (1 << 11);

4781
	if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4782 4783 4784
		val |= (1 << 23);

	if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4785
	    (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4786 4787 4788 4789 4790 4791 4792 4793 4794 4795
		val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;

	REG_WR(bp, BNX2_DMA_CONFIG, val);

	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		val = REG_RD(bp, BNX2_TDMA_CONFIG);
		val |= BNX2_TDMA_CONFIG_ONE_DMA;
		REG_WR(bp, BNX2_TDMA_CONFIG, val);
	}

4796
	if (bp->flags & BNX2_FLAG_PCIX) {
4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811
		u16 val16;

		pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
				     &val16);
		pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
				      val16 & ~PCI_X_CMD_ERO);
	}

	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
	       BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
	       BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
	       BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);

	/* Initialize context mapping and zero out the quick contexts.  The
	 * context block must have already been enabled. */
4812 4813 4814 4815 4816
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		rc = bnx2_init_5709_context(bp);
		if (rc)
			return rc;
	} else
4817
		bnx2_init_context(bp);
4818

4819 4820 4821
	if ((rc = bnx2_init_cpus(bp)) != 0)
		return rc;

4822 4823
	bnx2_init_nvram(bp);

4824
	bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4825 4826 4827 4828

	val = REG_RD(bp, BNX2_MQ_CONFIG);
	val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
	val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4829 4830 4831 4832 4833
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
		if (CHIP_REV(bp) == CHIP_REV_Ax)
			val |= BNX2_MQ_CONFIG_HALT_DIS;
	}
4834

4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858
	REG_WR(bp, BNX2_MQ_CONFIG, val);

	val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
	REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
	REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);

	val = (BCM_PAGE_BITS - 8) << 24;
	REG_WR(bp, BNX2_RV2P_CONFIG, val);

	/* Configure page size. */
	val = REG_RD(bp, BNX2_TBDR_CONFIG);
	val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
	val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
	REG_WR(bp, BNX2_TBDR_CONFIG, val);

	val = bp->mac_addr[0] +
	      (bp->mac_addr[1] << 8) +
	      (bp->mac_addr[2] << 16) +
	      bp->mac_addr[3] +
	      (bp->mac_addr[4] << 8) +
	      (bp->mac_addr[5] << 16);
	REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);

	/* Program the MTU.  Also include 4 bytes for CRC32. */
4859 4860
	mtu = bp->dev->mtu;
	val = mtu + ETH_HLEN + ETH_FCS_LEN;
4861 4862 4863 4864
	if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
		val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
	REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);

4865 4866 4867 4868 4869 4870 4871
	if (mtu < 1500)
		mtu = 1500;

	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));

4872
	memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4873 4874 4875
	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
		bp->bnx2_napi[i].last_status_idx = 0;

4876 4877
	bp->idle_chk_status_idx = 0xffff;

4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891
	bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;

	/* Set up how to generate a link change interrupt. */
	REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);

	REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
	       (u64) bp->status_blk_mapping & 0xffffffff);
	REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);

	REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
	       (u64) bp->stats_blk_mapping & 0xffffffff);
	REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
	       (u64) bp->stats_blk_mapping >> 32);

4892
	REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910
	       (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);

	REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
	       (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);

	REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
	       (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);

	REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);

	REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);

	REG_WR(bp, BNX2_HC_COM_TICKS,
	       (bp->com_ticks_int << 16) | bp->com_ticks);

	REG_WR(bp, BNX2_HC_CMD_TICKS,
	       (bp->cmd_ticks_int << 16) | bp->cmd_ticks);

4911
	if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4912 4913
		REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
	else
4914
		REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4915 4916 4917
	REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */

	if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4918
		val = BNX2_HC_CONFIG_COLLECT_STATS;
4919
	else {
4920 4921
		val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
		      BNX2_HC_CONFIG_COLLECT_STATS;
4922 4923
	}

4924
	if (bp->irq_nvecs > 1) {
4925 4926 4927
		REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
		       BNX2_HC_MSIX_BIT_VECTOR_VAL);

4928 4929 4930 4931
		val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
	}

	if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4932
		val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4933 4934 4935 4936 4937 4938 4939

	REG_WR(bp, BNX2_HC_CONFIG, val);

	for (i = 1; i < bp->irq_nvecs; i++) {
		u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
			   BNX2_HC_SB_CONFIG_1;

4940
		REG_WR(bp, base,
4941
			BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4942
			BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4943 4944
			BNX2_HC_SB_CONFIG_1_ONE_SHOT);

4945
		REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4946 4947 4948
			(bp->tx_quick_cons_trip_int << 16) |
			 bp->tx_quick_cons_trip);

4949
		REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4950 4951
			(bp->tx_ticks_int << 16) | bp->tx_ticks);

4952 4953 4954
		REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
		       (bp->rx_quick_cons_trip_int << 16) |
			bp->rx_quick_cons_trip);
4955

4956 4957 4958
		REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
			(bp->rx_ticks_int << 16) | bp->rx_ticks);
	}
4959

4960 4961 4962
	/* Clear internal stats counters. */
	REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);

4963
	REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4964 4965 4966 4967

	/* Initialize the receive filter. */
	bnx2_set_rx_mode(bp->dev);

4968 4969 4970 4971 4972
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
		val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
		REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
	}
4973
	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4974
			  1, 0);
4975

4976
	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4977 4978 4979 4980
	REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);

	udelay(20);

4981 4982
	bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);

4983
	return rc;
4984 4985
}

4986 4987 4988 4989
static void
bnx2_clear_ring_states(struct bnx2 *bp)
{
	struct bnx2_napi *bnapi;
4990
	struct bnx2_tx_ring_info *txr;
4991
	struct bnx2_rx_ring_info *rxr;
4992 4993 4994 4995
	int i;

	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
		bnapi = &bp->bnx2_napi[i];
4996
		txr = &bnapi->tx_ring;
4997
		rxr = &bnapi->rx_ring;
4998

4999 5000
		txr->tx_cons = 0;
		txr->hw_tx_cons = 0;
5001 5002 5003 5004 5005
		rxr->rx_prod_bseq = 0;
		rxr->rx_prod = 0;
		rxr->rx_cons = 0;
		rxr->rx_pg_prod = 0;
		rxr->rx_pg_cons = 0;
5006 5007 5008
	}
}

5009
static void
5010
bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5011 5012
{
	u32 val, offset0, offset1, offset2, offset3;
5013
	u32 cid_addr = GET_CID_ADDR(cid);
5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		offset0 = BNX2_L2CTX_TYPE_XI;
		offset1 = BNX2_L2CTX_CMD_TYPE_XI;
		offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
		offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
	} else {
		offset0 = BNX2_L2CTX_TYPE;
		offset1 = BNX2_L2CTX_CMD_TYPE;
		offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
		offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
	}
	val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5027
	bnx2_ctx_wr(bp, cid_addr, offset0, val);
5028 5029

	val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5030
	bnx2_ctx_wr(bp, cid_addr, offset1, val);
5031

5032
	val = (u64) txr->tx_desc_mapping >> 32;
5033
	bnx2_ctx_wr(bp, cid_addr, offset2, val);
5034

5035
	val = (u64) txr->tx_desc_mapping & 0xffffffff;
5036
	bnx2_ctx_wr(bp, cid_addr, offset3, val);
5037
}
5038 5039

static void
5040
bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5041 5042
{
	struct tx_bd *txbd;
5043 5044
	u32 cid = TX_CID;
	struct bnx2_napi *bnapi;
5045
	struct bnx2_tx_ring_info *txr;
5046

5047 5048 5049 5050 5051 5052 5053
	bnapi = &bp->bnx2_napi[ring_num];
	txr = &bnapi->tx_ring;

	if (ring_num == 0)
		cid = TX_CID;
	else
		cid = TX_TSS_CID + ring_num - 1;
5054

5055 5056
	bp->tx_wake_thresh = bp->tx_ring_size / 2;

5057
	txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5058

5059 5060
	txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
	txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5061

5062 5063
	txr->tx_prod = 0;
	txr->tx_prod_bseq = 0;
5064

5065 5066
	txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
	txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5067

5068
	bnx2_init_tx_context(bp, cid, txr);
5069 5070 5071
}

static void
5072 5073
bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
		     int num_rings)
5074 5075
{
	int i;
5076
	struct rx_bd *rxbd;
5077

5078
	for (i = 0; i < num_rings; i++) {
5079
		int j;
5080

5081
		rxbd = &rx_ring[i][0];
5082
		for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5083
			rxbd->rx_bd_len = buf_size;
5084 5085
			rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
		}
5086
		if (i == (num_rings - 1))
5087 5088 5089
			j = 0;
		else
			j = i + 1;
5090 5091
		rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
		rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5092
	}
5093 5094 5095
}

static void
5096
bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5097 5098 5099
{
	int i;
	u16 prod, ring_prod;
5100 5101 5102 5103 5104 5105 5106 5107 5108 5109
	u32 cid, rx_cid_addr, val;
	struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;

	if (ring_num == 0)
		cid = RX_CID;
	else
		cid = RX_RSS_CID + ring_num - 1;

	rx_cid_addr = GET_CID_ADDR(cid);
5110

5111
	bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5112 5113
			     bp->rx_buf_use_size, bp->rx_max_ring);

5114
	bnx2_init_rx_context(bp, cid);
5115 5116 5117 5118 5119 5120

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
		REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
	}

5121
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5122
	if (bp->rx_pg_ring_size) {
5123 5124
		bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
				     rxr->rx_pg_desc_mapping,
5125 5126
				     PAGE_SIZE, bp->rx_max_pg_ring);
		val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5127 5128
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5129
		       BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5130

5131
		val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5132
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5133

5134
		val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5135
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5136 5137 5138 5139

		if (CHIP_NUM(bp) == CHIP_NUM_5709)
			REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
	}
5140

5141
	val = (u64) rxr->rx_desc_mapping[0] >> 32;
5142
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5143

5144
	val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5145
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5146

5147
	ring_prod = prod = rxr->rx_pg_prod;
5148
	for (i = 0; i < bp->rx_pg_ring_size; i++) {
5149
		if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
5150 5151 5152 5153
			break;
		prod = NEXT_RX_BD(prod);
		ring_prod = RX_PG_RING_IDX(prod);
	}
5154
	rxr->rx_pg_prod = prod;
5155

5156
	ring_prod = prod = rxr->rx_prod;
5157
	for (i = 0; i < bp->rx_ring_size; i++) {
5158
		if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
5159 5160 5161 5162
			break;
		prod = NEXT_RX_BD(prod);
		ring_prod = RX_RING_IDX(prod);
	}
5163
	rxr->rx_prod = prod;
5164

5165 5166 5167
	rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
	rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
	rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5168

5169 5170 5171 5172
	REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
	REG_WR16(bp, rxr->rx_bidx_addr, prod);

	REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5173 5174
}

5175 5176 5177 5178
static void
bnx2_init_all_rings(struct bnx2 *bp)
{
	int i;
5179
	u32 val;
5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190

	bnx2_clear_ring_states(bp);

	REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
	for (i = 0; i < bp->num_tx_rings; i++)
		bnx2_init_tx_ring(bp, i);

	if (bp->num_tx_rings > 1)
		REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
		       (TX_TSS_CID << 7));

5191 5192 5193
	REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
	bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);

5194 5195
	for (i = 0; i < bp->num_rx_rings; i++)
		bnx2_init_rx_ring(bp, i);
5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217

	if (bp->num_rx_rings > 1) {
		u32 tbl_32;
		u8 *tbl = (u8 *) &tbl_32;

		bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
				BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);

		for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
			tbl[i % 4] = i % (bp->num_rx_rings - 1);
			if ((i % 4) == 3)
				bnx2_reg_wr_ind(bp,
						BNX2_RXP_SCRATCH_RSS_TBL + i,
						cpu_to_be32(tbl_32));
		}

		val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
		      BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;

		REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);

	}
5218 5219
}

5220
static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5221
{
5222
	u32 max, num_rings = 1;
5223

5224 5225
	while (ring_size > MAX_RX_DESC_CNT) {
		ring_size -= MAX_RX_DESC_CNT;
5226 5227 5228
		num_rings++;
	}
	/* round to next power of 2 */
5229
	max = max_size;
5230 5231 5232 5233 5234 5235
	while ((max & num_rings) == 0)
		max >>= 1;

	if (num_rings != max)
		max <<= 1;

5236 5237 5238 5239 5240 5241
	return max;
}

static void
bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
{
5242
	u32 rx_size, rx_space, jumbo_size;
5243 5244

	/* 8 for CRC and VLAN */
5245
	rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5246

5247 5248 5249
	rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
		sizeof(struct skb_shared_info);

5250
	bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5251 5252 5253
	bp->rx_pg_ring_size = 0;
	bp->rx_max_pg_ring = 0;
	bp->rx_max_pg_ring_idx = 0;
5254
	if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5255 5256 5257 5258 5259 5260 5261 5262 5263 5264
		int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;

		jumbo_size = size * pages;
		if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
			jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;

		bp->rx_pg_ring_size = jumbo_size;
		bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
							MAX_RX_PG_RINGS);
		bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5265
		rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5266 5267
		bp->rx_copy_thresh = 0;
	}
5268 5269 5270 5271

	bp->rx_buf_use_size = rx_size;
	/* hw alignment */
	bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5272
	bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5273 5274
	bp->rx_ring_size = size;
	bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5275 5276 5277
	bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
}

5278 5279 5280 5281 5282
static void
bnx2_free_tx_skbs(struct bnx2 *bp)
{
	int i;

5283 5284 5285 5286
	for (i = 0; i < bp->num_tx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
		int j;
5287

5288
		if (txr->tx_buf_ring == NULL)
5289 5290
			continue;

5291
		for (j = 0; j < TX_DESC_CNT; ) {
5292
			struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5293 5294 5295 5296 5297 5298 5299
			struct sk_buff *skb = tx_buf->skb;

			if (skb == NULL) {
				j++;
				continue;
			}

5300
			skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5301

5302
			tx_buf->skb = NULL;
5303

5304
			j += skb_shinfo(skb)->nr_frags + 1;
5305
			dev_kfree_skb(skb);
5306 5307 5308 5309 5310 5311 5312 5313 5314
		}
	}
}

static void
bnx2_free_rx_skbs(struct bnx2 *bp)
{
	int i;

5315 5316 5317 5318
	for (i = 0; i < bp->num_rx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
		int j;
5319

5320 5321
		if (rxr->rx_buf_ring == NULL)
			return;
5322

5323 5324 5325
		for (j = 0; j < bp->rx_max_ring_idx; j++) {
			struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
			struct sk_buff *skb = rx_buf->skb;
5326

5327 5328
			if (skb == NULL)
				continue;
5329

5330 5331 5332 5333
			pci_unmap_single(bp->pdev,
					 pci_unmap_addr(rx_buf, mapping),
					 bp->rx_buf_use_size,
					 PCI_DMA_FROMDEVICE);
5334

5335 5336 5337 5338 5339 5340
			rx_buf->skb = NULL;

			dev_kfree_skb(skb);
		}
		for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
			bnx2_free_rx_page(bp, rxr, j);
5341 5342 5343 5344 5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355 5356 5357 5358 5359 5360
	}
}

static void
bnx2_free_skbs(struct bnx2 *bp)
{
	bnx2_free_tx_skbs(bp);
	bnx2_free_rx_skbs(bp);
}

static int
bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
{
	int rc;

	rc = bnx2_reset_chip(bp, reset_code);
	bnx2_free_skbs(bp);
	if (rc)
		return rc;

5361 5362 5363
	if ((rc = bnx2_init_chip(bp)) != 0)
		return rc;

5364
	bnx2_init_all_rings(bp);
5365 5366 5367 5368
	return 0;
}

static int
5369
bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5370 5371 5372 5373 5374 5375
{
	int rc;

	if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
		return rc;

5376
	spin_lock_bh(&bp->phy_lock);
5377
	bnx2_init_phy(bp, reset_phy);
5378
	bnx2_set_link(bp);
5379 5380
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
		bnx2_remote_phy_event(bp);
5381
	spin_unlock_bh(&bp->phy_lock);
5382 5383 5384
	return 0;
}

5385 5386 5387 5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399
static int
bnx2_shutdown_chip(struct bnx2 *bp)
{
	u32 reset_code;

	if (bp->flags & BNX2_FLAG_NO_WOL)
		reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
	else if (bp->wol)
		reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
	else
		reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;

	return bnx2_reset_chip(bp, reset_code);
}

5400 5401 5402 5403
static int
bnx2_test_registers(struct bnx2 *bp)
{
	int ret;
5404
	int i, is_5709;
5405
	static const struct {
5406 5407
		u16   offset;
		u16   flags;
5408
#define BNX2_FL_NOT_5709	1
5409 5410 5411 5412 5413 5414 5415
		u32   rw_mask;
		u32   ro_mask;
	} reg_tbl[] = {
		{ 0x006c, 0, 0x00000000, 0x0000003f },
		{ 0x0090, 0, 0xffffffff, 0x00000000 },
		{ 0x0094, 0, 0x00000000, 0x00000000 },

5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435
		{ 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
		{ 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
		{ 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
		{ 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
		{ 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
		{ 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },

		{ 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
		{ 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
		{ 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
		{ 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },

		{ 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
		{ 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
		{ 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5436 5437

		{ 0x1000, 0, 0x00000000, 0x00000001 },
5438
		{ 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5439 5440 5441 5442

		{ 0x1408, 0, 0x01c00800, 0x00000000 },
		{ 0x149c, 0, 0x8000ffff, 0x00000000 },
		{ 0x14a8, 0, 0x00000000, 0x000001ff },
5443
		{ 0x14ac, 0, 0x0fffffff, 0x10000000 },
5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520
		{ 0x14b0, 0, 0x00000002, 0x00000001 },
		{ 0x14b8, 0, 0x00000000, 0x00000000 },
		{ 0x14c0, 0, 0x00000000, 0x00000009 },
		{ 0x14c4, 0, 0x00003fff, 0x00000000 },
		{ 0x14cc, 0, 0x00000000, 0x00000001 },
		{ 0x14d0, 0, 0xffffffff, 0x00000000 },

		{ 0x1800, 0, 0x00000000, 0x00000001 },
		{ 0x1804, 0, 0x00000000, 0x00000003 },

		{ 0x2800, 0, 0x00000000, 0x00000001 },
		{ 0x2804, 0, 0x00000000, 0x00003f01 },
		{ 0x2808, 0, 0x0f3f3f03, 0x00000000 },
		{ 0x2810, 0, 0xffff0000, 0x00000000 },
		{ 0x2814, 0, 0xffff0000, 0x00000000 },
		{ 0x2818, 0, 0xffff0000, 0x00000000 },
		{ 0x281c, 0, 0xffff0000, 0x00000000 },
		{ 0x2834, 0, 0xffffffff, 0x00000000 },
		{ 0x2840, 0, 0x00000000, 0xffffffff },
		{ 0x2844, 0, 0x00000000, 0xffffffff },
		{ 0x2848, 0, 0xffffffff, 0x00000000 },
		{ 0x284c, 0, 0xf800f800, 0x07ff07ff },

		{ 0x2c00, 0, 0x00000000, 0x00000011 },
		{ 0x2c04, 0, 0x00000000, 0x00030007 },

		{ 0x3c00, 0, 0x00000000, 0x00000001 },
		{ 0x3c04, 0, 0x00000000, 0x00070000 },
		{ 0x3c08, 0, 0x00007f71, 0x07f00000 },
		{ 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
		{ 0x3c10, 0, 0xffffffff, 0x00000000 },
		{ 0x3c14, 0, 0x00000000, 0xffffffff },
		{ 0x3c18, 0, 0x00000000, 0xffffffff },
		{ 0x3c1c, 0, 0xfffff000, 0x00000000 },
		{ 0x3c20, 0, 0xffffff00, 0x00000000 },

		{ 0x5004, 0, 0x00000000, 0x0000007f },
		{ 0x5008, 0, 0x0f0007ff, 0x00000000 },

		{ 0x5c00, 0, 0x00000000, 0x00000001 },
		{ 0x5c04, 0, 0x00000000, 0x0003000f },
		{ 0x5c08, 0, 0x00000003, 0x00000000 },
		{ 0x5c0c, 0, 0x0000fff8, 0x00000000 },
		{ 0x5c10, 0, 0x00000000, 0xffffffff },
		{ 0x5c80, 0, 0x00000000, 0x0f7113f1 },
		{ 0x5c84, 0, 0x00000000, 0x0000f333 },
		{ 0x5c88, 0, 0x00000000, 0x00077373 },
		{ 0x5c8c, 0, 0x00000000, 0x0007f737 },

		{ 0x6808, 0, 0x0000ff7f, 0x00000000 },
		{ 0x680c, 0, 0xffffffff, 0x00000000 },
		{ 0x6810, 0, 0xffffffff, 0x00000000 },
		{ 0x6814, 0, 0xffffffff, 0x00000000 },
		{ 0x6818, 0, 0xffffffff, 0x00000000 },
		{ 0x681c, 0, 0xffffffff, 0x00000000 },
		{ 0x6820, 0, 0x00ff00ff, 0x00000000 },
		{ 0x6824, 0, 0x00ff00ff, 0x00000000 },
		{ 0x6828, 0, 0x00ff00ff, 0x00000000 },
		{ 0x682c, 0, 0x03ff03ff, 0x00000000 },
		{ 0x6830, 0, 0x03ff03ff, 0x00000000 },
		{ 0x6834, 0, 0x03ff03ff, 0x00000000 },
		{ 0x6838, 0, 0x03ff03ff, 0x00000000 },
		{ 0x683c, 0, 0x0000ffff, 0x00000000 },
		{ 0x6840, 0, 0x00000ff0, 0x00000000 },
		{ 0x6844, 0, 0x00ffff00, 0x00000000 },
		{ 0x684c, 0, 0xffffffff, 0x00000000 },
		{ 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x6908, 0, 0x00000000, 0x0001ff0f },
		{ 0x690c, 0, 0x00000000, 0x0ffe00f0 },

		{ 0xffff, 0, 0x00000000, 0x00000000 },
	};

	ret = 0;
5521 5522 5523 5524
	is_5709 = 0;
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		is_5709 = 1;

5525 5526
	for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
		u32 offset, rw_mask, ro_mask, save_val, val;
5527 5528 5529 5530
		u16 flags = reg_tbl[i].flags;

		if (is_5709 && (flags & BNX2_FL_NOT_5709))
			continue;
5531 5532 5533 5534 5535

		offset = (u32) reg_tbl[i].offset;
		rw_mask = reg_tbl[i].rw_mask;
		ro_mask = reg_tbl[i].ro_mask;

5536
		save_val = readl(bp->regview + offset);
5537

5538
		writel(0, bp->regview + offset);
5539

5540
		val = readl(bp->regview + offset);
5541 5542 5543 5544 5545 5546 5547 5548
		if ((val & rw_mask) != 0) {
			goto reg_test_err;
		}

		if ((val & ro_mask) != (save_val & ro_mask)) {
			goto reg_test_err;
		}

5549
		writel(0xffffffff, bp->regview + offset);
5550

5551
		val = readl(bp->regview + offset);
5552 5553 5554 5555 5556 5557 5558 5559
		if ((val & rw_mask) != rw_mask) {
			goto reg_test_err;
		}

		if ((val & ro_mask) != (save_val & ro_mask)) {
			goto reg_test_err;
		}

5560
		writel(save_val, bp->regview + offset);
5561 5562 5563
		continue;

reg_test_err:
5564
		writel(save_val, bp->regview + offset);
5565 5566 5567 5568 5569 5570 5571 5572 5573
		ret = -ENODEV;
		break;
	}
	return ret;
}

static int
bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
{
5574
	static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5575 5576 5577 5578 5579 5580 5581 5582
		0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
	int i;

	for (i = 0; i < sizeof(test_pattern) / 4; i++) {
		u32 offset;

		for (offset = 0; offset < size; offset += 4) {

5583
			bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5584

5585
			if (bnx2_reg_rd_ind(bp, start + offset) !=
5586 5587 5588 5589 5590 5591 5592 5593 5594 5595 5596 5597 5598
				test_pattern[i]) {
				return -ENODEV;
			}
		}
	}
	return 0;
}

static int
bnx2_test_memory(struct bnx2 *bp)
{
	int ret = 0;
	int i;
5599
	static struct mem_entry {
5600 5601
		u32   offset;
		u32   len;
5602
	} mem_tbl_5706[] = {
5603
		{ 0x60000,  0x4000 },
5604
		{ 0xa0000,  0x3000 },
5605 5606 5607 5608 5609
		{ 0xe0000,  0x4000 },
		{ 0x120000, 0x4000 },
		{ 0x1a0000, 0x4000 },
		{ 0x160000, 0x4000 },
		{ 0xffffffff, 0    },
5610 5611 5612 5613 5614 5615 5616 5617
	},
	mem_tbl_5709[] = {
		{ 0x60000,  0x4000 },
		{ 0xa0000,  0x3000 },
		{ 0xe0000,  0x4000 },
		{ 0x120000, 0x4000 },
		{ 0x1a0000, 0x4000 },
		{ 0xffffffff, 0    },
5618
	};
5619 5620 5621 5622 5623 5624
	struct mem_entry *mem_tbl;

	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		mem_tbl = mem_tbl_5709;
	else
		mem_tbl = mem_tbl_5706;
5625 5626 5627 5628 5629 5630 5631

	for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
		if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
			mem_tbl[i].len)) != 0) {
			return ret;
		}
	}
5632

5633 5634 5635
	return ret;
}

5636 5637 5638
#define BNX2_MAC_LOOPBACK	0
#define BNX2_PHY_LOOPBACK	1

5639
static int
5640
bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5641 5642 5643 5644
{
	unsigned int pkt_size, num_pkts, i;
	struct sk_buff *skb, *rx_skb;
	unsigned char *packet;
5645
	u16 rx_start_idx, rx_idx;
5646 5647 5648 5649 5650
	dma_addr_t map;
	struct tx_bd *txbd;
	struct sw_bd *rx_buf;
	struct l2_fhdr *rx_hdr;
	int ret = -ENODEV;
5651
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5652
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5653
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5654 5655

	tx_napi = bnapi;
5656

5657
	txr = &tx_napi->tx_ring;
5658
	rxr = &bnapi->rx_ring;
5659 5660 5661 5662 5663
	if (loopback_mode == BNX2_MAC_LOOPBACK) {
		bp->loopback = MAC_LOOPBACK;
		bnx2_set_mac_loopback(bp);
	}
	else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5664
		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5665 5666
			return 0;

5667
		bp->loopback = PHY_LOOPBACK;
5668 5669 5670 5671
		bnx2_set_phy_loopback(bp);
	}
	else
		return -EINVAL;
5672

5673
	pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5674
	skb = netdev_alloc_skb(bp->dev, pkt_size);
5675 5676
	if (!skb)
		return -ENOMEM;
5677
	packet = skb_put(skb, pkt_size);
5678
	memcpy(packet, bp->dev->dev_addr, 6);
5679 5680 5681 5682
	memset(packet + 6, 0x0, 8);
	for (i = 14; i < pkt_size; i++)
		packet[i] = (unsigned char) (i & 0xff);

5683 5684 5685 5686
	if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
		dev_kfree_skb(skb);
		return -EIO;
	}
5687
	map = skb_shinfo(skb)->dma_head;
5688

5689 5690 5691
	REG_WR(bp, BNX2_HC_COMMAND,
	       bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);

5692 5693 5694
	REG_RD(bp, BNX2_HC_COMMAND);

	udelay(5);
5695
	rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5696 5697 5698

	num_pkts = 0;

5699
	txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5700 5701 5702 5703 5704 5705 5706

	txbd->tx_bd_haddr_hi = (u64) map >> 32;
	txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
	txbd->tx_bd_mss_nbytes = pkt_size;
	txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;

	num_pkts++;
5707 5708
	txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
	txr->tx_prod_bseq += pkt_size;
5709

5710 5711
	REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
	REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5712 5713 5714

	udelay(100);

5715 5716 5717
	REG_WR(bp, BNX2_HC_COMMAND,
	       bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);

5718 5719 5720 5721
	REG_RD(bp, BNX2_HC_COMMAND);

	udelay(5);

5722
	skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5723
	dev_kfree_skb(skb);
5724

5725
	if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5726 5727
		goto loopback_test_done;

5728
	rx_idx = bnx2_get_hw_rx_cons(bnapi);
5729 5730 5731 5732
	if (rx_idx != rx_start_idx + num_pkts) {
		goto loopback_test_done;
	}

5733
	rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5734 5735 5736
	rx_skb = rx_buf->skb;

	rx_hdr = (struct l2_fhdr *) rx_skb->data;
5737
	skb_reserve(rx_skb, BNX2_RX_OFFSET);
5738 5739 5740 5741 5742

	pci_dma_sync_single_for_cpu(bp->pdev,
		pci_unmap_addr(rx_buf, mapping),
		bp->rx_buf_size, PCI_DMA_FROMDEVICE);

5743
	if (rx_hdr->l2_fhdr_status &
5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757 5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769
		(L2_FHDR_ERRORS_BAD_CRC |
		L2_FHDR_ERRORS_PHY_DECODE |
		L2_FHDR_ERRORS_ALIGNMENT |
		L2_FHDR_ERRORS_TOO_SHORT |
		L2_FHDR_ERRORS_GIANT_FRAME)) {

		goto loopback_test_done;
	}

	if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
		goto loopback_test_done;
	}

	for (i = 14; i < pkt_size; i++) {
		if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
			goto loopback_test_done;
		}
	}

	ret = 0;

loopback_test_done:
	bp->loopback = 0;
	return ret;
}

5770 5771 5772 5773 5774 5775 5776 5777 5778 5779 5780 5781 5782 5783 5784
#define BNX2_MAC_LOOPBACK_FAILED	1
#define BNX2_PHY_LOOPBACK_FAILED	2
#define BNX2_LOOPBACK_FAILED		(BNX2_MAC_LOOPBACK_FAILED |	\
					 BNX2_PHY_LOOPBACK_FAILED)

static int
bnx2_test_loopback(struct bnx2 *bp)
{
	int rc = 0;

	if (!netif_running(bp->dev))
		return BNX2_LOOPBACK_FAILED;

	bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
	spin_lock_bh(&bp->phy_lock);
5785
	bnx2_init_phy(bp, 1);
5786 5787 5788 5789 5790 5791 5792 5793
	spin_unlock_bh(&bp->phy_lock);
	if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
		rc |= BNX2_MAC_LOOPBACK_FAILED;
	if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
		rc |= BNX2_PHY_LOOPBACK_FAILED;
	return rc;
}

5794 5795 5796 5797 5798 5799
#define NVRAM_SIZE 0x200
#define CRC32_RESIDUAL 0xdebb20e3

static int
bnx2_test_nvram(struct bnx2 *bp)
{
A
Al Viro 已提交
5800
	__be32 buf[NVRAM_SIZE / 4];
5801 5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818 5819 5820 5821 5822 5823 5824 5825 5826 5827 5828 5829 5830 5831 5832 5833 5834 5835 5836
	u8 *data = (u8 *) buf;
	int rc = 0;
	u32 magic, csum;

	if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
		goto test_nvram_done;

        magic = be32_to_cpu(buf[0]);
	if (magic != 0x669955aa) {
		rc = -ENODEV;
		goto test_nvram_done;
	}

	if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
		goto test_nvram_done;

	csum = ether_crc_le(0x100, data);
	if (csum != CRC32_RESIDUAL) {
		rc = -ENODEV;
		goto test_nvram_done;
	}

	csum = ether_crc_le(0x100, data + 0x100);
	if (csum != CRC32_RESIDUAL) {
		rc = -ENODEV;
	}

test_nvram_done:
	return rc;
}

static int
bnx2_test_link(struct bnx2 *bp)
{
	u32 bmsr;

5837 5838 5839
	if (!netif_running(bp->dev))
		return -ENODEV;

5840
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5841 5842 5843 5844
		if (bp->link_up)
			return 0;
		return -ENODEV;
	}
5845
	spin_lock_bh(&bp->phy_lock);
5846 5847 5848 5849
	bnx2_enable_bmsr1(bp);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_disable_bmsr1(bp);
5850
	spin_unlock_bh(&bp->phy_lock);
5851

5852 5853 5854 5855 5856 5857 5858 5859 5860 5861 5862 5863 5864 5865 5866 5867 5868 5869
	if (bmsr & BMSR_LSTATUS) {
		return 0;
	}
	return -ENODEV;
}

static int
bnx2_test_intr(struct bnx2 *bp)
{
	int i;
	u16 status_idx;

	if (!netif_running(bp->dev))
		return -ENODEV;

	status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;

	/* This register is not touched during run-time. */
5870
	REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5871 5872 5873 5874 5875 5876 5877 5878 5879 5880 5881 5882 5883 5884 5885 5886 5887
	REG_RD(bp, BNX2_HC_COMMAND);

	for (i = 0; i < 10; i++) {
		if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
			status_idx) {

			break;
		}

		msleep_interruptible(10);
	}
	if (i < 10)
		return 0;

	return -ENODEV;
}

5888
/* Determining link for parallel detection. */
5889 5890 5891 5892 5893
static int
bnx2_5706_serdes_has_link(struct bnx2 *bp)
{
	u32 mode_ctl, an_dbg, exp;

5894 5895 5896
	if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
		return 0;

5897 5898 5899 5900 5901 5902 5903 5904 5905 5906
	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);

	if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
		return 0;

	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);

5907
	if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5908 5909 5910 5911 5912 5913 5914 5915 5916 5917 5918 5919
		return 0;

	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);

	if (exp & MII_EXPAND_REG1_RUDI_C)	/* receiving CONFIG */
		return 0;

	return 1;
}

5920
static void
5921
bnx2_5706_serdes_timer(struct bnx2 *bp)
5922
{
5923 5924
	int check_link = 1;

5925
	spin_lock(&bp->phy_lock);
5926
	if (bp->serdes_an_pending) {
5927
		bp->serdes_an_pending--;
5928 5929
		check_link = 0;
	} else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5930
		u32 bmcr;
5931

5932
		bp->current_interval = BNX2_TIMER_INTERVAL;
5933

5934
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5935

5936
		if (bmcr & BMCR_ANENABLE) {
5937
			if (bnx2_5706_serdes_has_link(bp)) {
5938 5939
				bmcr &= ~BMCR_ANENABLE;
				bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5940
				bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5941
				bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5942
			}
5943
		}
5944 5945
	}
	else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5946
		 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5947
		u32 phy2;
5948

5949 5950 5951 5952
		bnx2_write_phy(bp, 0x17, 0x0f01);
		bnx2_read_phy(bp, 0x15, &phy2);
		if (phy2 & 0x20) {
			u32 bmcr;
5953

5954
			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5955
			bmcr |= BMCR_ANENABLE;
5956
			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5957

5958
			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5959 5960
		}
	} else
5961
		bp->current_interval = BNX2_TIMER_INTERVAL;
5962

5963
	if (check_link) {
5964 5965 5966 5967 5968 5969
		u32 val;

		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);

5970 5971 5972 5973 5974 5975 5976 5977
		if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
			if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
				bnx2_5706s_force_link_dn(bp, 1);
				bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
			} else
				bnx2_set_link(bp);
		} else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
			bnx2_set_link(bp);
5978
	}
5979 5980
	spin_unlock(&bp->phy_lock);
}
5981

5982 5983 5984
static void
bnx2_5708_serdes_timer(struct bnx2 *bp)
{
5985
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5986 5987
		return;

5988
	if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5989 5990 5991
		bp->serdes_an_pending = 0;
		return;
	}
5992

5993 5994 5995 5996 5997
	spin_lock(&bp->phy_lock);
	if (bp->serdes_an_pending)
		bp->serdes_an_pending--;
	else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
		u32 bmcr;
5998

5999
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6000
		if (bmcr & BMCR_ANENABLE) {
6001
			bnx2_enable_forced_2g5(bp);
6002
			bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6003
		} else {
6004
			bnx2_disable_forced_2g5(bp);
6005
			bp->serdes_an_pending = 2;
6006
			bp->current_interval = BNX2_TIMER_INTERVAL;
6007 6008
		}

6009
	} else
6010
		bp->current_interval = BNX2_TIMER_INTERVAL;
6011

6012 6013 6014
	spin_unlock(&bp->phy_lock);
}

6015 6016 6017 6018
static void
bnx2_timer(unsigned long data)
{
	struct bnx2 *bp = (struct bnx2 *) data;
6019

6020 6021
	if (!netif_running(bp->dev))
		return;
6022

6023 6024
	if (atomic_read(&bp->intr_sem) != 0)
		goto bnx2_restart_timer;
6025

6026 6027 6028 6029
	if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
	     BNX2_FLAG_USING_MSI)
		bnx2_chk_missed_msi(bp);

6030
	bnx2_send_heart_beat(bp);
6031

6032 6033
	bp->stats_blk->stat_FwRxDrop =
		bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6034

6035
	/* workaround occasional corrupted counters */
6036
	if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6037 6038 6039
		REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
					    BNX2_HC_COMMAND_STATS_NOW);

6040
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6041 6042
		if (CHIP_NUM(bp) == CHIP_NUM_5706)
			bnx2_5706_serdes_timer(bp);
6043
		else
6044
			bnx2_5708_serdes_timer(bp);
6045 6046 6047
	}

bnx2_restart_timer:
6048
	mod_timer(&bp->timer, jiffies + bp->current_interval);
6049 6050
}

6051 6052 6053
static int
bnx2_request_irq(struct bnx2 *bp)
{
6054
	unsigned long flags;
6055 6056
	struct bnx2_irq *irq;
	int rc = 0, i;
6057

6058
	if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6059 6060 6061
		flags = 0;
	else
		flags = IRQF_SHARED;
6062 6063 6064

	for (i = 0; i < bp->irq_nvecs; i++) {
		irq = &bp->irq_tbl[i];
6065
		rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6066
				 &bp->bnx2_napi[i]);
6067 6068 6069 6070
		if (rc)
			break;
		irq->requested = 1;
	}
6071 6072 6073 6074 6075 6076
	return rc;
}

static void
bnx2_free_irq(struct bnx2 *bp)
{
6077 6078
	struct bnx2_irq *irq;
	int i;
6079

6080 6081 6082
	for (i = 0; i < bp->irq_nvecs; i++) {
		irq = &bp->irq_tbl[i];
		if (irq->requested)
6083
			free_irq(irq->vector, &bp->bnx2_napi[i]);
6084
		irq->requested = 0;
6085
	}
6086
	if (bp->flags & BNX2_FLAG_USING_MSI)
6087
		pci_disable_msi(bp->pdev);
6088
	else if (bp->flags & BNX2_FLAG_USING_MSIX)
6089 6090
		pci_disable_msix(bp->pdev);

6091
	bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6092 6093 6094
}

static void
6095
bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6096
{
6097 6098
	int i, rc;
	struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6099 6100
	struct net_device *dev = bp->dev;
	const int len = sizeof(bp->irq_tbl[0].name);
6101

6102 6103 6104 6105
	bnx2_setup_msix_tbl(bp);
	REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
	REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
	REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6106 6107 6108 6109 6110 6111 6112 6113 6114 6115

	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
		msix_ent[i].entry = i;
		msix_ent[i].vector = 0;
	}

	rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
	if (rc != 0)
		return;

6116
	bp->irq_nvecs = msix_vecs;
6117
	bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6118
	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6119
		bp->irq_tbl[i].vector = msix_ent[i].vector;
6120 6121 6122
		snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
		bp->irq_tbl[i].handler = bnx2_msi_1shot;
	}
6123 6124 6125 6126 6127
}

static void
bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
{
6128
	int cpus = num_online_cpus();
6129
	int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6130

6131 6132
	bp->irq_tbl[0].handler = bnx2_interrupt;
	strcpy(bp->irq_tbl[0].name, bp->dev->name);
6133 6134 6135
	bp->irq_nvecs = 1;
	bp->irq_tbl[0].vector = bp->pdev->irq;

6136 6137
	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
		bnx2_enable_msix(bp, msix_vecs);
6138

6139 6140
	if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
	    !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6141
		if (pci_enable_msi(bp->pdev) == 0) {
6142
			bp->flags |= BNX2_FLAG_USING_MSI;
6143
			if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6144
				bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6145 6146 6147
				bp->irq_tbl[0].handler = bnx2_msi_1shot;
			} else
				bp->irq_tbl[0].handler = bnx2_msi;
6148 6149

			bp->irq_tbl[0].vector = bp->pdev->irq;
6150 6151
		}
	}
6152 6153 6154 6155

	bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
	bp->dev->real_num_tx_queues = bp->num_tx_rings;

6156
	bp->num_rx_rings = bp->irq_nvecs;
6157 6158
}

6159 6160 6161 6162
/* Called with rtnl_lock */
static int
bnx2_open(struct net_device *dev)
{
M
Michael Chan 已提交
6163
	struct bnx2 *bp = netdev_priv(dev);
6164 6165
	int rc;

6166 6167
	netif_carrier_off(dev);

6168
	bnx2_set_power_state(bp, PCI_D0);
6169 6170
	bnx2_disable_int(bp);

6171 6172
	bnx2_setup_int_mode(bp, disable_msi);
	bnx2_napi_enable(bp);
6173
	rc = bnx2_alloc_mem(bp);
6174 6175
	if (rc)
		goto open_err;
6176

6177
	rc = bnx2_request_irq(bp);
6178 6179
	if (rc)
		goto open_err;
6180

6181
	rc = bnx2_init_nic(bp, 1);
6182 6183
	if (rc)
		goto open_err;
6184

6185
	mod_timer(&bp->timer, jiffies + bp->current_interval);
6186 6187 6188 6189 6190

	atomic_set(&bp->intr_sem, 0);

	bnx2_enable_int(bp);

6191
	if (bp->flags & BNX2_FLAG_USING_MSI) {
6192 6193 6194 6195 6196 6197 6198 6199 6200 6201 6202
		/* Test MSI to make sure it is working
		 * If MSI test fails, go back to INTx mode
		 */
		if (bnx2_test_intr(bp) != 0) {
			printk(KERN_WARNING PFX "%s: No interrupt was generated"
			       " using MSI, switching to INTx mode. Please"
			       " report this failure to the PCI maintainer"
			       " and include system chipset information.\n",
			       bp->dev->name);

			bnx2_disable_int(bp);
6203
			bnx2_free_irq(bp);
6204

6205 6206
			bnx2_setup_int_mode(bp, 1);

6207
			rc = bnx2_init_nic(bp, 0);
6208

6209 6210 6211
			if (!rc)
				rc = bnx2_request_irq(bp);

6212 6213
			if (rc) {
				del_timer_sync(&bp->timer);
6214
				goto open_err;
6215 6216 6217 6218
			}
			bnx2_enable_int(bp);
		}
	}
6219
	if (bp->flags & BNX2_FLAG_USING_MSI)
6220
		printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
6221
	else if (bp->flags & BNX2_FLAG_USING_MSIX)
6222
		printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
6223

6224
	netif_tx_start_all_queues(dev);
6225 6226

	return 0;
6227 6228 6229 6230 6231 6232 6233

open_err:
	bnx2_napi_disable(bp);
	bnx2_free_skbs(bp);
	bnx2_free_irq(bp);
	bnx2_free_mem(bp);
	return rc;
6234 6235 6236
}

static void
6237
bnx2_reset_task(struct work_struct *work)
6238
{
6239
	struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6240

6241 6242 6243
	if (!netif_running(bp->dev))
		return;

6244 6245
	bnx2_netif_stop(bp);

6246
	bnx2_init_nic(bp, 1);
6247 6248 6249 6250 6251 6252 6253 6254

	atomic_set(&bp->intr_sem, 1);
	bnx2_netif_start(bp);
}

static void
bnx2_tx_timeout(struct net_device *dev)
{
M
Michael Chan 已提交
6255
	struct bnx2 *bp = netdev_priv(dev);
6256 6257 6258 6259 6260 6261 6262 6263 6264 6265

	/* This allows the netif to be shutdown gracefully before resetting */
	schedule_work(&bp->reset_task);
}

#ifdef BCM_VLAN
/* Called with rtnl_lock */
static void
bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
{
M
Michael Chan 已提交
6266
	struct bnx2 *bp = netdev_priv(dev);
6267

6268 6269
	if (netif_running(dev))
		bnx2_netif_stop(bp);
6270 6271

	bp->vlgrp = vlgrp;
6272 6273 6274 6275

	if (!netif_running(dev))
		return;

6276
	bnx2_set_rx_mode(dev);
6277 6278
	if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
		bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6279 6280 6281 6282 6283

	bnx2_netif_start(bp);
}
#endif

H
Herbert Xu 已提交
6284
/* Called with netif_tx_lock.
6285 6286
 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
 * netif_wake_queue().
6287
 */
6288
static netdev_tx_t
6289 6290
bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
M
Michael Chan 已提交
6291
	struct bnx2 *bp = netdev_priv(dev);
6292 6293
	dma_addr_t mapping;
	struct tx_bd *txbd;
6294
	struct sw_tx_bd *tx_buf;
6295 6296 6297
	u32 len, vlan_tag_flags, last_frag, mss;
	u16 prod, ring_prod;
	int i;
6298 6299 6300
	struct bnx2_napi *bnapi;
	struct bnx2_tx_ring_info *txr;
	struct netdev_queue *txq;
6301
	struct skb_shared_info *sp;
6302 6303 6304 6305 6306 6307

	/*  Determine which tx ring we will be placed on */
	i = skb_get_queue_mapping(skb);
	bnapi = &bp->bnx2_napi[i];
	txr = &bnapi->tx_ring;
	txq = netdev_get_tx_queue(dev, i);
6308

6309
	if (unlikely(bnx2_tx_avail(bp, txr) <
6310
	    (skb_shinfo(skb)->nr_frags + 1))) {
6311
		netif_tx_stop_queue(txq);
6312 6313 6314 6315 6316 6317
		printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
			dev->name);

		return NETDEV_TX_BUSY;
	}
	len = skb_headlen(skb);
6318
	prod = txr->tx_prod;
6319 6320 6321
	ring_prod = TX_RING_IDX(prod);

	vlan_tag_flags = 0;
6322
	if (skb->ip_summed == CHECKSUM_PARTIAL) {
6323 6324 6325
		vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
	}

6326
#ifdef BCM_VLAN
A
Al Viro 已提交
6327
	if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6328 6329 6330
		vlan_tag_flags |=
			(TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
	}
6331
#endif
6332
	if ((mss = skb_shinfo(skb)->gso_size)) {
6333
		u32 tcp_opt_len;
6334
		struct iphdr *iph;
6335 6336 6337

		vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;

6338 6339 6340 6341 6342
		tcp_opt_len = tcp_optlen(skb);

		if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
			u32 tcp_off = skb_transport_offset(skb) -
				      sizeof(struct ipv6hdr) - ETH_HLEN;
6343

6344 6345 6346 6347 6348 6349 6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361
			vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
					  TX_BD_FLAGS_SW_FLAGS;
			if (likely(tcp_off == 0))
				vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
			else {
				tcp_off >>= 3;
				vlan_tag_flags |= ((tcp_off & 0x3) <<
						   TX_BD_FLAGS_TCP6_OFF0_SHL) |
						  ((tcp_off & 0x10) <<
						   TX_BD_FLAGS_TCP6_OFF4_SHL);
				mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
			}
		} else {
			iph = ip_hdr(skb);
			if (tcp_opt_len || (iph->ihl > 5)) {
				vlan_tag_flags |= ((iph->ihl - 5) +
						   (tcp_opt_len >> 2)) << 8;
			}
6362
		}
6363
	} else
6364 6365
		mss = 0;

6366 6367 6368 6369 6370 6371
	if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
		dev_kfree_skb(skb);
		return NETDEV_TX_OK;
	}

	sp = skb_shinfo(skb);
6372
	mapping = sp->dma_head;
6373

6374
	tx_buf = &txr->tx_buf_ring[ring_prod];
6375 6376
	tx_buf->skb = skb;

6377
	txbd = &txr->tx_desc_ring[ring_prod];
6378 6379 6380 6381 6382 6383 6384

	txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
	txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
	txbd->tx_bd_mss_nbytes = len | (mss << 16);
	txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;

	last_frag = skb_shinfo(skb)->nr_frags;
6385 6386
	tx_buf->nr_frags = last_frag;
	tx_buf->is_gso = skb_is_gso(skb);
6387 6388 6389 6390 6391 6392

	for (i = 0; i < last_frag; i++) {
		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

		prod = NEXT_TX_BD(prod);
		ring_prod = TX_RING_IDX(prod);
6393
		txbd = &txr->tx_desc_ring[ring_prod];
6394 6395

		len = frag->size;
6396
		mapping = sp->dma_maps[i];
6397 6398 6399 6400 6401 6402 6403 6404 6405 6406

		txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
		txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
		txbd->tx_bd_mss_nbytes = len | (mss << 16);
		txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;

	}
	txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;

	prod = NEXT_TX_BD(prod);
6407
	txr->tx_prod_bseq += skb->len;
6408

6409 6410
	REG_WR16(bp, txr->tx_bidx_addr, prod);
	REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6411 6412 6413

	mmiowb();

6414
	txr->tx_prod = prod;
6415

6416
	if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6417
		netif_tx_stop_queue(txq);
6418
		if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6419
			netif_tx_wake_queue(txq);
6420 6421 6422 6423 6424 6425 6426 6427 6428
	}

	return NETDEV_TX_OK;
}

/* Called with rtnl_lock */
static int
bnx2_close(struct net_device *dev)
{
M
Michael Chan 已提交
6429
	struct bnx2 *bp = netdev_priv(dev);
6430

6431
	cancel_work_sync(&bp->reset_task);
6432

6433
	bnx2_disable_int_sync(bp);
6434
	bnx2_napi_disable(bp);
6435
	del_timer_sync(&bp->timer);
6436
	bnx2_shutdown_chip(bp);
6437
	bnx2_free_irq(bp);
6438 6439 6440 6441
	bnx2_free_skbs(bp);
	bnx2_free_mem(bp);
	bp->link_up = 0;
	netif_carrier_off(bp->dev);
6442
	bnx2_set_power_state(bp, PCI_D3hot);
6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461
	return 0;
}

#define GET_NET_STATS64(ctr)					\
	(unsigned long) ((unsigned long) (ctr##_hi) << 32) +	\
	(unsigned long) (ctr##_lo)

#define GET_NET_STATS32(ctr)		\
	(ctr##_lo)

#if (BITS_PER_LONG == 64)
#define GET_NET_STATS	GET_NET_STATS64
#else
#define GET_NET_STATS	GET_NET_STATS32
#endif

static struct net_device_stats *
bnx2_get_stats(struct net_device *dev)
{
M
Michael Chan 已提交
6462
	struct bnx2 *bp = netdev_priv(dev);
6463
	struct statistics_block *stats_blk = bp->stats_blk;
6464
	struct net_device_stats *net_stats = &dev->stats;
6465 6466 6467 6468 6469 6470 6471 6472 6473 6474 6475 6476 6477 6478 6479 6480 6481 6482 6483 6484

	if (bp->stats_blk == NULL) {
		return net_stats;
	}
	net_stats->rx_packets =
		GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);

	net_stats->tx_packets =
		GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);

	net_stats->rx_bytes =
		GET_NET_STATS(stats_blk->stat_IfHCInOctets);

	net_stats->tx_bytes =
		GET_NET_STATS(stats_blk->stat_IfHCOutOctets);

6485
	net_stats->multicast =
6486 6487
		GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);

6488
	net_stats->collisions =
6489 6490
		(unsigned long) stats_blk->stat_EtherStatsCollisions;

6491
	net_stats->rx_length_errors =
6492 6493 6494
		(unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
		stats_blk->stat_EtherStatsOverrsizePkts);

6495
	net_stats->rx_over_errors =
6496 6497
		(unsigned long) (stats_blk->stat_IfInFTQDiscards +
		stats_blk->stat_IfInMBUFDiscards);
6498

6499
	net_stats->rx_frame_errors =
6500 6501
		(unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;

6502
	net_stats->rx_crc_errors =
6503 6504 6505 6506 6507 6508 6509 6510 6511 6512
		(unsigned long) stats_blk->stat_Dot3StatsFCSErrors;

	net_stats->rx_errors = net_stats->rx_length_errors +
		net_stats->rx_over_errors + net_stats->rx_frame_errors +
		net_stats->rx_crc_errors;

	net_stats->tx_aborted_errors =
    		(unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
		stats_blk->stat_Dot3StatsLateCollisions);

6513 6514
	if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_A0))
6515 6516 6517 6518 6519 6520 6521 6522
		net_stats->tx_carrier_errors = 0;
	else {
		net_stats->tx_carrier_errors =
			(unsigned long)
			stats_blk->stat_Dot3StatsCarrierSenseErrors;
	}

	net_stats->tx_errors =
6523
    		(unsigned long)
6524 6525 6526 6527 6528
		stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
		+
		net_stats->tx_aborted_errors +
		net_stats->tx_carrier_errors;

6529
	net_stats->rx_missed_errors =
6530 6531
		(unsigned long) (stats_blk->stat_IfInFTQDiscards +
		stats_blk->stat_IfInMBUFDiscards + stats_blk->stat_FwRxDrop);
6532

6533 6534 6535 6536 6537 6538 6539 6540
	return net_stats;
}

/* All ethtool functions called with rtnl_lock */

static int
bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
M
Michael Chan 已提交
6541
	struct bnx2 *bp = netdev_priv(dev);
6542
	int support_serdes = 0, support_copper = 0;
6543 6544

	cmd->supported = SUPPORTED_Autoneg;
6545
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6546 6547 6548 6549 6550 6551 6552 6553
		support_serdes = 1;
		support_copper = 1;
	} else if (bp->phy_port == PORT_FIBRE)
		support_serdes = 1;
	else
		support_copper = 1;

	if (support_serdes) {
6554 6555
		cmd->supported |= SUPPORTED_1000baseT_Full |
			SUPPORTED_FIBRE;
6556
		if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6557
			cmd->supported |= SUPPORTED_2500baseX_Full;
6558 6559

	}
6560
	if (support_copper) {
6561 6562 6563 6564 6565 6566 6567 6568 6569
		cmd->supported |= SUPPORTED_10baseT_Half |
			SUPPORTED_10baseT_Full |
			SUPPORTED_100baseT_Half |
			SUPPORTED_100baseT_Full |
			SUPPORTED_1000baseT_Full |
			SUPPORTED_TP;

	}

6570 6571
	spin_lock_bh(&bp->phy_lock);
	cmd->port = bp->phy_port;
6572 6573 6574 6575 6576 6577 6578 6579 6580 6581 6582 6583 6584 6585 6586 6587 6588
	cmd->advertising = bp->advertising;

	if (bp->autoneg & AUTONEG_SPEED) {
		cmd->autoneg = AUTONEG_ENABLE;
	}
	else {
		cmd->autoneg = AUTONEG_DISABLE;
	}

	if (netif_carrier_ok(dev)) {
		cmd->speed = bp->line_speed;
		cmd->duplex = bp->duplex;
	}
	else {
		cmd->speed = -1;
		cmd->duplex = -1;
	}
6589
	spin_unlock_bh(&bp->phy_lock);
6590 6591 6592 6593 6594 6595

	cmd->transceiver = XCVR_INTERNAL;
	cmd->phy_address = bp->phy_addr;

	return 0;
}
6596

6597 6598 6599
static int
bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
M
Michael Chan 已提交
6600
	struct bnx2 *bp = netdev_priv(dev);
6601 6602 6603 6604
	u8 autoneg = bp->autoneg;
	u8 req_duplex = bp->req_duplex;
	u16 req_line_speed = bp->req_line_speed;
	u32 advertising = bp->advertising;
6605 6606 6607 6608 6609 6610 6611
	int err = -EINVAL;

	spin_lock_bh(&bp->phy_lock);

	if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
		goto err_out_unlock;

6612 6613
	if (cmd->port != bp->phy_port &&
	    !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6614
		goto err_out_unlock;
6615

6616 6617 6618 6619 6620 6621
	/* If device is down, we can store the settings only if the user
	 * is setting the currently active port.
	 */
	if (!netif_running(dev) && cmd->port != bp->phy_port)
		goto err_out_unlock;

6622 6623 6624
	if (cmd->autoneg == AUTONEG_ENABLE) {
		autoneg |= AUTONEG_SPEED;

6625
		cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6626 6627 6628 6629 6630 6631 6632

		/* allow advertising 1 speed */
		if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
			(cmd->advertising == ADVERTISED_10baseT_Full) ||
			(cmd->advertising == ADVERTISED_100baseT_Half) ||
			(cmd->advertising == ADVERTISED_100baseT_Full)) {

6633 6634
			if (cmd->port == PORT_FIBRE)
				goto err_out_unlock;
6635 6636 6637

			advertising = cmd->advertising;

6638
		} else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6639
			if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6640 6641 6642
			    (cmd->port == PORT_TP))
				goto err_out_unlock;
		} else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6643
			advertising = cmd->advertising;
6644 6645
		else if (cmd->advertising == ADVERTISED_1000baseT_Half)
			goto err_out_unlock;
6646
		else {
6647
			if (cmd->port == PORT_FIBRE)
6648
				advertising = ETHTOOL_ALL_FIBRE_SPEED;
6649
			else
6650 6651 6652 6653 6654
				advertising = ETHTOOL_ALL_COPPER_SPEED;
		}
		advertising |= ADVERTISED_Autoneg;
	}
	else {
6655
		if (cmd->port == PORT_FIBRE) {
6656 6657 6658
			if ((cmd->speed != SPEED_1000 &&
			     cmd->speed != SPEED_2500) ||
			    (cmd->duplex != DUPLEX_FULL))
6659
				goto err_out_unlock;
6660 6661

			if (cmd->speed == SPEED_2500 &&
6662
			    !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6663
				goto err_out_unlock;
6664
		}
6665 6666 6667
		else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
			goto err_out_unlock;

6668 6669 6670 6671 6672 6673 6674 6675 6676 6677 6678
		autoneg &= ~AUTONEG_SPEED;
		req_line_speed = cmd->speed;
		req_duplex = cmd->duplex;
		advertising = 0;
	}

	bp->autoneg = autoneg;
	bp->advertising = advertising;
	bp->req_line_speed = req_line_speed;
	bp->req_duplex = req_duplex;

6679 6680 6681 6682 6683 6684
	err = 0;
	/* If device is down, the new settings will be picked up when it is
	 * brought up.
	 */
	if (netif_running(dev))
		err = bnx2_setup_phy(bp, cmd->port);
6685

6686
err_out_unlock:
6687
	spin_unlock_bh(&bp->phy_lock);
6688

6689
	return err;
6690 6691 6692 6693 6694
}

static void
bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
M
Michael Chan 已提交
6695
	struct bnx2 *bp = netdev_priv(dev);
6696 6697 6698 6699

	strcpy(info->driver, DRV_MODULE_NAME);
	strcpy(info->version, DRV_MODULE_VERSION);
	strcpy(info->bus_info, pci_name(bp->pdev));
6700
	strcpy(info->fw_version, bp->fw_version);
6701 6702
}

6703 6704 6705 6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718 6719 6720 6721 6722 6723 6724 6725 6726 6727 6728 6729 6730 6731 6732 6733 6734 6735 6736 6737 6738 6739 6740 6741 6742 6743 6744 6745 6746 6747 6748 6749 6750 6751 6752 6753 6754 6755 6756 6757 6758 6759 6760
#define BNX2_REGDUMP_LEN		(32 * 1024)

static int
bnx2_get_regs_len(struct net_device *dev)
{
	return BNX2_REGDUMP_LEN;
}

static void
bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
{
	u32 *p = _p, i, offset;
	u8 *orig_p = _p;
	struct bnx2 *bp = netdev_priv(dev);
	u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
				 0x0800, 0x0880, 0x0c00, 0x0c10,
				 0x0c30, 0x0d08, 0x1000, 0x101c,
				 0x1040, 0x1048, 0x1080, 0x10a4,
				 0x1400, 0x1490, 0x1498, 0x14f0,
				 0x1500, 0x155c, 0x1580, 0x15dc,
				 0x1600, 0x1658, 0x1680, 0x16d8,
				 0x1800, 0x1820, 0x1840, 0x1854,
				 0x1880, 0x1894, 0x1900, 0x1984,
				 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
				 0x1c80, 0x1c94, 0x1d00, 0x1d84,
				 0x2000, 0x2030, 0x23c0, 0x2400,
				 0x2800, 0x2820, 0x2830, 0x2850,
				 0x2b40, 0x2c10, 0x2fc0, 0x3058,
				 0x3c00, 0x3c94, 0x4000, 0x4010,
				 0x4080, 0x4090, 0x43c0, 0x4458,
				 0x4c00, 0x4c18, 0x4c40, 0x4c54,
				 0x4fc0, 0x5010, 0x53c0, 0x5444,
				 0x5c00, 0x5c18, 0x5c80, 0x5c90,
				 0x5fc0, 0x6000, 0x6400, 0x6428,
				 0x6800, 0x6848, 0x684c, 0x6860,
				 0x6888, 0x6910, 0x8000 };

	regs->version = 0;

	memset(p, 0, BNX2_REGDUMP_LEN);

	if (!netif_running(bp->dev))
		return;

	i = 0;
	offset = reg_boundaries[0];
	p += offset;
	while (offset < BNX2_REGDUMP_LEN) {
		*p++ = REG_RD(bp, offset);
		offset += 4;
		if (offset == reg_boundaries[i + 1]) {
			offset = reg_boundaries[i + 2];
			p = (u32 *) (orig_p + offset);
			i += 2;
		}
	}
}

6761 6762 6763
static void
bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
M
Michael Chan 已提交
6764
	struct bnx2 *bp = netdev_priv(dev);
6765

6766
	if (bp->flags & BNX2_FLAG_NO_WOL) {
6767 6768 6769 6770 6771 6772 6773 6774 6775 6776 6777 6778 6779 6780 6781 6782
		wol->supported = 0;
		wol->wolopts = 0;
	}
	else {
		wol->supported = WAKE_MAGIC;
		if (bp->wol)
			wol->wolopts = WAKE_MAGIC;
		else
			wol->wolopts = 0;
	}
	memset(&wol->sopass, 0, sizeof(wol->sopass));
}

static int
bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
M
Michael Chan 已提交
6783
	struct bnx2 *bp = netdev_priv(dev);
6784 6785 6786 6787 6788

	if (wol->wolopts & ~WAKE_MAGIC)
		return -EINVAL;

	if (wol->wolopts & WAKE_MAGIC) {
6789
		if (bp->flags & BNX2_FLAG_NO_WOL)
6790 6791 6792 6793 6794 6795 6796 6797 6798 6799 6800 6801 6802
			return -EINVAL;

		bp->wol = 1;
	}
	else {
		bp->wol = 0;
	}
	return 0;
}

static int
bnx2_nway_reset(struct net_device *dev)
{
M
Michael Chan 已提交
6803
	struct bnx2 *bp = netdev_priv(dev);
6804 6805
	u32 bmcr;

6806 6807 6808
	if (!netif_running(dev))
		return -EAGAIN;

6809 6810 6811 6812
	if (!(bp->autoneg & AUTONEG_SPEED)) {
		return -EINVAL;
	}

6813
	spin_lock_bh(&bp->phy_lock);
6814

6815
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6816 6817 6818 6819 6820 6821 6822
		int rc;

		rc = bnx2_setup_remote_phy(bp, bp->phy_port);
		spin_unlock_bh(&bp->phy_lock);
		return rc;
	}

6823
	/* Force a link down visible on the other side */
6824
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6825
		bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6826
		spin_unlock_bh(&bp->phy_lock);
6827 6828 6829

		msleep(20);

6830
		spin_lock_bh(&bp->phy_lock);
6831

6832
		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6833 6834
		bp->serdes_an_pending = 1;
		mod_timer(&bp->timer, jiffies + bp->current_interval);
6835 6836
	}

6837
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6838
	bmcr &= ~BMCR_LOOPBACK;
6839
	bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6840

6841
	spin_unlock_bh(&bp->phy_lock);
6842 6843 6844 6845

	return 0;
}

6846 6847 6848 6849 6850 6851 6852 6853
static u32
bnx2_get_link(struct net_device *dev)
{
	struct bnx2 *bp = netdev_priv(dev);

	return bp->link_up;
}

6854 6855 6856
static int
bnx2_get_eeprom_len(struct net_device *dev)
{
M
Michael Chan 已提交
6857
	struct bnx2 *bp = netdev_priv(dev);
6858

M
Michael Chan 已提交
6859
	if (bp->flash_info == NULL)
6860 6861
		return 0;

M
Michael Chan 已提交
6862
	return (int) bp->flash_size;
6863 6864 6865 6866 6867 6868
}

static int
bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
		u8 *eebuf)
{
M
Michael Chan 已提交
6869
	struct bnx2 *bp = netdev_priv(dev);
6870 6871
	int rc;

6872 6873 6874
	if (!netif_running(dev))
		return -EAGAIN;

6875
	/* parameters already validated in ethtool_get_eeprom */
6876 6877 6878 6879 6880 6881 6882 6883 6884 6885

	rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);

	return rc;
}

static int
bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
		u8 *eebuf)
{
M
Michael Chan 已提交
6886
	struct bnx2 *bp = netdev_priv(dev);
6887 6888
	int rc;

6889 6890 6891
	if (!netif_running(dev))
		return -EAGAIN;

6892
	/* parameters already validated in ethtool_set_eeprom */
6893 6894 6895 6896 6897 6898 6899 6900 6901

	rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);

	return rc;
}

static int
bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
{
M
Michael Chan 已提交
6902
	struct bnx2 *bp = netdev_priv(dev);
6903 6904 6905 6906 6907 6908 6909 6910 6911 6912 6913 6914 6915 6916 6917 6918 6919 6920 6921 6922 6923

	memset(coal, 0, sizeof(struct ethtool_coalesce));

	coal->rx_coalesce_usecs = bp->rx_ticks;
	coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
	coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
	coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;

	coal->tx_coalesce_usecs = bp->tx_ticks;
	coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
	coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
	coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;

	coal->stats_block_coalesce_usecs = bp->stats_ticks;

	return 0;
}

static int
bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
{
M
Michael Chan 已提交
6924
	struct bnx2 *bp = netdev_priv(dev);
6925 6926 6927 6928

	bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
	if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;

6929
	bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6930 6931 6932 6933 6934 6935 6936 6937 6938 6939 6940 6941 6942 6943 6944 6945 6946 6947 6948 6949 6950 6951 6952
	if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;

	bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
	if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;

	bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
	if (bp->rx_quick_cons_trip_int > 0xff)
		bp->rx_quick_cons_trip_int = 0xff;

	bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
	if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;

	bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
	if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;

	bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
	if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;

	bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
	if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
		0xff;

	bp->stats_ticks = coal->stats_block_coalesce_usecs;
6953
	if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
6954 6955 6956
		if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
			bp->stats_ticks = USEC_PER_SEC;
	}
6957 6958 6959
	if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
		bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
	bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6960 6961 6962

	if (netif_running(bp->dev)) {
		bnx2_netif_stop(bp);
6963
		bnx2_init_nic(bp, 0);
6964 6965 6966 6967 6968 6969 6970 6971 6972
		bnx2_netif_start(bp);
	}

	return 0;
}

static void
bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
{
M
Michael Chan 已提交
6973
	struct bnx2 *bp = netdev_priv(dev);
6974

6975
	ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6976
	ering->rx_mini_max_pending = 0;
6977
	ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6978 6979 6980

	ering->rx_pending = bp->rx_ring_size;
	ering->rx_mini_pending = 0;
6981
	ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6982 6983 6984 6985 6986 6987

	ering->tx_max_pending = MAX_TX_DESC_CNT;
	ering->tx_pending = bp->tx_ring_size;
}

static int
6988
bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6989
{
6990 6991 6992 6993 6994 6995 6996
	if (netif_running(bp->dev)) {
		bnx2_netif_stop(bp);
		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
		bnx2_free_skbs(bp);
		bnx2_free_mem(bp);
	}

6997 6998
	bnx2_set_rx_ring_size(bp, rx);
	bp->tx_ring_size = tx;
6999 7000

	if (netif_running(bp->dev)) {
7001 7002 7003
		int rc;

		rc = bnx2_alloc_mem(bp);
7004 7005 7006 7007 7008 7009
		if (!rc)
			rc = bnx2_init_nic(bp, 0);

		if (rc) {
			bnx2_napi_enable(bp);
			dev_close(bp->dev);
7010
			return rc;
7011
		}
7012 7013 7014 7015 7016
		bnx2_netif_start(bp);
	}
	return 0;
}

7017 7018 7019 7020 7021 7022 7023 7024 7025 7026 7027 7028 7029 7030 7031 7032
static int
bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
{
	struct bnx2 *bp = netdev_priv(dev);
	int rc;

	if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
		(ering->tx_pending > MAX_TX_DESC_CNT) ||
		(ering->tx_pending <= MAX_SKB_FRAGS)) {

		return -EINVAL;
	}
	rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
	return rc;
}

7033 7034 7035
static void
bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
M
Michael Chan 已提交
7036
	struct bnx2 *bp = netdev_priv(dev);
7037 7038 7039 7040 7041 7042 7043 7044 7045

	epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
	epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
	epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
}

static int
bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
M
Michael Chan 已提交
7046
	struct bnx2 *bp = netdev_priv(dev);
7047 7048 7049 7050 7051 7052 7053 7054 7055 7056 7057 7058 7059 7060

	bp->req_flow_ctrl = 0;
	if (epause->rx_pause)
		bp->req_flow_ctrl |= FLOW_CTRL_RX;
	if (epause->tx_pause)
		bp->req_flow_ctrl |= FLOW_CTRL_TX;

	if (epause->autoneg) {
		bp->autoneg |= AUTONEG_FLOW_CTRL;
	}
	else {
		bp->autoneg &= ~AUTONEG_FLOW_CTRL;
	}

7061 7062 7063 7064 7065
	if (netif_running(dev)) {
		spin_lock_bh(&bp->phy_lock);
		bnx2_setup_phy(bp, bp->phy_port);
		spin_unlock_bh(&bp->phy_lock);
	}
7066 7067 7068 7069 7070 7071 7072

	return 0;
}

static u32
bnx2_get_rx_csum(struct net_device *dev)
{
M
Michael Chan 已提交
7073
	struct bnx2 *bp = netdev_priv(dev);
7074 7075 7076 7077 7078 7079 7080

	return bp->rx_csum;
}

static int
bnx2_set_rx_csum(struct net_device *dev, u32 data)
{
M
Michael Chan 已提交
7081
	struct bnx2 *bp = netdev_priv(dev);
7082 7083 7084 7085 7086

	bp->rx_csum = data;
	return 0;
}

7087 7088 7089
static int
bnx2_set_tso(struct net_device *dev, u32 data)
{
7090 7091 7092
	struct bnx2 *bp = netdev_priv(dev);

	if (data) {
7093
		dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7094 7095 7096 7097 7098
		if (CHIP_NUM(bp) == CHIP_NUM_5709)
			dev->features |= NETIF_F_TSO6;
	} else
		dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
				   NETIF_F_TSO_ECN);
7099 7100 7101
	return 0;
}

7102
static struct {
7103
	char string[ETH_GSTRING_LEN];
7104
} bnx2_stats_str_arr[] = {
7105 7106 7107 7108 7109 7110 7111 7112 7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125 7126 7127 7128 7129 7130 7131 7132 7133 7134 7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148
	{ "rx_bytes" },
	{ "rx_error_bytes" },
	{ "tx_bytes" },
	{ "tx_error_bytes" },
	{ "rx_ucast_packets" },
	{ "rx_mcast_packets" },
	{ "rx_bcast_packets" },
	{ "tx_ucast_packets" },
	{ "tx_mcast_packets" },
	{ "tx_bcast_packets" },
	{ "tx_mac_errors" },
	{ "tx_carrier_errors" },
	{ "rx_crc_errors" },
	{ "rx_align_errors" },
	{ "tx_single_collisions" },
	{ "tx_multi_collisions" },
	{ "tx_deferred" },
	{ "tx_excess_collisions" },
	{ "tx_late_collisions" },
	{ "tx_total_collisions" },
	{ "rx_fragments" },
	{ "rx_jabbers" },
	{ "rx_undersize_packets" },
	{ "rx_oversize_packets" },
	{ "rx_64_byte_packets" },
	{ "rx_65_to_127_byte_packets" },
	{ "rx_128_to_255_byte_packets" },
	{ "rx_256_to_511_byte_packets" },
	{ "rx_512_to_1023_byte_packets" },
	{ "rx_1024_to_1522_byte_packets" },
	{ "rx_1523_to_9022_byte_packets" },
	{ "tx_64_byte_packets" },
	{ "tx_65_to_127_byte_packets" },
	{ "tx_128_to_255_byte_packets" },
	{ "tx_256_to_511_byte_packets" },
	{ "tx_512_to_1023_byte_packets" },
	{ "tx_1024_to_1522_byte_packets" },
	{ "tx_1523_to_9022_byte_packets" },
	{ "rx_xon_frames" },
	{ "rx_xoff_frames" },
	{ "tx_xon_frames" },
	{ "tx_xoff_frames" },
	{ "rx_mac_ctrl_frames" },
	{ "rx_filtered_packets" },
7149
	{ "rx_ftq_discards" },
7150
	{ "rx_discards" },
7151
	{ "rx_fw_discards" },
7152 7153
};

7154 7155 7156
#define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
			sizeof(bnx2_stats_str_arr[0]))

7157 7158
#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)

7159
static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170
    STATS_OFFSET32(stat_IfHCInOctets_hi),
    STATS_OFFSET32(stat_IfHCInBadOctets_hi),
    STATS_OFFSET32(stat_IfHCOutOctets_hi),
    STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
    STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
    STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
    STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
    STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
    STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
    STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
    STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7171 7172 7173 7174 7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187 7188 7189 7190 7191 7192 7193 7194 7195 7196 7197 7198 7199 7200 7201 7202 7203
    STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
    STATS_OFFSET32(stat_Dot3StatsFCSErrors),
    STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
    STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
    STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
    STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
    STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
    STATS_OFFSET32(stat_Dot3StatsLateCollisions),
    STATS_OFFSET32(stat_EtherStatsCollisions),
    STATS_OFFSET32(stat_EtherStatsFragments),
    STATS_OFFSET32(stat_EtherStatsJabbers),
    STATS_OFFSET32(stat_EtherStatsUndersizePkts),
    STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
    STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
    STATS_OFFSET32(stat_XonPauseFramesReceived),
    STATS_OFFSET32(stat_XoffPauseFramesReceived),
    STATS_OFFSET32(stat_OutXonSent),
    STATS_OFFSET32(stat_OutXoffSent),
    STATS_OFFSET32(stat_MacControlFramesReceived),
    STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7204
    STATS_OFFSET32(stat_IfInFTQDiscards),
7205
    STATS_OFFSET32(stat_IfInMBUFDiscards),
7206
    STATS_OFFSET32(stat_FwRxDrop),
7207 7208 7209 7210
};

/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
 * skipped because of errata.
7211
 */
7212
static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7213 7214 7215 7216
	8,0,8,8,8,8,8,8,8,8,
	4,0,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
7217
	4,4,4,4,4,4,4,
7218 7219
};

7220 7221 7222 7223 7224
static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
	8,0,8,8,8,8,8,8,8,8,
	4,4,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
7225
	4,4,4,4,4,4,4,
7226 7227
};

7228 7229
#define BNX2_NUM_TESTS 6

7230
static struct {
7231 7232 7233 7234 7235 7236 7237 7238 7239 7240 7241
	char string[ETH_GSTRING_LEN];
} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
	{ "register_test (offline)" },
	{ "memory_test (offline)" },
	{ "loopback_test (offline)" },
	{ "nvram_test (online)" },
	{ "interrupt_test (online)" },
	{ "link_test (online)" },
};

static int
7242
bnx2_get_sset_count(struct net_device *dev, int sset)
7243
{
7244 7245 7246 7247 7248 7249 7250 7251
	switch (sset) {
	case ETH_SS_TEST:
		return BNX2_NUM_TESTS;
	case ETH_SS_STATS:
		return BNX2_NUM_STATS;
	default:
		return -EOPNOTSUPP;
	}
7252 7253 7254 7255 7256
}

static void
bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
{
M
Michael Chan 已提交
7257
	struct bnx2 *bp = netdev_priv(dev);
7258

7259 7260
	bnx2_set_power_state(bp, PCI_D0);

7261 7262
	memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
	if (etest->flags & ETH_TEST_FL_OFFLINE) {
7263 7264
		int i;

7265 7266 7267 7268 7269 7270 7271 7272 7273 7274 7275 7276
		bnx2_netif_stop(bp);
		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
		bnx2_free_skbs(bp);

		if (bnx2_test_registers(bp) != 0) {
			buf[0] = 1;
			etest->flags |= ETH_TEST_FL_FAILED;
		}
		if (bnx2_test_memory(bp) != 0) {
			buf[1] = 1;
			etest->flags |= ETH_TEST_FL_FAILED;
		}
7277
		if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7278 7279
			etest->flags |= ETH_TEST_FL_FAILED;

7280 7281
		if (!netif_running(bp->dev))
			bnx2_shutdown_chip(bp);
7282
		else {
7283
			bnx2_init_nic(bp, 1);
7284 7285 7286 7287
			bnx2_netif_start(bp);
		}

		/* wait for link up */
7288 7289 7290 7291 7292
		for (i = 0; i < 7; i++) {
			if (bp->link_up)
				break;
			msleep_interruptible(1000);
		}
7293 7294 7295 7296 7297 7298 7299 7300 7301 7302 7303 7304 7305 7306 7307 7308
	}

	if (bnx2_test_nvram(bp) != 0) {
		buf[3] = 1;
		etest->flags |= ETH_TEST_FL_FAILED;
	}
	if (bnx2_test_intr(bp) != 0) {
		buf[4] = 1;
		etest->flags |= ETH_TEST_FL_FAILED;
	}

	if (bnx2_test_link(bp) != 0) {
		buf[5] = 1;
		etest->flags |= ETH_TEST_FL_FAILED;

	}
7309 7310
	if (!netif_running(bp->dev))
		bnx2_set_power_state(bp, PCI_D3hot);
7311 7312 7313 7314 7315 7316 7317 7318 7319 7320 7321 7322 7323 7324 7325 7326 7327 7328 7329 7330 7331
}

static void
bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
{
	switch (stringset) {
	case ETH_SS_STATS:
		memcpy(buf, bnx2_stats_str_arr,
			sizeof(bnx2_stats_str_arr));
		break;
	case ETH_SS_TEST:
		memcpy(buf, bnx2_tests_str_arr,
			sizeof(bnx2_tests_str_arr));
		break;
	}
}

static void
bnx2_get_ethtool_stats(struct net_device *dev,
		struct ethtool_stats *stats, u64 *buf)
{
M
Michael Chan 已提交
7332
	struct bnx2 *bp = netdev_priv(dev);
7333 7334
	int i;
	u32 *hw_stats = (u32 *) bp->stats_blk;
7335
	u8 *stats_len_arr = NULL;
7336 7337 7338 7339 7340 7341

	if (hw_stats == NULL) {
		memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
		return;
	}

7342 7343 7344 7345
	if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
	    (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
	    (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_A0))
7346
		stats_len_arr = bnx2_5706_stats_len_arr;
7347 7348
	else
		stats_len_arr = bnx2_5708_stats_len_arr;
7349 7350 7351 7352 7353 7354 7355 7356 7357 7358 7359 7360 7361 7362 7363 7364 7365 7366 7367 7368 7369 7370 7371

	for (i = 0; i < BNX2_NUM_STATS; i++) {
		if (stats_len_arr[i] == 0) {
			/* skip this counter */
			buf[i] = 0;
			continue;
		}
		if (stats_len_arr[i] == 4) {
			/* 4-byte counter */
			buf[i] = (u64)
				*(hw_stats + bnx2_stats_offset_arr[i]);
			continue;
		}
		/* 8-byte counter */
		buf[i] = (((u64) *(hw_stats +
					bnx2_stats_offset_arr[i])) << 32) +
				*(hw_stats + bnx2_stats_offset_arr[i] + 1);
	}
}

static int
bnx2_phys_id(struct net_device *dev, u32 data)
{
M
Michael Chan 已提交
7372
	struct bnx2 *bp = netdev_priv(dev);
7373 7374 7375
	int i;
	u32 save;

7376 7377
	bnx2_set_power_state(bp, PCI_D0);

7378 7379 7380 7381 7382 7383 7384 7385 7386 7387 7388 7389 7390 7391 7392 7393 7394 7395 7396 7397 7398 7399 7400 7401
	if (data == 0)
		data = 2;

	save = REG_RD(bp, BNX2_MISC_CFG);
	REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);

	for (i = 0; i < (data * 2); i++) {
		if ((i % 2) == 0) {
			REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
		}
		else {
			REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
				BNX2_EMAC_LED_1000MB_OVERRIDE |
				BNX2_EMAC_LED_100MB_OVERRIDE |
				BNX2_EMAC_LED_10MB_OVERRIDE |
				BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
				BNX2_EMAC_LED_TRAFFIC);
		}
		msleep_interruptible(500);
		if (signal_pending(current))
			break;
	}
	REG_WR(bp, BNX2_EMAC_LED, 0);
	REG_WR(bp, BNX2_MISC_CFG, save);
7402 7403 7404 7405

	if (!netif_running(dev))
		bnx2_set_power_state(bp, PCI_D3hot);

7406 7407 7408
	return 0;
}

7409 7410 7411 7412 7413 7414
static int
bnx2_set_tx_csum(struct net_device *dev, u32 data)
{
	struct bnx2 *bp = netdev_priv(dev);

	if (CHIP_NUM(bp) == CHIP_NUM_5709)
7415
		return (ethtool_op_set_tx_ipv6_csum(dev, data));
7416 7417 7418 7419
	else
		return (ethtool_op_set_tx_csum(dev, data));
}

7420
static const struct ethtool_ops bnx2_ethtool_ops = {
7421 7422 7423
	.get_settings		= bnx2_get_settings,
	.set_settings		= bnx2_set_settings,
	.get_drvinfo		= bnx2_get_drvinfo,
7424 7425
	.get_regs_len		= bnx2_get_regs_len,
	.get_regs		= bnx2_get_regs,
7426 7427 7428
	.get_wol		= bnx2_get_wol,
	.set_wol		= bnx2_set_wol,
	.nway_reset		= bnx2_nway_reset,
7429
	.get_link		= bnx2_get_link,
7430 7431 7432 7433 7434 7435 7436 7437 7438 7439 7440
	.get_eeprom_len		= bnx2_get_eeprom_len,
	.get_eeprom		= bnx2_get_eeprom,
	.set_eeprom		= bnx2_set_eeprom,
	.get_coalesce		= bnx2_get_coalesce,
	.set_coalesce		= bnx2_set_coalesce,
	.get_ringparam		= bnx2_get_ringparam,
	.set_ringparam		= bnx2_set_ringparam,
	.get_pauseparam		= bnx2_get_pauseparam,
	.set_pauseparam		= bnx2_set_pauseparam,
	.get_rx_csum		= bnx2_get_rx_csum,
	.set_rx_csum		= bnx2_set_rx_csum,
7441
	.set_tx_csum		= bnx2_set_tx_csum,
7442
	.set_sg			= ethtool_op_set_sg,
7443
	.set_tso		= bnx2_set_tso,
7444 7445 7446 7447
	.self_test		= bnx2_self_test,
	.get_strings		= bnx2_get_strings,
	.phys_id		= bnx2_phys_id,
	.get_ethtool_stats	= bnx2_get_ethtool_stats,
7448
	.get_sset_count		= bnx2_get_sset_count,
7449 7450 7451 7452 7453 7454
};

/* Called with rtnl_lock */
static int
bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
7455
	struct mii_ioctl_data *data = if_mii(ifr);
M
Michael Chan 已提交
7456
	struct bnx2 *bp = netdev_priv(dev);
7457 7458 7459 7460 7461 7462 7463 7464 7465 7466
	int err;

	switch(cmd) {
	case SIOCGMIIPHY:
		data->phy_id = bp->phy_addr;

		/* fallthru */
	case SIOCGMIIREG: {
		u32 mii_regval;

7467
		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7468 7469
			return -EOPNOTSUPP;

7470 7471 7472
		if (!netif_running(dev))
			return -EAGAIN;

7473
		spin_lock_bh(&bp->phy_lock);
7474
		err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7475
		spin_unlock_bh(&bp->phy_lock);
7476 7477 7478 7479 7480 7481 7482

		data->val_out = mii_regval;

		return err;
	}

	case SIOCSMIIREG:
7483
		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7484 7485
			return -EOPNOTSUPP;

7486 7487 7488
		if (!netif_running(dev))
			return -EAGAIN;

7489
		spin_lock_bh(&bp->phy_lock);
7490
		err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7491
		spin_unlock_bh(&bp->phy_lock);
7492 7493 7494 7495 7496 7497 7498 7499 7500 7501 7502 7503 7504 7505 7506

		return err;

	default:
		/* do nothing */
		break;
	}
	return -EOPNOTSUPP;
}

/* Called with rtnl_lock */
static int
bnx2_change_mac_addr(struct net_device *dev, void *p)
{
	struct sockaddr *addr = p;
M
Michael Chan 已提交
7507
	struct bnx2 *bp = netdev_priv(dev);
7508

7509 7510 7511
	if (!is_valid_ether_addr(addr->sa_data))
		return -EINVAL;

7512 7513
	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
	if (netif_running(dev))
7514
		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7515 7516 7517 7518 7519 7520 7521 7522

	return 0;
}

/* Called with rtnl_lock */
static int
bnx2_change_mtu(struct net_device *dev, int new_mtu)
{
M
Michael Chan 已提交
7523
	struct bnx2 *bp = netdev_priv(dev);
7524 7525 7526 7527 7528 7529

	if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
		((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
		return -EINVAL;

	dev->mtu = new_mtu;
7530
	return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7531 7532 7533 7534 7535 7536
}

#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
static void
poll_bnx2(struct net_device *dev)
{
M
Michael Chan 已提交
7537
	struct bnx2 *bp = netdev_priv(dev);
7538
	int i;
7539

7540 7541 7542 7543 7544
	for (i = 0; i < bp->irq_nvecs; i++) {
		disable_irq(bp->irq_tbl[i].vector);
		bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
		enable_irq(bp->irq_tbl[i].vector);
	}
7545 7546 7547
}
#endif

7548 7549 7550 7551 7552 7553 7554 7555 7556 7557
static void __devinit
bnx2_get_5709_media(struct bnx2 *bp)
{
	u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
	u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
	u32 strap;

	if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
		return;
	else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7558
		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7559 7560 7561 7562 7563 7564 7565 7566 7567 7568 7569 7570 7571
		return;
	}

	if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
		strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
	else
		strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;

	if (PCI_FUNC(bp->pdev->devfn) == 0) {
		switch (strap) {
		case 0x4:
		case 0x5:
		case 0x6:
7572
			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7573 7574 7575 7576 7577 7578 7579
			return;
		}
	} else {
		switch (strap) {
		case 0x1:
		case 0x2:
		case 0x4:
7580
			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7581 7582 7583 7584 7585
			return;
		}
	}
}

7586 7587 7588 7589 7590 7591 7592 7593 7594
static void __devinit
bnx2_get_pci_speed(struct bnx2 *bp)
{
	u32 reg;

	reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
	if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
		u32 clkreg;

7595
		bp->flags |= BNX2_FLAG_PCIX;
7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611 7612 7613 7614 7615 7616 7617 7618 7619 7620 7621 7622 7623 7624 7625 7626 7627 7628 7629 7630 7631 7632 7633

		clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);

		clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
		switch (clkreg) {
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
			bp->bus_speed_mhz = 133;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
			bp->bus_speed_mhz = 100;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
			bp->bus_speed_mhz = 66;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
			bp->bus_speed_mhz = 50;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
			bp->bus_speed_mhz = 33;
			break;
		}
	}
	else {
		if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
			bp->bus_speed_mhz = 66;
		else
			bp->bus_speed_mhz = 33;
	}

	if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7634
		bp->flags |= BNX2_FLAG_PCI_32BIT;
7635 7636 7637

}

7638 7639 7640 7641 7642
static int __devinit
bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
{
	struct bnx2 *bp;
	unsigned long mem_len;
7643
	int rc, i, j;
7644
	u32 reg;
7645
	u64 dma_mask, persist_dma_mask;
7646 7647

	SET_NETDEV_DEV(dev, &pdev->dev);
M
Michael Chan 已提交
7648
	bp = netdev_priv(dev);
7649 7650 7651 7652 7653 7654 7655

	bp->flags = 0;
	bp->phy_flags = 0;

	/* enable device (incl. PCI PM wakeup), and bus-mastering */
	rc = pci_enable_device(pdev);
	if (rc) {
7656
		dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7657 7658 7659 7660
		goto err_out;
	}

	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7661
		dev_err(&pdev->dev,
7662
			"Cannot find PCI device base address, aborting.\n");
7663 7664 7665 7666 7667 7668
		rc = -ENODEV;
		goto err_out_disable;
	}

	rc = pci_request_regions(pdev, DRV_MODULE_NAME);
	if (rc) {
7669
		dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7670 7671 7672 7673
		goto err_out_disable;
	}

	pci_set_master(pdev);
W
Wendy Xiong 已提交
7674
	pci_save_state(pdev);
7675 7676 7677

	bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
	if (bp->pm_cap == 0) {
7678
		dev_err(&pdev->dev,
7679
			"Cannot find power management capability, aborting.\n");
7680 7681 7682 7683 7684 7685 7686 7687
		rc = -EIO;
		goto err_out_release;
	}

	bp->dev = dev;
	bp->pdev = pdev;

	spin_lock_init(&bp->phy_lock);
7688
	spin_lock_init(&bp->indirect_lock);
7689 7690 7691
#ifdef BCM_CNIC
	mutex_init(&bp->cnic_lock);
#endif
7692
	INIT_WORK(&bp->reset_task, bnx2_reset_task);
7693 7694

	dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7695
	mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7696 7697 7698 7699 7700 7701
	dev->mem_end = dev->mem_start + mem_len;
	dev->irq = pdev->irq;

	bp->regview = ioremap_nocache(dev->base_addr, mem_len);

	if (!bp->regview) {
7702
		dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7703 7704 7705 7706 7707 7708 7709 7710 7711 7712 7713 7714
		rc = -ENOMEM;
		goto err_out_release;
	}

	/* Configure byte swap and enable write to the reg_window registers.
	 * Rely on CPU to do target byte swapping on big endian systems
	 * The chip's target access swapping will not swap all accesses
	 */
	pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
			       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
			       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);

7715
	bnx2_set_power_state(bp, PCI_D0);
7716 7717 7718

	bp->chip_id = REG_RD(bp, BNX2_MISC_ID);

7719 7720 7721 7722 7723 7724 7725
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
			dev_err(&pdev->dev,
				"Cannot find PCIE capability, aborting.\n");
			rc = -EIO;
			goto err_out_unmap;
		}
7726
		bp->flags |= BNX2_FLAG_PCIE;
7727
		if (CHIP_REV(bp) == CHIP_REV_Ax)
7728
			bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7729
	} else {
7730 7731 7732 7733 7734 7735 7736
		bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
		if (bp->pcix_cap == 0) {
			dev_err(&pdev->dev,
				"Cannot find PCIX capability, aborting.\n");
			rc = -EIO;
			goto err_out_unmap;
		}
7737
		bp->flags |= BNX2_FLAG_BROKEN_STATS;
7738 7739
	}

7740 7741
	if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
		if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7742
			bp->flags |= BNX2_FLAG_MSIX_CAP;
7743 7744
	}

7745 7746
	if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
		if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7747
			bp->flags |= BNX2_FLAG_MSI_CAP;
7748 7749
	}

7750 7751
	/* 5708 cannot support DMA addresses > 40-bit.  */
	if (CHIP_NUM(bp) == CHIP_NUM_5708)
7752
		persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7753
	else
7754
		persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7755 7756 7757 7758 7759 7760 7761 7762 7763 7764

	/* Configure DMA attributes. */
	if (pci_set_dma_mask(pdev, dma_mask) == 0) {
		dev->features |= NETIF_F_HIGHDMA;
		rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
		if (rc) {
			dev_err(&pdev->dev,
				"pci_set_consistent_dma_mask failed, aborting.\n");
			goto err_out_unmap;
		}
7765
	} else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7766 7767 7768 7769
		dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
		goto err_out_unmap;
	}

7770
	if (!(bp->flags & BNX2_FLAG_PCIE))
7771
		bnx2_get_pci_speed(bp);
7772 7773 7774 7775 7776 7777 7778 7779

	/* 5706A0 may falsely detect SERR and PERR. */
	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		reg = REG_RD(bp, PCI_COMMAND);
		reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
		REG_WR(bp, PCI_COMMAND, reg);
	}
	else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7780
		!(bp->flags & BNX2_FLAG_PCIX)) {
7781

7782
		dev_err(&pdev->dev,
7783
			"5706 A1 can only be used in a PCIX bus, aborting.\n");
7784 7785 7786 7787 7788
		goto err_out_unmap;
	}

	bnx2_init_nvram(bp);

7789
	reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7790 7791

	if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7792 7793 7794
	    BNX2_SHM_HDR_SIGNATURE_SIG) {
		u32 off = PCI_FUNC(pdev->devfn) << 2;

7795
		bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7796
	} else
7797 7798
		bp->shmem_base = HOST_VIEW_SHMEM_BASE;

7799 7800 7801
	/* Get the permanent MAC address.  First we need to make sure the
	 * firmware is actually running.
	 */
7802
	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7803 7804 7805

	if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
	    BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7806
		dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7807 7808 7809 7810
		rc = -ENODEV;
		goto err_out_unmap;
	}

7811
	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7812 7813 7814 7815 7816 7817 7818 7819 7820 7821 7822 7823 7824
	for (i = 0, j = 0; i < 3; i++) {
		u8 num, k, skip0;

		num = (u8) (reg >> (24 - (i * 8)));
		for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
			if (num >= k || !skip0 || k == 1) {
				bp->fw_version[j++] = (num / k) + '0';
				skip0 = 0;
			}
		}
		if (i != 2)
			bp->fw_version[j++] = '.';
	}
7825
	reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7826 7827 7828 7829
	if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
		bp->wol = 1;

	if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7830
		bp->flags |= BNX2_FLAG_ASF_ENABLE;
7831 7832

		for (i = 0; i < 30; i++) {
7833
			reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7834 7835 7836 7837 7838
			if (reg & BNX2_CONDITION_MFW_RUN_MASK)
				break;
			msleep(10);
		}
	}
7839
	reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7840 7841 7842
	reg &= BNX2_CONDITION_MFW_RUN_MASK;
	if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
	    reg != BNX2_CONDITION_MFW_RUN_NONE) {
7843
		u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7844 7845 7846

		bp->fw_version[j++] = ' ';
		for (i = 0; i < 3; i++) {
7847
			reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7848 7849 7850 7851 7852
			reg = swab32(reg);
			memcpy(&bp->fw_version[j], &reg, 4);
			j += 4;
		}
	}
7853

7854
	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7855 7856 7857
	bp->mac_addr[0] = (u8) (reg >> 8);
	bp->mac_addr[1] = (u8) reg;

7858
	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7859 7860 7861 7862 7863 7864
	bp->mac_addr[2] = (u8) (reg >> 24);
	bp->mac_addr[3] = (u8) (reg >> 16);
	bp->mac_addr[4] = (u8) (reg >> 8);
	bp->mac_addr[5] = (u8) reg;

	bp->tx_ring_size = MAX_TX_DESC_CNT;
7865
	bnx2_set_rx_ring_size(bp, 255);
7866 7867 7868

	bp->rx_csum = 1;

7869
	bp->tx_quick_cons_trip_int = 2;
7870
	bp->tx_quick_cons_trip = 20;
7871
	bp->tx_ticks_int = 18;
7872
	bp->tx_ticks = 80;
7873

7874 7875
	bp->rx_quick_cons_trip_int = 2;
	bp->rx_quick_cons_trip = 12;
7876 7877 7878
	bp->rx_ticks_int = 18;
	bp->rx_ticks = 18;

7879
	bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7880

7881
	bp->current_interval = BNX2_TIMER_INTERVAL;
7882

7883 7884
	bp->phy_addr = 1;

7885
	/* Disable WOL support if we are running on a SERDES chip. */
7886 7887 7888
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_get_5709_media(bp);
	else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7889
		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
M
Michael Chan 已提交
7890

7891
	bp->phy_port = PORT_TP;
7892
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7893
		bp->phy_port = PORT_FIBRE;
7894
		reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7895
		if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7896
			bp->flags |= BNX2_FLAG_NO_WOL;
7897 7898
			bp->wol = 0;
		}
7899 7900 7901 7902 7903 7904 7905 7906 7907
		if (CHIP_NUM(bp) == CHIP_NUM_5706) {
			/* Don't do parallel detect on this board because of
			 * some board problems.  The link will not go down
			 * if we do parallel detect.
			 */
			if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
			    pdev->subsystem_device == 0x310c)
				bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
		} else {
7908 7909
			bp->phy_addr = 2;
			if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7910
				bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7911
		}
7912 7913
	} else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
		   CHIP_NUM(bp) == CHIP_NUM_5708)
7914
		bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7915 7916 7917
	else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
		 (CHIP_REV(bp) == CHIP_REV_Ax ||
		  CHIP_REV(bp) == CHIP_REV_Bx))
7918
		bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7919

7920 7921
	bnx2_init_fw_cap(bp);

7922 7923
	if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7924 7925
	    (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
	    !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
7926
		bp->flags |= BNX2_FLAG_NO_WOL;
7927 7928
		bp->wol = 0;
	}
M
Michael Chan 已提交
7929

7930 7931 7932 7933 7934 7935 7936 7937 7938 7939 7940 7941
	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		bp->tx_quick_cons_trip_int =
			bp->tx_quick_cons_trip;
		bp->tx_ticks_int = bp->tx_ticks;
		bp->rx_quick_cons_trip_int =
			bp->rx_quick_cons_trip;
		bp->rx_ticks_int = bp->rx_ticks;
		bp->comp_prod_trip_int = bp->comp_prod_trip;
		bp->com_ticks_int = bp->com_ticks;
		bp->cmd_ticks_int = bp->cmd_ticks;
	}

7942 7943 7944 7945 7946 7947 7948 7949
	/* Disable MSI on 5706 if AMD 8132 bridge is found.
	 *
	 * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
	 * with byte enables disabled on the unused 32-bit word.  This is legal
	 * but causes problems on the AMD 8132 which will eventually stop
	 * responding after a while.
	 *
	 * AMD believes this incompatibility is unique to the 5706, and
7950
	 * prefers to locally disable MSI rather than globally disabling it.
7951 7952 7953 7954 7955 7956 7957 7958
	 */
	if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
		struct pci_dev *amd_8132 = NULL;

		while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
						  PCI_DEVICE_ID_AMD_8132_BRIDGE,
						  amd_8132))) {

7959 7960
			if (amd_8132->revision >= 0x10 &&
			    amd_8132->revision <= 0x13) {
7961 7962 7963 7964 7965 7966 7967
				disable_msi = 1;
				pci_dev_put(amd_8132);
				break;
			}
		}
	}

7968
	bnx2_set_default_link(bp);
7969 7970
	bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;

7971
	init_timer(&bp->timer);
7972
	bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7973 7974 7975
	bp->timer.data = (unsigned long) bp;
	bp->timer.function = bnx2_timer;

7976 7977 7978 7979 7980
	return 0;

err_out_unmap:
	if (bp->regview) {
		iounmap(bp->regview);
7981
		bp->regview = NULL;
7982 7983 7984 7985 7986 7987 7988 7989 7990 7991 7992 7993 7994
	}

err_out_release:
	pci_release_regions(pdev);

err_out_disable:
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);

err_out:
	return rc;
}

7995 7996 7997 7998 7999
static char * __devinit
bnx2_bus_string(struct bnx2 *bp, char *str)
{
	char *s = str;

8000
	if (bp->flags & BNX2_FLAG_PCIE) {
8001 8002 8003
		s += sprintf(s, "PCI Express");
	} else {
		s += sprintf(s, "PCI");
8004
		if (bp->flags & BNX2_FLAG_PCIX)
8005
			s += sprintf(s, "-X");
8006
		if (bp->flags & BNX2_FLAG_PCI_32BIT)
8007 8008 8009 8010 8011 8012 8013 8014
			s += sprintf(s, " 32-bit");
		else
			s += sprintf(s, " 64-bit");
		s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
	}
	return str;
}

8015
static void __devinit
8016 8017
bnx2_init_napi(struct bnx2 *bp)
{
8018
	int i;
8019

8020
	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
8021 8022 8023 8024 8025 8026
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		int (*poll)(struct napi_struct *, int);

		if (i == 0)
			poll = bnx2_poll;
		else
8027
			poll = bnx2_poll_msix;
8028 8029

		netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8030 8031
		bnapi->bp = bp;
	}
8032 8033
}

8034 8035 8036 8037 8038 8039 8040 8041 8042 8043 8044 8045 8046 8047 8048 8049 8050 8051 8052
static const struct net_device_ops bnx2_netdev_ops = {
	.ndo_open		= bnx2_open,
	.ndo_start_xmit		= bnx2_start_xmit,
	.ndo_stop		= bnx2_close,
	.ndo_get_stats		= bnx2_get_stats,
	.ndo_set_rx_mode	= bnx2_set_rx_mode,
	.ndo_do_ioctl		= bnx2_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= bnx2_change_mac_addr,
	.ndo_change_mtu		= bnx2_change_mtu,
	.ndo_tx_timeout		= bnx2_tx_timeout,
#ifdef BCM_VLAN
	.ndo_vlan_rx_register	= bnx2_vlan_rx_register,
#endif
#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
	.ndo_poll_controller	= poll_bnx2,
#endif
};

E
Eric Dumazet 已提交
8053 8054 8055 8056 8057 8058 8059
static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
{
#ifdef BCM_VLAN
	dev->vlan_features |= flags;
#endif
}

8060 8061 8062 8063 8064 8065
static int __devinit
bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int version_printed = 0;
	struct net_device *dev = NULL;
	struct bnx2 *bp;
8066
	int rc;
8067
	char str[40];
8068 8069 8070 8071 8072

	if (version_printed++ == 0)
		printk(KERN_INFO "%s", version);

	/* dev zeroed in init_etherdev */
8073
	dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8074 8075 8076 8077 8078 8079 8080 8081 8082 8083

	if (!dev)
		return -ENOMEM;

	rc = bnx2_init_board(pdev, dev);
	if (rc < 0) {
		free_netdev(dev);
		return rc;
	}

8084
	dev->netdev_ops = &bnx2_netdev_ops;
8085 8086 8087
	dev->watchdog_timeo = TX_TIMEOUT;
	dev->ethtool_ops = &bnx2_ethtool_ops;

M
Michael Chan 已提交
8088
	bp = netdev_priv(dev);
8089
	bnx2_init_napi(bp);
8090

8091 8092
	pci_set_drvdata(pdev, dev);

8093 8094 8095 8096
	rc = bnx2_request_firmware(bp);
	if (rc)
		goto error;

8097 8098 8099
	memcpy(dev->dev_addr, bp->mac_addr, 6);
	memcpy(dev->perm_addr, bp->mac_addr, 6);

8100
	dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
E
Eric Dumazet 已提交
8101 8102
	vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8103
		dev->features |= NETIF_F_IPV6_CSUM;
E
Eric Dumazet 已提交
8104 8105
		vlan_features_add(dev, NETIF_F_IPV6_CSUM);
	}
8106 8107 8108 8109
#ifdef BCM_VLAN
	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
#endif
	dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
E
Eric Dumazet 已提交
8110 8111
	vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8112
		dev->features |= NETIF_F_TSO6;
E
Eric Dumazet 已提交
8113 8114
		vlan_features_add(dev, NETIF_F_TSO6);
	}
8115
	if ((rc = register_netdev(dev))) {
8116
		dev_err(&pdev->dev, "Cannot register net device\n");
8117
		goto error;
8118 8119
	}

8120
	printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
8121
		"IRQ %d, node addr %pM\n",
8122
		dev->name,
8123
		board_info[ent->driver_data].name,
8124 8125
		((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
		((CHIP_ID(bp) & 0x0ff0) >> 4),
8126
		bnx2_bus_string(bp, str),
8127
		dev->base_addr,
8128
		bp->pdev->irq, dev->dev_addr);
8129 8130

	return 0;
8131 8132 8133 8134 8135 8136 8137 8138 8139 8140 8141 8142 8143 8144

error:
	if (bp->mips_firmware)
		release_firmware(bp->mips_firmware);
	if (bp->rv2p_firmware)
		release_firmware(bp->rv2p_firmware);

	if (bp->regview)
		iounmap(bp->regview);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);
	free_netdev(dev);
	return rc;
8145 8146 8147 8148 8149 8150
}

static void __devexit
bnx2_remove_one(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
M
Michael Chan 已提交
8151
	struct bnx2 *bp = netdev_priv(dev);
8152

8153 8154
	flush_scheduled_work();

8155 8156
	unregister_netdev(dev);

8157 8158 8159 8160 8161
	if (bp->mips_firmware)
		release_firmware(bp->mips_firmware);
	if (bp->rv2p_firmware)
		release_firmware(bp->rv2p_firmware);

8162 8163 8164 8165 8166 8167 8168 8169 8170 8171
	if (bp->regview)
		iounmap(bp->regview);

	free_netdev(dev);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);
}

static int
8172
bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8173 8174
{
	struct net_device *dev = pci_get_drvdata(pdev);
M
Michael Chan 已提交
8175
	struct bnx2 *bp = netdev_priv(dev);
8176

8177 8178 8179 8180 8181
	/* PCI register 4 needs to be saved whether netif_running() or not.
	 * MSI address and data need to be saved if using MSI and
	 * netif_running().
	 */
	pci_save_state(pdev);
8182 8183 8184
	if (!netif_running(dev))
		return 0;

M
Michael Chan 已提交
8185
	flush_scheduled_work();
8186 8187 8188
	bnx2_netif_stop(bp);
	netif_device_detach(dev);
	del_timer_sync(&bp->timer);
8189
	bnx2_shutdown_chip(bp);
8190
	bnx2_free_skbs(bp);
8191
	bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8192 8193 8194 8195 8196 8197 8198
	return 0;
}

static int
bnx2_resume(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
M
Michael Chan 已提交
8199
	struct bnx2 *bp = netdev_priv(dev);
8200

8201
	pci_restore_state(pdev);
8202 8203 8204
	if (!netif_running(dev))
		return 0;

8205
	bnx2_set_power_state(bp, PCI_D0);
8206
	netif_device_attach(dev);
8207
	bnx2_init_nic(bp, 1);
8208 8209 8210 8211
	bnx2_netif_start(bp);
	return 0;
}

W
Wendy Xiong 已提交
8212 8213 8214 8215 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225 8226 8227 8228
/**
 * bnx2_io_error_detected - called when PCI error is detected
 * @pdev: Pointer to PCI device
 * @state: The current pci connection state
 *
 * This function is called after a PCI bus error affecting
 * this device has been detected.
 */
static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
					       pci_channel_state_t state)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2 *bp = netdev_priv(dev);

	rtnl_lock();
	netif_device_detach(dev);

8229 8230 8231 8232 8233
	if (state == pci_channel_io_perm_failure) {
		rtnl_unlock();
		return PCI_ERS_RESULT_DISCONNECT;
	}

W
Wendy Xiong 已提交
8234 8235 8236 8237 8238 8239 8240 8241 8242 8243 8244 8245 8246 8247 8248 8249 8250 8251 8252 8253 8254 8255 8256 8257 8258 8259 8260 8261 8262 8263 8264 8265 8266 8267 8268 8269 8270 8271 8272 8273 8274 8275 8276 8277 8278 8279 8280 8281 8282 8283 8284 8285 8286 8287 8288 8289 8290 8291 8292 8293 8294 8295 8296 8297 8298 8299 8300 8301 8302
	if (netif_running(dev)) {
		bnx2_netif_stop(bp);
		del_timer_sync(&bp->timer);
		bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
	}

	pci_disable_device(pdev);
	rtnl_unlock();

	/* Request a slot slot reset. */
	return PCI_ERS_RESULT_NEED_RESET;
}

/**
 * bnx2_io_slot_reset - called after the pci bus has been reset.
 * @pdev: Pointer to PCI device
 *
 * Restart the card from scratch, as if from a cold-boot.
 */
static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2 *bp = netdev_priv(dev);

	rtnl_lock();
	if (pci_enable_device(pdev)) {
		dev_err(&pdev->dev,
			"Cannot re-enable PCI device after reset.\n");
		rtnl_unlock();
		return PCI_ERS_RESULT_DISCONNECT;
	}
	pci_set_master(pdev);
	pci_restore_state(pdev);

	if (netif_running(dev)) {
		bnx2_set_power_state(bp, PCI_D0);
		bnx2_init_nic(bp, 1);
	}

	rtnl_unlock();
	return PCI_ERS_RESULT_RECOVERED;
}

/**
 * bnx2_io_resume - called when traffic can start flowing again.
 * @pdev: Pointer to PCI device
 *
 * This callback is called when the error recovery driver tells us that
 * its OK to resume normal operation.
 */
static void bnx2_io_resume(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2 *bp = netdev_priv(dev);

	rtnl_lock();
	if (netif_running(dev))
		bnx2_netif_start(bp);

	netif_device_attach(dev);
	rtnl_unlock();
}

static struct pci_error_handlers bnx2_err_handler = {
	.error_detected	= bnx2_io_error_detected,
	.slot_reset	= bnx2_io_slot_reset,
	.resume		= bnx2_io_resume,
};

8303
static struct pci_driver bnx2_pci_driver = {
8304 8305 8306 8307 8308 8309
	.name		= DRV_MODULE_NAME,
	.id_table	= bnx2_pci_tbl,
	.probe		= bnx2_init_one,
	.remove		= __devexit_p(bnx2_remove_one),
	.suspend	= bnx2_suspend,
	.resume		= bnx2_resume,
W
Wendy Xiong 已提交
8310
	.err_handler	= &bnx2_err_handler,
8311 8312 8313 8314
};

static int __init bnx2_init(void)
{
8315
	return pci_register_driver(&bnx2_pci_driver);
8316 8317 8318 8319 8320 8321 8322 8323 8324 8325 8326 8327
}

static void __exit bnx2_cleanup(void)
{
	pci_unregister_driver(&bnx2_pci_driver);
}

module_init(bnx2_init);
module_exit(bnx2_cleanup);


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