bnx2.c 200.2 KB
Newer Older
1 2
/* bnx2.c: Broadcom NX2 network driver.
 *
3
 * Copyright (c) 2004-2009 Broadcom Corporation
4 5 6 7 8 9 10 11
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation.
 *
 * Written by: Michael Chan  (mchan@broadcom.com)
 */

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

#include <linux/module.h>
#include <linux/moduleparam.h>

#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/dma-mapping.h>
J
Jiri Slaby 已提交
29
#include <linux/bitops.h>
30 31 32 33
#include <asm/io.h>
#include <asm/irq.h>
#include <linux/delay.h>
#include <asm/byteorder.h>
34
#include <asm/page.h>
35 36 37 38
#include <linux/time.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
39
#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
40 41 42
#define BCM_VLAN 1
#endif
#include <net/ip.h>
43
#include <net/tcp.h>
44 45 46 47
#include <net/checksum.h>
#include <linux/workqueue.h>
#include <linux/crc32.h>
#include <linux/prefetch.h>
48
#include <linux/cache.h>
49
#include <linux/firmware.h>
50
#include <linux/log2.h>
51
#include <linux/list.h>
52

53 54 55 56
#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
#define BCM_CNIC 1
#include "cnic_if.h"
#endif
57 58
#include "bnx2.h"
#include "bnx2_fw.h"
59

60 61
#define DRV_MODULE_NAME		"bnx2"
#define PFX DRV_MODULE_NAME	": "
62 63
#define DRV_MODULE_VERSION	"2.0.1"
#define DRV_MODULE_RELDATE	"May 6, 2009"
64 65 66 67
#define FW_MIPS_FILE_06		"bnx2/bnx2-mips-06-4.6.16.fw"
#define FW_RV2P_FILE_06		"bnx2/bnx2-rv2p-06-4.6.16.fw"
#define FW_MIPS_FILE_09		"bnx2/bnx2-mips-09-4.6.17.fw"
#define FW_RV2P_FILE_09		"bnx2/bnx2-rv2p-09-4.6.15.fw"
68 69 70 71 72 73

#define RUN_AT(x) (jiffies + (x))

/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT  (5*HZ)

A
Andrew Morton 已提交
74
static char version[] __devinitdata =
75 76 77
	"Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";

MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
78
MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
79 80
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_MODULE_VERSION);
81 82 83 84
MODULE_FIRMWARE(FW_MIPS_FILE_06);
MODULE_FIRMWARE(FW_RV2P_FILE_06);
MODULE_FIRMWARE(FW_MIPS_FILE_09);
MODULE_FIRMWARE(FW_RV2P_FILE_09);
85 86 87 88 89 90 91 92 93 94 95 96

static int disable_msi = 0;

module_param(disable_msi, int, 0);
MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");

typedef enum {
	BCM5706 = 0,
	NC370T,
	NC370I,
	BCM5706S,
	NC370F,
97 98
	BCM5708,
	BCM5708S,
M
Michael Chan 已提交
99
	BCM5709,
100
	BCM5709S,
M
Michael Chan 已提交
101
	BCM5716,
102
	BCM5716S,
103 104 105
} board_t;

/* indexed by board_t, above */
A
Andrew Morton 已提交
106
static struct {
107 108 109 110 111 112 113
	char *name;
} board_info[] __devinitdata = {
	{ "Broadcom NetXtreme II BCM5706 1000Base-T" },
	{ "HP NC370T Multifunction Gigabit Server Adapter" },
	{ "HP NC370i Multifunction Gigabit Server Adapter" },
	{ "Broadcom NetXtreme II BCM5706 1000Base-SX" },
	{ "HP NC370F Multifunction Gigabit Server Adapter" },
114 115
	{ "Broadcom NetXtreme II BCM5708 1000Base-T" },
	{ "Broadcom NetXtreme II BCM5708 1000Base-SX" },
M
Michael Chan 已提交
116
	{ "Broadcom NetXtreme II BCM5709 1000Base-T" },
117
	{ "Broadcom NetXtreme II BCM5709 1000Base-SX" },
M
Michael Chan 已提交
118
	{ "Broadcom NetXtreme II BCM5716 1000Base-T" },
119
	{ "Broadcom NetXtreme II BCM5716 1000Base-SX" },
120 121
	};

M
Michael Chan 已提交
122
static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
123 124 125 126 127 128
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
	  PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
	  PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
129 130
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
131 132 133 134
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
	  PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
135 136
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
M
Michael Chan 已提交
137 138
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
139 140
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
M
Michael Chan 已提交
141 142
	{ PCI_VENDOR_ID_BROADCOM, 0x163b,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
143
	{ PCI_VENDOR_ID_BROADCOM, 0x163c,
144
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
145 146 147 148 149
	{ 0, }
};

static struct flash_spec flash_table[] =
{
150 151
#define BUFFERED_FLAGS		(BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
#define NONBUFFERED_FLAGS	(BNX2_NV_WREN)
152
	/* Slow EEPROM */
153
	{0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
154
	 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
155 156
	 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
	 "EEPROM - slow"},
157 158
	/* Expansion entry 0001 */
	{0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
159
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
160 161
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 0001"},
162 163
	/* Saifun SA25F010 (non-buffered flash) */
	/* strap, cfg1, & write1 need updates */
164
	{0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
165
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
166 167 168 169
	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
	 "Non-buffered flash (128kB)"},
	/* Saifun SA25F020 (non-buffered flash) */
	/* strap, cfg1, & write1 need updates */
170
	{0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
171
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
172 173
	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
	 "Non-buffered flash (256kB)"},
174 175
	/* Expansion entry 0100 */
	{0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
176
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
177 178 179
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 0100"},
	/* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
180
	{0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
181
	 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
182 183 184 185
	 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
	 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
	/* Entry 0110: ST M45PE20 (non-buffered flash)*/
	{0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
186
	 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
187 188 189 190 191
	 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
	 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
	/* Saifun SA25F005 (non-buffered flash) */
	/* strap, cfg1, & write1 need updates */
	{0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
192
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
193 194 195 196
	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
	 "Non-buffered flash (64kB)"},
	/* Fast EEPROM */
	{0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
197
	 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
198 199 200 201
	 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
	 "EEPROM - fast"},
	/* Expansion entry 1001 */
	{0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
202
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
203 204 205 206
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1001"},
	/* Expansion entry 1010 */
	{0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
207
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
208 209 210 211
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1010"},
	/* ATMEL AT45DB011B (buffered flash) */
	{0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
212
	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
213 214 215 216
	 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
	 "Buffered flash (128kB)"},
	/* Expansion entry 1100 */
	{0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
217
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
218 219 220 221
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1100"},
	/* Expansion entry 1101 */
	{0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
222
	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
223 224 225 226
	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1101"},
	/* Ateml Expansion entry 1110 */
	{0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
227
	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
228 229 230 231
	 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
	 "Entry 1110 (Atmel)"},
	/* ATMEL AT45DB021B (buffered flash) */
	{0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
232
	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
233 234
	 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
	 "Buffered flash (256kB)"},
235 236
};

237 238 239 240 241 242 243 244 245
static struct flash_spec flash_5709 = {
	.flags		= BNX2_NV_BUFFERED,
	.page_bits	= BCM5709_FLASH_PAGE_BITS,
	.page_size	= BCM5709_FLASH_PAGE_SIZE,
	.addr_mask	= BCM5709_FLASH_BYTE_ADDR_MASK,
	.total_size	= BUFFERED_FLASH_TOTAL_SIZE*2,
	.name		= "5709 Buffered flash (256kB)",
};

246 247
MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);

248
static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
249
{
250
	u32 diff;
251

252
	smp_mb();
253 254 255 256

	/* The ring uses 256 indices for 255 entries, one of them
	 * needs to be skipped.
	 */
257
	diff = txr->tx_prod - txr->tx_cons;
258 259 260 261 262
	if (unlikely(diff >= TX_DESC_CNT)) {
		diff &= 0xffff;
		if (diff == TX_DESC_CNT)
			diff = MAX_TX_DESC_CNT;
	}
263 264 265
	return (bp->tx_ring_size - diff);
}

266 267 268
static u32
bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
{
269 270 271
	u32 val;

	spin_lock_bh(&bp->indirect_lock);
272
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
273 274 275
	val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
	spin_unlock_bh(&bp->indirect_lock);
	return val;
276 277 278 279 280
}

static void
bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
{
281
	spin_lock_bh(&bp->indirect_lock);
282 283
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
284
	spin_unlock_bh(&bp->indirect_lock);
285 286
}

287 288 289 290 291 292 293 294 295 296 297 298
static void
bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
{
	bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
}

static u32
bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
{
	return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
}

299 300 301 302
static void
bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
{
	offset += cid_addr;
303
	spin_lock_bh(&bp->indirect_lock);
304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		int i;

		REG_WR(bp, BNX2_CTX_CTX_DATA, val);
		REG_WR(bp, BNX2_CTX_CTX_CTRL,
		       offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
		for (i = 0; i < 5; i++) {
			val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
			if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
				break;
			udelay(5);
		}
	} else {
		REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
		REG_WR(bp, BNX2_CTX_DATA, val);
	}
320
	spin_unlock_bh(&bp->indirect_lock);
321 322
}

323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474
#ifdef BCM_CNIC
static int
bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
{
	struct bnx2 *bp = netdev_priv(dev);
	struct drv_ctl_io *io = &info->data.io;

	switch (info->cmd) {
	case DRV_CTL_IO_WR_CMD:
		bnx2_reg_wr_ind(bp, io->offset, io->data);
		break;
	case DRV_CTL_IO_RD_CMD:
		io->data = bnx2_reg_rd_ind(bp, io->offset);
		break;
	case DRV_CTL_CTX_WR_CMD:
		bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
{
	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
	int sb_id;

	if (bp->flags & BNX2_FLAG_USING_MSIX) {
		cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
		bnapi->cnic_present = 0;
		sb_id = bp->irq_nvecs;
		cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
	} else {
		cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
		bnapi->cnic_tag = bnapi->last_status_idx;
		bnapi->cnic_present = 1;
		sb_id = 0;
		cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
	}

	cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
	cp->irq_arr[0].status_blk = (void *)
		((unsigned long) bnapi->status_blk.msi +
		(BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
	cp->irq_arr[0].status_blk_num = sb_id;
	cp->num_irq = 1;
}

static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
			      void *data)
{
	struct bnx2 *bp = netdev_priv(dev);
	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;

	if (ops == NULL)
		return -EINVAL;

	if (cp->drv_state & CNIC_DRV_STATE_REGD)
		return -EBUSY;

	bp->cnic_data = data;
	rcu_assign_pointer(bp->cnic_ops, ops);

	cp->num_irq = 0;
	cp->drv_state = CNIC_DRV_STATE_REGD;

	bnx2_setup_cnic_irq_info(bp);

	return 0;
}

static int bnx2_unregister_cnic(struct net_device *dev)
{
	struct bnx2 *bp = netdev_priv(dev);
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;

	cp->drv_state = 0;
	bnapi->cnic_present = 0;
	rcu_assign_pointer(bp->cnic_ops, NULL);
	synchronize_rcu();
	return 0;
}

struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
{
	struct bnx2 *bp = netdev_priv(dev);
	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;

	cp->drv_owner = THIS_MODULE;
	cp->chip_id = bp->chip_id;
	cp->pdev = bp->pdev;
	cp->io_base = bp->regview;
	cp->drv_ctl = bnx2_drv_ctl;
	cp->drv_register_cnic = bnx2_register_cnic;
	cp->drv_unregister_cnic = bnx2_unregister_cnic;

	return cp;
}
EXPORT_SYMBOL(bnx2_cnic_probe);

static void
bnx2_cnic_stop(struct bnx2 *bp)
{
	struct cnic_ops *c_ops;
	struct cnic_ctl_info info;

	rcu_read_lock();
	c_ops = rcu_dereference(bp->cnic_ops);
	if (c_ops) {
		info.cmd = CNIC_CTL_STOP_CMD;
		c_ops->cnic_ctl(bp->cnic_data, &info);
	}
	rcu_read_unlock();
}

static void
bnx2_cnic_start(struct bnx2 *bp)
{
	struct cnic_ops *c_ops;
	struct cnic_ctl_info info;

	rcu_read_lock();
	c_ops = rcu_dereference(bp->cnic_ops);
	if (c_ops) {
		if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
			struct bnx2_napi *bnapi = &bp->bnx2_napi[0];

			bnapi->cnic_tag = bnapi->last_status_idx;
		}
		info.cmd = CNIC_CTL_START_CMD;
		c_ops->cnic_ctl(bp->cnic_data, &info);
	}
	rcu_read_unlock();
}

#else

static void
bnx2_cnic_stop(struct bnx2 *bp)
{
}

static void
bnx2_cnic_start(struct bnx2 *bp)
{
}

#endif

475 476 477 478 479 480
static int
bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
{
	u32 val1;
	int i, ret;

481
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	val1 = (bp->phy_addr << 21) | (reg << 16) |
		BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
		BNX2_EMAC_MDIO_COMM_START_BUSY;
	REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);

	for (i = 0; i < 50; i++) {
		udelay(10);

		val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
		if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
			udelay(5);

			val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
			val1 &= BNX2_EMAC_MDIO_COMM_DATA;

			break;
		}
	}

	if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
		*val = 0x0;
		ret = -EBUSY;
	}
	else {
		*val = val1;
		ret = 0;
	}

519
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	return ret;
}

static int
bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
{
	u32 val1;
	int i, ret;

538
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
539 540 541 542 543 544 545 546 547 548 549 550 551
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	val1 = (bp->phy_addr << 21) | (reg << 16) | val |
		BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
		BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
	REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
552

553 554 555 556 557 558 559 560 561 562 563 564 565 566 567
	for (i = 0; i < 50; i++) {
		udelay(10);

		val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
		if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
			udelay(5);
			break;
		}
	}

	if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
        	ret = -EBUSY;
	else
		ret = 0;

568
	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
569 570 571 572 573 574 575 576 577 578 579 580 581 582 583
		val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
		val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;

		REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
		REG_RD(bp, BNX2_EMAC_MDIO_MODE);

		udelay(40);
	}

	return ret;
}

static void
bnx2_disable_int(struct bnx2 *bp)
{
584 585 586 587 588 589 590 591
	int i;
	struct bnx2_napi *bnapi;

	for (i = 0; i < bp->irq_nvecs; i++) {
		bnapi = &bp->bnx2_napi[i];
		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
		       BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
	}
592 593 594 595 596 597
	REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
}

static void
bnx2_enable_int(struct bnx2 *bp)
{
598 599
	int i;
	struct bnx2_napi *bnapi;
600

601 602
	for (i = 0; i < bp->irq_nvecs; i++) {
		bnapi = &bp->bnx2_napi[i];
603

604 605 606 607
		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
		       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
		       BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
		       bnapi->last_status_idx);
608

609 610 611 612
		REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
		       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
		       bnapi->last_status_idx);
	}
613
	REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
614 615 616 617 618
}

static void
bnx2_disable_int_sync(struct bnx2 *bp)
{
619 620
	int i;

621 622
	atomic_inc(&bp->intr_sem);
	bnx2_disable_int(bp);
623 624
	for (i = 0; i < bp->irq_nvecs; i++)
		synchronize_irq(bp->irq_tbl[i].vector);
625 626
}

627 628 629
static void
bnx2_napi_disable(struct bnx2 *bp)
{
630 631 632 633
	int i;

	for (i = 0; i < bp->irq_nvecs; i++)
		napi_disable(&bp->bnx2_napi[i].napi);
634 635 636 637 638
}

static void
bnx2_napi_enable(struct bnx2 *bp)
{
639 640 641 642
	int i;

	for (i = 0; i < bp->irq_nvecs; i++)
		napi_enable(&bp->bnx2_napi[i].napi);
643 644
}

645 646 647
static void
bnx2_netif_stop(struct bnx2 *bp)
{
648
	bnx2_cnic_stop(bp);
649 650
	bnx2_disable_int_sync(bp);
	if (netif_running(bp->dev)) {
651
		bnx2_napi_disable(bp);
652 653 654 655 656 657 658 659 660 661
		netif_tx_disable(bp->dev);
		bp->dev->trans_start = jiffies;	/* prevent tx timeout */
	}
}

static void
bnx2_netif_start(struct bnx2 *bp)
{
	if (atomic_dec_and_test(&bp->intr_sem)) {
		if (netif_running(bp->dev)) {
662
			netif_tx_wake_all_queues(bp->dev);
663
			bnx2_napi_enable(bp);
664
			bnx2_enable_int(bp);
665
			bnx2_cnic_start(bp);
666 667 668 669
		}
	}
}

670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689
static void
bnx2_free_tx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_tx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;

		if (txr->tx_desc_ring) {
			pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
					    txr->tx_desc_ring,
					    txr->tx_desc_mapping);
			txr->tx_desc_ring = NULL;
		}
		kfree(txr->tx_buf_ring);
		txr->tx_buf_ring = NULL;
	}
}

690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706
static void
bnx2_free_rx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_rx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
		int j;

		for (j = 0; j < bp->rx_max_ring; j++) {
			if (rxr->rx_desc_ring[j])
				pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
						    rxr->rx_desc_ring[j],
						    rxr->rx_desc_mapping[j]);
			rxr->rx_desc_ring[j] = NULL;
		}
707
		vfree(rxr->rx_buf_ring);
708 709 710 711 712
		rxr->rx_buf_ring = NULL;

		for (j = 0; j < bp->rx_max_pg_ring; j++) {
			if (rxr->rx_pg_desc_ring[j])
				pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
713 714 715
						    rxr->rx_pg_desc_ring[j],
						    rxr->rx_pg_desc_mapping[j]);
			rxr->rx_pg_desc_ring[j] = NULL;
716
		}
717
		vfree(rxr->rx_pg_ring);
718 719 720 721
		rxr->rx_pg_ring = NULL;
	}
}

722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743
static int
bnx2_alloc_tx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_tx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;

		txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
		if (txr->tx_buf_ring == NULL)
			return -ENOMEM;

		txr->tx_desc_ring =
			pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
					     &txr->tx_desc_mapping);
		if (txr->tx_desc_ring == NULL)
			return -ENOMEM;
	}
	return 0;
}

744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792
static int
bnx2_alloc_rx_mem(struct bnx2 *bp)
{
	int i;

	for (i = 0; i < bp->num_rx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
		int j;

		rxr->rx_buf_ring =
			vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
		if (rxr->rx_buf_ring == NULL)
			return -ENOMEM;

		memset(rxr->rx_buf_ring, 0,
		       SW_RXBD_RING_SIZE * bp->rx_max_ring);

		for (j = 0; j < bp->rx_max_ring; j++) {
			rxr->rx_desc_ring[j] =
				pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
						     &rxr->rx_desc_mapping[j]);
			if (rxr->rx_desc_ring[j] == NULL)
				return -ENOMEM;

		}

		if (bp->rx_pg_ring_size) {
			rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
						  bp->rx_max_pg_ring);
			if (rxr->rx_pg_ring == NULL)
				return -ENOMEM;

			memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
			       bp->rx_max_pg_ring);
		}

		for (j = 0; j < bp->rx_max_pg_ring; j++) {
			rxr->rx_pg_desc_ring[j] =
				pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
						&rxr->rx_pg_desc_mapping[j]);
			if (rxr->rx_pg_desc_ring[j] == NULL)
				return -ENOMEM;

		}
	}
	return 0;
}

793 794 795
static void
bnx2_free_mem(struct bnx2 *bp)
{
796
	int i;
797
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
798

799
	bnx2_free_tx_mem(bp);
800
	bnx2_free_rx_mem(bp);
801

802 803 804 805 806 807 808 809
	for (i = 0; i < bp->ctx_pages; i++) {
		if (bp->ctx_blk[i]) {
			pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
					    bp->ctx_blk[i],
					    bp->ctx_blk_mapping[i]);
			bp->ctx_blk[i] = NULL;
		}
	}
810
	if (bnapi->status_blk.msi) {
811
		pci_free_consistent(bp->pdev, bp->status_stats_size,
812 813 814
				    bnapi->status_blk.msi,
				    bp->status_blk_mapping);
		bnapi->status_blk.msi = NULL;
815
		bp->stats_blk = NULL;
816 817 818 819 820 821
	}
}

static int
bnx2_alloc_mem(struct bnx2 *bp)
{
822
	int i, status_blk_size, err;
823 824
	struct bnx2_napi *bnapi;
	void *status_blk;
825

826 827
	/* Combine status and statistics blocks into one allocation. */
	status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
828
	if (bp->flags & BNX2_FLAG_MSIX_CAP)
829 830
		status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
						 BNX2_SBLK_MSIX_ALIGN_SIZE);
831 832 833
	bp->status_stats_size = status_blk_size +
				sizeof(struct statistics_block);

834 835 836
	status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
					  &bp->status_blk_mapping);
	if (status_blk == NULL)
837 838
		goto alloc_mem_err;

839
	memset(status_blk, 0, bp->status_stats_size);
840

841 842 843 844 845 846
	bnapi = &bp->bnx2_napi[0];
	bnapi->status_blk.msi = status_blk;
	bnapi->hw_tx_cons_ptr =
		&bnapi->status_blk.msi->status_tx_quick_consumer_index0;
	bnapi->hw_rx_cons_ptr =
		&bnapi->status_blk.msi->status_rx_quick_consumer_index0;
847
	if (bp->flags & BNX2_FLAG_MSIX_CAP) {
848
		for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
849 850 851
			struct status_block_msix *sblk;

			bnapi = &bp->bnx2_napi[i];
852

853 854 855 856 857 858 859
			sblk = (void *) (status_blk +
					 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
			bnapi->status_blk.msix = sblk;
			bnapi->hw_tx_cons_ptr =
				&sblk->status_tx_quick_consumer_index;
			bnapi->hw_rx_cons_ptr =
				&sblk->status_rx_quick_consumer_index;
860 861 862
			bnapi->int_num = i << 24;
		}
	}
863

864
	bp->stats_blk = status_blk + status_blk_size;
865

866
	bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
867

868 869 870 871 872 873 874 875 876 877 878 879
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
		if (bp->ctx_pages == 0)
			bp->ctx_pages = 1;
		for (i = 0; i < bp->ctx_pages; i++) {
			bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
						BCM_PAGE_SIZE,
						&bp->ctx_blk_mapping[i]);
			if (bp->ctx_blk[i] == NULL)
				goto alloc_mem_err;
		}
	}
880

881 882 883 884
	err = bnx2_alloc_rx_mem(bp);
	if (err)
		goto alloc_mem_err;

885 886 887 888
	err = bnx2_alloc_tx_mem(bp);
	if (err)
		goto alloc_mem_err;

889 890 891 892 893 894 895
	return 0;

alloc_mem_err:
	bnx2_free_mem(bp);
	return -ENOMEM;
}

896 897 898 899 900
static void
bnx2_report_fw_link(struct bnx2 *bp)
{
	u32 fw_link_status = 0;

901
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
902 903
		return;

904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938
	if (bp->link_up) {
		u32 bmsr;

		switch (bp->line_speed) {
		case SPEED_10:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_10HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_10FULL;
			break;
		case SPEED_100:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_100HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_100FULL;
			break;
		case SPEED_1000:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_1000HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_1000FULL;
			break;
		case SPEED_2500:
			if (bp->duplex == DUPLEX_HALF)
				fw_link_status = BNX2_LINK_STATUS_2500HALF;
			else
				fw_link_status = BNX2_LINK_STATUS_2500FULL;
			break;
		}

		fw_link_status |= BNX2_LINK_STATUS_LINK_UP;

		if (bp->autoneg) {
			fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;

939 940
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
941 942

			if (!(bmsr & BMSR_ANEGCOMPLETE) ||
943
			    bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
944 945 946 947 948 949 950 951
				fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
			else
				fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
		}
	}
	else
		fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;

952
	bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
953 954
}

955 956 957 958
static char *
bnx2_xceiver_str(struct bnx2 *bp)
{
	return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
959
		((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
960 961 962
		 "Copper"));
}

963 964 965 966 967
static void
bnx2_report_link(struct bnx2 *bp)
{
	if (bp->link_up) {
		netif_carrier_on(bp->dev);
968 969
		printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
		       bnx2_xceiver_str(bp));
970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992

		printk("%d Mbps ", bp->line_speed);

		if (bp->duplex == DUPLEX_FULL)
			printk("full duplex");
		else
			printk("half duplex");

		if (bp->flow_ctrl) {
			if (bp->flow_ctrl & FLOW_CTRL_RX) {
				printk(", receive ");
				if (bp->flow_ctrl & FLOW_CTRL_TX)
					printk("& transmit ");
			}
			else {
				printk(", transmit ");
			}
			printk("flow control ON");
		}
		printk("\n");
	}
	else {
		netif_carrier_off(bp->dev);
993 994
		printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
		       bnx2_xceiver_str(bp));
995
	}
996 997

	bnx2_report_fw_link(bp);
998 999 1000 1001 1002 1003 1004 1005
}

static void
bnx2_resolve_flow_ctrl(struct bnx2 *bp)
{
	u32 local_adv, remote_adv;

	bp->flow_ctrl = 0;
1006
	if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018
		(AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {

		if (bp->duplex == DUPLEX_FULL) {
			bp->flow_ctrl = bp->req_flow_ctrl;
		}
		return;
	}

	if (bp->duplex != DUPLEX_FULL) {
		return;
	}

1019
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030
	    (CHIP_NUM(bp) == CHIP_NUM_5708)) {
		u32 val;

		bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
		if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
			bp->flow_ctrl |= FLOW_CTRL_TX;
		if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
			bp->flow_ctrl |= FLOW_CTRL_RX;
		return;
	}

1031 1032
	bnx2_read_phy(bp, bp->mii_adv, &local_adv);
	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1033

1034
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
		u32 new_local_adv = 0;
		u32 new_remote_adv = 0;

		if (local_adv & ADVERTISE_1000XPAUSE)
			new_local_adv |= ADVERTISE_PAUSE_CAP;
		if (local_adv & ADVERTISE_1000XPSE_ASYM)
			new_local_adv |= ADVERTISE_PAUSE_ASYM;
		if (remote_adv & ADVERTISE_1000XPAUSE)
			new_remote_adv |= ADVERTISE_PAUSE_CAP;
		if (remote_adv & ADVERTISE_1000XPSE_ASYM)
			new_remote_adv |= ADVERTISE_PAUSE_ASYM;

		local_adv = new_local_adv;
		remote_adv = new_remote_adv;
	}

	/* See Table 28B-3 of 802.3ab-1999 spec. */
	if (local_adv & ADVERTISE_PAUSE_CAP) {
		if(local_adv & ADVERTISE_PAUSE_ASYM) {
	                if (remote_adv & ADVERTISE_PAUSE_CAP) {
				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
			}
			else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
				bp->flow_ctrl = FLOW_CTRL_RX;
			}
		}
		else {
			if (remote_adv & ADVERTISE_PAUSE_CAP) {
				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
			}
		}
	}
	else if (local_adv & ADVERTISE_PAUSE_ASYM) {
		if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
			(remote_adv & ADVERTISE_PAUSE_ASYM)) {

			bp->flow_ctrl = FLOW_CTRL_TX;
		}
	}
}

1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114
static int
bnx2_5709s_linkup(struct bnx2 *bp)
{
	u32 val, speed;

	bp->link_up = 1;

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
	bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

	if ((bp->autoneg & AUTONEG_SPEED) == 0) {
		bp->line_speed = bp->req_line_speed;
		bp->duplex = bp->req_duplex;
		return 0;
	}
	speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
	switch (speed) {
		case MII_BNX2_GP_TOP_AN_SPEED_10:
			bp->line_speed = SPEED_10;
			break;
		case MII_BNX2_GP_TOP_AN_SPEED_100:
			bp->line_speed = SPEED_100;
			break;
		case MII_BNX2_GP_TOP_AN_SPEED_1G:
		case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
			bp->line_speed = SPEED_1000;
			break;
		case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
			bp->line_speed = SPEED_2500;
			break;
	}
	if (val & MII_BNX2_GP_TOP_AN_FD)
		bp->duplex = DUPLEX_FULL;
	else
		bp->duplex = DUPLEX_HALF;
	return 0;
}

1115
static int
1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145
bnx2_5708s_linkup(struct bnx2 *bp)
{
	u32 val;

	bp->link_up = 1;
	bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
	switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
		case BCM5708S_1000X_STAT1_SPEED_10:
			bp->line_speed = SPEED_10;
			break;
		case BCM5708S_1000X_STAT1_SPEED_100:
			bp->line_speed = SPEED_100;
			break;
		case BCM5708S_1000X_STAT1_SPEED_1G:
			bp->line_speed = SPEED_1000;
			break;
		case BCM5708S_1000X_STAT1_SPEED_2G5:
			bp->line_speed = SPEED_2500;
			break;
	}
	if (val & BCM5708S_1000X_STAT1_FD)
		bp->duplex = DUPLEX_FULL;
	else
		bp->duplex = DUPLEX_HALF;

	return 0;
}

static int
bnx2_5706s_linkup(struct bnx2 *bp)
1146 1147 1148 1149 1150 1151
{
	u32 bmcr, local_adv, remote_adv, common;

	bp->link_up = 1;
	bp->line_speed = SPEED_1000;

1152
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163
	if (bmcr & BMCR_FULLDPLX) {
		bp->duplex = DUPLEX_FULL;
	}
	else {
		bp->duplex = DUPLEX_HALF;
	}

	if (!(bmcr & BMCR_ANENABLE)) {
		return 0;
	}

1164 1165
	bnx2_read_phy(bp, bp->mii_adv, &local_adv);
	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185

	common = local_adv & remote_adv;
	if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {

		if (common & ADVERTISE_1000XFULL) {
			bp->duplex = DUPLEX_FULL;
		}
		else {
			bp->duplex = DUPLEX_HALF;
		}
	}

	return 0;
}

static int
bnx2_copper_linkup(struct bnx2 *bp)
{
	u32 bmcr;

1186
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202
	if (bmcr & BMCR_ANENABLE) {
		u32 local_adv, remote_adv, common;

		bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
		bnx2_read_phy(bp, MII_STAT1000, &remote_adv);

		common = local_adv & (remote_adv >> 2);
		if (common & ADVERTISE_1000FULL) {
			bp->line_speed = SPEED_1000;
			bp->duplex = DUPLEX_FULL;
		}
		else if (common & ADVERTISE_1000HALF) {
			bp->line_speed = SPEED_1000;
			bp->duplex = DUPLEX_HALF;
		}
		else {
1203 1204
			bnx2_read_phy(bp, bp->mii_adv, &local_adv);
			bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246

			common = local_adv & remote_adv;
			if (common & ADVERTISE_100FULL) {
				bp->line_speed = SPEED_100;
				bp->duplex = DUPLEX_FULL;
			}
			else if (common & ADVERTISE_100HALF) {
				bp->line_speed = SPEED_100;
				bp->duplex = DUPLEX_HALF;
			}
			else if (common & ADVERTISE_10FULL) {
				bp->line_speed = SPEED_10;
				bp->duplex = DUPLEX_FULL;
			}
			else if (common & ADVERTISE_10HALF) {
				bp->line_speed = SPEED_10;
				bp->duplex = DUPLEX_HALF;
			}
			else {
				bp->line_speed = 0;
				bp->link_up = 0;
			}
		}
	}
	else {
		if (bmcr & BMCR_SPEED100) {
			bp->line_speed = SPEED_100;
		}
		else {
			bp->line_speed = SPEED_10;
		}
		if (bmcr & BMCR_FULLDPLX) {
			bp->duplex = DUPLEX_FULL;
		}
		else {
			bp->duplex = DUPLEX_HALF;
		}
	}

	return 0;
}

1247
static void
1248
bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1249
{
1250
	u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282

	val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
	val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
	val |= 0x02 << 8;

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		u32 lo_water, hi_water;

		if (bp->flow_ctrl & FLOW_CTRL_TX)
			lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
		else
			lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
		if (lo_water >= bp->rx_ring_size)
			lo_water = 0;

		hi_water = bp->rx_ring_size / 4;

		if (hi_water <= lo_water)
			lo_water = 0;

		hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
		lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;

		if (hi_water > 0xf)
			hi_water = 0xf;
		else if (hi_water == 0)
			lo_water = 0;
		val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
	}
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
}

1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295
static void
bnx2_init_all_rx_contexts(struct bnx2 *bp)
{
	int i;
	u32 cid;

	for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
		if (i == 1)
			cid = RX_RSS_CID;
		bnx2_init_rx_context(bp, cid);
	}
}

1296
static void
1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310
bnx2_set_mac_link(struct bnx2 *bp)
{
	u32 val;

	REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
	if (bp->link_up && (bp->line_speed == SPEED_1000) &&
		(bp->duplex == DUPLEX_HALF)) {
		REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
	}

	/* Configure the EMAC mode register. */
	val = REG_RD(bp, BNX2_EMAC_MODE);

	val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1311
		BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1312
		BNX2_EMAC_MODE_25G_MODE);
1313 1314

	if (bp->link_up) {
1315 1316
		switch (bp->line_speed) {
			case SPEED_10:
1317 1318
				if (CHIP_NUM(bp) != CHIP_NUM_5706) {
					val |= BNX2_EMAC_MODE_PORT_MII_10M;
1319 1320 1321 1322 1323 1324 1325
					break;
				}
				/* fall through */
			case SPEED_100:
				val |= BNX2_EMAC_MODE_PORT_MII;
				break;
			case SPEED_2500:
1326
				val |= BNX2_EMAC_MODE_25G_MODE;
1327 1328 1329 1330 1331
				/* fall through */
			case SPEED_1000:
				val |= BNX2_EMAC_MODE_PORT_GMII;
				break;
		}
1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359
	}
	else {
		val |= BNX2_EMAC_MODE_PORT_GMII;
	}

	/* Set the MAC to operate in the appropriate duplex mode. */
	if (bp->duplex == DUPLEX_HALF)
		val |= BNX2_EMAC_MODE_HALF_DUPLEX;
	REG_WR(bp, BNX2_EMAC_MODE, val);

	/* Enable/disable rx PAUSE. */
	bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;

	if (bp->flow_ctrl & FLOW_CTRL_RX)
		bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
	REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);

	/* Enable/disable tx PAUSE. */
	val = REG_RD(bp, BNX2_EMAC_TX_MODE);
	val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;

	if (bp->flow_ctrl & FLOW_CTRL_TX)
		val |= BNX2_EMAC_TX_MODE_FLOW_EN;
	REG_WR(bp, BNX2_EMAC_TX_MODE, val);

	/* Acknowledge the interrupt. */
	REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);

1360
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
1361
		bnx2_init_all_rx_contexts(bp);
1362 1363
}

1364 1365 1366
static void
bnx2_enable_bmsr1(struct bnx2 *bp)
{
1367
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1368 1369 1370 1371 1372 1373 1374 1375
	    (CHIP_NUM(bp) == CHIP_NUM_5709))
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_GP_STATUS);
}

static void
bnx2_disable_bmsr1(struct bnx2 *bp)
{
1376
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1377 1378 1379 1380 1381
	    (CHIP_NUM(bp) == CHIP_NUM_5709))
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
}

1382 1383 1384 1385 1386 1387
static int
bnx2_test_and_enable_2g5(struct bnx2 *bp)
{
	u32 up1;
	int ret = 1;

1388
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1389 1390 1391 1392 1393
		return 0;

	if (bp->autoneg & AUTONEG_SPEED)
		bp->advertising |= ADVERTISED_2500baseX_Full;

1394 1395 1396
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);

1397 1398 1399 1400 1401 1402 1403
	bnx2_read_phy(bp, bp->mii_up1, &up1);
	if (!(up1 & BCM5708S_UP1_2G5)) {
		up1 |= BCM5708S_UP1_2G5;
		bnx2_write_phy(bp, bp->mii_up1, up1);
		ret = 0;
	}

1404 1405 1406 1407
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

1408 1409 1410 1411 1412 1413 1414 1415 1416
	return ret;
}

static int
bnx2_test_and_disable_2g5(struct bnx2 *bp)
{
	u32 up1;
	int ret = 0;

1417
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1418 1419
		return 0;

1420 1421 1422
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);

1423 1424 1425 1426 1427 1428 1429
	bnx2_read_phy(bp, bp->mii_up1, &up1);
	if (up1 & BCM5708S_UP1_2G5) {
		up1 &= ~BCM5708S_UP1_2G5;
		bnx2_write_phy(bp, bp->mii_up1, up1);
		ret = 1;
	}

1430 1431 1432 1433
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

1434 1435 1436 1437 1438 1439 1440 1441
	return ret;
}

static void
bnx2_enable_forced_2g5(struct bnx2 *bp)
{
	u32 bmcr;

1442
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1443 1444
		return;

1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		u32 val;

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_SERDES_DIG);
		bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
		val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
		val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
		bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);

	} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
		bmcr |= BCM5708S_BMCR_FORCE_2500;
	}

	if (bp->autoneg & AUTONEG_SPEED) {
		bmcr &= ~BMCR_ANENABLE;
		if (bp->req_duplex == DUPLEX_FULL)
			bmcr |= BMCR_FULLDPLX;
	}
	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
}

static void
bnx2_disable_forced_2g5(struct bnx2 *bp)
{
	u32 bmcr;

1477
	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1478 1479
		return;

1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		u32 val;

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_SERDES_DIG);
		bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
		val &= ~MII_BNX2_SD_MISC1_FORCE;
		bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);

		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
			       MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);

	} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1494 1495 1496 1497 1498 1499 1500 1501 1502
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
		bmcr &= ~BCM5708S_BMCR_FORCE_2500;
	}

	if (bp->autoneg & AUTONEG_SPEED)
		bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
}

1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515
static void
bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
{
	u32 val;

	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
	if (start)
		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
	else
		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
}

1516 1517 1518 1519 1520 1521
static int
bnx2_set_link(struct bnx2 *bp)
{
	u32 bmsr;
	u8 link_up;

1522
	if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1523 1524 1525 1526
		bp->link_up = 1;
		return 0;
	}

1527
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1528 1529
		return 0;

1530 1531
	link_up = bp->link_up;

1532 1533 1534 1535
	bnx2_enable_bmsr1(bp);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_disable_bmsr1(bp);
1536

1537
	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1538
	    (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1539
		u32 val, an_dbg;
1540

1541
		if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1542
			bnx2_5706s_force_link_dn(bp, 0);
1543
			bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1544
		}
1545
		val = REG_RD(bp, BNX2_EMAC_STATUS);
1546 1547 1548 1549 1550 1551 1552

		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);

		if ((val & BNX2_EMAC_STATUS_LINK) &&
		    !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1553 1554 1555 1556 1557 1558 1559 1560
			bmsr |= BMSR_LSTATUS;
		else
			bmsr &= ~BMSR_LSTATUS;
	}

	if (bmsr & BMSR_LSTATUS) {
		bp->link_up = 1;

1561
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1562 1563 1564 1565
			if (CHIP_NUM(bp) == CHIP_NUM_5706)
				bnx2_5706s_linkup(bp);
			else if (CHIP_NUM(bp) == CHIP_NUM_5708)
				bnx2_5708s_linkup(bp);
1566 1567
			else if (CHIP_NUM(bp) == CHIP_NUM_5709)
				bnx2_5709s_linkup(bp);
1568 1569 1570 1571 1572 1573 1574
		}
		else {
			bnx2_copper_linkup(bp);
		}
		bnx2_resolve_flow_ctrl(bp);
	}
	else {
1575
		if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1576 1577
		    (bp->autoneg & AUTONEG_SPEED))
			bnx2_disable_forced_2g5(bp);
1578

1579
		if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1580 1581 1582 1583 1584 1585
			u32 bmcr;

			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
			bmcr |= BMCR_ANENABLE;
			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);

1586
			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1587
		}
1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605
		bp->link_up = 0;
	}

	if (bp->link_up != link_up) {
		bnx2_report_link(bp);
	}

	bnx2_set_mac_link(bp);

	return 0;
}

static int
bnx2_reset_phy(struct bnx2 *bp)
{
	int i;
	u32 reg;

1606
        bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1607 1608 1609 1610 1611

#define PHY_RESET_MAX_WAIT 100
	for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
		udelay(10);

1612
		bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631
		if (!(reg & BMCR_RESET)) {
			udelay(20);
			break;
		}
	}
	if (i == PHY_RESET_MAX_WAIT) {
		return -EBUSY;
	}
	return 0;
}

static u32
bnx2_phy_get_pause_adv(struct bnx2 *bp)
{
	u32 adv = 0;

	if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
		(FLOW_CTRL_RX | FLOW_CTRL_TX)) {

1632
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1633 1634 1635 1636 1637 1638 1639
			adv = ADVERTISE_1000XPAUSE;
		}
		else {
			adv = ADVERTISE_PAUSE_CAP;
		}
	}
	else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1640
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1641 1642 1643 1644 1645 1646 1647
			adv = ADVERTISE_1000XPSE_ASYM;
		}
		else {
			adv = ADVERTISE_PAUSE_ASYM;
		}
	}
	else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1648
		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1649 1650 1651 1652 1653 1654 1655 1656 1657
			adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
		}
		else {
			adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
		}
	}
	return adv;
}

1658
static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1659

1660
static int
1661
bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1662 1663
__releases(&bp->phy_lock)
__acquires(&bp->phy_lock)
1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702
{
	u32 speed_arg = 0, pause_adv;

	pause_adv = bnx2_phy_get_pause_adv(bp);

	if (bp->autoneg & AUTONEG_SPEED) {
		speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
		if (bp->advertising & ADVERTISED_10baseT_Half)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
		if (bp->advertising & ADVERTISED_10baseT_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
		if (bp->advertising & ADVERTISED_100baseT_Half)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
		if (bp->advertising & ADVERTISED_100baseT_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
		if (bp->advertising & ADVERTISED_1000baseT_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
		if (bp->advertising & ADVERTISED_2500baseX_Full)
			speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
	} else {
		if (bp->req_line_speed == SPEED_2500)
			speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
		else if (bp->req_line_speed == SPEED_1000)
			speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
		else if (bp->req_line_speed == SPEED_100) {
			if (bp->req_duplex == DUPLEX_FULL)
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
			else
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
		} else if (bp->req_line_speed == SPEED_10) {
			if (bp->req_duplex == DUPLEX_FULL)
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
			else
				speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
		}
	}

	if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
		speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1703
	if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1704 1705 1706 1707 1708 1709
		speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;

	if (port == PORT_TP)
		speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
			     BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;

1710
	bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1711 1712

	spin_unlock_bh(&bp->phy_lock);
1713
	bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1714 1715 1716 1717 1718 1719 1720
	spin_lock_bh(&bp->phy_lock);

	return 0;
}

static int
bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1721 1722
__releases(&bp->phy_lock)
__acquires(&bp->phy_lock)
1723
{
1724
	u32 adv, bmcr;
1725 1726
	u32 new_adv = 0;

1727
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1728 1729
		return (bnx2_setup_remote_phy(bp, port));

1730 1731
	if (!(bp->autoneg & AUTONEG_SPEED)) {
		u32 new_bmcr;
1732 1733
		int force_link_down = 0;

1734 1735 1736 1737 1738 1739 1740
		if (bp->req_line_speed == SPEED_2500) {
			if (!bnx2_test_and_enable_2g5(bp))
				force_link_down = 1;
		} else if (bp->req_line_speed == SPEED_1000) {
			if (bnx2_test_and_disable_2g5(bp))
				force_link_down = 1;
		}
1741
		bnx2_read_phy(bp, bp->mii_adv, &adv);
1742 1743
		adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);

1744
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1745
		new_bmcr = bmcr & ~BMCR_ANENABLE;
1746
		new_bmcr |= BMCR_SPEED1000;
1747

1748 1749 1750 1751 1752 1753 1754 1755 1756
		if (CHIP_NUM(bp) == CHIP_NUM_5709) {
			if (bp->req_line_speed == SPEED_2500)
				bnx2_enable_forced_2g5(bp);
			else if (bp->req_line_speed == SPEED_1000) {
				bnx2_disable_forced_2g5(bp);
				new_bmcr &= ~0x2000;
			}

		} else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1757 1758 1759 1760
			if (bp->req_line_speed == SPEED_2500)
				new_bmcr |= BCM5708S_BMCR_FORCE_2500;
			else
				new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1761 1762
		}

1763
		if (bp->req_duplex == DUPLEX_FULL) {
1764
			adv |= ADVERTISE_1000XFULL;
1765 1766 1767
			new_bmcr |= BMCR_FULLDPLX;
		}
		else {
1768
			adv |= ADVERTISE_1000XHALF;
1769 1770
			new_bmcr &= ~BMCR_FULLDPLX;
		}
1771
		if ((new_bmcr != bmcr) || (force_link_down)) {
1772 1773
			/* Force a link down visible on the other side */
			if (bp->link_up) {
1774
				bnx2_write_phy(bp, bp->mii_adv, adv &
1775 1776
					       ~(ADVERTISE_1000XFULL |
						 ADVERTISE_1000XHALF));
1777
				bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1778 1779 1780 1781
					BMCR_ANRESTART | BMCR_ANENABLE);

				bp->link_up = 0;
				netif_carrier_off(bp->dev);
1782
				bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1783
				bnx2_report_link(bp);
1784
			}
1785 1786
			bnx2_write_phy(bp, bp->mii_adv, adv);
			bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1787 1788 1789
		} else {
			bnx2_resolve_flow_ctrl(bp);
			bnx2_set_mac_link(bp);
1790 1791 1792 1793
		}
		return 0;
	}

1794
	bnx2_test_and_enable_2g5(bp);
1795

1796 1797 1798 1799 1800
	if (bp->advertising & ADVERTISED_1000baseT_Full)
		new_adv |= ADVERTISE_1000XFULL;

	new_adv |= bnx2_phy_get_pause_adv(bp);

1801 1802
	bnx2_read_phy(bp, bp->mii_adv, &adv);
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1803 1804 1805 1806 1807

	bp->serdes_an_pending = 0;
	if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
		/* Force a link down visible on the other side */
		if (bp->link_up) {
1808
			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1809 1810 1811
			spin_unlock_bh(&bp->phy_lock);
			msleep(20);
			spin_lock_bh(&bp->phy_lock);
1812 1813
		}

1814 1815
		bnx2_write_phy(bp, bp->mii_adv, new_adv);
		bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1816
			BMCR_ANENABLE);
1817 1818 1819 1820 1821 1822 1823 1824
		/* Speed up link-up time when the link partner
		 * does not autonegotiate which is very common
		 * in blade servers. Some blade servers use
		 * IPMI for kerboard input and it's important
		 * to minimize link disruptions. Autoneg. involves
		 * exchanging base pages plus 3 next pages and
		 * normally completes in about 120 msec.
		 */
1825
		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1826 1827
		bp->serdes_an_pending = 1;
		mod_timer(&bp->timer, jiffies + bp->current_interval);
1828 1829 1830
	} else {
		bnx2_resolve_flow_ctrl(bp);
		bnx2_set_mac_link(bp);
1831 1832 1833 1834 1835 1836
	}

	return 0;
}

#define ETHTOOL_ALL_FIBRE_SPEED						\
1837
	(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?			\
1838 1839
		(ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
		(ADVERTISED_1000baseT_Full)
1840 1841 1842 1843 1844 1845 1846 1847

#define ETHTOOL_ALL_COPPER_SPEED					\
	(ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |		\
	ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |		\
	ADVERTISED_1000baseT_Full)

#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
	ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1848

1849 1850
#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)

1851 1852 1853 1854 1855 1856
static void
bnx2_set_default_remote_link(struct bnx2 *bp)
{
	u32 link;

	if (bp->phy_port == PORT_TP)
1857
		link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1858
	else
1859
		link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897

	if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
		bp->req_line_speed = 0;
		bp->autoneg |= AUTONEG_SPEED;
		bp->advertising = ADVERTISED_Autoneg;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
			bp->advertising |= ADVERTISED_10baseT_Half;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
			bp->advertising |= ADVERTISED_10baseT_Full;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
			bp->advertising |= ADVERTISED_100baseT_Half;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
			bp->advertising |= ADVERTISED_100baseT_Full;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
			bp->advertising |= ADVERTISED_1000baseT_Full;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
			bp->advertising |= ADVERTISED_2500baseX_Full;
	} else {
		bp->autoneg = 0;
		bp->advertising = 0;
		bp->req_duplex = DUPLEX_FULL;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
			bp->req_line_speed = SPEED_10;
			if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
				bp->req_duplex = DUPLEX_HALF;
		}
		if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
			bp->req_line_speed = SPEED_100;
			if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
				bp->req_duplex = DUPLEX_HALF;
		}
		if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
			bp->req_line_speed = SPEED_1000;
		if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
			bp->req_line_speed = SPEED_2500;
	}
}

1898 1899 1900
static void
bnx2_set_default_link(struct bnx2 *bp)
{
1901 1902 1903 1904
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
		bnx2_set_default_remote_link(bp);
		return;
	}
1905

1906 1907
	bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
	bp->req_line_speed = 0;
1908
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1909 1910 1911 1912
		u32 reg;

		bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;

1913
		reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1914 1915 1916 1917 1918 1919 1920 1921 1922 1923
		reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
		if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
			bp->autoneg = 0;
			bp->req_line_speed = bp->line_speed = SPEED_1000;
			bp->req_duplex = DUPLEX_FULL;
		}
	} else
		bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
}

1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937
static void
bnx2_send_heart_beat(struct bnx2 *bp)
{
	u32 msg;
	u32 addr;

	spin_lock(&bp->indirect_lock);
	msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
	addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
	REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
	spin_unlock(&bp->indirect_lock);
}

1938 1939 1940 1941 1942 1943 1944
static void
bnx2_remote_phy_event(struct bnx2 *bp)
{
	u32 msg;
	u8 link_up = bp->link_up;
	u8 old_port;

1945
	msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1946

1947 1948 1949 1950 1951
	if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
		bnx2_send_heart_beat(bp);

	msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;

1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019
	if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
		bp->link_up = 0;
	else {
		u32 speed;

		bp->link_up = 1;
		speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
		bp->duplex = DUPLEX_FULL;
		switch (speed) {
			case BNX2_LINK_STATUS_10HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_10FULL:
				bp->line_speed = SPEED_10;
				break;
			case BNX2_LINK_STATUS_100HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_100BASE_T4:
			case BNX2_LINK_STATUS_100FULL:
				bp->line_speed = SPEED_100;
				break;
			case BNX2_LINK_STATUS_1000HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_1000FULL:
				bp->line_speed = SPEED_1000;
				break;
			case BNX2_LINK_STATUS_2500HALF:
				bp->duplex = DUPLEX_HALF;
			case BNX2_LINK_STATUS_2500FULL:
				bp->line_speed = SPEED_2500;
				break;
			default:
				bp->line_speed = 0;
				break;
		}

		bp->flow_ctrl = 0;
		if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
		    (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
			if (bp->duplex == DUPLEX_FULL)
				bp->flow_ctrl = bp->req_flow_ctrl;
		} else {
			if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
				bp->flow_ctrl |= FLOW_CTRL_TX;
			if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
				bp->flow_ctrl |= FLOW_CTRL_RX;
		}

		old_port = bp->phy_port;
		if (msg & BNX2_LINK_STATUS_SERDES_LINK)
			bp->phy_port = PORT_FIBRE;
		else
			bp->phy_port = PORT_TP;

		if (old_port != bp->phy_port)
			bnx2_set_default_link(bp);

	}
	if (bp->link_up != link_up)
		bnx2_report_link(bp);

	bnx2_set_mac_link(bp);
}

static int
bnx2_set_remote_link(struct bnx2 *bp)
{
	u32 evt_code;

2020
	evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2021 2022 2023 2024 2025 2026
	switch (evt_code) {
		case BNX2_FW_EVT_CODE_LINK_EVENT:
			bnx2_remote_phy_event(bp);
			break;
		case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
		default:
2027
			bnx2_send_heart_beat(bp);
2028 2029 2030 2031 2032
			break;
	}
	return 0;
}

2033 2034
static int
bnx2_setup_copper_phy(struct bnx2 *bp)
2035 2036
__releases(&bp->phy_lock)
__acquires(&bp->phy_lock)
2037 2038 2039 2040
{
	u32 bmcr;
	u32 new_bmcr;

2041
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2042 2043 2044 2045 2046 2047

	if (bp->autoneg & AUTONEG_SPEED) {
		u32 adv_reg, adv1000_reg;
		u32 new_adv_reg = 0;
		u32 new_adv1000_reg = 0;

2048
		bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064
		adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
			ADVERTISE_PAUSE_ASYM);

		bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
		adv1000_reg &= PHY_ALL_1000_SPEED;

		if (bp->advertising & ADVERTISED_10baseT_Half)
			new_adv_reg |= ADVERTISE_10HALF;
		if (bp->advertising & ADVERTISED_10baseT_Full)
			new_adv_reg |= ADVERTISE_10FULL;
		if (bp->advertising & ADVERTISED_100baseT_Half)
			new_adv_reg |= ADVERTISE_100HALF;
		if (bp->advertising & ADVERTISED_100baseT_Full)
			new_adv_reg |= ADVERTISE_100FULL;
		if (bp->advertising & ADVERTISED_1000baseT_Full)
			new_adv1000_reg |= ADVERTISE_1000FULL;
2065

2066 2067 2068 2069 2070 2071 2072 2073
		new_adv_reg |= ADVERTISE_CSMA;

		new_adv_reg |= bnx2_phy_get_pause_adv(bp);

		if ((adv1000_reg != new_adv1000_reg) ||
			(adv_reg != new_adv_reg) ||
			((bmcr & BMCR_ANENABLE) == 0)) {

2074
			bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2075
			bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2076
			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098
				BMCR_ANENABLE);
		}
		else if (bp->link_up) {
			/* Flow ctrl may have changed from auto to forced */
			/* or vice-versa. */

			bnx2_resolve_flow_ctrl(bp);
			bnx2_set_mac_link(bp);
		}
		return 0;
	}

	new_bmcr = 0;
	if (bp->req_line_speed == SPEED_100) {
		new_bmcr |= BMCR_SPEED100;
	}
	if (bp->req_duplex == DUPLEX_FULL) {
		new_bmcr |= BMCR_FULLDPLX;
	}
	if (new_bmcr != bmcr) {
		u32 bmsr;

2099 2100
		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2101

2102 2103
		if (bmsr & BMSR_LSTATUS) {
			/* Force link down */
2104
			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2105 2106 2107 2108
			spin_unlock_bh(&bp->phy_lock);
			msleep(50);
			spin_lock_bh(&bp->phy_lock);

2109 2110
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2111 2112
		}

2113
		bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124

		/* Normally, the new speed is setup after the link has
		 * gone down and up again. In some cases, link will not go
		 * down so we need to set up the new speed here.
		 */
		if (bmsr & BMSR_LSTATUS) {
			bp->line_speed = bp->req_line_speed;
			bp->duplex = bp->req_duplex;
			bnx2_resolve_flow_ctrl(bp);
			bnx2_set_mac_link(bp);
		}
2125 2126 2127
	} else {
		bnx2_resolve_flow_ctrl(bp);
		bnx2_set_mac_link(bp);
2128 2129 2130 2131 2132
	}
	return 0;
}

static int
2133
bnx2_setup_phy(struct bnx2 *bp, u8 port)
2134 2135
__releases(&bp->phy_lock)
__acquires(&bp->phy_lock)
2136 2137 2138 2139
{
	if (bp->loopback == MAC_LOOPBACK)
		return 0;

2140
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2141
		return (bnx2_setup_serdes_phy(bp, port));
2142 2143 2144 2145 2146 2147
	}
	else {
		return (bnx2_setup_copper_phy(bp));
	}
}

2148
static int
2149
bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163
{
	u32 val;

	bp->mii_bmcr = MII_BMCR + 0x10;
	bp->mii_bmsr = MII_BMSR + 0x10;
	bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
	bp->mii_adv = MII_ADVERTISE + 0x10;
	bp->mii_lpa = MII_LPA + 0x10;
	bp->mii_up1 = MII_BNX2_OVER1G_UP1;

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
	bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2164 2165
	if (reset_phy)
		bnx2_reset_phy(bp);
2166 2167 2168 2169 2170 2171 2172 2173 2174 2175

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);

	bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
	val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
	val |= MII_BNX2_SD_1000XCTL1_FIBER;
	bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
	bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2176
	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197
		val |= BCM5708S_UP1_2G5;
	else
		val &= ~BCM5708S_UP1_2G5;
	bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
	bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
	val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
	bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);

	val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
	      MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
	bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);

	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);

	return 0;
}

2198
static int
2199
bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2200 2201 2202
{
	u32 val;

2203 2204
	if (reset_phy)
		bnx2_reset_phy(bp);
2205 2206 2207

	bp->mii_up1 = BCM5708S_UP1;

2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219
	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
	bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);

	bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
	val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
	bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);

	bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
	val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
	bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);

2220
	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2221 2222 2223 2224 2225 2226
		bnx2_read_phy(bp, BCM5708S_UP1, &val);
		val |= BCM5708S_UP1_2G5;
		bnx2_write_phy(bp, BCM5708S_UP1, val);
	}

	if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
M
Michael Chan 已提交
2227 2228
	    (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2229 2230 2231 2232 2233 2234 2235 2236 2237
		/* increase tx signal amplitude */
		bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
			       BCM5708S_BLK_ADDR_TX_MISC);
		bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
		val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
		bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
		bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
	}

2238
	val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2239 2240 2241 2242 2243
	      BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;

	if (val) {
		u32 is_backplane;

2244
		is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256
		if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
				       BCM5708S_BLK_ADDR_TX_MISC);
			bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
				       BCM5708S_BLK_ADDR_DIG);
		}
	}
	return 0;
}

static int
2257
bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2258
{
2259 2260
	if (reset_phy)
		bnx2_reset_phy(bp);
2261

2262
	bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2263

2264 2265
	if (CHIP_NUM(bp) == CHIP_NUM_5706)
        	REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294

	if (bp->dev->mtu > 1500) {
		u32 val;

		/* Set extended packet length bit */
		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);

		bnx2_write_phy(bp, 0x1c, 0x6c00);
		bnx2_read_phy(bp, 0x1c, &val);
		bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
	}
	else {
		u32 val;

		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, val & ~0x4007);

		bnx2_write_phy(bp, 0x1c, 0x6c00);
		bnx2_read_phy(bp, 0x1c, &val);
		bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
	}

	return 0;
}

static int
2295
bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2296
{
2297 2298
	u32 val;

2299 2300
	if (reset_phy)
		bnx2_reset_phy(bp);
2301

2302
	if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2303 2304 2305 2306 2307 2308 2309 2310 2311 2312
		bnx2_write_phy(bp, 0x18, 0x0c00);
		bnx2_write_phy(bp, 0x17, 0x000a);
		bnx2_write_phy(bp, 0x15, 0x310b);
		bnx2_write_phy(bp, 0x17, 0x201f);
		bnx2_write_phy(bp, 0x15, 0x9506);
		bnx2_write_phy(bp, 0x17, 0x401f);
		bnx2_write_phy(bp, 0x15, 0x14e2);
		bnx2_write_phy(bp, 0x18, 0x0400);
	}

2313
	if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2314 2315 2316 2317 2318 2319 2320
		bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
			       MII_BNX2_DSP_EXPAND_REG | 0x8);
		bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
		val &= ~(1 << 8);
		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
	}

2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338
	if (bp->dev->mtu > 1500) {
		/* Set extended packet length bit */
		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, val | 0x4000);

		bnx2_read_phy(bp, 0x10, &val);
		bnx2_write_phy(bp, 0x10, val | 0x1);
	}
	else {
		bnx2_write_phy(bp, 0x18, 0x7);
		bnx2_read_phy(bp, 0x18, &val);
		bnx2_write_phy(bp, 0x18, val & ~0x4007);

		bnx2_read_phy(bp, 0x10, &val);
		bnx2_write_phy(bp, 0x10, val & ~0x1);
	}

2339 2340 2341 2342
	/* ethernet@wirespeed */
	bnx2_write_phy(bp, 0x18, 0x7007);
	bnx2_read_phy(bp, 0x18, &val);
	bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2343 2344 2345 2346 2347
	return 0;
}


static int
2348
bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2349 2350
__releases(&bp->phy_lock)
__acquires(&bp->phy_lock)
2351 2352 2353 2354
{
	u32 val;
	int rc = 0;

2355 2356
	bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
	bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2357

2358 2359
	bp->mii_bmcr = MII_BMCR;
	bp->mii_bmsr = MII_BMSR;
2360
	bp->mii_bmsr1 = MII_BMSR;
2361 2362 2363
	bp->mii_adv = MII_ADVERTISE;
	bp->mii_lpa = MII_LPA;

2364 2365
        REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);

2366
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2367 2368
		goto setup_phy;

2369 2370 2371 2372 2373
	bnx2_read_phy(bp, MII_PHYSID1, &val);
	bp->phy_id = val << 16;
	bnx2_read_phy(bp, MII_PHYSID2, &val);
	bp->phy_id |= val & 0xffff;

2374
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2375
		if (CHIP_NUM(bp) == CHIP_NUM_5706)
2376
			rc = bnx2_init_5706s_phy(bp, reset_phy);
2377
		else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2378
			rc = bnx2_init_5708s_phy(bp, reset_phy);
2379
		else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2380
			rc = bnx2_init_5709s_phy(bp, reset_phy);
2381 2382
	}
	else {
2383
		rc = bnx2_init_copper_phy(bp, reset_phy);
2384 2385
	}

2386 2387 2388
setup_phy:
	if (!rc)
		rc = bnx2_setup_phy(bp, bp->phy_port);
2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405

	return rc;
}

static int
bnx2_set_mac_loopback(struct bnx2 *bp)
{
	u32 mac_mode;

	mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
	mac_mode &= ~BNX2_EMAC_MODE_PORT;
	mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
	REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
	bp->link_up = 1;
	return 0;
}

2406 2407 2408 2409 2410 2411 2412 2413 2414
static int bnx2_test_link(struct bnx2 *);

static int
bnx2_set_phy_loopback(struct bnx2 *bp)
{
	u32 mac_mode;
	int rc, i;

	spin_lock_bh(&bp->phy_lock);
2415
	rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2416 2417 2418 2419 2420 2421 2422 2423
			    BMCR_SPEED1000);
	spin_unlock_bh(&bp->phy_lock);
	if (rc)
		return rc;

	for (i = 0; i < 10; i++) {
		if (bnx2_test_link(bp) == 0)
			break;
2424
		msleep(100);
2425 2426 2427 2428 2429
	}

	mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
	mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
		      BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2430
		      BNX2_EMAC_MODE_25G_MODE);
2431 2432 2433 2434 2435 2436 2437

	mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
	REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
	bp->link_up = 1;
	return 0;
}

2438
static int
2439
bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2440 2441 2442 2443 2444 2445 2446
{
	int i;
	u32 val;

	bp->fw_wr_seq++;
	msg_data |= bp->fw_wr_seq;

2447
	bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2448

2449 2450 2451
	if (!ack)
		return 0;

2452
	/* wait for an acknowledgement. */
2453
	for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2454
		msleep(10);
2455

2456
		val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2457 2458 2459 2460

		if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
			break;
	}
2461 2462
	if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
		return 0;
2463 2464

	/* If we timed out, inform the firmware that this is the case. */
2465 2466 2467 2468
	if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
		if (!silent)
			printk(KERN_ERR PFX "fw sync timeout, reset code = "
					    "%x\n", msg_data);
2469 2470 2471 2472

		msg_data &= ~BNX2_DRV_MSG_CODE;
		msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;

2473
		bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2474 2475 2476 2477

		return -EBUSY;
	}

2478 2479 2480
	if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
		return -EIO;

2481 2482 2483
	return 0;
}

2484 2485 2486 2487 2488 2489 2490 2491 2492
static int
bnx2_init_5709_context(struct bnx2 *bp)
{
	int i, ret = 0;
	u32 val;

	val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
	val |= (BCM_PAGE_BITS - 8) << 16;
	REG_WR(bp, BNX2_CTX_COMMAND, val);
2493 2494 2495 2496 2497 2498 2499 2500 2501
	for (i = 0; i < 10; i++) {
		val = REG_RD(bp, BNX2_CTX_COMMAND);
		if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
			break;
		udelay(2);
	}
	if (val & BNX2_CTX_COMMAND_MEM_INIT)
		return -EBUSY;

2502 2503 2504
	for (i = 0; i < bp->ctx_pages; i++) {
		int j;

2505 2506 2507 2508 2509
		if (bp->ctx_blk[i])
			memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
		else
			return -ENOMEM;

2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531
		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
		       (bp->ctx_blk_mapping[i] & 0xffffffff) |
		       BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
		       (u64) bp->ctx_blk_mapping[i] >> 32);
		REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
		       BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
		for (j = 0; j < 10; j++) {

			val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
			if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
				break;
			udelay(5);
		}
		if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
			ret = -EBUSY;
			break;
		}
	}
	return ret;
}

2532 2533 2534 2535 2536 2537 2538 2539
static void
bnx2_init_context(struct bnx2 *bp)
{
	u32 vcid;

	vcid = 96;
	while (vcid) {
		u32 vcid_addr, pcid_addr, offset;
2540
		int i;
2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560

		vcid--;

		if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
			u32 new_vcid;

			vcid_addr = GET_PCID_ADDR(vcid);
			if (vcid & 0x8) {
				new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
			}
			else {
				new_vcid = vcid;
			}
			pcid_addr = GET_PCID_ADDR(new_vcid);
		}
		else {
	    		vcid_addr = GET_CID_ADDR(vcid);
			pcid_addr = vcid_addr;
		}

2561 2562 2563
		for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
			vcid_addr += (i << PHY_CTX_SHIFT);
			pcid_addr += (i << PHY_CTX_SHIFT);
2564

2565
			REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2566
			REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2567

2568 2569
			/* Zero out the context. */
			for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2570
				bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2571
		}
2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594
	}
}

static int
bnx2_alloc_bad_rbuf(struct bnx2 *bp)
{
	u16 *good_mbuf;
	u32 good_mbuf_cnt;
	u32 val;

	good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
	if (good_mbuf == NULL) {
		printk(KERN_ERR PFX "Failed to allocate memory in "
				    "bnx2_alloc_bad_rbuf\n");
		return -ENOMEM;
	}

	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
		BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);

	good_mbuf_cnt = 0;

	/* Allocate a bunch of mbufs and save the good ones in an array. */
2595
	val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2596
	while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2597 2598
		bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
				BNX2_RBUF_COMMAND_ALLOC_REQ);
2599

2600
		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2601 2602 2603 2604 2605 2606 2607 2608 2609

		val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;

		/* The addresses with Bit 9 set are bad memory blocks. */
		if (!(val & (1 << 9))) {
			good_mbuf[good_mbuf_cnt] = (u16) val;
			good_mbuf_cnt++;
		}

2610
		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2611 2612 2613 2614 2615 2616 2617 2618 2619 2620
	}

	/* Free the good ones back to the mbuf pool thus discarding
	 * all the bad ones. */
	while (good_mbuf_cnt) {
		good_mbuf_cnt--;

		val = good_mbuf[good_mbuf_cnt];
		val = (val << 9) | val | 1;

2621
		bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2622 2623 2624 2625 2626 2627
	}
	kfree(good_mbuf);
	return 0;
}

static void
2628
bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2629 2630 2631 2632 2633
{
	u32 val;

	val = (mac_addr[0] << 8) | mac_addr[1];

2634
	REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2635

2636
	val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2637 2638
		(mac_addr[4] << 8) | mac_addr[5];

2639
	REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2640 2641
}

2642
static inline int
2643
bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2644 2645
{
	dma_addr_t mapping;
2646
	struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2647
	struct rx_bd *rxbd =
2648
		&rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2649 2650 2651 2652 2653 2654
	struct page *page = alloc_page(GFP_ATOMIC);

	if (!page)
		return -ENOMEM;
	mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
			       PCI_DMA_FROMDEVICE);
2655 2656 2657 2658 2659
	if (pci_dma_mapping_error(bp->pdev, mapping)) {
		__free_page(page);
		return -EIO;
	}

2660 2661 2662 2663 2664 2665 2666 2667
	rx_pg->page = page;
	pci_unmap_addr_set(rx_pg, mapping, mapping);
	rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
	rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
	return 0;
}

static void
2668
bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2669
{
2670
	struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682
	struct page *page = rx_pg->page;

	if (!page)
		return;

	pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
		       PCI_DMA_FROMDEVICE);

	__free_page(page);
	rx_pg->page = NULL;
}

2683
static inline int
2684
bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2685 2686
{
	struct sk_buff *skb;
2687
	struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2688
	dma_addr_t mapping;
2689
	struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2690 2691
	unsigned long align;

2692
	skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2693 2694 2695 2696
	if (skb == NULL) {
		return -ENOMEM;
	}

2697 2698
	if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
		skb_reserve(skb, BNX2_RX_ALIGN - align);
2699 2700 2701

	mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
		PCI_DMA_FROMDEVICE);
2702 2703 2704 2705
	if (pci_dma_mapping_error(bp->pdev, mapping)) {
		dev_kfree_skb(skb);
		return -EIO;
	}
2706 2707 2708 2709 2710 2711 2712

	rx_buf->skb = skb;
	pci_unmap_addr_set(rx_buf, mapping, mapping);

	rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
	rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;

2713
	rxr->rx_prod_bseq += bp->rx_buf_use_size;
2714 2715 2716 2717

	return 0;
}

2718
static int
2719
bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2720
{
2721
	struct status_block *sblk = bnapi->status_blk.msi;
2722
	u32 new_link_state, old_link_state;
2723
	int is_set = 1;
2724

2725 2726
	new_link_state = sblk->status_attn_bits & event;
	old_link_state = sblk->status_attn_bits_ack & event;
2727
	if (new_link_state != old_link_state) {
2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738
		if (new_link_state)
			REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
		else
			REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
	} else
		is_set = 0;

	return is_set;
}

static void
2739
bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2740
{
2741 2742 2743
	spin_lock(&bp->phy_lock);

	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2744
		bnx2_set_link(bp);
2745
	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2746 2747
		bnx2_set_remote_link(bp);

2748 2749
	spin_unlock(&bp->phy_lock);

2750 2751
}

2752
static inline u16
2753
bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2754 2755 2756
{
	u16 cons;

2757 2758 2759
	/* Tell compiler that status block fields can change. */
	barrier();
	cons = *bnapi->hw_tx_cons_ptr;
2760
	barrier();
2761 2762 2763 2764 2765
	if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
		cons++;
	return cons;
}

2766 2767
static int
bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2768
{
2769
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2770
	u16 hw_cons, sw_cons, sw_ring_cons;
2771 2772 2773 2774 2775
	int tx_pkt = 0, index;
	struct netdev_queue *txq;

	index = (bnapi - bp->bnx2_napi);
	txq = netdev_get_tx_queue(bp->dev, index);
2776

2777
	hw_cons = bnx2_get_hw_tx_cons(bnapi);
2778
	sw_cons = txr->tx_cons;
2779 2780

	while (sw_cons != hw_cons) {
2781
		struct sw_tx_bd *tx_buf;
2782 2783 2784 2785 2786
		struct sk_buff *skb;
		int i, last;

		sw_ring_cons = TX_RING_IDX(sw_cons);

2787
		tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2788
		skb = tx_buf->skb;
2789

2790 2791 2792
		/* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
		prefetch(&skb->end);

2793
		/* partial BD completions possible with TSO packets */
2794
		if (tx_buf->is_gso) {
2795 2796
			u16 last_idx, last_ring_idx;

2797 2798
			last_idx = sw_cons + tx_buf->nr_frags + 1;
			last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2799 2800 2801 2802 2803 2804 2805
			if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
				last_idx++;
			}
			if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
				break;
			}
		}
2806

2807
		skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
2808 2809

		tx_buf->skb = NULL;
2810
		last = tx_buf->nr_frags;
2811 2812 2813 2814 2815 2816 2817

		for (i = 0; i < last; i++) {
			sw_cons = NEXT_TX_BD(sw_cons);
		}

		sw_cons = NEXT_TX_BD(sw_cons);

2818
		dev_kfree_skb(skb);
2819 2820 2821
		tx_pkt++;
		if (tx_pkt == budget)
			break;
2822

2823 2824
		if (hw_cons == sw_cons)
			hw_cons = bnx2_get_hw_tx_cons(bnapi);
2825 2826
	}

2827 2828
	txr->hw_tx_cons = hw_cons;
	txr->tx_cons = sw_cons;
2829

2830
	/* Need to make the tx_cons update visible to bnx2_start_xmit()
2831
	 * before checking for netif_tx_queue_stopped().  Without the
2832 2833 2834 2835
	 * memory barrier, there is a small possibility that bnx2_start_xmit()
	 * will miss it and cause the queue to be stopped forever.
	 */
	smp_mb();
2836

2837
	if (unlikely(netif_tx_queue_stopped(txq)) &&
2838
		     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2839 2840
		__netif_tx_lock(txq, smp_processor_id());
		if ((netif_tx_queue_stopped(txq)) &&
2841
		    (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2842 2843
			netif_tx_wake_queue(txq);
		__netif_tx_unlock(txq);
2844
	}
2845

2846
	return tx_pkt;
2847 2848
}

2849
static void
2850
bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2851
			struct sk_buff *skb, int count)
2852 2853 2854 2855
{
	struct sw_pg *cons_rx_pg, *prod_rx_pg;
	struct rx_bd *cons_bd, *prod_bd;
	int i;
2856
	u16 hw_prod, prod;
2857
	u16 cons = rxr->rx_pg_cons;
2858

2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879
	cons_rx_pg = &rxr->rx_pg_ring[cons];

	/* The caller was unable to allocate a new page to replace the
	 * last one in the frags array, so we need to recycle that page
	 * and then free the skb.
	 */
	if (skb) {
		struct page *page;
		struct skb_shared_info *shinfo;

		shinfo = skb_shinfo(skb);
		shinfo->nr_frags--;
		page = shinfo->frags[shinfo->nr_frags].page;
		shinfo->frags[shinfo->nr_frags].page = NULL;

		cons_rx_pg->page = page;
		dev_kfree_skb(skb);
	}

	hw_prod = rxr->rx_pg_prod;

2880 2881 2882
	for (i = 0; i < count; i++) {
		prod = RX_PG_RING_IDX(hw_prod);

2883 2884 2885 2886
		prod_rx_pg = &rxr->rx_pg_ring[prod];
		cons_rx_pg = &rxr->rx_pg_ring[cons];
		cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
		prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900

		if (prod != cons) {
			prod_rx_pg->page = cons_rx_pg->page;
			cons_rx_pg->page = NULL;
			pci_unmap_addr_set(prod_rx_pg, mapping,
				pci_unmap_addr(cons_rx_pg, mapping));

			prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
			prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;

		}
		cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
		hw_prod = NEXT_RX_BD(hw_prod);
	}
2901 2902
	rxr->rx_pg_prod = hw_prod;
	rxr->rx_pg_cons = cons;
2903 2904
}

2905
static inline void
2906 2907
bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
		  struct sk_buff *skb, u16 cons, u16 prod)
2908
{
2909 2910 2911
	struct sw_bd *cons_rx_buf, *prod_rx_buf;
	struct rx_bd *cons_bd, *prod_bd;

2912 2913
	cons_rx_buf = &rxr->rx_buf_ring[cons];
	prod_rx_buf = &rxr->rx_buf_ring[prod];
2914 2915 2916

	pci_dma_sync_single_for_device(bp->pdev,
		pci_unmap_addr(cons_rx_buf, mapping),
2917
		BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2918

2919
	rxr->rx_prod_bseq += bp->rx_buf_use_size;
2920

2921
	prod_rx_buf->skb = skb;
2922

2923 2924
	if (cons == prod)
		return;
2925

2926 2927 2928
	pci_unmap_addr_set(prod_rx_buf, mapping,
			pci_unmap_addr(cons_rx_buf, mapping));

2929 2930
	cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
	prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2931 2932
	prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
	prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2933 2934
}

2935
static int
2936
bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2937 2938
	    unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
	    u32 ring_idx)
2939 2940 2941 2942
{
	int err;
	u16 prod = ring_idx & 0xffff;

2943
	err = bnx2_alloc_rx_skb(bp, rxr, prod);
2944
	if (unlikely(err)) {
2945
		bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2946 2947 2948 2949
		if (hdr_len) {
			unsigned int raw_len = len + 4;
			int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;

2950
			bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2951
		}
2952 2953 2954
		return err;
	}

2955
	skb_reserve(skb, BNX2_RX_OFFSET);
2956 2957 2958
	pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
			 PCI_DMA_FROMDEVICE);

2959 2960 2961 2962 2963 2964
	if (hdr_len == 0) {
		skb_put(skb, len);
		return 0;
	} else {
		unsigned int i, frag_len, frag_size, pages;
		struct sw_pg *rx_pg;
2965 2966
		u16 pg_cons = rxr->rx_pg_cons;
		u16 pg_prod = rxr->rx_pg_prod;
2967 2968 2969 2970 2971 2972

		frag_size = len + 4 - hdr_len;
		pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
		skb_put(skb, hdr_len);

		for (i = 0; i < pages; i++) {
2973 2974
			dma_addr_t mapping_old;

2975 2976 2977 2978
			frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
			if (unlikely(frag_len <= 4)) {
				unsigned int tail = 4 - frag_len;

2979 2980 2981
				rxr->rx_pg_cons = pg_cons;
				rxr->rx_pg_prod = pg_prod;
				bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2982
							pages - i);
2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994
				skb->len -= tail;
				if (i == 0) {
					skb->tail -= tail;
				} else {
					skb_frag_t *frag =
						&skb_shinfo(skb)->frags[i - 1];
					frag->size -= tail;
					skb->data_len -= tail;
					skb->truesize -= tail;
				}
				return 0;
			}
2995
			rx_pg = &rxr->rx_pg_ring[pg_cons];
2996

2997 2998 2999 3000
			/* Don't unmap yet.  If we're unable to allocate a new
			 * page, we need to recycle the page and the DMA addr.
			 */
			mapping_old = pci_unmap_addr(rx_pg, mapping);
3001 3002 3003 3004 3005 3006
			if (i == pages - 1)
				frag_len -= 4;

			skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
			rx_pg->page = NULL;

3007 3008
			err = bnx2_alloc_rx_page(bp, rxr,
						 RX_PG_RING_IDX(pg_prod));
3009
			if (unlikely(err)) {
3010 3011 3012
				rxr->rx_pg_cons = pg_cons;
				rxr->rx_pg_prod = pg_prod;
				bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3013
							pages - i);
3014 3015 3016
				return err;
			}

3017 3018 3019
			pci_unmap_page(bp->pdev, mapping_old,
				       PAGE_SIZE, PCI_DMA_FROMDEVICE);

3020 3021 3022 3023 3024 3025 3026 3027
			frag_size -= frag_len;
			skb->data_len += frag_len;
			skb->truesize += frag_len;
			skb->len += frag_len;

			pg_prod = NEXT_RX_BD(pg_prod);
			pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
		}
3028 3029
		rxr->rx_pg_prod = pg_prod;
		rxr->rx_pg_cons = pg_cons;
3030
	}
3031 3032 3033
	return 0;
}

M
Michael Chan 已提交
3034
static inline u16
3035
bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
M
Michael Chan 已提交
3036
{
3037 3038
	u16 cons;

3039 3040 3041
	/* Tell compiler that status block fields can change. */
	barrier();
	cons = *bnapi->hw_rx_cons_ptr;
3042
	barrier();
M
Michael Chan 已提交
3043 3044 3045 3046 3047
	if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
		cons++;
	return cons;
}

3048
static int
3049
bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3050
{
3051
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3052 3053
	u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
	struct l2_fhdr *rx_hdr;
3054
	int rx_pkt = 0, pg_ring_used = 0;
3055

3056
	hw_cons = bnx2_get_hw_rx_cons(bnapi);
3057 3058
	sw_cons = rxr->rx_cons;
	sw_prod = rxr->rx_prod;
3059 3060 3061 3062 3063 3064

	/* Memory barrier necessary as speculative reads of the rx
	 * buffer can be ahead of the index in the status block
	 */
	rmb();
	while (sw_cons != hw_cons) {
3065
		unsigned int len, hdr_len;
3066
		u32 status;
3067 3068
		struct sw_bd *rx_buf;
		struct sk_buff *skb;
3069
		dma_addr_t dma_addr;
3070 3071
		u16 vtag = 0;
		int hw_vlan __maybe_unused = 0;
3072 3073 3074 3075

		sw_ring_cons = RX_RING_IDX(sw_cons);
		sw_ring_prod = RX_RING_IDX(sw_prod);

3076
		rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3077
		skb = rx_buf->skb;
3078 3079 3080 3081 3082 3083

		rx_buf->skb = NULL;

		dma_addr = pci_unmap_addr(rx_buf, mapping);

		pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3084 3085
			BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
			PCI_DMA_FROMDEVICE);
3086 3087

		rx_hdr = (struct l2_fhdr *) skb->data;
3088
		len = rx_hdr->l2_fhdr_pkt_len;
3089
		status = rx_hdr->l2_fhdr_status;
3090

3091 3092 3093 3094 3095 3096 3097 3098 3099
		hdr_len = 0;
		if (status & L2_FHDR_STATUS_SPLIT) {
			hdr_len = rx_hdr->l2_fhdr_ip_xsum;
			pg_ring_used = 1;
		} else if (len > bp->rx_jumbo_thresh) {
			hdr_len = bp->rx_jumbo_thresh;
			pg_ring_used = 1;
		}

3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117
		if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
				       L2_FHDR_ERRORS_PHY_DECODE |
				       L2_FHDR_ERRORS_ALIGNMENT |
				       L2_FHDR_ERRORS_TOO_SHORT |
				       L2_FHDR_ERRORS_GIANT_FRAME))) {

			bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
					  sw_ring_prod);
			if (pg_ring_used) {
				int pages;

				pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;

				bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
			}
			goto next_rx;
		}

3118
		len -= 4;
3119

3120
		if (len <= bp->rx_copy_thresh) {
3121 3122
			struct sk_buff *new_skb;

3123
			new_skb = netdev_alloc_skb(bp->dev, len + 6);
3124
			if (new_skb == NULL) {
3125
				bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3126 3127 3128
						  sw_ring_prod);
				goto next_rx;
			}
3129 3130

			/* aligned copy */
3131
			skb_copy_from_linear_data_offset(skb,
3132 3133 3134
							 BNX2_RX_OFFSET - 6,
				      new_skb->data, len + 6);
			skb_reserve(new_skb, 6);
3135 3136
			skb_put(new_skb, len);

3137
			bnx2_reuse_rx_skb(bp, rxr, skb,
3138 3139 3140
				sw_ring_cons, sw_ring_prod);

			skb = new_skb;
3141
		} else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3142
			   dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3143 3144
			goto next_rx;

3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163
		if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
		    !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
			vtag = rx_hdr->l2_fhdr_vlan_tag;
#ifdef BCM_VLAN
			if (bp->vlgrp)
				hw_vlan = 1;
			else
#endif
			{
				struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
					__skb_push(skb, 4);

				memmove(ve, skb->data + 4, ETH_ALEN * 2);
				ve->h_vlan_proto = htons(ETH_P_8021Q);
				ve->h_vlan_TCI = htons(vtag);
				len += 4;
			}
		}

3164 3165 3166
		skb->protocol = eth_type_trans(skb, bp->dev);

		if ((len > (bp->dev->mtu + ETH_HLEN)) &&
A
Alexey Dobriyan 已提交
3167
			(ntohs(skb->protocol) != 0x8100)) {
3168

3169
			dev_kfree_skb(skb);
3170 3171 3172 3173 3174 3175 3176 3177 3178
			goto next_rx;

		}

		skb->ip_summed = CHECKSUM_NONE;
		if (bp->rx_csum &&
			(status & (L2_FHDR_STATUS_TCP_SEGMENT |
			L2_FHDR_STATUS_UDP_DATAGRAM))) {

3179 3180
			if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
					      L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3181 3182 3183
				skb->ip_summed = CHECKSUM_UNNECESSARY;
		}

3184 3185
		skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);

3186
#ifdef BCM_VLAN
3187 3188
		if (hw_vlan)
			vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200
		else
#endif
			netif_receive_skb(skb);

		rx_pkt++;

next_rx:
		sw_cons = NEXT_RX_BD(sw_cons);
		sw_prod = NEXT_RX_BD(sw_prod);

		if ((rx_pkt == budget))
			break;
3201 3202 3203

		/* Refresh hw_cons to see if there is new work */
		if (sw_cons == hw_cons) {
3204
			hw_cons = bnx2_get_hw_rx_cons(bnapi);
3205 3206
			rmb();
		}
3207
	}
3208 3209
	rxr->rx_cons = sw_cons;
	rxr->rx_prod = sw_prod;
3210

3211
	if (pg_ring_used)
3212
		REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3213

3214
	REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3215

3216
	REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227

	mmiowb();

	return rx_pkt;

}

/* MSI ISR - The only difference between this and the INTx ISR
 * is that the MSI interrupt is always serviced.
 */
static irqreturn_t
3228
bnx2_msi(int irq, void *dev_instance)
3229
{
3230 3231
	struct bnx2_napi *bnapi = dev_instance;
	struct bnx2 *bp = bnapi->bp;
3232

3233
	prefetch(bnapi->status_blk.msi);
3234 3235 3236 3237 3238
	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
		BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
		BNX2_PCICFG_INT_ACK_CMD_MASK_INT);

	/* Return here if interrupt is disabled. */
3239 3240
	if (unlikely(atomic_read(&bp->intr_sem) != 0))
		return IRQ_HANDLED;
3241

3242
	napi_schedule(&bnapi->napi);
3243

3244
	return IRQ_HANDLED;
3245 3246
}

3247 3248 3249
static irqreturn_t
bnx2_msi_1shot(int irq, void *dev_instance)
{
3250 3251
	struct bnx2_napi *bnapi = dev_instance;
	struct bnx2 *bp = bnapi->bp;
3252

3253
	prefetch(bnapi->status_blk.msi);
3254 3255 3256 3257 3258

	/* Return here if interrupt is disabled. */
	if (unlikely(atomic_read(&bp->intr_sem) != 0))
		return IRQ_HANDLED;

3259
	napi_schedule(&bnapi->napi);
3260 3261 3262 3263

	return IRQ_HANDLED;
}

3264
static irqreturn_t
3265
bnx2_interrupt(int irq, void *dev_instance)
3266
{
3267 3268
	struct bnx2_napi *bnapi = dev_instance;
	struct bnx2 *bp = bnapi->bp;
3269
	struct status_block *sblk = bnapi->status_blk.msi;
3270 3271 3272 3273 3274 3275 3276

	/* When using INTx, it is possible for the interrupt to arrive
	 * at the CPU before the status block posted prior to the
	 * interrupt. Reading a register will flush the status block.
	 * When using MSI, the MSI message will always complete after
	 * the status block write.
	 */
3277
	if ((sblk->status_idx == bnapi->last_status_idx) &&
3278 3279
	    (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
	     BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3280
		return IRQ_NONE;
3281 3282 3283 3284 3285

	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
		BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
		BNX2_PCICFG_INT_ACK_CMD_MASK_INT);

3286 3287 3288 3289 3290
	/* Read back to deassert IRQ immediately to avoid too many
	 * spurious interrupts.
	 */
	REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);

3291
	/* Return here if interrupt is shared and is disabled. */
3292 3293
	if (unlikely(atomic_read(&bp->intr_sem) != 0))
		return IRQ_HANDLED;
3294

3295
	if (napi_schedule_prep(&bnapi->napi)) {
3296
		bnapi->last_status_idx = sblk->status_idx;
3297
		__napi_schedule(&bnapi->napi);
3298
	}
3299

3300
	return IRQ_HANDLED;
3301 3302
}

3303
static inline int
3304
bnx2_has_fast_work(struct bnx2_napi *bnapi)
3305
{
3306
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3307
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3308

3309
	if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3310
	    (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3311
		return 1;
3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324
	return 0;
}

#define STATUS_ATTN_EVENTS	(STATUS_ATTN_BITS_LINK_STATE | \
				 STATUS_ATTN_BITS_TIMER_ABORT)

static inline int
bnx2_has_work(struct bnx2_napi *bnapi)
{
	struct status_block *sblk = bnapi->status_blk.msi;

	if (bnx2_has_fast_work(bnapi))
		return 1;
3325

3326 3327 3328 3329 3330
#ifdef BCM_CNIC
	if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
		return 1;
#endif

3331 3332
	if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
	    (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3333 3334 3335 3336 3337
		return 1;

	return 0;
}

3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359
static void
bnx2_chk_missed_msi(struct bnx2 *bp)
{
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
	u32 msi_ctrl;

	if (bnx2_has_work(bnapi)) {
		msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
		if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
			return;

		if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
			REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
			       ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
			REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
			bnx2_msi(bp->irq_tbl[0].vector, bnapi);
		}
	}

	bp->idle_chk_status_idx = bnapi->last_status_idx;
}

3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376
#ifdef BCM_CNIC
static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
{
	struct cnic_ops *c_ops;

	if (!bnapi->cnic_present)
		return;

	rcu_read_lock();
	c_ops = rcu_dereference(bp->cnic_ops);
	if (c_ops)
		bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
						      bnapi->status_blk.msi);
	rcu_read_unlock();
}
#endif

3377
static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3378
{
3379
	struct status_block *sblk = bnapi->status_blk.msi;
3380 3381
	u32 status_attn_bits = sblk->status_attn_bits;
	u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3382

3383 3384
	if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
	    (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3385

3386
		bnx2_phy_int(bp, bnapi);
3387 3388 3389 3390 3391 3392 3393

		/* This is needed to take care of transient status
		 * during link changes.
		 */
		REG_WR(bp, BNX2_HC_COMMAND,
		       bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
		REG_RD(bp, BNX2_HC_COMMAND);
3394
	}
3395 3396 3397 3398 3399 3400 3401
}

static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
			  int work_done, int budget)
{
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3402

3403
	if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3404
		bnx2_tx_int(bp, bnapi, 0);
3405

3406
	if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3407
		work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3408

3409 3410 3411
	return work_done;
}

3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428
static int bnx2_poll_msix(struct napi_struct *napi, int budget)
{
	struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
	struct bnx2 *bp = bnapi->bp;
	int work_done = 0;
	struct status_block_msix *sblk = bnapi->status_blk.msix;

	while (1) {
		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
		if (unlikely(work_done >= budget))
			break;

		bnapi->last_status_idx = sblk->status_idx;
		/* status idx must be read before checking for more work. */
		rmb();
		if (likely(!bnx2_has_fast_work(bnapi))) {

3429
			napi_complete(napi);
3430 3431 3432 3433 3434 3435 3436 3437 3438
			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
			       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
			       bnapi->last_status_idx);
			break;
		}
	}
	return work_done;
}

3439 3440
static int bnx2_poll(struct napi_struct *napi, int budget)
{
3441 3442
	struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
	struct bnx2 *bp = bnapi->bp;
3443
	int work_done = 0;
3444
	struct status_block *sblk = bnapi->status_blk.msi;
3445 3446

	while (1) {
3447 3448
		bnx2_poll_link(bp, bnapi);

3449
		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3450

3451 3452 3453 3454
#ifdef BCM_CNIC
		bnx2_poll_cnic(bp, bnapi);
#endif

3455
		/* bnapi->last_status_idx is used below to tell the hw how
3456 3457 3458
		 * much work has been processed, so we must read it before
		 * checking for more work.
		 */
3459
		bnapi->last_status_idx = sblk->status_idx;
3460 3461 3462 3463

		if (unlikely(work_done >= budget))
			break;

3464
		rmb();
3465
		if (likely(!bnx2_has_work(bnapi))) {
3466
			napi_complete(napi);
3467
			if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3468 3469
				REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
				       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3470
				       bnapi->last_status_idx);
3471
				break;
3472
			}
3473 3474
			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
			       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3475
			       BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3476
			       bnapi->last_status_idx);
3477

3478 3479
			REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
			       BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3480
			       bnapi->last_status_idx);
3481 3482
			break;
		}
3483 3484
	}

3485
	return work_done;
3486 3487
}

H
Herbert Xu 已提交
3488
/* Called with rtnl_lock from vlan functions and also netif_tx_lock
3489 3490 3491 3492 3493
 * from set_multicast.
 */
static void
bnx2_set_rx_mode(struct net_device *dev)
{
M
Michael Chan 已提交
3494
	struct bnx2 *bp = netdev_priv(dev);
3495
	u32 rx_mode, sort_mode;
3496
	struct netdev_hw_addr *ha;
3497 3498
	int i;

3499 3500 3501
	if (!netif_running(dev))
		return;

3502
	spin_lock_bh(&bp->phy_lock);
3503 3504 3505 3506 3507

	rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
				  BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
	sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
#ifdef BCM_VLAN
3508
	if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3509 3510
		rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
#else
3511
	if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
M
Michael Chan 已提交
3512
		rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3513 3514 3515 3516
#endif
	if (dev->flags & IFF_PROMISC) {
		/* Promiscuous mode. */
		rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
M
Michael Chan 已提交
3517 3518
		sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
			     BNX2_RPM_SORT_USER0_PROM_VLAN;
3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554
	}
	else if (dev->flags & IFF_ALLMULTI) {
		for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
			REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
			       0xffffffff);
        	}
		sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
	}
	else {
		/* Accept one or more multicast(s). */
		struct dev_mc_list *mclist;
		u32 mc_filter[NUM_MC_HASH_REGISTERS];
		u32 regidx;
		u32 bit;
		u32 crc;

		memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);

		for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
		     i++, mclist = mclist->next) {

			crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
			bit = crc & 0xff;
			regidx = (bit & 0xe0) >> 5;
			bit &= 0x1f;
			mc_filter[regidx] |= (1 << bit);
		}

		for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
			REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
			       mc_filter[i]);
		}

		sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
	}

3555
	if (dev->uc.count > BNX2_MAX_UNICAST_ADDRESSES) {
3556 3557 3558 3559 3560
		rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
		sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
			     BNX2_RPM_SORT_USER0_PROM_VLAN;
	} else if (!(dev->flags & IFF_PROMISC)) {
		/* Add all entries into to the match filter list */
3561
		i = 0;
3562
		list_for_each_entry(ha, &dev->uc.list, list) {
3563
			bnx2_set_mac_addr(bp, ha->addr,
3564 3565 3566
					  i + BNX2_START_UNICAST_ADDRESS_INDEX);
			sort_mode |= (1 <<
				      (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3567
			i++;
3568 3569 3570 3571
		}

	}

3572 3573 3574 3575 3576 3577 3578 3579 3580
	if (rx_mode != bp->rx_mode) {
		bp->rx_mode = rx_mode;
		REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
	}

	REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
	REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
	REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);

3581
	spin_unlock_bh(&bp->phy_lock);
3582 3583
}

3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612
static int __devinit
check_fw_section(const struct firmware *fw,
		 const struct bnx2_fw_file_section *section,
		 u32 alignment, bool non_empty)
{
	u32 offset = be32_to_cpu(section->offset);
	u32 len = be32_to_cpu(section->len);

	if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
		return -EINVAL;
	if ((non_empty && len == 0) || len > fw->size - offset ||
	    len & (alignment - 1))
		return -EINVAL;
	return 0;
}

static int __devinit
check_mips_fw_entry(const struct firmware *fw,
		    const struct bnx2_mips_fw_file_entry *entry)
{
	if (check_fw_section(fw, &entry->text, 4, true) ||
	    check_fw_section(fw, &entry->data, 4, false) ||
	    check_fw_section(fw, &entry->rodata, 4, false))
		return -EINVAL;
	return 0;
}

static int __devinit
bnx2_request_firmware(struct bnx2 *bp)
3613
{
3614
	const char *mips_fw_file, *rv2p_fw_file;
3615 3616
	const struct bnx2_mips_fw_file *mips_fw;
	const struct bnx2_rv2p_fw_file *rv2p_fw;
3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639
	int rc;

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		mips_fw_file = FW_MIPS_FILE_09;
		rv2p_fw_file = FW_RV2P_FILE_09;
	} else {
		mips_fw_file = FW_MIPS_FILE_06;
		rv2p_fw_file = FW_RV2P_FILE_06;
	}

	rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
	if (rc) {
		printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
		       mips_fw_file);
		return rc;
	}

	rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
	if (rc) {
		printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
		       rv2p_fw_file);
		return rc;
	}
3640 3641 3642 3643 3644 3645 3646 3647
	mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
	rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
	if (bp->mips_firmware->size < sizeof(*mips_fw) ||
	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3648 3649 3650 3651
		printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
		       mips_fw_file);
		return -EINVAL;
	}
3652 3653 3654
	if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680
		printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
		       rv2p_fw_file);
		return -EINVAL;
	}

	return 0;
}

static u32
rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
{
	switch (idx) {
	case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
		rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
		rv2p_code |= RV2P_BD_PAGE_SIZE;
		break;
	}
	return rv2p_code;
}

static int
load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
	     const struct bnx2_rv2p_fw_file_entry *fw_entry)
{
	u32 rv2p_code_len, file_offset;
	__be32 *rv2p_code;
3681
	int i;
3682 3683 3684 3685 3686 3687
	u32 val, cmd, addr;

	rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
	file_offset = be32_to_cpu(fw_entry->rv2p.offset);

	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3688

3689 3690 3691 3692 3693 3694
	if (rv2p_proc == RV2P_PROC1) {
		cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
		addr = BNX2_RV2P_PROC1_ADDR_CMD;
	} else {
		cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
		addr = BNX2_RV2P_PROC2_ADDR_CMD;
3695
	}
3696 3697

	for (i = 0; i < rv2p_code_len; i += 8) {
3698
		REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3699
		rv2p_code++;
3700
		REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3701 3702
		rv2p_code++;

3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720
		val = (i / 8) | cmd;
		REG_WR(bp, addr, val);
	}

	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
	for (i = 0; i < 8; i++) {
		u32 loc, code;

		loc = be32_to_cpu(fw_entry->fixup[i]);
		if (loc && ((loc * 4) < rv2p_code_len)) {
			code = be32_to_cpu(*(rv2p_code + loc - 1));
			REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
			code = be32_to_cpu(*(rv2p_code + loc));
			code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
			REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);

			val = (loc / 2) | cmd;
			REG_WR(bp, addr, val);
3721 3722 3723 3724 3725 3726 3727 3728 3729 3730
		}
	}

	/* Reset the processor, un-stall is done later. */
	if (rv2p_proc == RV2P_PROC1) {
		REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
	}
	else {
		REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
	}
3731 3732

	return 0;
3733 3734
}

3735
static int
3736 3737
load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
	    const struct bnx2_mips_fw_file_entry *fw_entry)
3738
{
3739 3740
	u32 addr, len, file_offset;
	__be32 *data;
3741 3742 3743 3744
	u32 offset;
	u32 val;

	/* Halt the CPU. */
3745
	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3746
	val |= cpu_reg->mode_value_halt;
3747 3748
	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3749 3750

	/* Load the Text area. */
3751 3752 3753 3754
	addr = be32_to_cpu(fw_entry->text.addr);
	len = be32_to_cpu(fw_entry->text.len);
	file_offset = be32_to_cpu(fw_entry->text.offset);
	data = (__be32 *)(bp->mips_firmware->data + file_offset);
3755

3756 3757
	offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
	if (len) {
3758 3759
		int j;

3760 3761
		for (j = 0; j < (len / 4); j++, offset += 4)
			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3762 3763
	}

3764 3765 3766 3767 3768
	/* Load the Data area. */
	addr = be32_to_cpu(fw_entry->data.addr);
	len = be32_to_cpu(fw_entry->data.len);
	file_offset = be32_to_cpu(fw_entry->data.offset);
	data = (__be32 *)(bp->mips_firmware->data + file_offset);
3769

3770 3771
	offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
	if (len) {
3772 3773
		int j;

3774 3775
		for (j = 0; j < (len / 4); j++, offset += 4)
			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3776 3777 3778
	}

	/* Load the Read-Only area. */
3779 3780 3781 3782 3783 3784 3785
	addr = be32_to_cpu(fw_entry->rodata.addr);
	len = be32_to_cpu(fw_entry->rodata.len);
	file_offset = be32_to_cpu(fw_entry->rodata.offset);
	data = (__be32 *)(bp->mips_firmware->data + file_offset);

	offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
	if (len) {
3786 3787
		int j;

3788 3789
		for (j = 0; j < (len / 4); j++, offset += 4)
			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3790 3791 3792
	}

	/* Clear the pre-fetch instruction. */
3793
	bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3794 3795 3796

	val = be32_to_cpu(fw_entry->start_addr);
	bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3797 3798

	/* Start the CPU. */
3799
	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3800
	val &= ~cpu_reg->mode_value_halt;
3801 3802
	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3803 3804

	return 0;
3805 3806
}

3807
static int
3808 3809
bnx2_init_cpus(struct bnx2 *bp)
{
3810 3811 3812 3813 3814
	const struct bnx2_mips_fw_file *mips_fw =
		(const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
	const struct bnx2_rv2p_fw_file *rv2p_fw =
		(const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
	int rc;
3815 3816

	/* Initialize the RV2P processor. */
3817 3818
	load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
	load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3819 3820

	/* Initialize the RX Processor. */
3821
	rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3822 3823 3824
	if (rc)
		goto init_cpu_err;

3825
	/* Initialize the TX Processor. */
3826
	rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3827 3828 3829
	if (rc)
		goto init_cpu_err;

3830
	/* Initialize the TX Patch-up Processor. */
3831
	rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3832 3833 3834
	if (rc)
		goto init_cpu_err;

3835
	/* Initialize the Completion Processor. */
3836
	rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3837 3838 3839
	if (rc)
		goto init_cpu_err;

3840
	/* Initialize the Command Processor. */
3841
	rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3842

3843 3844
init_cpu_err:
	return rc;
3845 3846 3847
}

static int
3848
bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3849 3850 3851 3852 3853 3854
{
	u16 pmcsr;

	pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);

	switch (state) {
3855
	case PCI_D0: {
3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875
		u32 val;

		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
			(pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
			PCI_PM_CTRL_PME_STATUS);

		if (pmcsr & PCI_PM_CTRL_STATE_MASK)
			/* delay required during transition out of D3hot */
			msleep(20);

		val = REG_RD(bp, BNX2_EMAC_MODE);
		val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
		val &= ~BNX2_EMAC_MODE_MPKT;
		REG_WR(bp, BNX2_EMAC_MODE, val);

		val = REG_RD(bp, BNX2_RPM_CONFIG);
		val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
		REG_WR(bp, BNX2_RPM_CONFIG, val);
		break;
	}
3876
	case PCI_D3hot: {
3877 3878 3879 3880 3881 3882 3883 3884 3885 3886
		int i;
		u32 val, wol_msg;

		if (bp->wol) {
			u32 advertising;
			u8 autoneg;

			autoneg = bp->autoneg;
			advertising = bp->advertising;

3887 3888 3889 3890 3891 3892 3893 3894
			if (bp->phy_port == PORT_TP) {
				bp->autoneg = AUTONEG_SPEED;
				bp->advertising = ADVERTISED_10baseT_Half |
					ADVERTISED_10baseT_Full |
					ADVERTISED_100baseT_Half |
					ADVERTISED_100baseT_Full |
					ADVERTISED_Autoneg;
			}
3895

3896 3897 3898
			spin_lock_bh(&bp->phy_lock);
			bnx2_setup_phy(bp, bp->phy_port);
			spin_unlock_bh(&bp->phy_lock);
3899 3900 3901 3902

			bp->autoneg = autoneg;
			bp->advertising = advertising;

3903
			bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3904 3905 3906 3907 3908

			val = REG_RD(bp, BNX2_EMAC_MODE);

			/* Enable port mode. */
			val &= ~BNX2_EMAC_MODE_PORT;
3909
			val |= BNX2_EMAC_MODE_MPKT_RCVD |
3910 3911
			       BNX2_EMAC_MODE_ACPI_RCVD |
			       BNX2_EMAC_MODE_MPKT;
3912 3913 3914 3915 3916 3917 3918
			if (bp->phy_port == PORT_TP)
				val |= BNX2_EMAC_MODE_PORT_MII;
			else {
				val |= BNX2_EMAC_MODE_PORT_GMII;
				if (bp->line_speed == SPEED_2500)
					val |= BNX2_EMAC_MODE_25G_MODE;
			}
3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952

			REG_WR(bp, BNX2_EMAC_MODE, val);

			/* receive all multicast */
			for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
				REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
				       0xffffffff);
			}
			REG_WR(bp, BNX2_EMAC_RX_MODE,
			       BNX2_EMAC_RX_MODE_SORT_MODE);

			val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
			      BNX2_RPM_SORT_USER0_MC_EN;
			REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
			REG_WR(bp, BNX2_RPM_SORT_USER0, val);
			REG_WR(bp, BNX2_RPM_SORT_USER0, val |
			       BNX2_RPM_SORT_USER0_ENA);

			/* Need to enable EMAC and RPM for WOL. */
			REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
			       BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
			       BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
			       BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);

			val = REG_RD(bp, BNX2_RPM_CONFIG);
			val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
			REG_WR(bp, BNX2_RPM_CONFIG, val);

			wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
		}
		else {
			wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
		}

3953
		if (!(bp->flags & BNX2_FLAG_NO_WOL))
3954 3955
			bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
				     1, 0);
3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036 4037 4038

		pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
		if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
		    (CHIP_ID(bp) == CHIP_ID_5706_A1)) {

			if (bp->wol)
				pmcsr |= 3;
		}
		else {
			pmcsr |= 3;
		}
		if (bp->wol) {
			pmcsr |= PCI_PM_CTRL_PME_ENABLE;
		}
		pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
				      pmcsr);

		/* No more memory access after this point until
		 * device is brought back to D0.
		 */
		udelay(50);
		break;
	}
	default:
		return -EINVAL;
	}
	return 0;
}

static int
bnx2_acquire_nvram_lock(struct bnx2 *bp)
{
	u32 val;
	int j;

	/* Request access to the flash interface. */
	REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		val = REG_RD(bp, BNX2_NVM_SW_ARB);
		if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
			break;

		udelay(5);
	}

	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}

static int
bnx2_release_nvram_lock(struct bnx2 *bp)
{
	int j;
	u32 val;

	/* Relinquish nvram interface. */
	REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);

	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		val = REG_RD(bp, BNX2_NVM_SW_ARB);
		if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
			break;

		udelay(5);
	}

	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}


static int
bnx2_enable_nvram_write(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_MISC_CFG);
	REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);

4039
	if (bp->flash_info->flags & BNX2_NV_WREN) {
4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076
		int j;

		REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
		REG_WR(bp, BNX2_NVM_COMMAND,
		       BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);

		for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
			udelay(5);

			val = REG_RD(bp, BNX2_NVM_COMMAND);
			if (val & BNX2_NVM_COMMAND_DONE)
				break;
		}

		if (j >= NVRAM_TIMEOUT_COUNT)
			return -EBUSY;
	}
	return 0;
}

static void
bnx2_disable_nvram_write(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_MISC_CFG);
	REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
}


static void
bnx2_enable_nvram_access(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
	/* Enable both bits, even on read. */
4077
	REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4078 4079 4080 4081 4082 4083 4084 4085 4086 4087
	       val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
}

static void
bnx2_disable_nvram_access(struct bnx2 *bp)
{
	u32 val;

	val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
	/* Disable both bits, even after read. */
4088
	REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4089 4090 4091 4092 4093 4094 4095 4096 4097 4098
		val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
			BNX2_NVM_ACCESS_ENABLE_WR_EN));
}

static int
bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
{
	u32 cmd;
	int j;

4099
	if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141
		/* Buffered flash, no erase needed */
		return 0;

	/* Build an erase command */
	cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
	      BNX2_NVM_COMMAND_DOIT;

	/* Need to clear DONE bit separately. */
	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);

	/* Address of the NVRAM to read from. */
	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);

	/* Issue an erase command. */
	REG_WR(bp, BNX2_NVM_COMMAND, cmd);

	/* Wait for completion. */
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		u32 val;

		udelay(5);

		val = REG_RD(bp, BNX2_NVM_COMMAND);
		if (val & BNX2_NVM_COMMAND_DONE)
			break;
	}

	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}

static int
bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
{
	u32 cmd;
	int j;

	/* Build the command word. */
	cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;

4142 4143
	/* Calculate an offset of a buffered flash, not needed for 5709. */
	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165
		offset = ((offset / bp->flash_info->page_size) <<
			   bp->flash_info->page_bits) +
			  (offset % bp->flash_info->page_size);
	}

	/* Need to clear DONE bit separately. */
	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);

	/* Address of the NVRAM to read from. */
	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);

	/* Issue a read command. */
	REG_WR(bp, BNX2_NVM_COMMAND, cmd);

	/* Wait for completion. */
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		u32 val;

		udelay(5);

		val = REG_RD(bp, BNX2_NVM_COMMAND);
		if (val & BNX2_NVM_COMMAND_DONE) {
A
Al Viro 已提交
4166 4167
			__be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
			memcpy(ret_val, &v, 4);
4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180
			break;
		}
	}
	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}


static int
bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
{
A
Al Viro 已提交
4181 4182
	u32 cmd;
	__be32 val32;
4183 4184 4185 4186 4187
	int j;

	/* Build the command word. */
	cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;

4188 4189
	/* Calculate an offset of a buffered flash, not needed for 5709. */
	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200
		offset = ((offset / bp->flash_info->page_size) <<
			  bp->flash_info->page_bits) +
			 (offset % bp->flash_info->page_size);
	}

	/* Need to clear DONE bit separately. */
	REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);

	memcpy(&val32, val, 4);

	/* Write the data. */
A
Al Viro 已提交
4201
	REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225

	/* Address of the NVRAM to write to. */
	REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);

	/* Issue the write command. */
	REG_WR(bp, BNX2_NVM_COMMAND, cmd);

	/* Wait for completion. */
	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
		udelay(5);

		if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
			break;
	}
	if (j >= NVRAM_TIMEOUT_COUNT)
		return -EBUSY;

	return 0;
}

static int
bnx2_init_nvram(struct bnx2 *bp)
{
	u32 val;
4226
	int j, entry_count, rc = 0;
4227 4228
	struct flash_spec *flash;

4229 4230 4231 4232 4233
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		bp->flash_info = &flash_5709;
		goto get_flash_size;
	}

4234 4235 4236
	/* Determine the selected interface. */
	val = REG_RD(bp, BNX2_NVM_CFG1);

4237
	entry_count = ARRAY_SIZE(flash_table);
4238 4239 4240 4241 4242

	if (val & 0x40000000) {

		/* Flash interface has been reconfigured */
		for (j = 0, flash = &flash_table[0]; j < entry_count;
4243 4244 4245
		     j++, flash++) {
			if ((val & FLASH_BACKUP_STRAP_MASK) ==
			    (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4246 4247 4248 4249 4250 4251
				bp->flash_info = flash;
				break;
			}
		}
	}
	else {
4252
		u32 mask;
4253 4254
		/* Not yet been reconfigured */

4255 4256 4257 4258 4259
		if (val & (1 << 23))
			mask = FLASH_BACKUP_STRAP_MASK;
		else
			mask = FLASH_STRAP_MASK;

4260 4261 4262
		for (j = 0, flash = &flash_table[0]; j < entry_count;
			j++, flash++) {

4263
			if ((val & mask) == (flash->strapping & mask)) {
4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289
				bp->flash_info = flash;

				/* Request access to the flash interface. */
				if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
					return rc;

				/* Enable access to flash interface */
				bnx2_enable_nvram_access(bp);

				/* Reconfigure the flash interface */
				REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
				REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
				REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
				REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);

				/* Disable access to flash interface */
				bnx2_disable_nvram_access(bp);
				bnx2_release_nvram_lock(bp);

				break;
			}
		}
	} /* if (val & 0x40000000) */

	if (j == entry_count) {
		bp->flash_info = NULL;
4290
		printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
M
Michael Chan 已提交
4291
		return -ENODEV;
4292 4293
	}

4294
get_flash_size:
4295
	val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
M
Michael Chan 已提交
4296 4297 4298 4299 4300 4301
	val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
	if (val)
		bp->flash_size = val;
	else
		bp->flash_size = bp->flash_info->total_size;

4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419
	return rc;
}

static int
bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
		int buf_size)
{
	int rc = 0;
	u32 cmd_flags, offset32, len32, extra;

	if (buf_size == 0)
		return 0;

	/* Request access to the flash interface. */
	if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
		return rc;

	/* Enable access to flash interface */
	bnx2_enable_nvram_access(bp);

	len32 = buf_size;
	offset32 = offset;
	extra = 0;

	cmd_flags = 0;

	if (offset32 & 3) {
		u8 buf[4];
		u32 pre_len;

		offset32 &= ~3;
		pre_len = 4 - (offset & 3);

		if (pre_len >= len32) {
			pre_len = len32;
			cmd_flags = BNX2_NVM_COMMAND_FIRST |
				    BNX2_NVM_COMMAND_LAST;
		}
		else {
			cmd_flags = BNX2_NVM_COMMAND_FIRST;
		}

		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);

		if (rc)
			return rc;

		memcpy(ret_buf, buf + (offset & 3), pre_len);

		offset32 += 4;
		ret_buf += pre_len;
		len32 -= pre_len;
	}
	if (len32 & 3) {
		extra = 4 - (len32 & 3);
		len32 = (len32 + 4) & ~3;
	}

	if (len32 == 4) {
		u8 buf[4];

		if (cmd_flags)
			cmd_flags = BNX2_NVM_COMMAND_LAST;
		else
			cmd_flags = BNX2_NVM_COMMAND_FIRST |
				    BNX2_NVM_COMMAND_LAST;

		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);

		memcpy(ret_buf, buf, 4 - extra);
	}
	else if (len32 > 0) {
		u8 buf[4];

		/* Read the first word. */
		if (cmd_flags)
			cmd_flags = 0;
		else
			cmd_flags = BNX2_NVM_COMMAND_FIRST;

		rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);

		/* Advance to the next dword. */
		offset32 += 4;
		ret_buf += 4;
		len32 -= 4;

		while (len32 > 4 && rc == 0) {
			rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);

			/* Advance to the next dword. */
			offset32 += 4;
			ret_buf += 4;
			len32 -= 4;
		}

		if (rc)
			return rc;

		cmd_flags = BNX2_NVM_COMMAND_LAST;
		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);

		memcpy(ret_buf, buf, 4 - extra);
	}

	/* Disable access to flash interface */
	bnx2_disable_nvram_access(bp);

	bnx2_release_nvram_lock(bp);

	return rc;
}

static int
bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
		int buf_size)
{
	u32 written, offset32, len32;
4420
	u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4421 4422 4423 4424 4425 4426 4427 4428 4429 4430
	int rc = 0;
	int align_start, align_end;

	buf = data_buf;
	offset32 = offset;
	len32 = buf_size;
	align_start = align_end = 0;

	if ((align_start = (offset32 & 3))) {
		offset32 &= ~3;
4431 4432 4433
		len32 += align_start;
		if (len32 < 4)
			len32 = 4;
4434 4435 4436 4437 4438
		if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
			return rc;
	}

	if (len32 & 3) {
4439 4440 4441 4442
		align_end = 4 - (len32 & 3);
		len32 += align_end;
		if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
			return rc;
4443 4444 4445
	}

	if (align_start || align_end) {
4446 4447
		align_buf = kmalloc(len32, GFP_KERNEL);
		if (align_buf == NULL)
4448 4449
			return -ENOMEM;
		if (align_start) {
4450
			memcpy(align_buf, start, 4);
4451 4452
		}
		if (align_end) {
4453
			memcpy(align_buf + len32 - 4, end, 4);
4454
		}
4455 4456
		memcpy(align_buf + align_start, data_buf, buf_size);
		buf = align_buf;
4457 4458
	}

4459
	if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4460 4461 4462 4463 4464 4465 4466
		flash_buffer = kmalloc(264, GFP_KERNEL);
		if (flash_buffer == NULL) {
			rc = -ENOMEM;
			goto nvram_write_end;
		}
	}

4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480
	written = 0;
	while ((written < len32) && (rc == 0)) {
		u32 page_start, page_end, data_start, data_end;
		u32 addr, cmd_flags;
		int i;

	        /* Find the page_start addr */
		page_start = offset32 + written;
		page_start -= (page_start % bp->flash_info->page_size);
		/* Find the page_end addr */
		page_end = page_start + bp->flash_info->page_size;
		/* Find the data_start addr */
		data_start = (written == 0) ? offset32 : page_start;
		/* Find the data_end addr */
4481
		data_end = (page_end > offset32 + len32) ?
4482 4483 4484 4485 4486 4487 4488 4489 4490 4491
			(offset32 + len32) : page_end;

		/* Request access to the flash interface. */
		if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
			goto nvram_write_end;

		/* Enable access to flash interface */
		bnx2_enable_nvram_access(bp);

		cmd_flags = BNX2_NVM_COMMAND_FIRST;
4492
		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4493 4494 4495 4496 4497 4498 4499 4500 4501
			int j;

			/* Read the whole page into the buffer
			 * (non-buffer flash only) */
			for (j = 0; j < bp->flash_info->page_size; j += 4) {
				if (j == (bp->flash_info->page_size - 4)) {
					cmd_flags |= BNX2_NVM_COMMAND_LAST;
				}
				rc = bnx2_nvram_read_dword(bp,
4502 4503
					page_start + j,
					&flash_buffer[j],
4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519
					cmd_flags);

				if (rc)
					goto nvram_write_end;

				cmd_flags = 0;
			}
		}

		/* Enable writes to flash interface (unlock write-protect) */
		if ((rc = bnx2_enable_nvram_write(bp)) != 0)
			goto nvram_write_end;

		/* Loop to write back the buffer data from page_start to
		 * data_start */
		i = 0;
4520
		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4521 4522 4523 4524 4525 4526 4527
			/* Erase the page */
			if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
				goto nvram_write_end;

			/* Re-enable the write again for the actual write */
			bnx2_enable_nvram_write(bp);

4528 4529
			for (addr = page_start; addr < data_start;
				addr += 4, i += 4) {
4530

4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541
				rc = bnx2_nvram_write_dword(bp, addr,
					&flash_buffer[i], cmd_flags);

				if (rc != 0)
					goto nvram_write_end;

				cmd_flags = 0;
			}
		}

		/* Loop to write the new data from data_start to data_end */
4542
		for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4543
			if ((addr == page_end - 4) ||
4544
				((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560
				 (addr == data_end - 4))) {

				cmd_flags |= BNX2_NVM_COMMAND_LAST;
			}
			rc = bnx2_nvram_write_dword(bp, addr, buf,
				cmd_flags);

			if (rc != 0)
				goto nvram_write_end;

			cmd_flags = 0;
			buf += 4;
		}

		/* Loop to write back the buffer data from data_end
		 * to page_end */
4561
		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4562 4563
			for (addr = data_end; addr < page_end;
				addr += 4, i += 4) {
4564

4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589
				if (addr == page_end-4) {
					cmd_flags = BNX2_NVM_COMMAND_LAST;
                		}
				rc = bnx2_nvram_write_dword(bp, addr,
					&flash_buffer[i], cmd_flags);

				if (rc != 0)
					goto nvram_write_end;

				cmd_flags = 0;
			}
		}

		/* Disable writes to flash interface (lock write-protect) */
		bnx2_disable_nvram_write(bp);

		/* Disable access to flash interface */
		bnx2_disable_nvram_access(bp);
		bnx2_release_nvram_lock(bp);

		/* Increment written */
		written += data_end - data_start;
	}

nvram_write_end:
4590 4591
	kfree(flash_buffer);
	kfree(align_buf);
4592 4593 4594
	return rc;
}

4595
static void
4596
bnx2_init_fw_cap(struct bnx2 *bp)
4597
{
4598
	u32 val, sig = 0;
4599

4600
	bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4601 4602 4603 4604
	bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;

	if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4605

4606
	val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4607 4608 4609
	if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
		return;

4610 4611 4612 4613 4614 4615 4616 4617 4618
	if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
		sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
	}

	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
	    (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
		u32 link;

4619
		bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4620

4621 4622
		link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
		if (link & BNX2_LINK_STATUS_SERDES_LINK)
4623 4624 4625
			bp->phy_port = PORT_FIBRE;
		else
			bp->phy_port = PORT_TP;
4626

4627 4628
		sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
		       BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4629
	}
4630 4631 4632

	if (netif_running(bp->dev) && sig)
		bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4633 4634
}

4635 4636 4637 4638 4639 4640 4641 4642 4643
static void
bnx2_setup_msix_tbl(struct bnx2 *bp)
{
	REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);

	REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
	REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
}

4644 4645 4646 4647 4648
static int
bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
{
	u32 val;
	int i, rc = 0;
4649
	u8 old_port;
4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660

	/* Wait for the current PCI transaction to complete before
	 * issuing a reset. */
	REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
	       BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
	       BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
	       BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
	       BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
	val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
	udelay(5);

4661
	/* Wait for the firmware to tell us it is ok to issue a reset. */
4662
	bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4663

4664 4665
	/* Deposit a driver reset signature so the firmware knows that
	 * this is a soft reset. */
4666 4667
	bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
		      BNX2_DRV_RESET_SIGNATURE_MAGIC);
4668 4669 4670 4671 4672

	/* Do a dummy read to force the chip to complete all current transaction
	 * before we issue a reset. */
	val = REG_RD(bp, BNX2_MISC_ID);

4673 4674 4675 4676
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
		REG_RD(bp, BNX2_MISC_COMMAND);
		udelay(5);
4677

4678 4679
		val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
		      BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4680

4681
		pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4682

4683 4684 4685 4686 4687 4688 4689 4690
	} else {
		val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
		      BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
		      BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;

		/* Chip reset. */
		REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);

4691 4692 4693 4694
		/* Reading back any register after chip reset will hang the
		 * bus on 5706 A0 and A1.  The msleep below provides plenty
		 * of margin for write posting.
		 */
4695
		if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
A
Arjan van de Ven 已提交
4696 4697
		    (CHIP_ID(bp) == CHIP_ID_5706_A1))
			msleep(20);
4698

4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712
		/* Reset takes approximate 30 usec */
		for (i = 0; i < 10; i++) {
			val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
			if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
				    BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
				break;
			udelay(10);
		}

		if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
			   BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
			printk(KERN_ERR PFX "Chip reset did not complete\n");
			return -EBUSY;
		}
4713 4714 4715 4716 4717 4718 4719 4720 4721 4722
	}

	/* Make sure byte swapping is properly configured. */
	val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
	if (val != 0x01020304) {
		printk(KERN_ERR PFX "Chip not in correct endian mode\n");
		return -ENODEV;
	}

	/* Wait for the firmware to finish its initialization. */
4723
	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4724 4725
	if (rc)
		return rc;
4726

4727
	spin_lock_bh(&bp->phy_lock);
4728
	old_port = bp->phy_port;
4729
	bnx2_init_fw_cap(bp);
4730 4731
	if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
	    old_port != bp->phy_port)
4732 4733 4734
		bnx2_set_default_remote_link(bp);
	spin_unlock_bh(&bp->phy_lock);

4735 4736 4737 4738 4739 4740 4741 4742 4743
	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		/* Adjust the voltage regular to two steps lower.  The default
		 * of this register is 0x0000000e. */
		REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);

		/* Remove bad rbuf memory from the free pool. */
		rc = bnx2_alloc_bad_rbuf(bp);
	}

4744
	if (bp->flags & BNX2_FLAG_USING_MSIX)
4745 4746
		bnx2_setup_msix_tbl(bp);

4747 4748 4749 4750 4751 4752
	return rc;
}

static int
bnx2_init_chip(struct bnx2 *bp)
{
4753
	u32 val, mtu;
4754
	int rc, i;
4755 4756 4757 4758 4759 4760 4761

	/* Make sure the interrupt is not active. */
	REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);

	val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
	      BNX2_DMA_CONFIG_DATA_WORD_SWAP |
#ifdef __BIG_ENDIAN
4762
	      BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4763
#endif
4764
	      BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4765 4766 4767 4768 4769
	      DMA_READ_CHANS << 12 |
	      DMA_WRITE_CHANS << 16;

	val |= (0x2 << 20) | (1 << 11);

4770
	if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4771 4772 4773
		val |= (1 << 23);

	if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4774
	    (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4775 4776 4777 4778 4779 4780 4781 4782 4783 4784
		val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;

	REG_WR(bp, BNX2_DMA_CONFIG, val);

	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		val = REG_RD(bp, BNX2_TDMA_CONFIG);
		val |= BNX2_TDMA_CONFIG_ONE_DMA;
		REG_WR(bp, BNX2_TDMA_CONFIG, val);
	}

4785
	if (bp->flags & BNX2_FLAG_PCIX) {
4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800
		u16 val16;

		pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
				     &val16);
		pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
				      val16 & ~PCI_X_CMD_ERO);
	}

	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
	       BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
	       BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
	       BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);

	/* Initialize context mapping and zero out the quick contexts.  The
	 * context block must have already been enabled. */
4801 4802 4803 4804 4805
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		rc = bnx2_init_5709_context(bp);
		if (rc)
			return rc;
	} else
4806
		bnx2_init_context(bp);
4807

4808 4809 4810
	if ((rc = bnx2_init_cpus(bp)) != 0)
		return rc;

4811 4812
	bnx2_init_nvram(bp);

4813
	bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4814 4815 4816 4817

	val = REG_RD(bp, BNX2_MQ_CONFIG);
	val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
	val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4818 4819 4820 4821 4822
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
		if (CHIP_REV(bp) == CHIP_REV_Ax)
			val |= BNX2_MQ_CONFIG_HALT_DIS;
	}
4823

4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847
	REG_WR(bp, BNX2_MQ_CONFIG, val);

	val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
	REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
	REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);

	val = (BCM_PAGE_BITS - 8) << 24;
	REG_WR(bp, BNX2_RV2P_CONFIG, val);

	/* Configure page size. */
	val = REG_RD(bp, BNX2_TBDR_CONFIG);
	val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
	val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
	REG_WR(bp, BNX2_TBDR_CONFIG, val);

	val = bp->mac_addr[0] +
	      (bp->mac_addr[1] << 8) +
	      (bp->mac_addr[2] << 16) +
	      bp->mac_addr[3] +
	      (bp->mac_addr[4] << 8) +
	      (bp->mac_addr[5] << 16);
	REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);

	/* Program the MTU.  Also include 4 bytes for CRC32. */
4848 4849
	mtu = bp->dev->mtu;
	val = mtu + ETH_HLEN + ETH_FCS_LEN;
4850 4851 4852 4853
	if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
		val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
	REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);

4854 4855 4856 4857 4858 4859 4860
	if (mtu < 1500)
		mtu = 1500;

	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));

4861
	memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4862 4863 4864
	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
		bp->bnx2_napi[i].last_status_idx = 0;

4865 4866
	bp->idle_chk_status_idx = 0xffff;

4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880
	bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;

	/* Set up how to generate a link change interrupt. */
	REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);

	REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
	       (u64) bp->status_blk_mapping & 0xffffffff);
	REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);

	REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
	       (u64) bp->stats_blk_mapping & 0xffffffff);
	REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
	       (u64) bp->stats_blk_mapping >> 32);

4881
	REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899
	       (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);

	REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
	       (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);

	REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
	       (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);

	REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);

	REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);

	REG_WR(bp, BNX2_HC_COM_TICKS,
	       (bp->com_ticks_int << 16) | bp->com_ticks);

	REG_WR(bp, BNX2_HC_CMD_TICKS,
	       (bp->cmd_ticks_int << 16) | bp->cmd_ticks);

4900 4901 4902
	if (CHIP_NUM(bp) == CHIP_NUM_5708)
		REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
	else
4903
		REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4904 4905 4906
	REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */

	if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4907
		val = BNX2_HC_CONFIG_COLLECT_STATS;
4908
	else {
4909 4910
		val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
		      BNX2_HC_CONFIG_COLLECT_STATS;
4911 4912
	}

4913
	if (bp->irq_nvecs > 1) {
4914 4915 4916
		REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
		       BNX2_HC_MSIX_BIT_VECTOR_VAL);

4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928
		val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
	}

	if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
		val |= BNX2_HC_CONFIG_ONE_SHOT;

	REG_WR(bp, BNX2_HC_CONFIG, val);

	for (i = 1; i < bp->irq_nvecs; i++) {
		u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
			   BNX2_HC_SB_CONFIG_1;

4929
		REG_WR(bp, base,
4930
			BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4931
			BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4932 4933
			BNX2_HC_SB_CONFIG_1_ONE_SHOT);

4934
		REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4935 4936 4937
			(bp->tx_quick_cons_trip_int << 16) |
			 bp->tx_quick_cons_trip);

4938
		REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4939 4940
			(bp->tx_ticks_int << 16) | bp->tx_ticks);

4941 4942 4943
		REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
		       (bp->rx_quick_cons_trip_int << 16) |
			bp->rx_quick_cons_trip);
4944

4945 4946 4947
		REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
			(bp->rx_ticks_int << 16) | bp->rx_ticks);
	}
4948

4949 4950 4951
	/* Clear internal stats counters. */
	REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);

4952
	REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4953 4954 4955 4956

	/* Initialize the receive filter. */
	bnx2_set_rx_mode(bp->dev);

4957 4958 4959 4960 4961
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
		val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
		REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
	}
4962
	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4963
			  1, 0);
4964

4965
	REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4966 4967 4968 4969
	REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);

	udelay(20);

4970 4971
	bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);

4972
	return rc;
4973 4974
}

4975 4976 4977 4978
static void
bnx2_clear_ring_states(struct bnx2 *bp)
{
	struct bnx2_napi *bnapi;
4979
	struct bnx2_tx_ring_info *txr;
4980
	struct bnx2_rx_ring_info *rxr;
4981 4982 4983 4984
	int i;

	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
		bnapi = &bp->bnx2_napi[i];
4985
		txr = &bnapi->tx_ring;
4986
		rxr = &bnapi->rx_ring;
4987

4988 4989
		txr->tx_cons = 0;
		txr->hw_tx_cons = 0;
4990 4991 4992 4993 4994
		rxr->rx_prod_bseq = 0;
		rxr->rx_prod = 0;
		rxr->rx_cons = 0;
		rxr->rx_pg_prod = 0;
		rxr->rx_pg_cons = 0;
4995 4996 4997
	}
}

4998
static void
4999
bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5000 5001
{
	u32 val, offset0, offset1, offset2, offset3;
5002
	u32 cid_addr = GET_CID_ADDR(cid);
5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		offset0 = BNX2_L2CTX_TYPE_XI;
		offset1 = BNX2_L2CTX_CMD_TYPE_XI;
		offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
		offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
	} else {
		offset0 = BNX2_L2CTX_TYPE;
		offset1 = BNX2_L2CTX_CMD_TYPE;
		offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
		offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
	}
	val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5016
	bnx2_ctx_wr(bp, cid_addr, offset0, val);
5017 5018

	val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5019
	bnx2_ctx_wr(bp, cid_addr, offset1, val);
5020

5021
	val = (u64) txr->tx_desc_mapping >> 32;
5022
	bnx2_ctx_wr(bp, cid_addr, offset2, val);
5023

5024
	val = (u64) txr->tx_desc_mapping & 0xffffffff;
5025
	bnx2_ctx_wr(bp, cid_addr, offset3, val);
5026
}
5027 5028

static void
5029
bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5030 5031
{
	struct tx_bd *txbd;
5032 5033
	u32 cid = TX_CID;
	struct bnx2_napi *bnapi;
5034
	struct bnx2_tx_ring_info *txr;
5035

5036 5037 5038 5039 5040 5041 5042
	bnapi = &bp->bnx2_napi[ring_num];
	txr = &bnapi->tx_ring;

	if (ring_num == 0)
		cid = TX_CID;
	else
		cid = TX_TSS_CID + ring_num - 1;
5043

5044 5045
	bp->tx_wake_thresh = bp->tx_ring_size / 2;

5046
	txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5047

5048 5049
	txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
	txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5050

5051 5052
	txr->tx_prod = 0;
	txr->tx_prod_bseq = 0;
5053

5054 5055
	txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
	txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5056

5057
	bnx2_init_tx_context(bp, cid, txr);
5058 5059 5060
}

static void
5061 5062
bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
		     int num_rings)
5063 5064
{
	int i;
5065
	struct rx_bd *rxbd;
5066

5067
	for (i = 0; i < num_rings; i++) {
5068
		int j;
5069

5070
		rxbd = &rx_ring[i][0];
5071
		for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5072
			rxbd->rx_bd_len = buf_size;
5073 5074
			rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
		}
5075
		if (i == (num_rings - 1))
5076 5077 5078
			j = 0;
		else
			j = i + 1;
5079 5080
		rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
		rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5081
	}
5082 5083 5084
}

static void
5085
bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5086 5087 5088
{
	int i;
	u16 prod, ring_prod;
5089 5090 5091 5092 5093 5094 5095 5096 5097 5098
	u32 cid, rx_cid_addr, val;
	struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;

	if (ring_num == 0)
		cid = RX_CID;
	else
		cid = RX_RSS_CID + ring_num - 1;

	rx_cid_addr = GET_CID_ADDR(cid);
5099

5100
	bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5101 5102
			     bp->rx_buf_use_size, bp->rx_max_ring);

5103
	bnx2_init_rx_context(bp, cid);
5104 5105 5106 5107 5108 5109

	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
		REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
	}

5110
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5111
	if (bp->rx_pg_ring_size) {
5112 5113
		bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
				     rxr->rx_pg_desc_mapping,
5114 5115
				     PAGE_SIZE, bp->rx_max_pg_ring);
		val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5116 5117
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5118
		       BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5119

5120
		val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5121
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5122

5123
		val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5124
		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5125 5126 5127 5128

		if (CHIP_NUM(bp) == CHIP_NUM_5709)
			REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
	}
5129

5130
	val = (u64) rxr->rx_desc_mapping[0] >> 32;
5131
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5132

5133
	val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5134
	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5135

5136
	ring_prod = prod = rxr->rx_pg_prod;
5137
	for (i = 0; i < bp->rx_pg_ring_size; i++) {
5138
		if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
5139 5140 5141 5142
			break;
		prod = NEXT_RX_BD(prod);
		ring_prod = RX_PG_RING_IDX(prod);
	}
5143
	rxr->rx_pg_prod = prod;
5144

5145
	ring_prod = prod = rxr->rx_prod;
5146
	for (i = 0; i < bp->rx_ring_size; i++) {
5147
		if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
5148 5149 5150 5151
			break;
		prod = NEXT_RX_BD(prod);
		ring_prod = RX_RING_IDX(prod);
	}
5152
	rxr->rx_prod = prod;
5153

5154 5155 5156
	rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
	rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
	rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5157

5158 5159 5160 5161
	REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
	REG_WR16(bp, rxr->rx_bidx_addr, prod);

	REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5162 5163
}

5164 5165 5166 5167
static void
bnx2_init_all_rings(struct bnx2 *bp)
{
	int i;
5168
	u32 val;
5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179

	bnx2_clear_ring_states(bp);

	REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
	for (i = 0; i < bp->num_tx_rings; i++)
		bnx2_init_tx_ring(bp, i);

	if (bp->num_tx_rings > 1)
		REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
		       (TX_TSS_CID << 7));

5180 5181 5182
	REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
	bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);

5183 5184
	for (i = 0; i < bp->num_rx_rings; i++)
		bnx2_init_rx_ring(bp, i);
5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206

	if (bp->num_rx_rings > 1) {
		u32 tbl_32;
		u8 *tbl = (u8 *) &tbl_32;

		bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
				BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);

		for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
			tbl[i % 4] = i % (bp->num_rx_rings - 1);
			if ((i % 4) == 3)
				bnx2_reg_wr_ind(bp,
						BNX2_RXP_SCRATCH_RSS_TBL + i,
						cpu_to_be32(tbl_32));
		}

		val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
		      BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;

		REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);

	}
5207 5208
}

5209
static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5210
{
5211
	u32 max, num_rings = 1;
5212

5213 5214
	while (ring_size > MAX_RX_DESC_CNT) {
		ring_size -= MAX_RX_DESC_CNT;
5215 5216 5217
		num_rings++;
	}
	/* round to next power of 2 */
5218
	max = max_size;
5219 5220 5221 5222 5223 5224
	while ((max & num_rings) == 0)
		max >>= 1;

	if (num_rings != max)
		max <<= 1;

5225 5226 5227 5228 5229 5230
	return max;
}

static void
bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
{
5231
	u32 rx_size, rx_space, jumbo_size;
5232 5233

	/* 8 for CRC and VLAN */
5234
	rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5235

5236 5237 5238
	rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
		sizeof(struct skb_shared_info);

5239
	bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5240 5241 5242
	bp->rx_pg_ring_size = 0;
	bp->rx_max_pg_ring = 0;
	bp->rx_max_pg_ring_idx = 0;
5243
	if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5244 5245 5246 5247 5248 5249 5250 5251 5252 5253
		int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;

		jumbo_size = size * pages;
		if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
			jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;

		bp->rx_pg_ring_size = jumbo_size;
		bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
							MAX_RX_PG_RINGS);
		bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5254
		rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5255 5256
		bp->rx_copy_thresh = 0;
	}
5257 5258 5259 5260

	bp->rx_buf_use_size = rx_size;
	/* hw alignment */
	bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5261
	bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5262 5263
	bp->rx_ring_size = size;
	bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5264 5265 5266
	bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
}

5267 5268 5269 5270 5271
static void
bnx2_free_tx_skbs(struct bnx2 *bp)
{
	int i;

5272 5273 5274 5275
	for (i = 0; i < bp->num_tx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
		int j;
5276

5277
		if (txr->tx_buf_ring == NULL)
5278 5279
			continue;

5280
		for (j = 0; j < TX_DESC_CNT; ) {
5281
			struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5282 5283 5284 5285 5286 5287 5288
			struct sk_buff *skb = tx_buf->skb;

			if (skb == NULL) {
				j++;
				continue;
			}

5289
			skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5290

5291
			tx_buf->skb = NULL;
5292

5293
			j += skb_shinfo(skb)->nr_frags + 1;
5294
			dev_kfree_skb(skb);
5295 5296 5297 5298 5299 5300 5301 5302 5303
		}
	}
}

static void
bnx2_free_rx_skbs(struct bnx2 *bp)
{
	int i;

5304 5305 5306 5307
	for (i = 0; i < bp->num_rx_rings; i++) {
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
		int j;
5308

5309 5310
		if (rxr->rx_buf_ring == NULL)
			return;
5311

5312 5313 5314
		for (j = 0; j < bp->rx_max_ring_idx; j++) {
			struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
			struct sk_buff *skb = rx_buf->skb;
5315

5316 5317
			if (skb == NULL)
				continue;
5318

5319 5320 5321 5322
			pci_unmap_single(bp->pdev,
					 pci_unmap_addr(rx_buf, mapping),
					 bp->rx_buf_use_size,
					 PCI_DMA_FROMDEVICE);
5323

5324 5325 5326 5327 5328 5329
			rx_buf->skb = NULL;

			dev_kfree_skb(skb);
		}
		for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
			bnx2_free_rx_page(bp, rxr, j);
5330 5331 5332 5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343 5344 5345 5346 5347 5348 5349
	}
}

static void
bnx2_free_skbs(struct bnx2 *bp)
{
	bnx2_free_tx_skbs(bp);
	bnx2_free_rx_skbs(bp);
}

static int
bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
{
	int rc;

	rc = bnx2_reset_chip(bp, reset_code);
	bnx2_free_skbs(bp);
	if (rc)
		return rc;

5350 5351 5352
	if ((rc = bnx2_init_chip(bp)) != 0)
		return rc;

5353
	bnx2_init_all_rings(bp);
5354 5355 5356 5357
	return 0;
}

static int
5358
bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5359 5360 5361 5362 5363 5364
{
	int rc;

	if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
		return rc;

5365
	spin_lock_bh(&bp->phy_lock);
5366
	bnx2_init_phy(bp, reset_phy);
5367
	bnx2_set_link(bp);
5368 5369
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
		bnx2_remote_phy_event(bp);
5370
	spin_unlock_bh(&bp->phy_lock);
5371 5372 5373
	return 0;
}

5374 5375 5376 5377 5378 5379 5380 5381 5382 5383 5384 5385 5386 5387 5388
static int
bnx2_shutdown_chip(struct bnx2 *bp)
{
	u32 reset_code;

	if (bp->flags & BNX2_FLAG_NO_WOL)
		reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
	else if (bp->wol)
		reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
	else
		reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;

	return bnx2_reset_chip(bp, reset_code);
}

5389 5390 5391 5392
static int
bnx2_test_registers(struct bnx2 *bp)
{
	int ret;
5393
	int i, is_5709;
5394
	static const struct {
5395 5396
		u16   offset;
		u16   flags;
5397
#define BNX2_FL_NOT_5709	1
5398 5399 5400 5401 5402 5403 5404
		u32   rw_mask;
		u32   ro_mask;
	} reg_tbl[] = {
		{ 0x006c, 0, 0x00000000, 0x0000003f },
		{ 0x0090, 0, 0xffffffff, 0x00000000 },
		{ 0x0094, 0, 0x00000000, 0x00000000 },

5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424
		{ 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
		{ 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
		{ 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
		{ 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
		{ 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
		{ 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },

		{ 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
		{ 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
		{ 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
		{ 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
		{ 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },

		{ 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
		{ 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
		{ 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5425 5426

		{ 0x1000, 0, 0x00000000, 0x00000001 },
5427
		{ 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5428 5429 5430 5431

		{ 0x1408, 0, 0x01c00800, 0x00000000 },
		{ 0x149c, 0, 0x8000ffff, 0x00000000 },
		{ 0x14a8, 0, 0x00000000, 0x000001ff },
5432
		{ 0x14ac, 0, 0x0fffffff, 0x10000000 },
5433 5434 5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445 5446 5447 5448 5449 5450 5451 5452 5453 5454 5455 5456 5457 5458 5459 5460 5461 5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509
		{ 0x14b0, 0, 0x00000002, 0x00000001 },
		{ 0x14b8, 0, 0x00000000, 0x00000000 },
		{ 0x14c0, 0, 0x00000000, 0x00000009 },
		{ 0x14c4, 0, 0x00003fff, 0x00000000 },
		{ 0x14cc, 0, 0x00000000, 0x00000001 },
		{ 0x14d0, 0, 0xffffffff, 0x00000000 },

		{ 0x1800, 0, 0x00000000, 0x00000001 },
		{ 0x1804, 0, 0x00000000, 0x00000003 },

		{ 0x2800, 0, 0x00000000, 0x00000001 },
		{ 0x2804, 0, 0x00000000, 0x00003f01 },
		{ 0x2808, 0, 0x0f3f3f03, 0x00000000 },
		{ 0x2810, 0, 0xffff0000, 0x00000000 },
		{ 0x2814, 0, 0xffff0000, 0x00000000 },
		{ 0x2818, 0, 0xffff0000, 0x00000000 },
		{ 0x281c, 0, 0xffff0000, 0x00000000 },
		{ 0x2834, 0, 0xffffffff, 0x00000000 },
		{ 0x2840, 0, 0x00000000, 0xffffffff },
		{ 0x2844, 0, 0x00000000, 0xffffffff },
		{ 0x2848, 0, 0xffffffff, 0x00000000 },
		{ 0x284c, 0, 0xf800f800, 0x07ff07ff },

		{ 0x2c00, 0, 0x00000000, 0x00000011 },
		{ 0x2c04, 0, 0x00000000, 0x00030007 },

		{ 0x3c00, 0, 0x00000000, 0x00000001 },
		{ 0x3c04, 0, 0x00000000, 0x00070000 },
		{ 0x3c08, 0, 0x00007f71, 0x07f00000 },
		{ 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
		{ 0x3c10, 0, 0xffffffff, 0x00000000 },
		{ 0x3c14, 0, 0x00000000, 0xffffffff },
		{ 0x3c18, 0, 0x00000000, 0xffffffff },
		{ 0x3c1c, 0, 0xfffff000, 0x00000000 },
		{ 0x3c20, 0, 0xffffff00, 0x00000000 },

		{ 0x5004, 0, 0x00000000, 0x0000007f },
		{ 0x5008, 0, 0x0f0007ff, 0x00000000 },

		{ 0x5c00, 0, 0x00000000, 0x00000001 },
		{ 0x5c04, 0, 0x00000000, 0x0003000f },
		{ 0x5c08, 0, 0x00000003, 0x00000000 },
		{ 0x5c0c, 0, 0x0000fff8, 0x00000000 },
		{ 0x5c10, 0, 0x00000000, 0xffffffff },
		{ 0x5c80, 0, 0x00000000, 0x0f7113f1 },
		{ 0x5c84, 0, 0x00000000, 0x0000f333 },
		{ 0x5c88, 0, 0x00000000, 0x00077373 },
		{ 0x5c8c, 0, 0x00000000, 0x0007f737 },

		{ 0x6808, 0, 0x0000ff7f, 0x00000000 },
		{ 0x680c, 0, 0xffffffff, 0x00000000 },
		{ 0x6810, 0, 0xffffffff, 0x00000000 },
		{ 0x6814, 0, 0xffffffff, 0x00000000 },
		{ 0x6818, 0, 0xffffffff, 0x00000000 },
		{ 0x681c, 0, 0xffffffff, 0x00000000 },
		{ 0x6820, 0, 0x00ff00ff, 0x00000000 },
		{ 0x6824, 0, 0x00ff00ff, 0x00000000 },
		{ 0x6828, 0, 0x00ff00ff, 0x00000000 },
		{ 0x682c, 0, 0x03ff03ff, 0x00000000 },
		{ 0x6830, 0, 0x03ff03ff, 0x00000000 },
		{ 0x6834, 0, 0x03ff03ff, 0x00000000 },
		{ 0x6838, 0, 0x03ff03ff, 0x00000000 },
		{ 0x683c, 0, 0x0000ffff, 0x00000000 },
		{ 0x6840, 0, 0x00000ff0, 0x00000000 },
		{ 0x6844, 0, 0x00ffff00, 0x00000000 },
		{ 0x684c, 0, 0xffffffff, 0x00000000 },
		{ 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
		{ 0x6908, 0, 0x00000000, 0x0001ff0f },
		{ 0x690c, 0, 0x00000000, 0x0ffe00f0 },

		{ 0xffff, 0, 0x00000000, 0x00000000 },
	};

	ret = 0;
5510 5511 5512 5513
	is_5709 = 0;
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		is_5709 = 1;

5514 5515
	for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
		u32 offset, rw_mask, ro_mask, save_val, val;
5516 5517 5518 5519
		u16 flags = reg_tbl[i].flags;

		if (is_5709 && (flags & BNX2_FL_NOT_5709))
			continue;
5520 5521 5522 5523 5524

		offset = (u32) reg_tbl[i].offset;
		rw_mask = reg_tbl[i].rw_mask;
		ro_mask = reg_tbl[i].ro_mask;

5525
		save_val = readl(bp->regview + offset);
5526

5527
		writel(0, bp->regview + offset);
5528

5529
		val = readl(bp->regview + offset);
5530 5531 5532 5533 5534 5535 5536 5537
		if ((val & rw_mask) != 0) {
			goto reg_test_err;
		}

		if ((val & ro_mask) != (save_val & ro_mask)) {
			goto reg_test_err;
		}

5538
		writel(0xffffffff, bp->regview + offset);
5539

5540
		val = readl(bp->regview + offset);
5541 5542 5543 5544 5545 5546 5547 5548
		if ((val & rw_mask) != rw_mask) {
			goto reg_test_err;
		}

		if ((val & ro_mask) != (save_val & ro_mask)) {
			goto reg_test_err;
		}

5549
		writel(save_val, bp->regview + offset);
5550 5551 5552
		continue;

reg_test_err:
5553
		writel(save_val, bp->regview + offset);
5554 5555 5556 5557 5558 5559 5560 5561 5562
		ret = -ENODEV;
		break;
	}
	return ret;
}

static int
bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
{
5563
	static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5564 5565 5566 5567 5568 5569 5570 5571
		0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
	int i;

	for (i = 0; i < sizeof(test_pattern) / 4; i++) {
		u32 offset;

		for (offset = 0; offset < size; offset += 4) {

5572
			bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5573

5574
			if (bnx2_reg_rd_ind(bp, start + offset) !=
5575 5576 5577 5578 5579 5580 5581 5582 5583 5584 5585 5586 5587
				test_pattern[i]) {
				return -ENODEV;
			}
		}
	}
	return 0;
}

static int
bnx2_test_memory(struct bnx2 *bp)
{
	int ret = 0;
	int i;
5588
	static struct mem_entry {
5589 5590
		u32   offset;
		u32   len;
5591
	} mem_tbl_5706[] = {
5592
		{ 0x60000,  0x4000 },
5593
		{ 0xa0000,  0x3000 },
5594 5595 5596 5597 5598
		{ 0xe0000,  0x4000 },
		{ 0x120000, 0x4000 },
		{ 0x1a0000, 0x4000 },
		{ 0x160000, 0x4000 },
		{ 0xffffffff, 0    },
5599 5600 5601 5602 5603 5604 5605 5606
	},
	mem_tbl_5709[] = {
		{ 0x60000,  0x4000 },
		{ 0xa0000,  0x3000 },
		{ 0xe0000,  0x4000 },
		{ 0x120000, 0x4000 },
		{ 0x1a0000, 0x4000 },
		{ 0xffffffff, 0    },
5607
	};
5608 5609 5610 5611 5612 5613
	struct mem_entry *mem_tbl;

	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		mem_tbl = mem_tbl_5709;
	else
		mem_tbl = mem_tbl_5706;
5614 5615 5616 5617 5618 5619 5620

	for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
		if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
			mem_tbl[i].len)) != 0) {
			return ret;
		}
	}
5621

5622 5623 5624
	return ret;
}

5625 5626 5627
#define BNX2_MAC_LOOPBACK	0
#define BNX2_PHY_LOOPBACK	1

5628
static int
5629
bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5630 5631 5632 5633
{
	unsigned int pkt_size, num_pkts, i;
	struct sk_buff *skb, *rx_skb;
	unsigned char *packet;
5634
	u16 rx_start_idx, rx_idx;
5635 5636 5637 5638 5639
	dma_addr_t map;
	struct tx_bd *txbd;
	struct sw_bd *rx_buf;
	struct l2_fhdr *rx_hdr;
	int ret = -ENODEV;
5640
	struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5641
	struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5642
	struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5643 5644

	tx_napi = bnapi;
5645

5646
	txr = &tx_napi->tx_ring;
5647
	rxr = &bnapi->rx_ring;
5648 5649 5650 5651 5652
	if (loopback_mode == BNX2_MAC_LOOPBACK) {
		bp->loopback = MAC_LOOPBACK;
		bnx2_set_mac_loopback(bp);
	}
	else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5653
		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5654 5655
			return 0;

5656
		bp->loopback = PHY_LOOPBACK;
5657 5658 5659 5660
		bnx2_set_phy_loopback(bp);
	}
	else
		return -EINVAL;
5661

5662
	pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5663
	skb = netdev_alloc_skb(bp->dev, pkt_size);
5664 5665
	if (!skb)
		return -ENOMEM;
5666
	packet = skb_put(skb, pkt_size);
5667
	memcpy(packet, bp->dev->dev_addr, 6);
5668 5669 5670 5671
	memset(packet + 6, 0x0, 8);
	for (i = 14; i < pkt_size; i++)
		packet[i] = (unsigned char) (i & 0xff);

5672 5673 5674 5675
	if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
		dev_kfree_skb(skb);
		return -EIO;
	}
5676
	map = skb_shinfo(skb)->dma_head;
5677

5678 5679 5680
	REG_WR(bp, BNX2_HC_COMMAND,
	       bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);

5681 5682 5683
	REG_RD(bp, BNX2_HC_COMMAND);

	udelay(5);
5684
	rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5685 5686 5687

	num_pkts = 0;

5688
	txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5689 5690 5691 5692 5693 5694 5695

	txbd->tx_bd_haddr_hi = (u64) map >> 32;
	txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
	txbd->tx_bd_mss_nbytes = pkt_size;
	txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;

	num_pkts++;
5696 5697
	txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
	txr->tx_prod_bseq += pkt_size;
5698

5699 5700
	REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
	REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5701 5702 5703

	udelay(100);

5704 5705 5706
	REG_WR(bp, BNX2_HC_COMMAND,
	       bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);

5707 5708 5709 5710
	REG_RD(bp, BNX2_HC_COMMAND);

	udelay(5);

5711
	skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5712
	dev_kfree_skb(skb);
5713

5714
	if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5715 5716
		goto loopback_test_done;

5717
	rx_idx = bnx2_get_hw_rx_cons(bnapi);
5718 5719 5720 5721
	if (rx_idx != rx_start_idx + num_pkts) {
		goto loopback_test_done;
	}

5722
	rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5723 5724 5725
	rx_skb = rx_buf->skb;

	rx_hdr = (struct l2_fhdr *) rx_skb->data;
5726
	skb_reserve(rx_skb, BNX2_RX_OFFSET);
5727 5728 5729 5730 5731

	pci_dma_sync_single_for_cpu(bp->pdev,
		pci_unmap_addr(rx_buf, mapping),
		bp->rx_buf_size, PCI_DMA_FROMDEVICE);

5732
	if (rx_hdr->l2_fhdr_status &
5733 5734 5735 5736 5737 5738 5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754 5755 5756 5757 5758
		(L2_FHDR_ERRORS_BAD_CRC |
		L2_FHDR_ERRORS_PHY_DECODE |
		L2_FHDR_ERRORS_ALIGNMENT |
		L2_FHDR_ERRORS_TOO_SHORT |
		L2_FHDR_ERRORS_GIANT_FRAME)) {

		goto loopback_test_done;
	}

	if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
		goto loopback_test_done;
	}

	for (i = 14; i < pkt_size; i++) {
		if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
			goto loopback_test_done;
		}
	}

	ret = 0;

loopback_test_done:
	bp->loopback = 0;
	return ret;
}

5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772 5773
#define BNX2_MAC_LOOPBACK_FAILED	1
#define BNX2_PHY_LOOPBACK_FAILED	2
#define BNX2_LOOPBACK_FAILED		(BNX2_MAC_LOOPBACK_FAILED |	\
					 BNX2_PHY_LOOPBACK_FAILED)

static int
bnx2_test_loopback(struct bnx2 *bp)
{
	int rc = 0;

	if (!netif_running(bp->dev))
		return BNX2_LOOPBACK_FAILED;

	bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
	spin_lock_bh(&bp->phy_lock);
5774
	bnx2_init_phy(bp, 1);
5775 5776 5777 5778 5779 5780 5781 5782
	spin_unlock_bh(&bp->phy_lock);
	if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
		rc |= BNX2_MAC_LOOPBACK_FAILED;
	if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
		rc |= BNX2_PHY_LOOPBACK_FAILED;
	return rc;
}

5783 5784 5785 5786 5787 5788
#define NVRAM_SIZE 0x200
#define CRC32_RESIDUAL 0xdebb20e3

static int
bnx2_test_nvram(struct bnx2 *bp)
{
A
Al Viro 已提交
5789
	__be32 buf[NVRAM_SIZE / 4];
5790 5791 5792 5793 5794 5795 5796 5797 5798 5799 5800 5801 5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818 5819 5820 5821 5822 5823 5824 5825
	u8 *data = (u8 *) buf;
	int rc = 0;
	u32 magic, csum;

	if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
		goto test_nvram_done;

        magic = be32_to_cpu(buf[0]);
	if (magic != 0x669955aa) {
		rc = -ENODEV;
		goto test_nvram_done;
	}

	if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
		goto test_nvram_done;

	csum = ether_crc_le(0x100, data);
	if (csum != CRC32_RESIDUAL) {
		rc = -ENODEV;
		goto test_nvram_done;
	}

	csum = ether_crc_le(0x100, data + 0x100);
	if (csum != CRC32_RESIDUAL) {
		rc = -ENODEV;
	}

test_nvram_done:
	return rc;
}

static int
bnx2_test_link(struct bnx2 *bp)
{
	u32 bmsr;

5826 5827 5828
	if (!netif_running(bp->dev))
		return -ENODEV;

5829
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5830 5831 5832 5833
		if (bp->link_up)
			return 0;
		return -ENODEV;
	}
5834
	spin_lock_bh(&bp->phy_lock);
5835 5836 5837 5838
	bnx2_enable_bmsr1(bp);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
	bnx2_disable_bmsr1(bp);
5839
	spin_unlock_bh(&bp->phy_lock);
5840

5841 5842 5843 5844 5845 5846 5847 5848 5849 5850 5851 5852 5853 5854 5855 5856 5857 5858
	if (bmsr & BMSR_LSTATUS) {
		return 0;
	}
	return -ENODEV;
}

static int
bnx2_test_intr(struct bnx2 *bp)
{
	int i;
	u16 status_idx;

	if (!netif_running(bp->dev))
		return -ENODEV;

	status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;

	/* This register is not touched during run-time. */
5859
	REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5860 5861 5862 5863 5864 5865 5866 5867 5868 5869 5870 5871 5872 5873 5874 5875 5876
	REG_RD(bp, BNX2_HC_COMMAND);

	for (i = 0; i < 10; i++) {
		if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
			status_idx) {

			break;
		}

		msleep_interruptible(10);
	}
	if (i < 10)
		return 0;

	return -ENODEV;
}

5877
/* Determining link for parallel detection. */
5878 5879 5880 5881 5882
static int
bnx2_5706_serdes_has_link(struct bnx2 *bp)
{
	u32 mode_ctl, an_dbg, exp;

5883 5884 5885
	if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
		return 0;

5886 5887 5888 5889 5890 5891 5892 5893 5894 5895
	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);

	if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
		return 0;

	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);

5896
	if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5897 5898 5899 5900 5901 5902 5903 5904 5905 5906 5907 5908
		return 0;

	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);

	if (exp & MII_EXPAND_REG1_RUDI_C)	/* receiving CONFIG */
		return 0;

	return 1;
}

5909
static void
5910
bnx2_5706_serdes_timer(struct bnx2 *bp)
5911
{
5912 5913
	int check_link = 1;

5914
	spin_lock(&bp->phy_lock);
5915
	if (bp->serdes_an_pending) {
5916
		bp->serdes_an_pending--;
5917 5918
		check_link = 0;
	} else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5919
		u32 bmcr;
5920

5921
		bp->current_interval = BNX2_TIMER_INTERVAL;
5922

5923
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5924

5925
		if (bmcr & BMCR_ANENABLE) {
5926
			if (bnx2_5706_serdes_has_link(bp)) {
5927 5928
				bmcr &= ~BMCR_ANENABLE;
				bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5929
				bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5930
				bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5931
			}
5932
		}
5933 5934
	}
	else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5935
		 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5936
		u32 phy2;
5937

5938 5939 5940 5941
		bnx2_write_phy(bp, 0x17, 0x0f01);
		bnx2_read_phy(bp, 0x15, &phy2);
		if (phy2 & 0x20) {
			u32 bmcr;
5942

5943
			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5944
			bmcr |= BMCR_ANENABLE;
5945
			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5946

5947
			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5948 5949
		}
	} else
5950
		bp->current_interval = BNX2_TIMER_INTERVAL;
5951

5952
	if (check_link) {
5953 5954 5955 5956 5957 5958
		u32 val;

		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);

5959 5960 5961 5962 5963 5964 5965 5966
		if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
			if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
				bnx2_5706s_force_link_dn(bp, 1);
				bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
			} else
				bnx2_set_link(bp);
		} else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
			bnx2_set_link(bp);
5967
	}
5968 5969
	spin_unlock(&bp->phy_lock);
}
5970

5971 5972 5973
static void
bnx2_5708_serdes_timer(struct bnx2 *bp)
{
5974
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5975 5976
		return;

5977
	if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5978 5979 5980
		bp->serdes_an_pending = 0;
		return;
	}
5981

5982 5983 5984 5985 5986
	spin_lock(&bp->phy_lock);
	if (bp->serdes_an_pending)
		bp->serdes_an_pending--;
	else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
		u32 bmcr;
5987

5988
		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5989
		if (bmcr & BMCR_ANENABLE) {
5990
			bnx2_enable_forced_2g5(bp);
5991
			bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
5992
		} else {
5993
			bnx2_disable_forced_2g5(bp);
5994
			bp->serdes_an_pending = 2;
5995
			bp->current_interval = BNX2_TIMER_INTERVAL;
5996 5997
		}

5998
	} else
5999
		bp->current_interval = BNX2_TIMER_INTERVAL;
6000

6001 6002 6003
	spin_unlock(&bp->phy_lock);
}

6004 6005 6006 6007
static void
bnx2_timer(unsigned long data)
{
	struct bnx2 *bp = (struct bnx2 *) data;
6008

6009 6010
	if (!netif_running(bp->dev))
		return;
6011

6012 6013
	if (atomic_read(&bp->intr_sem) != 0)
		goto bnx2_restart_timer;
6014

6015 6016 6017 6018
	if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
	     BNX2_FLAG_USING_MSI)
		bnx2_chk_missed_msi(bp);

6019
	bnx2_send_heart_beat(bp);
6020

6021 6022
	bp->stats_blk->stat_FwRxDrop =
		bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6023

6024 6025 6026 6027 6028
	/* workaround occasional corrupted counters */
	if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
		REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
					    BNX2_HC_COMMAND_STATS_NOW);

6029
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6030 6031
		if (CHIP_NUM(bp) == CHIP_NUM_5706)
			bnx2_5706_serdes_timer(bp);
6032
		else
6033
			bnx2_5708_serdes_timer(bp);
6034 6035 6036
	}

bnx2_restart_timer:
6037
	mod_timer(&bp->timer, jiffies + bp->current_interval);
6038 6039
}

6040 6041 6042
static int
bnx2_request_irq(struct bnx2 *bp)
{
6043
	unsigned long flags;
6044 6045
	struct bnx2_irq *irq;
	int rc = 0, i;
6046

6047
	if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6048 6049 6050
		flags = 0;
	else
		flags = IRQF_SHARED;
6051 6052 6053

	for (i = 0; i < bp->irq_nvecs; i++) {
		irq = &bp->irq_tbl[i];
6054
		rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6055
				 &bp->bnx2_napi[i]);
6056 6057 6058 6059
		if (rc)
			break;
		irq->requested = 1;
	}
6060 6061 6062 6063 6064 6065
	return rc;
}

static void
bnx2_free_irq(struct bnx2 *bp)
{
6066 6067
	struct bnx2_irq *irq;
	int i;
6068

6069 6070 6071
	for (i = 0; i < bp->irq_nvecs; i++) {
		irq = &bp->irq_tbl[i];
		if (irq->requested)
6072
			free_irq(irq->vector, &bp->bnx2_napi[i]);
6073
		irq->requested = 0;
6074
	}
6075
	if (bp->flags & BNX2_FLAG_USING_MSI)
6076
		pci_disable_msi(bp->pdev);
6077
	else if (bp->flags & BNX2_FLAG_USING_MSIX)
6078 6079
		pci_disable_msix(bp->pdev);

6080
	bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6081 6082 6083
}

static void
6084
bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6085
{
6086 6087
	int i, rc;
	struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6088 6089
	struct net_device *dev = bp->dev;
	const int len = sizeof(bp->irq_tbl[0].name);
6090

6091 6092 6093 6094
	bnx2_setup_msix_tbl(bp);
	REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
	REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
	REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6095 6096 6097 6098 6099 6100 6101 6102 6103 6104

	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
		msix_ent[i].entry = i;
		msix_ent[i].vector = 0;
	}

	rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
	if (rc != 0)
		return;

6105
	bp->irq_nvecs = msix_vecs;
6106
	bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6107
	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6108
		bp->irq_tbl[i].vector = msix_ent[i].vector;
6109 6110 6111
		snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
		bp->irq_tbl[i].handler = bnx2_msi_1shot;
	}
6112 6113 6114 6115 6116
}

static void
bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
{
6117
	int cpus = num_online_cpus();
6118
	int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6119

6120 6121
	bp->irq_tbl[0].handler = bnx2_interrupt;
	strcpy(bp->irq_tbl[0].name, bp->dev->name);
6122 6123 6124
	bp->irq_nvecs = 1;
	bp->irq_tbl[0].vector = bp->pdev->irq;

6125 6126
	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
		bnx2_enable_msix(bp, msix_vecs);
6127

6128 6129
	if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
	    !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6130
		if (pci_enable_msi(bp->pdev) == 0) {
6131
			bp->flags |= BNX2_FLAG_USING_MSI;
6132
			if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6133
				bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6134 6135 6136
				bp->irq_tbl[0].handler = bnx2_msi_1shot;
			} else
				bp->irq_tbl[0].handler = bnx2_msi;
6137 6138

			bp->irq_tbl[0].vector = bp->pdev->irq;
6139 6140
		}
	}
6141 6142 6143 6144

	bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
	bp->dev->real_num_tx_queues = bp->num_tx_rings;

6145
	bp->num_rx_rings = bp->irq_nvecs;
6146 6147
}

6148 6149 6150 6151
/* Called with rtnl_lock */
static int
bnx2_open(struct net_device *dev)
{
M
Michael Chan 已提交
6152
	struct bnx2 *bp = netdev_priv(dev);
6153 6154
	int rc;

6155 6156
	netif_carrier_off(dev);

6157
	bnx2_set_power_state(bp, PCI_D0);
6158 6159
	bnx2_disable_int(bp);

6160 6161
	bnx2_setup_int_mode(bp, disable_msi);
	bnx2_napi_enable(bp);
6162
	rc = bnx2_alloc_mem(bp);
6163 6164
	if (rc)
		goto open_err;
6165

6166
	rc = bnx2_request_irq(bp);
6167 6168
	if (rc)
		goto open_err;
6169

6170
	rc = bnx2_init_nic(bp, 1);
6171 6172
	if (rc)
		goto open_err;
6173

6174
	mod_timer(&bp->timer, jiffies + bp->current_interval);
6175 6176 6177 6178 6179

	atomic_set(&bp->intr_sem, 0);

	bnx2_enable_int(bp);

6180
	if (bp->flags & BNX2_FLAG_USING_MSI) {
6181 6182 6183 6184 6185 6186 6187 6188 6189 6190 6191
		/* Test MSI to make sure it is working
		 * If MSI test fails, go back to INTx mode
		 */
		if (bnx2_test_intr(bp) != 0) {
			printk(KERN_WARNING PFX "%s: No interrupt was generated"
			       " using MSI, switching to INTx mode. Please"
			       " report this failure to the PCI maintainer"
			       " and include system chipset information.\n",
			       bp->dev->name);

			bnx2_disable_int(bp);
6192
			bnx2_free_irq(bp);
6193

6194 6195
			bnx2_setup_int_mode(bp, 1);

6196
			rc = bnx2_init_nic(bp, 0);
6197

6198 6199 6200
			if (!rc)
				rc = bnx2_request_irq(bp);

6201 6202
			if (rc) {
				del_timer_sync(&bp->timer);
6203
				goto open_err;
6204 6205 6206 6207
			}
			bnx2_enable_int(bp);
		}
	}
6208
	if (bp->flags & BNX2_FLAG_USING_MSI)
6209
		printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
6210
	else if (bp->flags & BNX2_FLAG_USING_MSIX)
6211
		printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
6212

6213
	netif_tx_start_all_queues(dev);
6214 6215

	return 0;
6216 6217 6218 6219 6220 6221 6222

open_err:
	bnx2_napi_disable(bp);
	bnx2_free_skbs(bp);
	bnx2_free_irq(bp);
	bnx2_free_mem(bp);
	return rc;
6223 6224 6225
}

static void
6226
bnx2_reset_task(struct work_struct *work)
6227
{
6228
	struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6229

6230 6231 6232
	if (!netif_running(bp->dev))
		return;

6233 6234
	bnx2_netif_stop(bp);

6235
	bnx2_init_nic(bp, 1);
6236 6237 6238 6239 6240 6241 6242 6243

	atomic_set(&bp->intr_sem, 1);
	bnx2_netif_start(bp);
}

static void
bnx2_tx_timeout(struct net_device *dev)
{
M
Michael Chan 已提交
6244
	struct bnx2 *bp = netdev_priv(dev);
6245 6246 6247 6248 6249 6250 6251 6252 6253 6254

	/* This allows the netif to be shutdown gracefully before resetting */
	schedule_work(&bp->reset_task);
}

#ifdef BCM_VLAN
/* Called with rtnl_lock */
static void
bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
{
M
Michael Chan 已提交
6255
	struct bnx2 *bp = netdev_priv(dev);
6256 6257 6258 6259 6260

	bnx2_netif_stop(bp);

	bp->vlgrp = vlgrp;
	bnx2_set_rx_mode(dev);
6261 6262
	if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
		bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6263 6264 6265 6266 6267

	bnx2_netif_start(bp);
}
#endif

H
Herbert Xu 已提交
6268
/* Called with netif_tx_lock.
6269 6270
 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
 * netif_wake_queue().
6271 6272 6273 6274
 */
static int
bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
M
Michael Chan 已提交
6275
	struct bnx2 *bp = netdev_priv(dev);
6276 6277
	dma_addr_t mapping;
	struct tx_bd *txbd;
6278
	struct sw_tx_bd *tx_buf;
6279 6280 6281
	u32 len, vlan_tag_flags, last_frag, mss;
	u16 prod, ring_prod;
	int i;
6282 6283 6284
	struct bnx2_napi *bnapi;
	struct bnx2_tx_ring_info *txr;
	struct netdev_queue *txq;
6285
	struct skb_shared_info *sp;
6286 6287 6288 6289 6290 6291

	/*  Determine which tx ring we will be placed on */
	i = skb_get_queue_mapping(skb);
	bnapi = &bp->bnx2_napi[i];
	txr = &bnapi->tx_ring;
	txq = netdev_get_tx_queue(dev, i);
6292

6293
	if (unlikely(bnx2_tx_avail(bp, txr) <
6294
	    (skb_shinfo(skb)->nr_frags + 1))) {
6295
		netif_tx_stop_queue(txq);
6296 6297 6298 6299 6300 6301
		printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
			dev->name);

		return NETDEV_TX_BUSY;
	}
	len = skb_headlen(skb);
6302
	prod = txr->tx_prod;
6303 6304 6305
	ring_prod = TX_RING_IDX(prod);

	vlan_tag_flags = 0;
6306
	if (skb->ip_summed == CHECKSUM_PARTIAL) {
6307 6308 6309
		vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
	}

6310
#ifdef BCM_VLAN
A
Al Viro 已提交
6311
	if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6312 6313 6314
		vlan_tag_flags |=
			(TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
	}
6315
#endif
6316
	if ((mss = skb_shinfo(skb)->gso_size)) {
6317
		u32 tcp_opt_len;
6318
		struct iphdr *iph;
6319 6320 6321

		vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;

6322 6323 6324 6325 6326
		tcp_opt_len = tcp_optlen(skb);

		if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
			u32 tcp_off = skb_transport_offset(skb) -
				      sizeof(struct ipv6hdr) - ETH_HLEN;
6327

6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344 6345
			vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
					  TX_BD_FLAGS_SW_FLAGS;
			if (likely(tcp_off == 0))
				vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
			else {
				tcp_off >>= 3;
				vlan_tag_flags |= ((tcp_off & 0x3) <<
						   TX_BD_FLAGS_TCP6_OFF0_SHL) |
						  ((tcp_off & 0x10) <<
						   TX_BD_FLAGS_TCP6_OFF4_SHL);
				mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
			}
		} else {
			iph = ip_hdr(skb);
			if (tcp_opt_len || (iph->ihl > 5)) {
				vlan_tag_flags |= ((iph->ihl - 5) +
						   (tcp_opt_len >> 2)) << 8;
			}
6346
		}
6347
	} else
6348 6349
		mss = 0;

6350 6351 6352 6353 6354 6355
	if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
		dev_kfree_skb(skb);
		return NETDEV_TX_OK;
	}

	sp = skb_shinfo(skb);
6356
	mapping = sp->dma_head;
6357

6358
	tx_buf = &txr->tx_buf_ring[ring_prod];
6359 6360
	tx_buf->skb = skb;

6361
	txbd = &txr->tx_desc_ring[ring_prod];
6362 6363 6364 6365 6366 6367 6368

	txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
	txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
	txbd->tx_bd_mss_nbytes = len | (mss << 16);
	txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;

	last_frag = skb_shinfo(skb)->nr_frags;
6369 6370
	tx_buf->nr_frags = last_frag;
	tx_buf->is_gso = skb_is_gso(skb);
6371 6372 6373 6374 6375 6376

	for (i = 0; i < last_frag; i++) {
		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];

		prod = NEXT_TX_BD(prod);
		ring_prod = TX_RING_IDX(prod);
6377
		txbd = &txr->tx_desc_ring[ring_prod];
6378 6379

		len = frag->size;
6380
		mapping = sp->dma_maps[i];
6381 6382 6383 6384 6385 6386 6387 6388 6389 6390

		txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
		txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
		txbd->tx_bd_mss_nbytes = len | (mss << 16);
		txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;

	}
	txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;

	prod = NEXT_TX_BD(prod);
6391
	txr->tx_prod_bseq += skb->len;
6392

6393 6394
	REG_WR16(bp, txr->tx_bidx_addr, prod);
	REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6395 6396 6397

	mmiowb();

6398
	txr->tx_prod = prod;
6399

6400
	if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6401
		netif_tx_stop_queue(txq);
6402
		if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6403
			netif_tx_wake_queue(txq);
6404 6405 6406 6407 6408 6409 6410 6411 6412
	}

	return NETDEV_TX_OK;
}

/* Called with rtnl_lock */
static int
bnx2_close(struct net_device *dev)
{
M
Michael Chan 已提交
6413
	struct bnx2 *bp = netdev_priv(dev);
6414

6415
	cancel_work_sync(&bp->reset_task);
6416

6417
	bnx2_disable_int_sync(bp);
6418
	bnx2_napi_disable(bp);
6419
	del_timer_sync(&bp->timer);
6420
	bnx2_shutdown_chip(bp);
6421
	bnx2_free_irq(bp);
6422 6423 6424 6425
	bnx2_free_skbs(bp);
	bnx2_free_mem(bp);
	bp->link_up = 0;
	netif_carrier_off(bp->dev);
6426
	bnx2_set_power_state(bp, PCI_D3hot);
6427 6428 6429 6430 6431 6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444 6445
	return 0;
}

#define GET_NET_STATS64(ctr)					\
	(unsigned long) ((unsigned long) (ctr##_hi) << 32) +	\
	(unsigned long) (ctr##_lo)

#define GET_NET_STATS32(ctr)		\
	(ctr##_lo)

#if (BITS_PER_LONG == 64)
#define GET_NET_STATS	GET_NET_STATS64
#else
#define GET_NET_STATS	GET_NET_STATS32
#endif

static struct net_device_stats *
bnx2_get_stats(struct net_device *dev)
{
M
Michael Chan 已提交
6446
	struct bnx2 *bp = netdev_priv(dev);
6447
	struct statistics_block *stats_blk = bp->stats_blk;
6448
	struct net_device_stats *net_stats = &dev->stats;
6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465 6466 6467 6468

	if (bp->stats_blk == NULL) {
		return net_stats;
	}
	net_stats->rx_packets =
		GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);

	net_stats->tx_packets =
		GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
		GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);

	net_stats->rx_bytes =
		GET_NET_STATS(stats_blk->stat_IfHCInOctets);

	net_stats->tx_bytes =
		GET_NET_STATS(stats_blk->stat_IfHCOutOctets);

6469
	net_stats->multicast =
6470 6471
		GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);

6472
	net_stats->collisions =
6473 6474
		(unsigned long) stats_blk->stat_EtherStatsCollisions;

6475
	net_stats->rx_length_errors =
6476 6477 6478
		(unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
		stats_blk->stat_EtherStatsOverrsizePkts);

6479
	net_stats->rx_over_errors =
6480 6481
		(unsigned long) stats_blk->stat_IfInMBUFDiscards;

6482
	net_stats->rx_frame_errors =
6483 6484
		(unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;

6485
	net_stats->rx_crc_errors =
6486 6487 6488 6489 6490 6491 6492 6493 6494 6495
		(unsigned long) stats_blk->stat_Dot3StatsFCSErrors;

	net_stats->rx_errors = net_stats->rx_length_errors +
		net_stats->rx_over_errors + net_stats->rx_frame_errors +
		net_stats->rx_crc_errors;

	net_stats->tx_aborted_errors =
    		(unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
		stats_blk->stat_Dot3StatsLateCollisions);

6496 6497
	if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_A0))
6498 6499 6500 6501 6502 6503 6504 6505
		net_stats->tx_carrier_errors = 0;
	else {
		net_stats->tx_carrier_errors =
			(unsigned long)
			stats_blk->stat_Dot3StatsCarrierSenseErrors;
	}

	net_stats->tx_errors =
6506
    		(unsigned long)
6507 6508 6509 6510 6511
		stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
		+
		net_stats->tx_aborted_errors +
		net_stats->tx_carrier_errors;

6512 6513 6514 6515
	net_stats->rx_missed_errors =
		(unsigned long) (stats_blk->stat_IfInMBUFDiscards +
		stats_blk->stat_FwRxDrop);

6516 6517 6518 6519 6520 6521 6522 6523
	return net_stats;
}

/* All ethtool functions called with rtnl_lock */

static int
bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
M
Michael Chan 已提交
6524
	struct bnx2 *bp = netdev_priv(dev);
6525
	int support_serdes = 0, support_copper = 0;
6526 6527

	cmd->supported = SUPPORTED_Autoneg;
6528
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6529 6530 6531 6532 6533 6534 6535 6536
		support_serdes = 1;
		support_copper = 1;
	} else if (bp->phy_port == PORT_FIBRE)
		support_serdes = 1;
	else
		support_copper = 1;

	if (support_serdes) {
6537 6538
		cmd->supported |= SUPPORTED_1000baseT_Full |
			SUPPORTED_FIBRE;
6539
		if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6540
			cmd->supported |= SUPPORTED_2500baseX_Full;
6541 6542

	}
6543
	if (support_copper) {
6544 6545 6546 6547 6548 6549 6550 6551 6552
		cmd->supported |= SUPPORTED_10baseT_Half |
			SUPPORTED_10baseT_Full |
			SUPPORTED_100baseT_Half |
			SUPPORTED_100baseT_Full |
			SUPPORTED_1000baseT_Full |
			SUPPORTED_TP;

	}

6553 6554
	spin_lock_bh(&bp->phy_lock);
	cmd->port = bp->phy_port;
6555 6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567 6568 6569 6570 6571
	cmd->advertising = bp->advertising;

	if (bp->autoneg & AUTONEG_SPEED) {
		cmd->autoneg = AUTONEG_ENABLE;
	}
	else {
		cmd->autoneg = AUTONEG_DISABLE;
	}

	if (netif_carrier_ok(dev)) {
		cmd->speed = bp->line_speed;
		cmd->duplex = bp->duplex;
	}
	else {
		cmd->speed = -1;
		cmd->duplex = -1;
	}
6572
	spin_unlock_bh(&bp->phy_lock);
6573 6574 6575 6576 6577 6578

	cmd->transceiver = XCVR_INTERNAL;
	cmd->phy_address = bp->phy_addr;

	return 0;
}
6579

6580 6581 6582
static int
bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
M
Michael Chan 已提交
6583
	struct bnx2 *bp = netdev_priv(dev);
6584 6585 6586 6587
	u8 autoneg = bp->autoneg;
	u8 req_duplex = bp->req_duplex;
	u16 req_line_speed = bp->req_line_speed;
	u32 advertising = bp->advertising;
6588 6589 6590 6591 6592 6593 6594
	int err = -EINVAL;

	spin_lock_bh(&bp->phy_lock);

	if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
		goto err_out_unlock;

6595 6596
	if (cmd->port != bp->phy_port &&
	    !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6597
		goto err_out_unlock;
6598

6599 6600 6601 6602 6603 6604
	/* If device is down, we can store the settings only if the user
	 * is setting the currently active port.
	 */
	if (!netif_running(dev) && cmd->port != bp->phy_port)
		goto err_out_unlock;

6605 6606 6607
	if (cmd->autoneg == AUTONEG_ENABLE) {
		autoneg |= AUTONEG_SPEED;

6608
		cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6609 6610 6611 6612 6613 6614 6615

		/* allow advertising 1 speed */
		if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
			(cmd->advertising == ADVERTISED_10baseT_Full) ||
			(cmd->advertising == ADVERTISED_100baseT_Half) ||
			(cmd->advertising == ADVERTISED_100baseT_Full)) {

6616 6617
			if (cmd->port == PORT_FIBRE)
				goto err_out_unlock;
6618 6619 6620

			advertising = cmd->advertising;

6621
		} else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6622
			if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6623 6624 6625
			    (cmd->port == PORT_TP))
				goto err_out_unlock;
		} else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6626
			advertising = cmd->advertising;
6627 6628
		else if (cmd->advertising == ADVERTISED_1000baseT_Half)
			goto err_out_unlock;
6629
		else {
6630
			if (cmd->port == PORT_FIBRE)
6631
				advertising = ETHTOOL_ALL_FIBRE_SPEED;
6632
			else
6633 6634 6635 6636 6637
				advertising = ETHTOOL_ALL_COPPER_SPEED;
		}
		advertising |= ADVERTISED_Autoneg;
	}
	else {
6638
		if (cmd->port == PORT_FIBRE) {
6639 6640 6641
			if ((cmd->speed != SPEED_1000 &&
			     cmd->speed != SPEED_2500) ||
			    (cmd->duplex != DUPLEX_FULL))
6642
				goto err_out_unlock;
6643 6644

			if (cmd->speed == SPEED_2500 &&
6645
			    !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6646
				goto err_out_unlock;
6647
		}
6648 6649 6650
		else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
			goto err_out_unlock;

6651 6652 6653 6654 6655 6656 6657 6658 6659 6660 6661
		autoneg &= ~AUTONEG_SPEED;
		req_line_speed = cmd->speed;
		req_duplex = cmd->duplex;
		advertising = 0;
	}

	bp->autoneg = autoneg;
	bp->advertising = advertising;
	bp->req_line_speed = req_line_speed;
	bp->req_duplex = req_duplex;

6662 6663 6664 6665 6666 6667
	err = 0;
	/* If device is down, the new settings will be picked up when it is
	 * brought up.
	 */
	if (netif_running(dev))
		err = bnx2_setup_phy(bp, cmd->port);
6668

6669
err_out_unlock:
6670
	spin_unlock_bh(&bp->phy_lock);
6671

6672
	return err;
6673 6674 6675 6676 6677
}

static void
bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
{
M
Michael Chan 已提交
6678
	struct bnx2 *bp = netdev_priv(dev);
6679 6680 6681 6682

	strcpy(info->driver, DRV_MODULE_NAME);
	strcpy(info->version, DRV_MODULE_VERSION);
	strcpy(info->bus_info, pci_name(bp->pdev));
6683
	strcpy(info->fw_version, bp->fw_version);
6684 6685
}

6686 6687 6688 6689 6690 6691 6692 6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718 6719 6720 6721 6722 6723 6724 6725 6726 6727 6728 6729 6730 6731 6732 6733 6734 6735 6736 6737 6738 6739 6740 6741 6742 6743
#define BNX2_REGDUMP_LEN		(32 * 1024)

static int
bnx2_get_regs_len(struct net_device *dev)
{
	return BNX2_REGDUMP_LEN;
}

static void
bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
{
	u32 *p = _p, i, offset;
	u8 *orig_p = _p;
	struct bnx2 *bp = netdev_priv(dev);
	u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
				 0x0800, 0x0880, 0x0c00, 0x0c10,
				 0x0c30, 0x0d08, 0x1000, 0x101c,
				 0x1040, 0x1048, 0x1080, 0x10a4,
				 0x1400, 0x1490, 0x1498, 0x14f0,
				 0x1500, 0x155c, 0x1580, 0x15dc,
				 0x1600, 0x1658, 0x1680, 0x16d8,
				 0x1800, 0x1820, 0x1840, 0x1854,
				 0x1880, 0x1894, 0x1900, 0x1984,
				 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
				 0x1c80, 0x1c94, 0x1d00, 0x1d84,
				 0x2000, 0x2030, 0x23c0, 0x2400,
				 0x2800, 0x2820, 0x2830, 0x2850,
				 0x2b40, 0x2c10, 0x2fc0, 0x3058,
				 0x3c00, 0x3c94, 0x4000, 0x4010,
				 0x4080, 0x4090, 0x43c0, 0x4458,
				 0x4c00, 0x4c18, 0x4c40, 0x4c54,
				 0x4fc0, 0x5010, 0x53c0, 0x5444,
				 0x5c00, 0x5c18, 0x5c80, 0x5c90,
				 0x5fc0, 0x6000, 0x6400, 0x6428,
				 0x6800, 0x6848, 0x684c, 0x6860,
				 0x6888, 0x6910, 0x8000 };

	regs->version = 0;

	memset(p, 0, BNX2_REGDUMP_LEN);

	if (!netif_running(bp->dev))
		return;

	i = 0;
	offset = reg_boundaries[0];
	p += offset;
	while (offset < BNX2_REGDUMP_LEN) {
		*p++ = REG_RD(bp, offset);
		offset += 4;
		if (offset == reg_boundaries[i + 1]) {
			offset = reg_boundaries[i + 2];
			p = (u32 *) (orig_p + offset);
			i += 2;
		}
	}
}

6744 6745 6746
static void
bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
M
Michael Chan 已提交
6747
	struct bnx2 *bp = netdev_priv(dev);
6748

6749
	if (bp->flags & BNX2_FLAG_NO_WOL) {
6750 6751 6752 6753 6754 6755 6756 6757 6758 6759 6760 6761 6762 6763 6764 6765
		wol->supported = 0;
		wol->wolopts = 0;
	}
	else {
		wol->supported = WAKE_MAGIC;
		if (bp->wol)
			wol->wolopts = WAKE_MAGIC;
		else
			wol->wolopts = 0;
	}
	memset(&wol->sopass, 0, sizeof(wol->sopass));
}

static int
bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
M
Michael Chan 已提交
6766
	struct bnx2 *bp = netdev_priv(dev);
6767 6768 6769 6770 6771

	if (wol->wolopts & ~WAKE_MAGIC)
		return -EINVAL;

	if (wol->wolopts & WAKE_MAGIC) {
6772
		if (bp->flags & BNX2_FLAG_NO_WOL)
6773 6774 6775 6776 6777 6778 6779 6780 6781 6782 6783 6784 6785
			return -EINVAL;

		bp->wol = 1;
	}
	else {
		bp->wol = 0;
	}
	return 0;
}

static int
bnx2_nway_reset(struct net_device *dev)
{
M
Michael Chan 已提交
6786
	struct bnx2 *bp = netdev_priv(dev);
6787 6788
	u32 bmcr;

6789 6790 6791
	if (!netif_running(dev))
		return -EAGAIN;

6792 6793 6794 6795
	if (!(bp->autoneg & AUTONEG_SPEED)) {
		return -EINVAL;
	}

6796
	spin_lock_bh(&bp->phy_lock);
6797

6798
	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6799 6800 6801 6802 6803 6804 6805
		int rc;

		rc = bnx2_setup_remote_phy(bp, bp->phy_port);
		spin_unlock_bh(&bp->phy_lock);
		return rc;
	}

6806
	/* Force a link down visible on the other side */
6807
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6808
		bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6809
		spin_unlock_bh(&bp->phy_lock);
6810 6811 6812

		msleep(20);

6813
		spin_lock_bh(&bp->phy_lock);
6814

6815
		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6816 6817
		bp->serdes_an_pending = 1;
		mod_timer(&bp->timer, jiffies + bp->current_interval);
6818 6819
	}

6820
	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6821
	bmcr &= ~BMCR_LOOPBACK;
6822
	bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6823

6824
	spin_unlock_bh(&bp->phy_lock);
6825 6826 6827 6828

	return 0;
}

6829 6830 6831 6832 6833 6834 6835 6836
static u32
bnx2_get_link(struct net_device *dev)
{
	struct bnx2 *bp = netdev_priv(dev);

	return bp->link_up;
}

6837 6838 6839
static int
bnx2_get_eeprom_len(struct net_device *dev)
{
M
Michael Chan 已提交
6840
	struct bnx2 *bp = netdev_priv(dev);
6841

M
Michael Chan 已提交
6842
	if (bp->flash_info == NULL)
6843 6844
		return 0;

M
Michael Chan 已提交
6845
	return (int) bp->flash_size;
6846 6847 6848 6849 6850 6851
}

static int
bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
		u8 *eebuf)
{
M
Michael Chan 已提交
6852
	struct bnx2 *bp = netdev_priv(dev);
6853 6854
	int rc;

6855 6856 6857
	if (!netif_running(dev))
		return -EAGAIN;

6858
	/* parameters already validated in ethtool_get_eeprom */
6859 6860 6861 6862 6863 6864 6865 6866 6867 6868

	rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);

	return rc;
}

static int
bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
		u8 *eebuf)
{
M
Michael Chan 已提交
6869
	struct bnx2 *bp = netdev_priv(dev);
6870 6871
	int rc;

6872 6873 6874
	if (!netif_running(dev))
		return -EAGAIN;

6875
	/* parameters already validated in ethtool_set_eeprom */
6876 6877 6878 6879 6880 6881 6882 6883 6884

	rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);

	return rc;
}

static int
bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
{
M
Michael Chan 已提交
6885
	struct bnx2 *bp = netdev_priv(dev);
6886 6887 6888 6889 6890 6891 6892 6893 6894 6895 6896 6897 6898 6899 6900 6901 6902 6903 6904 6905 6906

	memset(coal, 0, sizeof(struct ethtool_coalesce));

	coal->rx_coalesce_usecs = bp->rx_ticks;
	coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
	coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
	coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;

	coal->tx_coalesce_usecs = bp->tx_ticks;
	coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
	coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
	coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;

	coal->stats_block_coalesce_usecs = bp->stats_ticks;

	return 0;
}

static int
bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
{
M
Michael Chan 已提交
6907
	struct bnx2 *bp = netdev_priv(dev);
6908 6909 6910 6911

	bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
	if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;

6912
	bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6913 6914 6915 6916 6917 6918 6919 6920 6921 6922 6923 6924 6925 6926 6927 6928 6929 6930 6931 6932 6933 6934 6935
	if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;

	bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
	if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;

	bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
	if (bp->rx_quick_cons_trip_int > 0xff)
		bp->rx_quick_cons_trip_int = 0xff;

	bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
	if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;

	bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
	if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;

	bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
	if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;

	bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
	if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
		0xff;

	bp->stats_ticks = coal->stats_block_coalesce_usecs;
6936 6937 6938 6939
	if (CHIP_NUM(bp) == CHIP_NUM_5708) {
		if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
			bp->stats_ticks = USEC_PER_SEC;
	}
6940 6941 6942
	if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
		bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
	bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6943 6944 6945

	if (netif_running(bp->dev)) {
		bnx2_netif_stop(bp);
6946
		bnx2_init_nic(bp, 0);
6947 6948 6949 6950 6951 6952 6953 6954 6955
		bnx2_netif_start(bp);
	}

	return 0;
}

static void
bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
{
M
Michael Chan 已提交
6956
	struct bnx2 *bp = netdev_priv(dev);
6957

6958
	ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6959
	ering->rx_mini_max_pending = 0;
6960
	ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6961 6962 6963

	ering->rx_pending = bp->rx_ring_size;
	ering->rx_mini_pending = 0;
6964
	ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6965 6966 6967 6968 6969 6970

	ering->tx_max_pending = MAX_TX_DESC_CNT;
	ering->tx_pending = bp->tx_ring_size;
}

static int
6971
bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6972
{
6973 6974 6975 6976 6977 6978 6979
	if (netif_running(bp->dev)) {
		bnx2_netif_stop(bp);
		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
		bnx2_free_skbs(bp);
		bnx2_free_mem(bp);
	}

6980 6981
	bnx2_set_rx_ring_size(bp, rx);
	bp->tx_ring_size = tx;
6982 6983

	if (netif_running(bp->dev)) {
6984 6985 6986 6987 6988
		int rc;

		rc = bnx2_alloc_mem(bp);
		if (rc)
			return rc;
6989
		bnx2_init_nic(bp, 0);
6990 6991 6992 6993 6994
		bnx2_netif_start(bp);
	}
	return 0;
}

6995 6996 6997 6998 6999 7000 7001 7002 7003 7004 7005 7006 7007 7008 7009 7010
static int
bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
{
	struct bnx2 *bp = netdev_priv(dev);
	int rc;

	if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
		(ering->tx_pending > MAX_TX_DESC_CNT) ||
		(ering->tx_pending <= MAX_SKB_FRAGS)) {

		return -EINVAL;
	}
	rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
	return rc;
}

7011 7012 7013
static void
bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
M
Michael Chan 已提交
7014
	struct bnx2 *bp = netdev_priv(dev);
7015 7016 7017 7018 7019 7020 7021 7022 7023

	epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
	epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
	epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
}

static int
bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
{
M
Michael Chan 已提交
7024
	struct bnx2 *bp = netdev_priv(dev);
7025 7026 7027 7028 7029 7030 7031 7032 7033 7034 7035 7036 7037 7038

	bp->req_flow_ctrl = 0;
	if (epause->rx_pause)
		bp->req_flow_ctrl |= FLOW_CTRL_RX;
	if (epause->tx_pause)
		bp->req_flow_ctrl |= FLOW_CTRL_TX;

	if (epause->autoneg) {
		bp->autoneg |= AUTONEG_FLOW_CTRL;
	}
	else {
		bp->autoneg &= ~AUTONEG_FLOW_CTRL;
	}

7039 7040 7041 7042 7043
	if (netif_running(dev)) {
		spin_lock_bh(&bp->phy_lock);
		bnx2_setup_phy(bp, bp->phy_port);
		spin_unlock_bh(&bp->phy_lock);
	}
7044 7045 7046 7047 7048 7049 7050

	return 0;
}

static u32
bnx2_get_rx_csum(struct net_device *dev)
{
M
Michael Chan 已提交
7051
	struct bnx2 *bp = netdev_priv(dev);
7052 7053 7054 7055 7056 7057 7058

	return bp->rx_csum;
}

static int
bnx2_set_rx_csum(struct net_device *dev, u32 data)
{
M
Michael Chan 已提交
7059
	struct bnx2 *bp = netdev_priv(dev);
7060 7061 7062 7063 7064

	bp->rx_csum = data;
	return 0;
}

7065 7066 7067
static int
bnx2_set_tso(struct net_device *dev, u32 data)
{
7068 7069 7070
	struct bnx2 *bp = netdev_priv(dev);

	if (data) {
7071
		dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7072 7073 7074 7075 7076
		if (CHIP_NUM(bp) == CHIP_NUM_5709)
			dev->features |= NETIF_F_TSO6;
	} else
		dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
				   NETIF_F_TSO_ECN);
7077 7078 7079
	return 0;
}

7080
#define BNX2_NUM_STATS 46
7081

7082
static struct {
7083 7084 7085 7086 7087 7088 7089 7090 7091 7092 7093 7094 7095 7096 7097 7098 7099 7100 7101 7102 7103 7104 7105 7106 7107 7108 7109 7110 7111 7112 7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125 7126 7127 7128 7129
	char string[ETH_GSTRING_LEN];
} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
	{ "rx_bytes" },
	{ "rx_error_bytes" },
	{ "tx_bytes" },
	{ "tx_error_bytes" },
	{ "rx_ucast_packets" },
	{ "rx_mcast_packets" },
	{ "rx_bcast_packets" },
	{ "tx_ucast_packets" },
	{ "tx_mcast_packets" },
	{ "tx_bcast_packets" },
	{ "tx_mac_errors" },
	{ "tx_carrier_errors" },
	{ "rx_crc_errors" },
	{ "rx_align_errors" },
	{ "tx_single_collisions" },
	{ "tx_multi_collisions" },
	{ "tx_deferred" },
	{ "tx_excess_collisions" },
	{ "tx_late_collisions" },
	{ "tx_total_collisions" },
	{ "rx_fragments" },
	{ "rx_jabbers" },
	{ "rx_undersize_packets" },
	{ "rx_oversize_packets" },
	{ "rx_64_byte_packets" },
	{ "rx_65_to_127_byte_packets" },
	{ "rx_128_to_255_byte_packets" },
	{ "rx_256_to_511_byte_packets" },
	{ "rx_512_to_1023_byte_packets" },
	{ "rx_1024_to_1522_byte_packets" },
	{ "rx_1523_to_9022_byte_packets" },
	{ "tx_64_byte_packets" },
	{ "tx_65_to_127_byte_packets" },
	{ "tx_128_to_255_byte_packets" },
	{ "tx_256_to_511_byte_packets" },
	{ "tx_512_to_1023_byte_packets" },
	{ "tx_1024_to_1522_byte_packets" },
	{ "tx_1523_to_9022_byte_packets" },
	{ "rx_xon_frames" },
	{ "rx_xoff_frames" },
	{ "tx_xon_frames" },
	{ "tx_xoff_frames" },
	{ "rx_mac_ctrl_frames" },
	{ "rx_filtered_packets" },
	{ "rx_discards" },
7130
	{ "rx_fw_discards" },
7131 7132 7133 7134
};

#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)

7135
static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146
    STATS_OFFSET32(stat_IfHCInOctets_hi),
    STATS_OFFSET32(stat_IfHCInBadOctets_hi),
    STATS_OFFSET32(stat_IfHCOutOctets_hi),
    STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
    STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
    STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
    STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
    STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
    STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
    STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
    STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7147 7148 7149 7150 7151 7152 7153 7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170 7171 7172 7173 7174 7175 7176 7177 7178 7179 7180
    STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
    STATS_OFFSET32(stat_Dot3StatsFCSErrors),
    STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
    STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
    STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
    STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
    STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
    STATS_OFFSET32(stat_Dot3StatsLateCollisions),
    STATS_OFFSET32(stat_EtherStatsCollisions),
    STATS_OFFSET32(stat_EtherStatsFragments),
    STATS_OFFSET32(stat_EtherStatsJabbers),
    STATS_OFFSET32(stat_EtherStatsUndersizePkts),
    STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
    STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
    STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
    STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
    STATS_OFFSET32(stat_XonPauseFramesReceived),
    STATS_OFFSET32(stat_XoffPauseFramesReceived),
    STATS_OFFSET32(stat_OutXonSent),
    STATS_OFFSET32(stat_OutXoffSent),
    STATS_OFFSET32(stat_MacControlFramesReceived),
    STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
    STATS_OFFSET32(stat_IfInMBUFDiscards),
7181
    STATS_OFFSET32(stat_FwRxDrop),
7182 7183 7184 7185
};

/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
 * skipped because of errata.
7186
 */
7187
static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7188 7189 7190 7191
	8,0,8,8,8,8,8,8,8,8,
	4,0,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
7192
	4,4,4,4,4,4,
7193 7194
};

7195 7196 7197 7198 7199
static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
	8,0,8,8,8,8,8,8,8,8,
	4,4,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
	4,4,4,4,4,4,4,4,4,4,
7200
	4,4,4,4,4,4,
7201 7202
};

7203 7204
#define BNX2_NUM_TESTS 6

7205
static struct {
7206 7207 7208 7209 7210 7211 7212 7213 7214 7215 7216
	char string[ETH_GSTRING_LEN];
} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
	{ "register_test (offline)" },
	{ "memory_test (offline)" },
	{ "loopback_test (offline)" },
	{ "nvram_test (online)" },
	{ "interrupt_test (online)" },
	{ "link_test (online)" },
};

static int
7217
bnx2_get_sset_count(struct net_device *dev, int sset)
7218
{
7219 7220 7221 7222 7223 7224 7225 7226
	switch (sset) {
	case ETH_SS_TEST:
		return BNX2_NUM_TESTS;
	case ETH_SS_STATS:
		return BNX2_NUM_STATS;
	default:
		return -EOPNOTSUPP;
	}
7227 7228 7229 7230 7231
}

static void
bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
{
M
Michael Chan 已提交
7232
	struct bnx2 *bp = netdev_priv(dev);
7233

7234 7235
	bnx2_set_power_state(bp, PCI_D0);

7236 7237
	memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
	if (etest->flags & ETH_TEST_FL_OFFLINE) {
7238 7239
		int i;

7240 7241 7242 7243 7244 7245 7246 7247 7248 7249 7250 7251
		bnx2_netif_stop(bp);
		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
		bnx2_free_skbs(bp);

		if (bnx2_test_registers(bp) != 0) {
			buf[0] = 1;
			etest->flags |= ETH_TEST_FL_FAILED;
		}
		if (bnx2_test_memory(bp) != 0) {
			buf[1] = 1;
			etest->flags |= ETH_TEST_FL_FAILED;
		}
7252
		if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7253 7254
			etest->flags |= ETH_TEST_FL_FAILED;

7255 7256
		if (!netif_running(bp->dev))
			bnx2_shutdown_chip(bp);
7257
		else {
7258
			bnx2_init_nic(bp, 1);
7259 7260 7261 7262
			bnx2_netif_start(bp);
		}

		/* wait for link up */
7263 7264 7265 7266 7267
		for (i = 0; i < 7; i++) {
			if (bp->link_up)
				break;
			msleep_interruptible(1000);
		}
7268 7269 7270 7271 7272 7273 7274 7275 7276 7277 7278 7279 7280 7281 7282 7283
	}

	if (bnx2_test_nvram(bp) != 0) {
		buf[3] = 1;
		etest->flags |= ETH_TEST_FL_FAILED;
	}
	if (bnx2_test_intr(bp) != 0) {
		buf[4] = 1;
		etest->flags |= ETH_TEST_FL_FAILED;
	}

	if (bnx2_test_link(bp) != 0) {
		buf[5] = 1;
		etest->flags |= ETH_TEST_FL_FAILED;

	}
7284 7285
	if (!netif_running(bp->dev))
		bnx2_set_power_state(bp, PCI_D3hot);
7286 7287 7288 7289 7290 7291 7292 7293 7294 7295 7296 7297 7298 7299 7300 7301 7302 7303 7304 7305 7306
}

static void
bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
{
	switch (stringset) {
	case ETH_SS_STATS:
		memcpy(buf, bnx2_stats_str_arr,
			sizeof(bnx2_stats_str_arr));
		break;
	case ETH_SS_TEST:
		memcpy(buf, bnx2_tests_str_arr,
			sizeof(bnx2_tests_str_arr));
		break;
	}
}

static void
bnx2_get_ethtool_stats(struct net_device *dev,
		struct ethtool_stats *stats, u64 *buf)
{
M
Michael Chan 已提交
7307
	struct bnx2 *bp = netdev_priv(dev);
7308 7309
	int i;
	u32 *hw_stats = (u32 *) bp->stats_blk;
7310
	u8 *stats_len_arr = NULL;
7311 7312 7313 7314 7315 7316

	if (hw_stats == NULL) {
		memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
		return;
	}

7317 7318 7319 7320
	if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
	    (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
	    (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_A0))
7321
		stats_len_arr = bnx2_5706_stats_len_arr;
7322 7323
	else
		stats_len_arr = bnx2_5708_stats_len_arr;
7324 7325 7326 7327 7328 7329 7330 7331 7332 7333 7334 7335 7336 7337 7338 7339 7340 7341 7342 7343 7344 7345 7346

	for (i = 0; i < BNX2_NUM_STATS; i++) {
		if (stats_len_arr[i] == 0) {
			/* skip this counter */
			buf[i] = 0;
			continue;
		}
		if (stats_len_arr[i] == 4) {
			/* 4-byte counter */
			buf[i] = (u64)
				*(hw_stats + bnx2_stats_offset_arr[i]);
			continue;
		}
		/* 8-byte counter */
		buf[i] = (((u64) *(hw_stats +
					bnx2_stats_offset_arr[i])) << 32) +
				*(hw_stats + bnx2_stats_offset_arr[i] + 1);
	}
}

static int
bnx2_phys_id(struct net_device *dev, u32 data)
{
M
Michael Chan 已提交
7347
	struct bnx2 *bp = netdev_priv(dev);
7348 7349 7350
	int i;
	u32 save;

7351 7352
	bnx2_set_power_state(bp, PCI_D0);

7353 7354 7355 7356 7357 7358 7359 7360 7361 7362 7363 7364 7365 7366 7367 7368 7369 7370 7371 7372 7373 7374 7375 7376
	if (data == 0)
		data = 2;

	save = REG_RD(bp, BNX2_MISC_CFG);
	REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);

	for (i = 0; i < (data * 2); i++) {
		if ((i % 2) == 0) {
			REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
		}
		else {
			REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
				BNX2_EMAC_LED_1000MB_OVERRIDE |
				BNX2_EMAC_LED_100MB_OVERRIDE |
				BNX2_EMAC_LED_10MB_OVERRIDE |
				BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
				BNX2_EMAC_LED_TRAFFIC);
		}
		msleep_interruptible(500);
		if (signal_pending(current))
			break;
	}
	REG_WR(bp, BNX2_EMAC_LED, 0);
	REG_WR(bp, BNX2_MISC_CFG, save);
7377 7378 7379 7380

	if (!netif_running(dev))
		bnx2_set_power_state(bp, PCI_D3hot);

7381 7382 7383
	return 0;
}

7384 7385 7386 7387 7388 7389
static int
bnx2_set_tx_csum(struct net_device *dev, u32 data)
{
	struct bnx2 *bp = netdev_priv(dev);

	if (CHIP_NUM(bp) == CHIP_NUM_5709)
7390
		return (ethtool_op_set_tx_ipv6_csum(dev, data));
7391 7392 7393 7394
	else
		return (ethtool_op_set_tx_csum(dev, data));
}

7395
static const struct ethtool_ops bnx2_ethtool_ops = {
7396 7397 7398
	.get_settings		= bnx2_get_settings,
	.set_settings		= bnx2_set_settings,
	.get_drvinfo		= bnx2_get_drvinfo,
7399 7400
	.get_regs_len		= bnx2_get_regs_len,
	.get_regs		= bnx2_get_regs,
7401 7402 7403
	.get_wol		= bnx2_get_wol,
	.set_wol		= bnx2_set_wol,
	.nway_reset		= bnx2_nway_reset,
7404
	.get_link		= bnx2_get_link,
7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7415
	.get_eeprom_len		= bnx2_get_eeprom_len,
	.get_eeprom		= bnx2_get_eeprom,
	.set_eeprom		= bnx2_set_eeprom,
	.get_coalesce		= bnx2_get_coalesce,
	.set_coalesce		= bnx2_set_coalesce,
	.get_ringparam		= bnx2_get_ringparam,
	.set_ringparam		= bnx2_set_ringparam,
	.get_pauseparam		= bnx2_get_pauseparam,
	.set_pauseparam		= bnx2_set_pauseparam,
	.get_rx_csum		= bnx2_get_rx_csum,
	.set_rx_csum		= bnx2_set_rx_csum,
7416
	.set_tx_csum		= bnx2_set_tx_csum,
7417
	.set_sg			= ethtool_op_set_sg,
7418
	.set_tso		= bnx2_set_tso,
7419 7420 7421 7422
	.self_test		= bnx2_self_test,
	.get_strings		= bnx2_get_strings,
	.phys_id		= bnx2_phys_id,
	.get_ethtool_stats	= bnx2_get_ethtool_stats,
7423
	.get_sset_count		= bnx2_get_sset_count,
7424 7425 7426 7427 7428 7429
};

/* Called with rtnl_lock */
static int
bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
7430
	struct mii_ioctl_data *data = if_mii(ifr);
M
Michael Chan 已提交
7431
	struct bnx2 *bp = netdev_priv(dev);
7432 7433 7434 7435 7436 7437 7438 7439 7440 7441
	int err;

	switch(cmd) {
	case SIOCGMIIPHY:
		data->phy_id = bp->phy_addr;

		/* fallthru */
	case SIOCGMIIREG: {
		u32 mii_regval;

7442
		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7443 7444
			return -EOPNOTSUPP;

7445 7446 7447
		if (!netif_running(dev))
			return -EAGAIN;

7448
		spin_lock_bh(&bp->phy_lock);
7449
		err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7450
		spin_unlock_bh(&bp->phy_lock);
7451 7452 7453 7454 7455 7456 7457 7458 7459 7460

		data->val_out = mii_regval;

		return err;
	}

	case SIOCSMIIREG:
		if (!capable(CAP_NET_ADMIN))
			return -EPERM;

7461
		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7462 7463
			return -EOPNOTSUPP;

7464 7465 7466
		if (!netif_running(dev))
			return -EAGAIN;

7467
		spin_lock_bh(&bp->phy_lock);
7468
		err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7469
		spin_unlock_bh(&bp->phy_lock);
7470 7471 7472 7473 7474 7475 7476 7477 7478 7479 7480 7481 7482 7483 7484

		return err;

	default:
		/* do nothing */
		break;
	}
	return -EOPNOTSUPP;
}

/* Called with rtnl_lock */
static int
bnx2_change_mac_addr(struct net_device *dev, void *p)
{
	struct sockaddr *addr = p;
M
Michael Chan 已提交
7485
	struct bnx2 *bp = netdev_priv(dev);
7486

7487 7488 7489
	if (!is_valid_ether_addr(addr->sa_data))
		return -EINVAL;

7490 7491
	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
	if (netif_running(dev))
7492
		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7493 7494 7495 7496 7497 7498 7499 7500

	return 0;
}

/* Called with rtnl_lock */
static int
bnx2_change_mtu(struct net_device *dev, int new_mtu)
{
M
Michael Chan 已提交
7501
	struct bnx2 *bp = netdev_priv(dev);
7502 7503 7504 7505 7506 7507

	if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
		((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
		return -EINVAL;

	dev->mtu = new_mtu;
7508
	return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7509 7510 7511 7512 7513 7514
}

#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
static void
poll_bnx2(struct net_device *dev)
{
M
Michael Chan 已提交
7515
	struct bnx2 *bp = netdev_priv(dev);
7516
	int i;
7517

7518 7519 7520 7521 7522
	for (i = 0; i < bp->irq_nvecs; i++) {
		disable_irq(bp->irq_tbl[i].vector);
		bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
		enable_irq(bp->irq_tbl[i].vector);
	}
7523 7524 7525
}
#endif

7526 7527 7528 7529 7530 7531 7532 7533 7534 7535
static void __devinit
bnx2_get_5709_media(struct bnx2 *bp)
{
	u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
	u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
	u32 strap;

	if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
		return;
	else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7536
		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7537 7538 7539 7540 7541 7542 7543 7544 7545 7546 7547 7548 7549
		return;
	}

	if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
		strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
	else
		strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;

	if (PCI_FUNC(bp->pdev->devfn) == 0) {
		switch (strap) {
		case 0x4:
		case 0x5:
		case 0x6:
7550
			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7551 7552 7553 7554 7555 7556 7557
			return;
		}
	} else {
		switch (strap) {
		case 0x1:
		case 0x2:
		case 0x4:
7558
			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7559 7560 7561 7562 7563
			return;
		}
	}
}

7564 7565 7566 7567 7568 7569 7570 7571 7572
static void __devinit
bnx2_get_pci_speed(struct bnx2 *bp)
{
	u32 reg;

	reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
	if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
		u32 clkreg;

7573
		bp->flags |= BNX2_FLAG_PCIX;
7574 7575 7576 7577 7578 7579 7580 7581 7582 7583 7584 7585 7586 7587 7588 7589 7590 7591 7592 7593 7594 7595 7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611

		clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);

		clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
		switch (clkreg) {
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
			bp->bus_speed_mhz = 133;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
			bp->bus_speed_mhz = 100;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
			bp->bus_speed_mhz = 66;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
			bp->bus_speed_mhz = 50;
			break;

		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
		case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
			bp->bus_speed_mhz = 33;
			break;
		}
	}
	else {
		if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
			bp->bus_speed_mhz = 66;
		else
			bp->bus_speed_mhz = 33;
	}

	if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7612
		bp->flags |= BNX2_FLAG_PCI_32BIT;
7613 7614 7615

}

7616 7617 7618 7619 7620
static int __devinit
bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
{
	struct bnx2 *bp;
	unsigned long mem_len;
7621
	int rc, i, j;
7622
	u32 reg;
7623
	u64 dma_mask, persist_dma_mask;
7624 7625

	SET_NETDEV_DEV(dev, &pdev->dev);
M
Michael Chan 已提交
7626
	bp = netdev_priv(dev);
7627 7628 7629 7630 7631 7632 7633

	bp->flags = 0;
	bp->phy_flags = 0;

	/* enable device (incl. PCI PM wakeup), and bus-mastering */
	rc = pci_enable_device(pdev);
	if (rc) {
7634
		dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7635 7636 7637 7638
		goto err_out;
	}

	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7639
		dev_err(&pdev->dev,
7640
			"Cannot find PCI device base address, aborting.\n");
7641 7642 7643 7644 7645 7646
		rc = -ENODEV;
		goto err_out_disable;
	}

	rc = pci_request_regions(pdev, DRV_MODULE_NAME);
	if (rc) {
7647
		dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7648 7649 7650 7651
		goto err_out_disable;
	}

	pci_set_master(pdev);
W
Wendy Xiong 已提交
7652
	pci_save_state(pdev);
7653 7654 7655

	bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
	if (bp->pm_cap == 0) {
7656
		dev_err(&pdev->dev,
7657
			"Cannot find power management capability, aborting.\n");
7658 7659 7660 7661 7662 7663 7664 7665
		rc = -EIO;
		goto err_out_release;
	}

	bp->dev = dev;
	bp->pdev = pdev;

	spin_lock_init(&bp->phy_lock);
7666
	spin_lock_init(&bp->indirect_lock);
7667
	INIT_WORK(&bp->reset_task, bnx2_reset_task);
7668 7669

	dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7670
	mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7671 7672 7673 7674 7675 7676
	dev->mem_end = dev->mem_start + mem_len;
	dev->irq = pdev->irq;

	bp->regview = ioremap_nocache(dev->base_addr, mem_len);

	if (!bp->regview) {
7677
		dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7678 7679 7680 7681 7682 7683 7684 7685 7686 7687 7688 7689
		rc = -ENOMEM;
		goto err_out_release;
	}

	/* Configure byte swap and enable write to the reg_window registers.
	 * Rely on CPU to do target byte swapping on big endian systems
	 * The chip's target access swapping will not swap all accesses
	 */
	pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
			       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
			       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);

7690
	bnx2_set_power_state(bp, PCI_D0);
7691 7692 7693

	bp->chip_id = REG_RD(bp, BNX2_MISC_ID);

7694 7695 7696 7697 7698 7699 7700
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
		if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
			dev_err(&pdev->dev,
				"Cannot find PCIE capability, aborting.\n");
			rc = -EIO;
			goto err_out_unmap;
		}
7701
		bp->flags |= BNX2_FLAG_PCIE;
7702
		if (CHIP_REV(bp) == CHIP_REV_Ax)
7703
			bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7704
	} else {
7705 7706 7707 7708 7709 7710 7711 7712 7713
		bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
		if (bp->pcix_cap == 0) {
			dev_err(&pdev->dev,
				"Cannot find PCIX capability, aborting.\n");
			rc = -EIO;
			goto err_out_unmap;
		}
	}

7714 7715
	if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
		if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7716
			bp->flags |= BNX2_FLAG_MSIX_CAP;
7717 7718
	}

7719 7720
	if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
		if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7721
			bp->flags |= BNX2_FLAG_MSI_CAP;
7722 7723
	}

7724 7725
	/* 5708 cannot support DMA addresses > 40-bit.  */
	if (CHIP_NUM(bp) == CHIP_NUM_5708)
7726
		persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7727
	else
7728
		persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7729 7730 7731 7732 7733 7734 7735 7736 7737 7738

	/* Configure DMA attributes. */
	if (pci_set_dma_mask(pdev, dma_mask) == 0) {
		dev->features |= NETIF_F_HIGHDMA;
		rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
		if (rc) {
			dev_err(&pdev->dev,
				"pci_set_consistent_dma_mask failed, aborting.\n");
			goto err_out_unmap;
		}
7739
	} else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7740 7741 7742 7743
		dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
		goto err_out_unmap;
	}

7744
	if (!(bp->flags & BNX2_FLAG_PCIE))
7745
		bnx2_get_pci_speed(bp);
7746 7747 7748 7749 7750 7751 7752 7753

	/* 5706A0 may falsely detect SERR and PERR. */
	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		reg = REG_RD(bp, PCI_COMMAND);
		reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
		REG_WR(bp, PCI_COMMAND, reg);
	}
	else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7754
		!(bp->flags & BNX2_FLAG_PCIX)) {
7755

7756
		dev_err(&pdev->dev,
7757
			"5706 A1 can only be used in a PCIX bus, aborting.\n");
7758 7759 7760 7761 7762
		goto err_out_unmap;
	}

	bnx2_init_nvram(bp);

7763
	reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7764 7765

	if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7766 7767 7768
	    BNX2_SHM_HDR_SIGNATURE_SIG) {
		u32 off = PCI_FUNC(pdev->devfn) << 2;

7769
		bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7770
	} else
7771 7772
		bp->shmem_base = HOST_VIEW_SHMEM_BASE;

7773 7774 7775
	/* Get the permanent MAC address.  First we need to make sure the
	 * firmware is actually running.
	 */
7776
	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7777 7778 7779

	if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
	    BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7780
		dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7781 7782 7783 7784
		rc = -ENODEV;
		goto err_out_unmap;
	}

7785
	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7786 7787 7788 7789 7790 7791 7792 7793 7794 7795 7796 7797 7798
	for (i = 0, j = 0; i < 3; i++) {
		u8 num, k, skip0;

		num = (u8) (reg >> (24 - (i * 8)));
		for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
			if (num >= k || !skip0 || k == 1) {
				bp->fw_version[j++] = (num / k) + '0';
				skip0 = 0;
			}
		}
		if (i != 2)
			bp->fw_version[j++] = '.';
	}
7799
	reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7800 7801 7802 7803
	if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
		bp->wol = 1;

	if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7804
		bp->flags |= BNX2_FLAG_ASF_ENABLE;
7805 7806

		for (i = 0; i < 30; i++) {
7807
			reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7808 7809 7810 7811 7812
			if (reg & BNX2_CONDITION_MFW_RUN_MASK)
				break;
			msleep(10);
		}
	}
7813
	reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7814 7815 7816
	reg &= BNX2_CONDITION_MFW_RUN_MASK;
	if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
	    reg != BNX2_CONDITION_MFW_RUN_NONE) {
7817
		u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7818 7819 7820

		bp->fw_version[j++] = ' ';
		for (i = 0; i < 3; i++) {
7821
			reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7822 7823 7824 7825 7826
			reg = swab32(reg);
			memcpy(&bp->fw_version[j], &reg, 4);
			j += 4;
		}
	}
7827

7828
	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7829 7830 7831
	bp->mac_addr[0] = (u8) (reg >> 8);
	bp->mac_addr[1] = (u8) reg;

7832
	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7833 7834 7835 7836 7837 7838
	bp->mac_addr[2] = (u8) (reg >> 24);
	bp->mac_addr[3] = (u8) (reg >> 16);
	bp->mac_addr[4] = (u8) (reg >> 8);
	bp->mac_addr[5] = (u8) reg;

	bp->tx_ring_size = MAX_TX_DESC_CNT;
7839
	bnx2_set_rx_ring_size(bp, 255);
7840 7841 7842 7843 7844 7845 7846

	bp->rx_csum = 1;

	bp->tx_quick_cons_trip_int = 20;
	bp->tx_quick_cons_trip = 20;
	bp->tx_ticks_int = 80;
	bp->tx_ticks = 80;
7847

7848 7849 7850 7851 7852
	bp->rx_quick_cons_trip_int = 6;
	bp->rx_quick_cons_trip = 6;
	bp->rx_ticks_int = 18;
	bp->rx_ticks = 18;

7853
	bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7854

7855
	bp->current_interval = BNX2_TIMER_INTERVAL;
7856

7857 7858
	bp->phy_addr = 1;

7859
	/* Disable WOL support if we are running on a SERDES chip. */
7860 7861 7862
	if (CHIP_NUM(bp) == CHIP_NUM_5709)
		bnx2_get_5709_media(bp);
	else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7863
		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
M
Michael Chan 已提交
7864

7865
	bp->phy_port = PORT_TP;
7866
	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7867
		bp->phy_port = PORT_FIBRE;
7868
		reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7869
		if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7870
			bp->flags |= BNX2_FLAG_NO_WOL;
7871 7872
			bp->wol = 0;
		}
7873 7874 7875 7876 7877 7878 7879 7880 7881
		if (CHIP_NUM(bp) == CHIP_NUM_5706) {
			/* Don't do parallel detect on this board because of
			 * some board problems.  The link will not go down
			 * if we do parallel detect.
			 */
			if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
			    pdev->subsystem_device == 0x310c)
				bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
		} else {
7882 7883
			bp->phy_addr = 2;
			if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7884
				bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7885
		}
7886 7887
	} else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
		   CHIP_NUM(bp) == CHIP_NUM_5708)
7888
		bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7889 7890 7891
	else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
		 (CHIP_REV(bp) == CHIP_REV_Ax ||
		  CHIP_REV(bp) == CHIP_REV_Bx))
7892
		bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7893

7894 7895
	bnx2_init_fw_cap(bp);

7896 7897
	if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
	    (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7898 7899
	    (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
	    !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
7900
		bp->flags |= BNX2_FLAG_NO_WOL;
7901 7902
		bp->wol = 0;
	}
M
Michael Chan 已提交
7903

7904 7905 7906 7907 7908 7909 7910 7911 7912 7913 7914 7915
	if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
		bp->tx_quick_cons_trip_int =
			bp->tx_quick_cons_trip;
		bp->tx_ticks_int = bp->tx_ticks;
		bp->rx_quick_cons_trip_int =
			bp->rx_quick_cons_trip;
		bp->rx_ticks_int = bp->rx_ticks;
		bp->comp_prod_trip_int = bp->comp_prod_trip;
		bp->com_ticks_int = bp->com_ticks;
		bp->cmd_ticks_int = bp->cmd_ticks;
	}

7916 7917 7918 7919 7920 7921 7922 7923
	/* Disable MSI on 5706 if AMD 8132 bridge is found.
	 *
	 * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
	 * with byte enables disabled on the unused 32-bit word.  This is legal
	 * but causes problems on the AMD 8132 which will eventually stop
	 * responding after a while.
	 *
	 * AMD believes this incompatibility is unique to the 5706, and
7924
	 * prefers to locally disable MSI rather than globally disabling it.
7925 7926 7927 7928 7929 7930 7931 7932
	 */
	if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
		struct pci_dev *amd_8132 = NULL;

		while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
						  PCI_DEVICE_ID_AMD_8132_BRIDGE,
						  amd_8132))) {

7933 7934
			if (amd_8132->revision >= 0x10 &&
			    amd_8132->revision <= 0x13) {
7935 7936 7937 7938 7939 7940 7941
				disable_msi = 1;
				pci_dev_put(amd_8132);
				break;
			}
		}
	}

7942
	bnx2_set_default_link(bp);
7943 7944
	bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;

7945
	init_timer(&bp->timer);
7946
	bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7947 7948 7949
	bp->timer.data = (unsigned long) bp;
	bp->timer.function = bnx2_timer;

7950 7951 7952 7953 7954
	return 0;

err_out_unmap:
	if (bp->regview) {
		iounmap(bp->regview);
7955
		bp->regview = NULL;
7956 7957 7958 7959 7960 7961 7962 7963 7964 7965 7966 7967 7968
	}

err_out_release:
	pci_release_regions(pdev);

err_out_disable:
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);

err_out:
	return rc;
}

7969 7970 7971 7972 7973
static char * __devinit
bnx2_bus_string(struct bnx2 *bp, char *str)
{
	char *s = str;

7974
	if (bp->flags & BNX2_FLAG_PCIE) {
7975 7976 7977
		s += sprintf(s, "PCI Express");
	} else {
		s += sprintf(s, "PCI");
7978
		if (bp->flags & BNX2_FLAG_PCIX)
7979
			s += sprintf(s, "-X");
7980
		if (bp->flags & BNX2_FLAG_PCI_32BIT)
7981 7982 7983 7984 7985 7986 7987 7988
			s += sprintf(s, " 32-bit");
		else
			s += sprintf(s, " 64-bit");
		s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
	}
	return str;
}

7989
static void __devinit
7990 7991
bnx2_init_napi(struct bnx2 *bp)
{
7992
	int i;
7993

7994
	for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7995 7996 7997 7998 7999 8000
		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
		int (*poll)(struct napi_struct *, int);

		if (i == 0)
			poll = bnx2_poll;
		else
8001
			poll = bnx2_poll_msix;
8002 8003

		netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8004 8005
		bnapi->bp = bp;
	}
8006 8007
}

8008 8009 8010 8011 8012 8013 8014 8015 8016 8017 8018 8019 8020 8021 8022 8023 8024 8025 8026
static const struct net_device_ops bnx2_netdev_ops = {
	.ndo_open		= bnx2_open,
	.ndo_start_xmit		= bnx2_start_xmit,
	.ndo_stop		= bnx2_close,
	.ndo_get_stats		= bnx2_get_stats,
	.ndo_set_rx_mode	= bnx2_set_rx_mode,
	.ndo_do_ioctl		= bnx2_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_set_mac_address	= bnx2_change_mac_addr,
	.ndo_change_mtu		= bnx2_change_mtu,
	.ndo_tx_timeout		= bnx2_tx_timeout,
#ifdef BCM_VLAN
	.ndo_vlan_rx_register	= bnx2_vlan_rx_register,
#endif
#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
	.ndo_poll_controller	= poll_bnx2,
#endif
};

E
Eric Dumazet 已提交
8027 8028 8029 8030 8031 8032 8033
static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
{
#ifdef BCM_VLAN
	dev->vlan_features |= flags;
#endif
}

8034 8035 8036 8037 8038 8039
static int __devinit
bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int version_printed = 0;
	struct net_device *dev = NULL;
	struct bnx2 *bp;
8040
	int rc;
8041
	char str[40];
8042 8043 8044 8045 8046

	if (version_printed++ == 0)
		printk(KERN_INFO "%s", version);

	/* dev zeroed in init_etherdev */
8047
	dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8048 8049 8050 8051 8052 8053 8054 8055 8056 8057

	if (!dev)
		return -ENOMEM;

	rc = bnx2_init_board(pdev, dev);
	if (rc < 0) {
		free_netdev(dev);
		return rc;
	}

8058
	dev->netdev_ops = &bnx2_netdev_ops;
8059 8060 8061
	dev->watchdog_timeo = TX_TIMEOUT;
	dev->ethtool_ops = &bnx2_ethtool_ops;

M
Michael Chan 已提交
8062
	bp = netdev_priv(dev);
8063
	bnx2_init_napi(bp);
8064

8065 8066
	pci_set_drvdata(pdev, dev);

8067 8068 8069 8070
	rc = bnx2_request_firmware(bp);
	if (rc)
		goto error;

8071 8072 8073
	memcpy(dev->dev_addr, bp->mac_addr, 6);
	memcpy(dev->perm_addr, bp->mac_addr, 6);

8074
	dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
E
Eric Dumazet 已提交
8075 8076
	vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8077
		dev->features |= NETIF_F_IPV6_CSUM;
E
Eric Dumazet 已提交
8078 8079
		vlan_features_add(dev, NETIF_F_IPV6_CSUM);
	}
8080 8081 8082 8083
#ifdef BCM_VLAN
	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
#endif
	dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
E
Eric Dumazet 已提交
8084 8085
	vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
	if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8086
		dev->features |= NETIF_F_TSO6;
E
Eric Dumazet 已提交
8087 8088
		vlan_features_add(dev, NETIF_F_TSO6);
	}
8089
	if ((rc = register_netdev(dev))) {
8090
		dev_err(&pdev->dev, "Cannot register net device\n");
8091
		goto error;
8092 8093
	}

8094
	printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
8095
		"IRQ %d, node addr %pM\n",
8096
		dev->name,
8097
		board_info[ent->driver_data].name,
8098 8099
		((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
		((CHIP_ID(bp) & 0x0ff0) >> 4),
8100
		bnx2_bus_string(bp, str),
8101
		dev->base_addr,
8102
		bp->pdev->irq, dev->dev_addr);
8103 8104

	return 0;
8105 8106 8107 8108 8109 8110 8111 8112 8113 8114 8115 8116 8117 8118

error:
	if (bp->mips_firmware)
		release_firmware(bp->mips_firmware);
	if (bp->rv2p_firmware)
		release_firmware(bp->rv2p_firmware);

	if (bp->regview)
		iounmap(bp->regview);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);
	free_netdev(dev);
	return rc;
8119 8120 8121 8122 8123 8124
}

static void __devexit
bnx2_remove_one(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
M
Michael Chan 已提交
8125
	struct bnx2 *bp = netdev_priv(dev);
8126

8127 8128
	flush_scheduled_work();

8129 8130
	unregister_netdev(dev);

8131 8132 8133 8134 8135
	if (bp->mips_firmware)
		release_firmware(bp->mips_firmware);
	if (bp->rv2p_firmware)
		release_firmware(bp->rv2p_firmware);

8136 8137 8138 8139 8140 8141 8142 8143 8144 8145
	if (bp->regview)
		iounmap(bp->regview);

	free_netdev(dev);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);
}

static int
8146
bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8147 8148
{
	struct net_device *dev = pci_get_drvdata(pdev);
M
Michael Chan 已提交
8149
	struct bnx2 *bp = netdev_priv(dev);
8150

8151 8152 8153 8154 8155
	/* PCI register 4 needs to be saved whether netif_running() or not.
	 * MSI address and data need to be saved if using MSI and
	 * netif_running().
	 */
	pci_save_state(pdev);
8156 8157 8158
	if (!netif_running(dev))
		return 0;

M
Michael Chan 已提交
8159
	flush_scheduled_work();
8160 8161 8162
	bnx2_netif_stop(bp);
	netif_device_detach(dev);
	del_timer_sync(&bp->timer);
8163
	bnx2_shutdown_chip(bp);
8164
	bnx2_free_skbs(bp);
8165
	bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8166 8167 8168 8169 8170 8171 8172
	return 0;
}

static int
bnx2_resume(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
M
Michael Chan 已提交
8173
	struct bnx2 *bp = netdev_priv(dev);
8174

8175
	pci_restore_state(pdev);
8176 8177 8178
	if (!netif_running(dev))
		return 0;

8179
	bnx2_set_power_state(bp, PCI_D0);
8180
	netif_device_attach(dev);
8181
	bnx2_init_nic(bp, 1);
8182 8183 8184 8185
	bnx2_netif_start(bp);
	return 0;
}

W
Wendy Xiong 已提交
8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 8201 8202
/**
 * bnx2_io_error_detected - called when PCI error is detected
 * @pdev: Pointer to PCI device
 * @state: The current pci connection state
 *
 * This function is called after a PCI bus error affecting
 * this device has been detected.
 */
static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
					       pci_channel_state_t state)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2 *bp = netdev_priv(dev);

	rtnl_lock();
	netif_device_detach(dev);

8203 8204 8205 8206 8207
	if (state == pci_channel_io_perm_failure) {
		rtnl_unlock();
		return PCI_ERS_RESULT_DISCONNECT;
	}

W
Wendy Xiong 已提交
8208 8209 8210 8211 8212 8213 8214 8215 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225 8226 8227 8228 8229 8230 8231 8232 8233 8234 8235 8236 8237 8238 8239 8240 8241 8242 8243 8244 8245 8246 8247 8248 8249 8250 8251 8252 8253 8254 8255 8256 8257 8258 8259 8260 8261 8262 8263 8264 8265 8266 8267 8268 8269 8270 8271 8272 8273 8274 8275 8276
	if (netif_running(dev)) {
		bnx2_netif_stop(bp);
		del_timer_sync(&bp->timer);
		bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
	}

	pci_disable_device(pdev);
	rtnl_unlock();

	/* Request a slot slot reset. */
	return PCI_ERS_RESULT_NEED_RESET;
}

/**
 * bnx2_io_slot_reset - called after the pci bus has been reset.
 * @pdev: Pointer to PCI device
 *
 * Restart the card from scratch, as if from a cold-boot.
 */
static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2 *bp = netdev_priv(dev);

	rtnl_lock();
	if (pci_enable_device(pdev)) {
		dev_err(&pdev->dev,
			"Cannot re-enable PCI device after reset.\n");
		rtnl_unlock();
		return PCI_ERS_RESULT_DISCONNECT;
	}
	pci_set_master(pdev);
	pci_restore_state(pdev);

	if (netif_running(dev)) {
		bnx2_set_power_state(bp, PCI_D0);
		bnx2_init_nic(bp, 1);
	}

	rtnl_unlock();
	return PCI_ERS_RESULT_RECOVERED;
}

/**
 * bnx2_io_resume - called when traffic can start flowing again.
 * @pdev: Pointer to PCI device
 *
 * This callback is called when the error recovery driver tells us that
 * its OK to resume normal operation.
 */
static void bnx2_io_resume(struct pci_dev *pdev)
{
	struct net_device *dev = pci_get_drvdata(pdev);
	struct bnx2 *bp = netdev_priv(dev);

	rtnl_lock();
	if (netif_running(dev))
		bnx2_netif_start(bp);

	netif_device_attach(dev);
	rtnl_unlock();
}

static struct pci_error_handlers bnx2_err_handler = {
	.error_detected	= bnx2_io_error_detected,
	.slot_reset	= bnx2_io_slot_reset,
	.resume		= bnx2_io_resume,
};

8277
static struct pci_driver bnx2_pci_driver = {
8278 8279 8280 8281 8282 8283
	.name		= DRV_MODULE_NAME,
	.id_table	= bnx2_pci_tbl,
	.probe		= bnx2_init_one,
	.remove		= __devexit_p(bnx2_remove_one),
	.suspend	= bnx2_suspend,
	.resume		= bnx2_resume,
W
Wendy Xiong 已提交
8284
	.err_handler	= &bnx2_err_handler,
8285 8286 8287 8288
};

static int __init bnx2_init(void)
{
8289
	return pci_register_driver(&bnx2_pci_driver);
8290 8291 8292 8293 8294 8295 8296 8297 8298 8299 8300 8301
}

static void __exit bnx2_cleanup(void)
{
	pci_unregister_driver(&bnx2_pci_driver);
}

module_init(bnx2_init);
module_exit(bnx2_cleanup);


新手
引导
客服 返回
顶部