helper.c 74.6 KB
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#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "cpu.h"
#include "exec-all.h"
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#include "gdbstub.h"
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#include "helpers.h"
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#include "qemu-common.h"
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#include "host-utils.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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static uint32_t cortexa9_cp15_c0_c1[8] =
{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };

static uint32_t cortexa9_cp15_c0_c2[8] =
{ 0x00101111, 0x13112111, 0x21232041, 0x11112131, 0x00111142, 0, 0, 0 };

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static uint32_t cortexa8_cp15_c0_c1[8] =
{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };

static uint32_t cortexa8_cp15_c0_c2[8] =
{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };

static uint32_t mpcore_cp15_c0_c1[8] =
{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };

static uint32_t mpcore_cp15_c0_c2[8] =
{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };

static uint32_t arm1136_cp15_c0_c1[8] =
{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };

static uint32_t arm1136_cp15_c0_c2[8] =
{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
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static uint32_t cpu_arm_find_by_name(const char *name);

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static inline void set_feature(CPUARMState *env, int feature)
{
    env->features |= 1u << feature;
}

static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
    env->cp15.c0_cpuid = id;
    switch (id) {
    case ARM_CPUID_ARM926:
        set_feature(env, ARM_FEATURE_VFP);
        env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
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        env->cp15.c0_cachetype = 0x1dd20d2;
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        env->cp15.c1_sys = 0x00090078;
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        break;
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    case ARM_CPUID_ARM946:
        set_feature(env, ARM_FEATURE_MPU);
        env->cp15.c0_cachetype = 0x0f004006;
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        env->cp15.c1_sys = 0x00000078;
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        break;
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    case ARM_CPUID_ARM1026:
        set_feature(env, ARM_FEATURE_VFP);
        set_feature(env, ARM_FEATURE_AUXCR);
        env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
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        env->cp15.c0_cachetype = 0x1dd20d2;
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        env->cp15.c1_sys = 0x00090078;
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        break;
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    case ARM_CPUID_ARM1136_R2:
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    case ARM_CPUID_ARM1136:
        set_feature(env, ARM_FEATURE_V6);
        set_feature(env, ARM_FEATURE_VFP);
        set_feature(env, ARM_FEATURE_AUXCR);
        env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
        env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
        env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
        memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
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        memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
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        env->cp15.c0_cachetype = 0x1dd20d2;
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        env->cp15.c1_sys = 0x00050078;
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        break;
    case ARM_CPUID_ARM11MPCORE:
        set_feature(env, ARM_FEATURE_V6);
        set_feature(env, ARM_FEATURE_V6K);
        set_feature(env, ARM_FEATURE_VFP);
        set_feature(env, ARM_FEATURE_AUXCR);
        env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
        env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
        env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
        memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
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        memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
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        env->cp15.c0_cachetype = 0x1dd20d2;
        break;
    case ARM_CPUID_CORTEXA8:
        set_feature(env, ARM_FEATURE_V6);
        set_feature(env, ARM_FEATURE_V6K);
        set_feature(env, ARM_FEATURE_V7);
        set_feature(env, ARM_FEATURE_AUXCR);
        set_feature(env, ARM_FEATURE_THUMB2);
        set_feature(env, ARM_FEATURE_VFP);
        set_feature(env, ARM_FEATURE_VFP3);
        set_feature(env, ARM_FEATURE_NEON);
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        set_feature(env, ARM_FEATURE_THUMB2EE);
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        env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
        env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
        env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
        memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
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        memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
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        env->cp15.c0_cachetype = 0x82048004;
        env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
        env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
        env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
        env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
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        env->cp15.c1_sys = 0x00c50078;
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        break;
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    case ARM_CPUID_CORTEXA9:
        set_feature(env, ARM_FEATURE_V6);
        set_feature(env, ARM_FEATURE_V6K);
        set_feature(env, ARM_FEATURE_V7);
        set_feature(env, ARM_FEATURE_AUXCR);
        set_feature(env, ARM_FEATURE_THUMB2);
        set_feature(env, ARM_FEATURE_VFP);
        set_feature(env, ARM_FEATURE_VFP3);
        set_feature(env, ARM_FEATURE_VFP_FP16);
        set_feature(env, ARM_FEATURE_NEON);
        set_feature(env, ARM_FEATURE_THUMB2EE);
        env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
        env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
        env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
        memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
        memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
        env->cp15.c0_cachetype = 0x80038003;
        env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
        env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
        env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
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        env->cp15.c1_sys = 0x00c50078;
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        break;
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    case ARM_CPUID_CORTEXM3:
        set_feature(env, ARM_FEATURE_V6);
        set_feature(env, ARM_FEATURE_THUMB2);
        set_feature(env, ARM_FEATURE_V7);
        set_feature(env, ARM_FEATURE_M);
        set_feature(env, ARM_FEATURE_DIV);
        break;
    case ARM_CPUID_ANY: /* For userspace emulation.  */
        set_feature(env, ARM_FEATURE_V6);
        set_feature(env, ARM_FEATURE_V6K);
        set_feature(env, ARM_FEATURE_V7);
        set_feature(env, ARM_FEATURE_THUMB2);
        set_feature(env, ARM_FEATURE_VFP);
        set_feature(env, ARM_FEATURE_VFP3);
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        set_feature(env, ARM_FEATURE_VFP_FP16);
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        set_feature(env, ARM_FEATURE_NEON);
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        set_feature(env, ARM_FEATURE_THUMB2EE);
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        set_feature(env, ARM_FEATURE_DIV);
        break;
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    case ARM_CPUID_TI915T:
    case ARM_CPUID_TI925T:
        set_feature(env, ARM_FEATURE_OMAPCP);
        env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring.  */
        env->cp15.c0_cachetype = 0x5109149;
        env->cp15.c1_sys = 0x00000070;
        env->cp15.c15_i_max = 0x000;
        env->cp15.c15_i_min = 0xff0;
        break;
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    case ARM_CPUID_PXA250:
    case ARM_CPUID_PXA255:
    case ARM_CPUID_PXA260:
    case ARM_CPUID_PXA261:
    case ARM_CPUID_PXA262:
        set_feature(env, ARM_FEATURE_XSCALE);
        /* JTAG_ID is ((id << 28) | 0x09265013) */
        env->cp15.c0_cachetype = 0xd172172;
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        env->cp15.c1_sys = 0x00000078;
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        break;
    case ARM_CPUID_PXA270_A0:
    case ARM_CPUID_PXA270_A1:
    case ARM_CPUID_PXA270_B0:
    case ARM_CPUID_PXA270_B1:
    case ARM_CPUID_PXA270_C0:
    case ARM_CPUID_PXA270_C5:
        set_feature(env, ARM_FEATURE_XSCALE);
        /* JTAG_ID is ((id << 28) | 0x09265013) */
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        set_feature(env, ARM_FEATURE_IWMMXT);
        env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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        env->cp15.c0_cachetype = 0xd172172;
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        env->cp15.c1_sys = 0x00000078;
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        break;
    default:
        cpu_abort(env, "Bad CPU ID: %x\n", id);
        break;
    }
}

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void cpu_reset(CPUARMState *env)
{
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    uint32_t id;
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    if (qemu_loglevel_mask(CPU_LOG_RESET)) {
        qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
        log_cpu_state(env, 0);
    }

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    id = env->cp15.c0_cpuid;
    memset(env, 0, offsetof(CPUARMState, breakpoints));
    if (id)
        cpu_reset_model_id(env, id);
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#if defined (CONFIG_USER_ONLY)
    env->uncached_cpsr = ARM_CPU_MODE_USR;
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    /* For user mode we must enable access to coprocessors */
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    env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
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    if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
        env->cp15.c15_cpar = 3;
    } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
        env->cp15.c15_cpar = 1;
    }
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#else
    /* SVC mode with interrupts disabled.  */
    env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
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    /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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       clear at reset.  Initial SP and PC are loaded from ROM.  */
    if (IS_M(env)) {
        uint32_t pc;
        uint8_t *rom;
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        env->uncached_cpsr &= ~CPSR_I;
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        rom = rom_ptr(0);
        if (rom) {
            /* We should really use ldl_phys here, in case the guest
               modified flash and reset itself.  However images
               loaded via -kenrel have not been copied yet, so load the
               values directly from there.  */
            env->regs[13] = ldl_p(rom);
            pc = ldl_p(rom + 4);
            env->thumb = pc & 1;
            env->regs[15] = pc & ~1;
        }
    }
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    env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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    env->cp15.c2_base_mask = 0xffffc000u;
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#endif
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    set_flush_to_zero(1, &env->vfp.standard_fp_status);
    set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
    set_default_nan_mode(1, &env->vfp.standard_fp_status);
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    tlb_flush(env, 1);
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}

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static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
{
    int nregs;

    /* VFP data registers are always little-endian.  */
    nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
    if (reg < nregs) {
        stfq_le_p(buf, env->vfp.regs[reg]);
        return 8;
    }
    if (arm_feature(env, ARM_FEATURE_NEON)) {
        /* Aliases for Q regs.  */
        nregs += 16;
        if (reg < nregs) {
            stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
            stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
            return 16;
        }
    }
    switch (reg - nregs) {
    case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
    case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
    case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
    }
    return 0;
}

static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
{
    int nregs;

    nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
    if (reg < nregs) {
        env->vfp.regs[reg] = ldfq_le_p(buf);
        return 8;
    }
    if (arm_feature(env, ARM_FEATURE_NEON)) {
        nregs += 16;
        if (reg < nregs) {
            env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
            env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
            return 16;
        }
    }
    switch (reg - nregs) {
    case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
    case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
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    case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
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    }
    return 0;
}

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CPUARMState *cpu_arm_init(const char *cpu_model)
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{
    CPUARMState *env;
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    uint32_t id;
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    static int inited = 0;
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    id = cpu_arm_find_by_name(cpu_model);
    if (id == 0)
        return NULL;
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    env = qemu_mallocz(sizeof(CPUARMState));
    cpu_exec_init(env);
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    if (!inited) {
        inited = 1;
        arm_translate_init();
    }

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    env->cpu_model_str = cpu_model;
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    env->cp15.c0_cpuid = id;
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    cpu_reset(env);
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    if (arm_feature(env, ARM_FEATURE_NEON)) {
        gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
                                 51, "arm-neon.xml", 0);
    } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
        gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
                                 35, "arm-vfp3.xml", 0);
    } else if (arm_feature(env, ARM_FEATURE_VFP)) {
        gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
                                 19, "arm-vfp.xml", 0);
    }
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    qemu_init_vcpu(env);
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    return env;
}

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struct arm_cpu_t {
    uint32_t id;
    const char *name;
};

static const struct arm_cpu_t arm_cpu_names[] = {
    { ARM_CPUID_ARM926, "arm926"},
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    { ARM_CPUID_ARM946, "arm946"},
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    { ARM_CPUID_ARM1026, "arm1026"},
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    { ARM_CPUID_ARM1136, "arm1136"},
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    { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
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    { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
    { ARM_CPUID_CORTEXM3, "cortex-m3"},
    { ARM_CPUID_CORTEXA8, "cortex-a8"},
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    { ARM_CPUID_CORTEXA9, "cortex-a9"},
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    { ARM_CPUID_TI925T, "ti925t" },
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    { ARM_CPUID_PXA250, "pxa250" },
    { ARM_CPUID_PXA255, "pxa255" },
    { ARM_CPUID_PXA260, "pxa260" },
    { ARM_CPUID_PXA261, "pxa261" },
    { ARM_CPUID_PXA262, "pxa262" },
    { ARM_CPUID_PXA270, "pxa270" },
    { ARM_CPUID_PXA270_A0, "pxa270-a0" },
    { ARM_CPUID_PXA270_A1, "pxa270-a1" },
    { ARM_CPUID_PXA270_B0, "pxa270-b0" },
    { ARM_CPUID_PXA270_B1, "pxa270-b1" },
    { ARM_CPUID_PXA270_C0, "pxa270-c0" },
    { ARM_CPUID_PXA270_C5, "pxa270-c5" },
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    { ARM_CPUID_ANY, "any"},
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    { 0, NULL}
};

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void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
    int i;

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    (*cpu_fprintf)(f, "Available CPUs:\n");
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    for (i = 0; arm_cpu_names[i].name; i++) {
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        (*cpu_fprintf)(f, "  %s\n", arm_cpu_names[i].name);
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    }
}

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/* return 0 if not found */
static uint32_t cpu_arm_find_by_name(const char *name)
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{
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    int i;
    uint32_t id;

    id = 0;
    for (i = 0; arm_cpu_names[i].name; i++) {
        if (strcmp(name, arm_cpu_names[i].name) == 0) {
            id = arm_cpu_names[i].id;
            break;
        }
    }
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    return id;
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}

void cpu_arm_close(CPUARMState *env)
{
    free(env);
}

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uint32_t cpsr_read(CPUARMState *env)
{
    int ZF;
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    ZF = (env->ZF == 0);
    return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
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        (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
        | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
        | ((env->condexec_bits & 0xfc) << 8)
        | (env->GE << 16);
}

void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
{
    if (mask & CPSR_NZCV) {
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        env->ZF = (~val) & CPSR_Z;
        env->NF = val;
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        env->CF = (val >> 29) & 1;
        env->VF = (val << 3) & 0x80000000;
    }
    if (mask & CPSR_Q)
        env->QF = ((val & CPSR_Q) != 0);
    if (mask & CPSR_T)
        env->thumb = ((val & CPSR_T) != 0);
    if (mask & CPSR_IT_0_1) {
        env->condexec_bits &= ~3;
        env->condexec_bits |= (val >> 25) & 3;
    }
    if (mask & CPSR_IT_2_7) {
        env->condexec_bits &= 3;
        env->condexec_bits |= (val >> 8) & 0xfc;
    }
    if (mask & CPSR_GE) {
        env->GE = (val >> 16) & 0xf;
    }

    if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
        switch_mode(env, val & CPSR_M);
    }
    mask &= ~CACHED_CPSR_BITS;
    env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
}

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/* Sign/zero extend */
uint32_t HELPER(sxtb16)(uint32_t x)
{
    uint32_t res;
    res = (uint16_t)(int8_t)x;
    res |= (uint32_t)(int8_t)(x >> 16) << 16;
    return res;
}

uint32_t HELPER(uxtb16)(uint32_t x)
{
    uint32_t res;
    res = (uint16_t)(uint8_t)x;
    res |= (uint32_t)(uint8_t)(x >> 16) << 16;
    return res;
}

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uint32_t HELPER(clz)(uint32_t x)
{
455
    return clz32(x);
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}

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int32_t HELPER(sdiv)(int32_t num, int32_t den)
{
    if (den == 0)
      return 0;
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    if (num == INT_MIN && den == -1)
      return INT_MIN;
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    return num / den;
}

uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
{
    if (den == 0)
      return 0;
    return num / den;
}

uint32_t HELPER(rbit)(uint32_t x)
{
    x =  ((x & 0xff000000) >> 24)
       | ((x & 0x00ff0000) >> 8)
       | ((x & 0x0000ff00) << 8)
       | ((x & 0x000000ff) << 24);
    x =  ((x & 0xf0f0f0f0) >> 4)
       | ((x & 0x0f0f0f0f) << 4);
    x =  ((x & 0x88888888) >> 3)
       | ((x & 0x44444444) >> 1)
       | ((x & 0x22222222) << 1)
       | ((x & 0x11111111) << 3);
    return x;
}

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uint32_t HELPER(abs)(uint32_t x)
{
    return ((int32_t)x < 0) ? -x : x;
}

494
#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
{
    env->exception_index = -1;
}

int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
502
                              int mmu_idx, int is_softmmu)
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{
    if (rw == 2) {
        env->exception_index = EXCP_PREFETCH_ABORT;
        env->cp15.c6_insn = address;
    } else {
        env->exception_index = EXCP_DATA_ABORT;
        env->cp15.c6_data = address;
    }
    return 1;
}

/* These should probably raise undefined insn exceptions.  */
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void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
516 517 518 519 520 521
{
    int op1 = (insn >> 8) & 0xf;
    cpu_abort(env, "cp%i insn %08x\n", op1, insn);
    return;
}

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uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
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{
    int op1 = (insn >> 8) & 0xf;
    cpu_abort(env, "cp%i insn %08x\n", op1, insn);
    return 0;
}

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void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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{
    cpu_abort(env, "cp15 insn %08x\n", insn);
}

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uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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{
    cpu_abort(env, "cp15 insn %08x\n", insn);
}

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/* These should probably raise undefined insn exceptions.  */
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void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
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{
    cpu_abort(env, "v7m_mrs %d\n", reg);
}

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uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
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{
    cpu_abort(env, "v7m_mrs %d\n", reg);
    return 0;
}

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void switch_mode(CPUState *env, int mode)
{
    if (mode != ARM_CPU_MODE_USR)
        cpu_abort(env, "Tried to switch out of user mode\n");
}

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void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
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{
    cpu_abort(env, "banked r13 write\n");
}

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uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
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{
    cpu_abort(env, "banked r13 read\n");
    return 0;
}

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#else

570 571
extern int semihosting_enabled;

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/* Map CPU modes onto saved register banks.  */
static inline int bank_number (int mode)
{
    switch (mode) {
    case ARM_CPU_MODE_USR:
    case ARM_CPU_MODE_SYS:
        return 0;
    case ARM_CPU_MODE_SVC:
        return 1;
    case ARM_CPU_MODE_ABT:
        return 2;
    case ARM_CPU_MODE_UND:
        return 3;
    case ARM_CPU_MODE_IRQ:
        return 4;
    case ARM_CPU_MODE_FIQ:
        return 5;
    }
    cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
    return -1;
}

void switch_mode(CPUState *env, int mode)
{
    int old_mode;
    int i;

    old_mode = env->uncached_cpsr & CPSR_M;
    if (mode == old_mode)
        return;

    if (old_mode == ARM_CPU_MODE_FIQ) {
        memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
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        memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
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    } else if (mode == ARM_CPU_MODE_FIQ) {
        memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
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        memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
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    }

    i = bank_number(old_mode);
    env->banked_r13[i] = env->regs[13];
    env->banked_r14[i] = env->regs[14];
    env->banked_spsr[i] = env->spsr;

    i = bank_number(mode);
    env->regs[13] = env->banked_r13[i];
    env->regs[14] = env->banked_r14[i];
    env->spsr = env->banked_spsr[i];
}

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static void v7m_push(CPUARMState *env, uint32_t val)
{
    env->regs[13] -= 4;
    stl_phys(env->regs[13], val);
}

static uint32_t v7m_pop(CPUARMState *env)
{
    uint32_t val;
    val = ldl_phys(env->regs[13]);
    env->regs[13] += 4;
    return val;
}

/* Switch to V7M main or process stack pointer.  */
static void switch_v7m_sp(CPUARMState *env, int process)
{
    uint32_t tmp;
    if (env->v7m.current_sp != process) {
        tmp = env->v7m.other_sp;
        env->v7m.other_sp = env->regs[13];
        env->regs[13] = tmp;
        env->v7m.current_sp = process;
    }
}

static void do_v7m_exception_exit(CPUARMState *env)
{
    uint32_t type;
    uint32_t xpsr;

    type = env->regs[15];
    if (env->v7m.exception != 0)
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        armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
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    /* Switch to the target stack.  */
    switch_v7m_sp(env, (type & 4) != 0);
    /* Pop registers.  */
    env->regs[0] = v7m_pop(env);
    env->regs[1] = v7m_pop(env);
    env->regs[2] = v7m_pop(env);
    env->regs[3] = v7m_pop(env);
    env->regs[12] = v7m_pop(env);
    env->regs[14] = v7m_pop(env);
    env->regs[15] = v7m_pop(env);
    xpsr = v7m_pop(env);
    xpsr_write(env, xpsr, 0xfffffdff);
    /* Undo stack alignment.  */
    if (xpsr & 0x200)
        env->regs[13] |= 4;
    /* ??? The exception return type specifies Thread/Handler mode.  However
       this is also implied by the xPSR value. Not sure what to do
       if there is a mismatch.  */
    /* ??? Likewise for mismatches between the CONTROL register and the stack
       pointer.  */
}

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static void do_interrupt_v7m(CPUARMState *env)
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{
    uint32_t xpsr = xpsr_read(env);
    uint32_t lr;
    uint32_t addr;

    lr = 0xfffffff1;
    if (env->v7m.current_sp)
        lr |= 4;
    if (env->v7m.exception == 0)
        lr |= 8;

    /* For exceptions we just mark as pending on the NVIC, and let that
       handle it.  */
    /* TODO: Need to escalate if the current priority is higher than the
       one we're raising.  */
    switch (env->exception_index) {
    case EXCP_UDEF:
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        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
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        return;
    case EXCP_SWI:
        env->regs[15] += 2;
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        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
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        return;
    case EXCP_PREFETCH_ABORT:
    case EXCP_DATA_ABORT:
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        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
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        return;
    case EXCP_BKPT:
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        if (semihosting_enabled) {
            int nr;
            nr = lduw_code(env->regs[15]) & 0xff;
            if (nr == 0xab) {
                env->regs[15] += 2;
                env->regs[0] = do_arm_semihosting(env);
                return;
            }
        }
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        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
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        return;
    case EXCP_IRQ:
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        env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
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        break;
    case EXCP_EXCEPTION_EXIT:
        do_v7m_exception_exit(env);
        return;
    default:
        cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
        return; /* Never happens.  Keep compiler happy.  */
    }

    /* Align stack pointer.  */
    /* ??? Should only do this if Configuration Control Register
       STACKALIGN bit is set.  */
    if (env->regs[13] & 4) {
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        env->regs[13] -= 4;
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        xpsr |= 0x200;
    }
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    /* Switch to the handler mode.  */
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    v7m_push(env, xpsr);
    v7m_push(env, env->regs[15]);
    v7m_push(env, env->regs[14]);
    v7m_push(env, env->regs[12]);
    v7m_push(env, env->regs[3]);
    v7m_push(env, env->regs[2]);
    v7m_push(env, env->regs[1]);
    v7m_push(env, env->regs[0]);
    switch_v7m_sp(env, 0);
    env->uncached_cpsr &= ~CPSR_IT;
    env->regs[14] = lr;
    addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
    env->regs[15] = addr & 0xfffffffe;
    env->thumb = addr & 1;
}

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/* Handle a CPU exception.  */
void do_interrupt(CPUARMState *env)
{
    uint32_t addr;
    uint32_t mask;
    int new_mode;
    uint32_t offset;

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    if (IS_M(env)) {
        do_interrupt_v7m(env);
        return;
    }
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    /* TODO: Vectored interrupt controller.  */
    switch (env->exception_index) {
    case EXCP_UDEF:
        new_mode = ARM_CPU_MODE_UND;
        addr = 0x04;
        mask = CPSR_I;
        if (env->thumb)
            offset = 2;
        else
            offset = 4;
        break;
    case EXCP_SWI:
778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793
        if (semihosting_enabled) {
            /* Check for semihosting interrupt.  */
            if (env->thumb) {
                mask = lduw_code(env->regs[15] - 2) & 0xff;
            } else {
                mask = ldl_code(env->regs[15] - 4) & 0xffffff;
            }
            /* Only intercept calls from privileged modes, to provide some
               semblance of security.  */
            if (((mask == 0x123456 && !env->thumb)
                    || (mask == 0xab && env->thumb))
                  && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
                env->regs[0] = do_arm_semihosting(env);
                return;
            }
        }
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        new_mode = ARM_CPU_MODE_SVC;
        addr = 0x08;
        mask = CPSR_I;
797
        /* The PC already points to the next instruction.  */
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        offset = 0;
        break;
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    case EXCP_BKPT:
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        /* See if this is a semihosting syscall.  */
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        if (env->thumb && semihosting_enabled) {
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            mask = lduw_code(env->regs[15]) & 0xff;
            if (mask == 0xab
                  && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
                env->regs[15] += 2;
                env->regs[0] = do_arm_semihosting(env);
                return;
            }
        }
        /* Fall through to prefetch abort.  */
    case EXCP_PREFETCH_ABORT:
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        new_mode = ARM_CPU_MODE_ABT;
        addr = 0x0c;
        mask = CPSR_A | CPSR_I;
        offset = 4;
        break;
    case EXCP_DATA_ABORT:
        new_mode = ARM_CPU_MODE_ABT;
        addr = 0x10;
        mask = CPSR_A | CPSR_I;
        offset = 8;
        break;
    case EXCP_IRQ:
        new_mode = ARM_CPU_MODE_IRQ;
        addr = 0x18;
        /* Disable IRQ and imprecise data aborts.  */
        mask = CPSR_A | CPSR_I;
        offset = 4;
        break;
    case EXCP_FIQ:
        new_mode = ARM_CPU_MODE_FIQ;
        addr = 0x1c;
        /* Disable FIQ, IRQ and imprecise data aborts.  */
        mask = CPSR_A | CPSR_I | CPSR_F;
        offset = 4;
        break;
    default:
        cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
        return; /* Never happens.  Keep compiler happy.  */
    }
    /* High vectors.  */
    if (env->cp15.c1_sys & (1 << 13)) {
        addr += 0xffff0000;
    }
    switch_mode (env, new_mode);
    env->spsr = cpsr_read(env);
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    /* Clear IT bits.  */
    env->condexec_bits = 0;
850
    /* Switch to the new mode, and to the correct instruction set.  */
851
    env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
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    env->uncached_cpsr |= mask;
853
    env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
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    env->regs[14] = env->regs[15] + offset;
    env->regs[15] = addr;
    env->interrupt_request |= CPU_INTERRUPT_EXITTB;
}

/* Check section/page access permissions.
   Returns the page protection flags, or zero if the access is not
   permitted.  */
static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
                           int is_user)
{
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  int prot_ro;

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  if (domain == 3)
    return PAGE_READ | PAGE_WRITE;

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  if (access_type == 1)
      prot_ro = 0;
  else
      prot_ro = PAGE_READ;

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  switch (ap) {
  case 0:
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      if (access_type == 1)
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          return 0;
      switch ((env->cp15.c1_sys >> 8) & 3) {
      case 1:
          return is_user ? 0 : PAGE_READ;
      case 2:
          return PAGE_READ;
      default:
          return 0;
      }
  case 1:
      return is_user ? 0 : PAGE_READ | PAGE_WRITE;
  case 2:
      if (is_user)
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          return prot_ro;
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      else
          return PAGE_READ | PAGE_WRITE;
  case 3:
      return PAGE_READ | PAGE_WRITE;
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  case 4: /* Reserved.  */
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      return 0;
  case 5:
      return is_user ? 0 : prot_ro;
  case 6:
      return prot_ro;
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  case 7:
      if (!arm_feature (env, ARM_FEATURE_V7))
          return 0;
      return prot_ro;
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  default:
      abort();
  }
}

911 912 913 914 915 916 917 918 919 920 921 922 923
static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
{
    uint32_t table;

    if (address & env->cp15.c2_mask)
        table = env->cp15.c2_base1 & 0xffffc000;
    else
        table = env->cp15.c2_base0 & env->cp15.c2_base_mask;

    table |= (address >> 18) & 0x3ffc;
    return table;
}

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static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
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			    int is_user, uint32_t *phys_ptr, int *prot,
                            target_ulong *page_size)
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{
    int code;
    uint32_t table;
    uint32_t desc;
    int type;
    int ap;
    int domain;
    uint32_t phys_addr;

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    /* Pagetable walk.  */
    /* Lookup l1 descriptor.  */
938
    table = get_level1_table_address(env, address);
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    desc = ldl_phys(table);
    type = (desc & 3);
    domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
    if (type == 0) {
943
        /* Section translation fault.  */
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        code = 5;
        goto do_fault;
    }
    if (domain == 0 || domain == 2) {
        if (type == 2)
            code = 9; /* Section domain fault.  */
        else
            code = 11; /* Page domain fault.  */
        goto do_fault;
    }
    if (type == 2) {
        /* 1Mb section.  */
        phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
        ap = (desc >> 10) & 3;
        code = 13;
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        *page_size = 1024 * 1024;
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    } else {
        /* Lookup l2 entry.  */
	if (type == 1) {
	    /* Coarse pagetable.  */
	    table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
	} else {
	    /* Fine pagetable.  */
	    table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
	}
        desc = ldl_phys(table);
        switch (desc & 3) {
        case 0: /* Page translation fault.  */
            code = 7;
            goto do_fault;
        case 1: /* 64k page.  */
            phys_addr = (desc & 0xffff0000) | (address & 0xffff);
            ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
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            *page_size = 0x10000;
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            break;
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        case 2: /* 4k page.  */
            phys_addr = (desc & 0xfffff000) | (address & 0xfff);
            ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
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            *page_size = 0x1000;
P
pbrook 已提交
983
            break;
P
pbrook 已提交
984 985 986 987 988 989 990 991 992 993 994 995 996
        case 3: /* 1k page.  */
	    if (type == 1) {
		if (arm_feature(env, ARM_FEATURE_XSCALE)) {
		    phys_addr = (desc & 0xfffff000) | (address & 0xfff);
		} else {
		    /* Page translation fault.  */
		    code = 7;
		    goto do_fault;
		}
	    } else {
		phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
	    }
            ap = (desc >> 4) & 3;
P
Paul Brook 已提交
997
            *page_size = 0x400;
P
pbrook 已提交
998 999
            break;
        default:
P
pbrook 已提交
1000 1001
            /* Never happens, but compiler isn't smart enough to tell.  */
            abort();
P
pbrook 已提交
1002
        }
P
pbrook 已提交
1003 1004 1005 1006 1007 1008 1009
        code = 15;
    }
    *prot = check_ap(env, ap, domain, access_type, is_user);
    if (!*prot) {
        /* Access permission fault.  */
        goto do_fault;
    }
1010
    *prot |= PAGE_EXEC;
P
pbrook 已提交
1011 1012 1013 1014 1015 1016 1017
    *phys_ptr = phys_addr;
    return 0;
do_fault:
    return code | (domain << 4);
}

static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
P
Paul Brook 已提交
1018 1019
			    int is_user, uint32_t *phys_ptr, int *prot,
                            target_ulong *page_size)
P
pbrook 已提交
1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031
{
    int code;
    uint32_t table;
    uint32_t desc;
    uint32_t xn;
    int type;
    int ap;
    int domain;
    uint32_t phys_addr;

    /* Pagetable walk.  */
    /* Lookup l1 descriptor.  */
1032
    table = get_level1_table_address(env, address);
P
pbrook 已提交
1033 1034 1035
    desc = ldl_phys(table);
    type = (desc & 3);
    if (type == 0) {
1036
        /* Section translation fault.  */
P
pbrook 已提交
1037 1038 1039 1040 1041 1042
        code = 5;
        domain = 0;
        goto do_fault;
    } else if (type == 2 && (desc & (1 << 18))) {
        /* Supersection.  */
        domain = 0;
B
bellard 已提交
1043
    } else {
P
pbrook 已提交
1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058
        /* Section or page.  */
        domain = (desc >> 4) & 0x1e;
    }
    domain = (env->cp15.c3 >> domain) & 3;
    if (domain == 0 || domain == 2) {
        if (type == 2)
            code = 9; /* Section domain fault.  */
        else
            code = 11; /* Page domain fault.  */
        goto do_fault;
    }
    if (type == 2) {
        if (desc & (1 << 18)) {
            /* Supersection.  */
            phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
P
Paul Brook 已提交
1059
            *page_size = 0x1000000;
B
bellard 已提交
1060
        } else {
P
pbrook 已提交
1061 1062
            /* Section.  */
            phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
P
Paul Brook 已提交
1063
            *page_size = 0x100000;
B
bellard 已提交
1064
        }
P
pbrook 已提交
1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
        ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
        xn = desc & (1 << 4);
        code = 13;
    } else {
        /* Lookup l2 entry.  */
        table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
        desc = ldl_phys(table);
        ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
        switch (desc & 3) {
        case 0: /* Page translation fault.  */
            code = 7;
B
bellard 已提交
1076
            goto do_fault;
P
pbrook 已提交
1077 1078 1079
        case 1: /* 64k page.  */
            phys_addr = (desc & 0xffff0000) | (address & 0xffff);
            xn = desc & (1 << 15);
P
Paul Brook 已提交
1080
            *page_size = 0x10000;
P
pbrook 已提交
1081 1082 1083 1084
            break;
        case 2: case 3: /* 4k page.  */
            phys_addr = (desc & 0xfffff000) | (address & 0xfff);
            xn = desc & 1;
P
Paul Brook 已提交
1085
            *page_size = 0x1000;
P
pbrook 已提交
1086 1087 1088 1089
            break;
        default:
            /* Never happens, but compiler isn't smart enough to tell.  */
            abort();
B
bellard 已提交
1090
        }
P
pbrook 已提交
1091 1092
        code = 15;
    }
1093 1094 1095 1096 1097
    if (domain == 3) {
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
    } else {
        if (xn && access_type == 2)
            goto do_fault;
P
pbrook 已提交
1098

1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112
        /* The simplified model uses AP[0] as an access control bit.  */
        if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
            /* Access flag fault.  */
            code = (code == 15) ? 6 : 3;
            goto do_fault;
        }
        *prot = check_ap(env, ap, domain, access_type, is_user);
        if (!*prot) {
            /* Access permission fault.  */
            goto do_fault;
        }
        if (!xn) {
            *prot |= PAGE_EXEC;
        }
1113
    }
P
pbrook 已提交
1114
    *phys_ptr = phys_addr;
B
bellard 已提交
1115 1116 1117 1118 1119
    return 0;
do_fault:
    return code | (domain << 4);
}

P
pbrook 已提交
1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
			     int is_user, uint32_t *phys_ptr, int *prot)
{
    int n;
    uint32_t mask;
    uint32_t base;

    *phys_ptr = address;
    for (n = 7; n >= 0; n--) {
	base = env->cp15.c6_region[n];
	if ((base & 1) == 0)
	    continue;
	mask = 1 << ((base >> 1) & 0x1f);
	/* Keep this shift separate from the above to avoid an
	   (undefined) << 32.  */
	mask = (mask << 1) - 1;
	if (((base ^ address) & ~mask) == 0)
	    break;
    }
    if (n < 0)
	return 2;

    if (access_type == 2) {
	mask = env->cp15.c5_insn;
    } else {
	mask = env->cp15.c5_data;
    }
    mask = (mask >> (n * 4)) & 0xf;
    switch (mask) {
    case 0:
	return 1;
    case 1:
	if (is_user)
	  return 1;
	*prot = PAGE_READ | PAGE_WRITE;
	break;
    case 2:
	*prot = PAGE_READ;
	if (!is_user)
	    *prot |= PAGE_WRITE;
	break;
    case 3:
	*prot = PAGE_READ | PAGE_WRITE;
	break;
    case 5:
	if (is_user)
	    return 1;
	*prot = PAGE_READ;
	break;
    case 6:
	*prot = PAGE_READ;
	break;
    default:
	/* Bad permission.  */
	return 1;
    }
1176
    *prot |= PAGE_EXEC;
P
pbrook 已提交
1177 1178 1179 1180 1181
    return 0;
}

static inline int get_phys_addr(CPUState *env, uint32_t address,
                                int access_type, int is_user,
P
Paul Brook 已提交
1182 1183
                                uint32_t *phys_ptr, int *prot,
                                target_ulong *page_size)
P
pbrook 已提交
1184 1185 1186 1187 1188 1189 1190 1191
{
    /* Fast Context Switch Extension.  */
    if (address < 0x02000000)
        address += env->cp15.c13_fcse;

    if ((env->cp15.c1_sys & 1) == 0) {
        /* MMU/MPU disabled.  */
        *phys_ptr = address;
1192
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
P
Paul Brook 已提交
1193
        *page_size = TARGET_PAGE_SIZE;
P
pbrook 已提交
1194 1195
        return 0;
    } else if (arm_feature(env, ARM_FEATURE_MPU)) {
P
Paul Brook 已提交
1196
        *page_size = TARGET_PAGE_SIZE;
P
pbrook 已提交
1197 1198 1199 1200
	return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
				 prot);
    } else if (env->cp15.c1_sys & (1 << 23)) {
        return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
P
Paul Brook 已提交
1201
                                prot, page_size);
P
pbrook 已提交
1202 1203
    } else {
        return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
P
Paul Brook 已提交
1204
                                prot, page_size);
P
pbrook 已提交
1205 1206 1207
    }
}

B
bellard 已提交
1208
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
1209
                              int access_type, int mmu_idx, int is_softmmu)
B
bellard 已提交
1210 1211
{
    uint32_t phys_addr;
P
Paul Brook 已提交
1212
    target_ulong page_size;
B
bellard 已提交
1213
    int prot;
1214
    int ret, is_user;
B
bellard 已提交
1215

1216
    is_user = mmu_idx == MMU_USER_IDX;
P
Paul Brook 已提交
1217 1218
    ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
                        &page_size);
B
bellard 已提交
1219 1220 1221 1222
    if (ret == 0) {
        /* Map a single [sub]page.  */
        phys_addr &= ~(uint32_t)0x3ff;
        address &= ~(uint32_t)0x3ff;
1223
        tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
P
Paul Brook 已提交
1224
        return 0;
B
bellard 已提交
1225 1226 1227 1228 1229 1230 1231 1232
    }

    if (access_type == 2) {
        env->cp15.c5_insn = ret;
        env->cp15.c6_insn = address;
        env->exception_index = EXCP_PREFETCH_ABORT;
    } else {
        env->cp15.c5_data = ret;
P
pbrook 已提交
1233 1234
        if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
            env->cp15.c5_data |= (1 << 11);
B
bellard 已提交
1235 1236 1237 1238 1239 1240
        env->cp15.c6_data = address;
        env->exception_index = EXCP_DATA_ABORT;
    }
    return 1;
}

A
Anthony Liguori 已提交
1241
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
B
bellard 已提交
1242 1243
{
    uint32_t phys_addr;
P
Paul Brook 已提交
1244
    target_ulong page_size;
B
bellard 已提交
1245 1246 1247
    int prot;
    int ret;

P
Paul Brook 已提交
1248
    ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
B
bellard 已提交
1249 1250 1251 1252 1253 1254 1255

    if (ret != 0)
        return -1;

    return phys_addr;
}

P
pbrook 已提交
1256
void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267
{
    int cp_num = (insn >> 8) & 0xf;
    int cp_info = (insn >> 5) & 7;
    int src = (insn >> 16) & 0xf;
    int operand = insn & 0xf;

    if (env->cp[cp_num].cp_write)
        env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
                                 cp_info, src, operand, val);
}

P
pbrook 已提交
1268
uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
{
    int cp_num = (insn >> 8) & 0xf;
    int cp_info = (insn >> 5) & 7;
    int dest = (insn >> 16) & 0xf;
    int operand = insn & 0xf;

    if (env->cp[cp_num].cp_read)
        return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
                                       cp_info, dest, operand);
    return 0;
}

P
pbrook 已提交
1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310
/* Return basic MPU access permission bits.  */
static uint32_t simple_mpu_ap_bits(uint32_t val)
{
    uint32_t ret;
    uint32_t mask;
    int i;
    ret = 0;
    mask = 3;
    for (i = 0; i < 16; i += 2) {
        ret |= (val >> i) & mask;
        mask <<= 2;
    }
    return ret;
}

/* Pad basic MPU access permission bits to extended format.  */
static uint32_t extended_mpu_ap_bits(uint32_t val)
{
    uint32_t ret;
    uint32_t mask;
    int i;
    ret = 0;
    mask = 3;
    for (i = 0; i < 16; i += 2) {
        ret |= (val & mask) << i;
        mask <<= 2;
    }
    return ret;
}

P
pbrook 已提交
1311
void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
B
bellard 已提交
1312
{
P
pbrook 已提交
1313 1314 1315
    int op1;
    int op2;
    int crm;
B
bellard 已提交
1316

P
pbrook 已提交
1317
    op1 = (insn >> 21) & 7;
B
bellard 已提交
1318
    op2 = (insn >> 5) & 7;
P
pbrook 已提交
1319
    crm = insn & 0xf;
B
bellard 已提交
1320
    switch ((insn >> 16) & 0xf) {
P
pbrook 已提交
1321 1322
    case 0:
        /* ID codes.  */
1323 1324
        if (arm_feature(env, ARM_FEATURE_XSCALE))
            break;
1325 1326
        if (arm_feature(env, ARM_FEATURE_OMAPCP))
            break;
P
pbrook 已提交
1327 1328 1329 1330 1331
        if (arm_feature(env, ARM_FEATURE_V7)
                && op1 == 2 && crm == 0 && op2 == 0) {
            env->cp15.c0_cssel = val & 0xf;
            break;
        }
B
bellard 已提交
1332 1333
        goto bad_reg;
    case 1: /* System configuration.  */
1334 1335
        if (arm_feature(env, ARM_FEATURE_OMAPCP))
            op2 = 0;
B
bellard 已提交
1336 1337
        switch (op2) {
        case 0:
P
pbrook 已提交
1338
            if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
1339
                env->cp15.c1_sys = val;
B
bellard 已提交
1340 1341 1342 1343
            /* ??? Lots of these bits are not implemented.  */
            /* This may enable/disable the MMU, so do a TLB flush.  */
            tlb_flush(env, 1);
            break;
P
pbrook 已提交
1344
        case 1: /* Auxiliary cotrol register.  */
1345 1346
            if (arm_feature(env, ARM_FEATURE_XSCALE)) {
                env->cp15.c1_xscaleauxcr = val;
1347
                break;
1348
            }
P
pbrook 已提交
1349 1350
            /* Not implemented.  */
            break;
B
bellard 已提交
1351
        case 2:
1352 1353
            if (arm_feature(env, ARM_FEATURE_XSCALE))
                goto bad_reg;
1354 1355 1356 1357 1358
            if (env->cp15.c1_coproc != val) {
                env->cp15.c1_coproc = val;
                /* ??? Is this safe when called from within a TB?  */
                tb_flush(env);
            }
1359
            break;
B
bellard 已提交
1360 1361 1362 1363
        default:
            goto bad_reg;
        }
        break;
P
pbrook 已提交
1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376
    case 2: /* MMU Page table control / MPU cache control.  */
        if (arm_feature(env, ARM_FEATURE_MPU)) {
            switch (op2) {
            case 0:
                env->cp15.c2_data = val;
                break;
            case 1:
                env->cp15.c2_insn = val;
                break;
            default:
                goto bad_reg;
            }
        } else {
P
pbrook 已提交
1377 1378 1379 1380 1381 1382 1383 1384
	    switch (op2) {
	    case 0:
		env->cp15.c2_base0 = val;
		break;
	    case 1:
		env->cp15.c2_base1 = val;
		break;
	    case 2:
1385 1386
                val &= 7;
                env->cp15.c2_control = val;
P
pbrook 已提交
1387
		env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
1388
                env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
P
pbrook 已提交
1389 1390 1391 1392
		break;
	    default:
		goto bad_reg;
	    }
P
pbrook 已提交
1393
        }
B
bellard 已提交
1394
        break;
P
pbrook 已提交
1395
    case 3: /* MMU Domain access control / MPU write buffer control.  */
B
bellard 已提交
1396
        env->cp15.c3 = val;
1397
        tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
B
bellard 已提交
1398 1399 1400
        break;
    case 4: /* Reserved.  */
        goto bad_reg;
P
pbrook 已提交
1401
    case 5: /* MMU Fault status / MPU access permission.  */
1402 1403
        if (arm_feature(env, ARM_FEATURE_OMAPCP))
            op2 = 0;
B
bellard 已提交
1404 1405
        switch (op2) {
        case 0:
P
pbrook 已提交
1406 1407
            if (arm_feature(env, ARM_FEATURE_MPU))
                val = extended_mpu_ap_bits(val);
B
bellard 已提交
1408 1409 1410
            env->cp15.c5_data = val;
            break;
        case 1:
P
pbrook 已提交
1411 1412
            if (arm_feature(env, ARM_FEATURE_MPU))
                val = extended_mpu_ap_bits(val);
B
bellard 已提交
1413 1414
            env->cp15.c5_insn = val;
            break;
P
pbrook 已提交
1415 1416 1417 1418
        case 2:
            if (!arm_feature(env, ARM_FEATURE_MPU))
                goto bad_reg;
            env->cp15.c5_data = val;
B
bellard 已提交
1419
            break;
P
pbrook 已提交
1420 1421 1422 1423
        case 3:
            if (!arm_feature(env, ARM_FEATURE_MPU))
                goto bad_reg;
            env->cp15.c5_insn = val;
B
bellard 已提交
1424 1425 1426 1427 1428
            break;
        default:
            goto bad_reg;
        }
        break;
P
pbrook 已提交
1429 1430 1431 1432 1433 1434
    case 6: /* MMU Fault address / MPU base/size.  */
        if (arm_feature(env, ARM_FEATURE_MPU)) {
            if (crm >= 8)
                goto bad_reg;
            env->cp15.c6_region[crm] = val;
        } else {
1435 1436
            if (arm_feature(env, ARM_FEATURE_OMAPCP))
                op2 = 0;
P
pbrook 已提交
1437 1438 1439 1440
            switch (op2) {
            case 0:
                env->cp15.c6_data = val;
                break;
P
pbrook 已提交
1441 1442
            case 1: /* ??? This is WFAR on armv6 */
            case 2:
P
pbrook 已提交
1443 1444 1445 1446 1447 1448 1449
                env->cp15.c6_insn = val;
                break;
            default:
                goto bad_reg;
            }
        }
        break;
B
bellard 已提交
1450
    case 7: /* Cache control.  */
1451 1452
        env->cp15.c15_i_max = 0x000;
        env->cp15.c15_i_min = 0xff0;
B
bellard 已提交
1453
        /* No cache, so nothing to do.  */
P
pbrook 已提交
1454
        /* ??? MPCore has VA to PA translation functions.  */
B
bellard 已提交
1455 1456 1457 1458 1459 1460 1461
        break;
    case 8: /* MMU TLB control.  */
        switch (op2) {
        case 0: /* Invalidate all.  */
            tlb_flush(env, 0);
            break;
        case 1: /* Invalidate single TLB entry.  */
P
Paul Brook 已提交
1462
            tlb_flush_page(env, val & TARGET_PAGE_MASK);
B
bellard 已提交
1463
            break;
P
pbrook 已提交
1464 1465 1466 1467 1468 1469 1470
        case 2: /* Invalidate on ASID.  */
            tlb_flush(env, val == 0);
            break;
        case 3: /* Invalidate single entry on MVA.  */
            /* ??? This is like case 1, but ignores ASID.  */
            tlb_flush(env, 1);
            break;
B
bellard 已提交
1471 1472 1473 1474
        default:
            goto bad_reg;
        }
        break;
P
pbrook 已提交
1475
    case 9:
1476 1477
        if (arm_feature(env, ARM_FEATURE_OMAPCP))
            break;
P
pbrook 已提交
1478 1479
        switch (crm) {
        case 0: /* Cache lockdown.  */
P
pbrook 已提交
1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499
	    switch (op1) {
	    case 0: /* L1 cache.  */
		switch (op2) {
		case 0:
		    env->cp15.c9_data = val;
		    break;
		case 1:
		    env->cp15.c9_insn = val;
		    break;
		default:
		    goto bad_reg;
		}
		break;
	    case 1: /* L2 cache.  */
		/* Ignore writes to L2 lockdown/auxiliary registers.  */
		break;
	    default:
		goto bad_reg;
	    }
	    break;
P
pbrook 已提交
1500 1501 1502
        case 1: /* TCM memory region registers.  */
            /* Not implemented.  */
            goto bad_reg;
B
bellard 已提交
1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514
        default:
            goto bad_reg;
        }
        break;
    case 10: /* MMU TLB lockdown.  */
        /* ??? TLB lockdown not implemented.  */
        break;
    case 12: /* Reserved.  */
        goto bad_reg;
    case 13: /* Process ID.  */
        switch (op2) {
        case 0:
1515 1516 1517 1518 1519 1520
            /* Unlike real hardware the qemu TLB uses virtual addresses,
               not modified virtual addresses, so this causes a TLB flush.
             */
            if (env->cp15.c13_fcse != val)
              tlb_flush(env, 1);
            env->cp15.c13_fcse = val;
B
bellard 已提交
1521 1522
            break;
        case 1:
1523
            /* This changes the ASID, so do a TLB flush.  */
P
pbrook 已提交
1524 1525
            if (env->cp15.c13_context != val
                && !arm_feature(env, ARM_FEATURE_MPU))
1526 1527
              tlb_flush(env, 0);
            env->cp15.c13_context = val;
B
bellard 已提交
1528 1529 1530 1531 1532 1533 1534 1535
            break;
        default:
            goto bad_reg;
        }
        break;
    case 14: /* Reserved.  */
        goto bad_reg;
    case 15: /* Implementation specific.  */
1536
        if (arm_feature(env, ARM_FEATURE_XSCALE)) {
P
pbrook 已提交
1537
            if (op2 == 0 && crm == 1) {
1538 1539 1540 1541 1542
                if (env->cp15.c15_cpar != (val & 0x3fff)) {
                    /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
                    tb_flush(env);
                    env->cp15.c15_cpar = val & 0x3fff;
                }
1543 1544 1545 1546
                break;
            }
            goto bad_reg;
        }
1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571
        if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
            switch (crm) {
            case 0:
                break;
            case 1: /* Set TI925T configuration.  */
                env->cp15.c15_ticonfig = val & 0xe7;
                env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
                        ARM_CPUID_TI915T : ARM_CPUID_TI925T;
                break;
            case 2: /* Set I_max.  */
                env->cp15.c15_i_max = val;
                break;
            case 3: /* Set I_min.  */
                env->cp15.c15_i_min = val;
                break;
            case 4: /* Set thread-ID.  */
                env->cp15.c15_threadid = val & 0xffff;
                break;
            case 8: /* Wait-for-interrupt (deprecated).  */
                cpu_interrupt(env, CPU_INTERRUPT_HALT);
                break;
            default:
                goto bad_reg;
            }
        }
B
bellard 已提交
1572 1573 1574 1575 1576
        break;
    }
    return;
bad_reg:
    /* ??? For debugging only.  Should raise illegal instruction exception.  */
P
pbrook 已提交
1577 1578
    cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
              (insn >> 16) & 0xf, crm, op1, op2);
B
bellard 已提交
1579 1580
}

P
pbrook 已提交
1581
uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
B
bellard 已提交
1582
{
P
pbrook 已提交
1583 1584 1585
    int op1;
    int op2;
    int crm;
B
bellard 已提交
1586

P
pbrook 已提交
1587
    op1 = (insn >> 21) & 7;
B
bellard 已提交
1588
    op2 = (insn >> 5) & 7;
1589
    crm = insn & 0xf;
B
bellard 已提交
1590 1591
    switch ((insn >> 16) & 0xf) {
    case 0: /* ID codes.  */
P
pbrook 已提交
1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605
        switch (op1) {
        case 0:
            switch (crm) {
            case 0:
                switch (op2) {
                case 0: /* Device ID.  */
                    return env->cp15.c0_cpuid;
                case 1: /* Cache Type.  */
		    return env->cp15.c0_cachetype;
                case 2: /* TCM status.  */
                    return 0;
                case 3: /* TLB type register.  */
                    return 0; /* No lockable TLB entries.  */
                case 5: /* CPU ID */
P
Paul Brook 已提交
1606 1607 1608 1609 1610
                    if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
                        return env->cpu_index | 0x80000900;
                    } else {
                        return env->cpu_index;
                    }
P
pbrook 已提交
1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
                default:
                    goto bad_reg;
                }
            case 1:
                if (!arm_feature(env, ARM_FEATURE_V6))
                    goto bad_reg;
                return env->cp15.c0_c1[op2];
            case 2:
                if (!arm_feature(env, ARM_FEATURE_V6))
                    goto bad_reg;
                return env->cp15.c0_c2[op2];
            case 3: case 4: case 5: case 6: case 7:
                return 0;
            default:
                goto bad_reg;
            }
        case 1:
            /* These registers aren't documented on arm11 cores.  However
               Linux looks at them anyway.  */
            if (!arm_feature(env, ARM_FEATURE_V6))
                goto bad_reg;
            if (crm != 0)
                goto bad_reg;
P
pbrook 已提交
1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647
            if (!arm_feature(env, ARM_FEATURE_V7))
                return 0;

            switch (op2) {
            case 0:
                return env->cp15.c0_ccsid[env->cp15.c0_cssel];
            case 1:
                return env->cp15.c0_clid;
            case 7:
                return 0;
            }
            goto bad_reg;
        case 2:
            if (op2 != 0 || crm != 0)
1648
                goto bad_reg;
P
pbrook 已提交
1649
            return env->cp15.c0_cssel;
P
pbrook 已提交
1650 1651
        default:
            goto bad_reg;
B
bellard 已提交
1652 1653
        }
    case 1: /* System configuration.  */
1654 1655
        if (arm_feature(env, ARM_FEATURE_OMAPCP))
            op2 = 0;
B
bellard 已提交
1656 1657 1658 1659
        switch (op2) {
        case 0: /* Control register.  */
            return env->cp15.c1_sys;
        case 1: /* Auxiliary control register.  */
1660
            if (arm_feature(env, ARM_FEATURE_XSCALE))
1661
                return env->cp15.c1_xscaleauxcr;
P
pbrook 已提交
1662 1663 1664 1665 1666 1667
            if (!arm_feature(env, ARM_FEATURE_AUXCR))
                goto bad_reg;
            switch (ARM_CPUID(env)) {
            case ARM_CPUID_ARM1026:
                return 1;
            case ARM_CPUID_ARM1136:
B
balrog 已提交
1668
            case ARM_CPUID_ARM1136_R2:
P
pbrook 已提交
1669 1670 1671 1672
                return 7;
            case ARM_CPUID_ARM11MPCORE:
                return 1;
            case ARM_CPUID_CORTEXA8:
1673
                return 2;
P
Paul Brook 已提交
1674 1675
            case ARM_CPUID_CORTEXA9:
                return 0;
P
pbrook 已提交
1676 1677 1678
            default:
                goto bad_reg;
            }
B
bellard 已提交
1679
        case 2: /* Coprocessor access register.  */
1680 1681
            if (arm_feature(env, ARM_FEATURE_XSCALE))
                goto bad_reg;
B
bellard 已提交
1682 1683 1684 1685
            return env->cp15.c1_coproc;
        default:
            goto bad_reg;
        }
P
pbrook 已提交
1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698
    case 2: /* MMU Page table control / MPU cache control.  */
        if (arm_feature(env, ARM_FEATURE_MPU)) {
            switch (op2) {
            case 0:
                return env->cp15.c2_data;
                break;
            case 1:
                return env->cp15.c2_insn;
                break;
            default:
                goto bad_reg;
            }
        } else {
P
pbrook 已提交
1699 1700 1701 1702 1703 1704
	    switch (op2) {
	    case 0:
		return env->cp15.c2_base0;
	    case 1:
		return env->cp15.c2_base1;
	    case 2:
1705
                return env->cp15.c2_control;
P
pbrook 已提交
1706 1707 1708 1709
	    default:
		goto bad_reg;
	    }
	}
P
pbrook 已提交
1710
    case 3: /* MMU Domain access control / MPU write buffer control.  */
B
bellard 已提交
1711 1712 1713
        return env->cp15.c3;
    case 4: /* Reserved.  */
        goto bad_reg;
P
pbrook 已提交
1714
    case 5: /* MMU Fault status / MPU access permission.  */
1715 1716
        if (arm_feature(env, ARM_FEATURE_OMAPCP))
            op2 = 0;
B
bellard 已提交
1717 1718
        switch (op2) {
        case 0:
P
pbrook 已提交
1719 1720
            if (arm_feature(env, ARM_FEATURE_MPU))
                return simple_mpu_ap_bits(env->cp15.c5_data);
B
bellard 已提交
1721 1722
            return env->cp15.c5_data;
        case 1:
P
pbrook 已提交
1723 1724 1725 1726 1727 1728 1729 1730 1731 1732
            if (arm_feature(env, ARM_FEATURE_MPU))
                return simple_mpu_ap_bits(env->cp15.c5_data);
            return env->cp15.c5_insn;
        case 2:
            if (!arm_feature(env, ARM_FEATURE_MPU))
                goto bad_reg;
            return env->cp15.c5_data;
        case 3:
            if (!arm_feature(env, ARM_FEATURE_MPU))
                goto bad_reg;
B
bellard 已提交
1733 1734 1735 1736
            return env->cp15.c5_insn;
        default:
            goto bad_reg;
        }
P
pbrook 已提交
1737
    case 6: /* MMU Fault address.  */
P
pbrook 已提交
1738
        if (arm_feature(env, ARM_FEATURE_MPU)) {
P
pbrook 已提交
1739
            if (crm >= 8)
P
pbrook 已提交
1740
                goto bad_reg;
P
pbrook 已提交
1741
            return env->cp15.c6_region[crm];
P
pbrook 已提交
1742
        } else {
1743 1744
            if (arm_feature(env, ARM_FEATURE_OMAPCP))
                op2 = 0;
P
pbrook 已提交
1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767
	    switch (op2) {
	    case 0:
		return env->cp15.c6_data;
	    case 1:
		if (arm_feature(env, ARM_FEATURE_V6)) {
		    /* Watchpoint Fault Adrress.  */
		    return 0; /* Not implemented.  */
		} else {
		    /* Instruction Fault Adrress.  */
		    /* Arm9 doesn't have an IFAR, but implementing it anyway
		       shouldn't do any harm.  */
		    return env->cp15.c6_insn;
		}
	    case 2:
		if (arm_feature(env, ARM_FEATURE_V6)) {
		    /* Instruction Fault Adrress.  */
		    return env->cp15.c6_insn;
		} else {
		    goto bad_reg;
		}
	    default:
		goto bad_reg;
	    }
B
bellard 已提交
1768 1769
        }
    case 7: /* Cache control.  */
P
pbrook 已提交
1770 1771
        /* FIXME: Should only clear Z flag if destination is r15.  */
        env->ZF = 0;
B
bellard 已提交
1772 1773 1774 1775
        return 0;
    case 8: /* MMU TLB control.  */
        goto bad_reg;
    case 9: /* Cache lockdown.  */
P
pbrook 已提交
1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791
        switch (op1) {
        case 0: /* L1 cache.  */
	    if (arm_feature(env, ARM_FEATURE_OMAPCP))
		return 0;
            switch (op2) {
            case 0:
                return env->cp15.c9_data;
            case 1:
                return env->cp15.c9_insn;
            default:
                goto bad_reg;
            }
        case 1: /* L2 cache */
            if (crm != 0)
                goto bad_reg;
            /* L2 Lockdown and Auxiliary control.  */
1792
            return 0;
B
bellard 已提交
1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813
        default:
            goto bad_reg;
        }
    case 10: /* MMU TLB lockdown.  */
        /* ??? TLB lockdown not implemented.  */
        return 0;
    case 11: /* TCM DMA control.  */
    case 12: /* Reserved.  */
        goto bad_reg;
    case 13: /* Process ID.  */
        switch (op2) {
        case 0:
            return env->cp15.c13_fcse;
        case 1:
            return env->cp15.c13_context;
        default:
            goto bad_reg;
        }
    case 14: /* Reserved.  */
        goto bad_reg;
    case 15: /* Implementation specific.  */
1814
        if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1815
            if (op2 == 0 && crm == 1)
1816 1817 1818 1819
                return env->cp15.c15_cpar;

            goto bad_reg;
        }
1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834
        if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
            switch (crm) {
            case 0:
                return 0;
            case 1: /* Read TI925T configuration.  */
                return env->cp15.c15_ticonfig;
            case 2: /* Read I_max.  */
                return env->cp15.c15_i_max;
            case 3: /* Read I_min.  */
                return env->cp15.c15_i_min;
            case 4: /* Read thread-ID.  */
                return env->cp15.c15_threadid;
            case 8: /* TI925T_status */
                return 0;
            }
B
balrog 已提交
1835 1836 1837 1838
            /* TODO: Peripheral port remap register:
             * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
             * controller base address at $rn & ~0xfff and map size of
             * 0x200 << ($rn & 0xfff), when MMU is off.  */
1839 1840
            goto bad_reg;
        }
B
bellard 已提交
1841 1842 1843 1844
        return 0;
    }
bad_reg:
    /* ??? For debugging only.  Should raise illegal instruction exception.  */
P
pbrook 已提交
1845 1846
    cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
              (insn >> 16) & 0xf, crm, op1, op2);
B
bellard 已提交
1847 1848 1849
    return 0;
}

P
pbrook 已提交
1850
void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
P
pbrook 已提交
1851
{
1852 1853 1854 1855 1856
    if ((env->uncached_cpsr & CPSR_M) == mode) {
        env->regs[13] = val;
    } else {
        env->banked_r13[bank_number(mode)] = val;
    }
P
pbrook 已提交
1857 1858
}

P
pbrook 已提交
1859
uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
P
pbrook 已提交
1860
{
1861 1862 1863 1864 1865
    if ((env->uncached_cpsr & CPSR_M) == mode) {
        return env->regs[13];
    } else {
        return env->banked_r13[bank_number(mode)];
    }
P
pbrook 已提交
1866 1867
}

P
pbrook 已提交
1868
uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
P
pbrook 已提交
1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904
{
    switch (reg) {
    case 0: /* APSR */
        return xpsr_read(env) & 0xf8000000;
    case 1: /* IAPSR */
        return xpsr_read(env) & 0xf80001ff;
    case 2: /* EAPSR */
        return xpsr_read(env) & 0xff00fc00;
    case 3: /* xPSR */
        return xpsr_read(env) & 0xff00fdff;
    case 5: /* IPSR */
        return xpsr_read(env) & 0x000001ff;
    case 6: /* EPSR */
        return xpsr_read(env) & 0x0700fc00;
    case 7: /* IEPSR */
        return xpsr_read(env) & 0x0700edff;
    case 8: /* MSP */
        return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
    case 9: /* PSP */
        return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
    case 16: /* PRIMASK */
        return (env->uncached_cpsr & CPSR_I) != 0;
    case 17: /* FAULTMASK */
        return (env->uncached_cpsr & CPSR_F) != 0;
    case 18: /* BASEPRI */
    case 19: /* BASEPRI_MAX */
        return env->v7m.basepri;
    case 20: /* CONTROL */
        return env->v7m.control;
    default:
        /* ??? For debugging only.  */
        cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
        return 0;
    }
}

P
pbrook 已提交
1905
void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
P
pbrook 已提交
1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971
{
    switch (reg) {
    case 0: /* APSR */
        xpsr_write(env, val, 0xf8000000);
        break;
    case 1: /* IAPSR */
        xpsr_write(env, val, 0xf8000000);
        break;
    case 2: /* EAPSR */
        xpsr_write(env, val, 0xfe00fc00);
        break;
    case 3: /* xPSR */
        xpsr_write(env, val, 0xfe00fc00);
        break;
    case 5: /* IPSR */
        /* IPSR bits are readonly.  */
        break;
    case 6: /* EPSR */
        xpsr_write(env, val, 0x0600fc00);
        break;
    case 7: /* IEPSR */
        xpsr_write(env, val, 0x0600fc00);
        break;
    case 8: /* MSP */
        if (env->v7m.current_sp)
            env->v7m.other_sp = val;
        else
            env->regs[13] = val;
        break;
    case 9: /* PSP */
        if (env->v7m.current_sp)
            env->regs[13] = val;
        else
            env->v7m.other_sp = val;
        break;
    case 16: /* PRIMASK */
        if (val & 1)
            env->uncached_cpsr |= CPSR_I;
        else
            env->uncached_cpsr &= ~CPSR_I;
        break;
    case 17: /* FAULTMASK */
        if (val & 1)
            env->uncached_cpsr |= CPSR_F;
        else
            env->uncached_cpsr &= ~CPSR_F;
        break;
    case 18: /* BASEPRI */
        env->v7m.basepri = val & 0xff;
        break;
    case 19: /* BASEPRI_MAX */
        val &= 0xff;
        if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
            env->v7m.basepri = val;
        break;
    case 20: /* CONTROL */
        env->v7m.control = val & 3;
        switch_v7m_sp(env, (val & 2) != 0);
        break;
    default:
        /* ??? For debugging only.  */
        cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
        return;
    }
}

1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985
void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
                ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
                void *opaque)
{
    if (cpnum < 0 || cpnum > 14) {
        cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
        return;
    }

    env->cp[cpnum].cp_read = cp_read;
    env->cp[cpnum].cp_write = cp_write;
    env->cp[cpnum].opaque = opaque;
}

B
bellard 已提交
1986
#endif
P
pbrook 已提交
1987 1988 1989 1990 1991 1992 1993

/* Note that signed overflow is undefined in C.  The following routines are
   careful to use unsigned types where modulo arithmetic is required.
   Failure to do so _will_ break on newer gcc.  */

/* Signed saturating arithmetic.  */

A
aurel32 已提交
1994
/* Perform 16-bit signed saturating addition.  */
P
pbrook 已提交
1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008
static inline uint16_t add16_sat(uint16_t a, uint16_t b)
{
    uint16_t res;

    res = a + b;
    if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
        if (a & 0x8000)
            res = 0x8000;
        else
            res = 0x7fff;
    }
    return res;
}

A
aurel32 已提交
2009
/* Perform 8-bit signed saturating addition.  */
P
pbrook 已提交
2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023
static inline uint8_t add8_sat(uint8_t a, uint8_t b)
{
    uint8_t res;

    res = a + b;
    if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
        if (a & 0x80)
            res = 0x80;
        else
            res = 0x7f;
    }
    return res;
}

A
aurel32 已提交
2024
/* Perform 16-bit signed saturating subtraction.  */
P
pbrook 已提交
2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038
static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
{
    uint16_t res;

    res = a - b;
    if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
        if (a & 0x8000)
            res = 0x8000;
        else
            res = 0x7fff;
    }
    return res;
}

A
aurel32 已提交
2039
/* Perform 8-bit signed saturating subtraction.  */
P
pbrook 已提交
2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062
static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
{
    uint8_t res;

    res = a - b;
    if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
        if (a & 0x80)
            res = 0x80;
        else
            res = 0x7f;
    }
    return res;
}

#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
#define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
#define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
#define PFX q

#include "op_addsub.h"

/* Unsigned saturating arithmetic.  */
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static inline uint16_t add16_usat(uint16_t a, uint16_t b)
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{
    uint16_t res;
    res = a + b;
    if (res < a)
        res = 0xffff;
    return res;
}

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static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
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{
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    if (a > b)
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        return a - b;
    else
        return 0;
}

static inline uint8_t add8_usat(uint8_t a, uint8_t b)
{
    uint8_t res;
    res = a + b;
    if (res < a)
        res = 0xff;
    return res;
}

static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
{
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    if (a > b)
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        return a - b;
    else
        return 0;
}

#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
#define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
#define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
#define PFX uq

#include "op_addsub.h"

/* Signed modulo arithmetic.  */
#define SARITH16(a, b, n, op) do { \
    int32_t sum; \
    sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
    RESULT(sum, n, 16); \
    if (sum >= 0) \
        ge |= 3 << (n * 2); \
    } while(0)

#define SARITH8(a, b, n, op) do { \
    int32_t sum; \
    sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
    RESULT(sum, n, 8); \
    if (sum >= 0) \
        ge |= 1 << n; \
    } while(0)


#define ADD16(a, b, n) SARITH16(a, b, n, +)
#define SUB16(a, b, n) SARITH16(a, b, n, -)
#define ADD8(a, b, n)  SARITH8(a, b, n, +)
#define SUB8(a, b, n)  SARITH8(a, b, n, -)
#define PFX s
#define ARITH_GE

#include "op_addsub.h"

/* Unsigned modulo arithmetic.  */
#define ADD16(a, b, n) do { \
    uint32_t sum; \
    sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
    RESULT(sum, n, 16); \
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    if ((sum >> 16) == 1) \
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        ge |= 3 << (n * 2); \
    } while(0)

#define ADD8(a, b, n) do { \
    uint32_t sum; \
    sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
    RESULT(sum, n, 8); \
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    if ((sum >> 8) == 1) \
        ge |= 1 << n; \
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    } while(0)

#define SUB16(a, b, n) do { \
    uint32_t sum; \
    sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
    RESULT(sum, n, 16); \
    if ((sum >> 16) == 0) \
        ge |= 3 << (n * 2); \
    } while(0)

#define SUB8(a, b, n) do { \
    uint32_t sum; \
    sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
    RESULT(sum, n, 8); \
    if ((sum >> 8) == 0) \
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        ge |= 1 << n; \
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    } while(0)

#define PFX u
#define ARITH_GE

#include "op_addsub.h"

/* Halved signed arithmetic.  */
#define ADD16(a, b, n) \
  RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
#define SUB16(a, b, n) \
  RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
#define ADD8(a, b, n) \
  RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
#define SUB8(a, b, n) \
  RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
#define PFX sh

#include "op_addsub.h"

/* Halved unsigned arithmetic.  */
#define ADD16(a, b, n) \
  RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
#define SUB16(a, b, n) \
  RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
#define ADD8(a, b, n) \
  RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
#define SUB8(a, b, n) \
  RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
#define PFX uh

#include "op_addsub.h"

static inline uint8_t do_usad(uint8_t a, uint8_t b)
{
    if (a > b)
        return a - b;
    else
        return b - a;
}

/* Unsigned sum of absolute byte differences.  */
uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
{
    uint32_t sum;
    sum = do_usad(a, b);
    sum += do_usad(a >> 8, b >> 8);
    sum += do_usad(a >> 16, b >>16);
    sum += do_usad(a >> 24, b >> 24);
    return sum;
}

/* For ARMv6 SEL instruction.  */
uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
{
    uint32_t mask;

    mask = 0;
    if (flags & 1)
        mask |= 0xff;
    if (flags & 2)
        mask |= 0xff00;
    if (flags & 4)
        mask |= 0xff0000;
    if (flags & 8)
        mask |= 0xff000000;
    return (a & mask) | (b & ~mask);
}

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uint32_t HELPER(logicq_cc)(uint64_t val)
{
    return (val >> 32) | (val != 0);
}
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/* VFP support.  We follow the convention used for VFP instrunctions:
   Single precition routines have a "s" suffix, double precision a
   "d" suffix.  */

/* Convert host exception flags to vfp form.  */
static inline int vfp_exceptbits_from_host(int host_bits)
{
    int target_bits = 0;

    if (host_bits & float_flag_invalid)
        target_bits |= 1;
    if (host_bits & float_flag_divbyzero)
        target_bits |= 2;
    if (host_bits & float_flag_overflow)
        target_bits |= 4;
    if (host_bits & float_flag_underflow)
        target_bits |= 8;
    if (host_bits & float_flag_inexact)
        target_bits |= 0x10;
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    if (host_bits & float_flag_input_denormal)
        target_bits |= 0x80;
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    return target_bits;
}

uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
{
    int i;
    uint32_t fpscr;

    fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
            | (env->vfp.vec_len << 16)
            | (env->vfp.vec_stride << 20);
    i = get_float_exception_flags(&env->vfp.fp_status);
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    i |= get_float_exception_flags(&env->vfp.standard_fp_status);
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    fpscr |= vfp_exceptbits_from_host(i);
    return fpscr;
}

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uint32_t vfp_get_fpscr(CPUState *env)
{
    return HELPER(vfp_get_fpscr)(env);
}

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/* Convert vfp exception flags to target form.  */
static inline int vfp_exceptbits_to_host(int target_bits)
{
    int host_bits = 0;

    if (target_bits & 1)
        host_bits |= float_flag_invalid;
    if (target_bits & 2)
        host_bits |= float_flag_divbyzero;
    if (target_bits & 4)
        host_bits |= float_flag_overflow;
    if (target_bits & 8)
        host_bits |= float_flag_underflow;
    if (target_bits & 0x10)
        host_bits |= float_flag_inexact;
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    if (target_bits & 0x80)
        host_bits |= float_flag_input_denormal;
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    return host_bits;
}

void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
{
    int i;
    uint32_t changed;

    changed = env->vfp.xregs[ARM_VFP_FPSCR];
    env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
    env->vfp.vec_len = (val >> 16) & 7;
    env->vfp.vec_stride = (val >> 20) & 3;

    changed ^= val;
    if (changed & (3 << 22)) {
        i = (val >> 22) & 3;
        switch (i) {
        case 0:
            i = float_round_nearest_even;
            break;
        case 1:
            i = float_round_up;
            break;
        case 2:
            i = float_round_down;
            break;
        case 3:
            i = float_round_to_zero;
            break;
        }
        set_float_rounding_mode(i, &env->vfp.fp_status);
    }
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    if (changed & (1 << 24)) {
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        set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
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        set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
    }
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    if (changed & (1 << 25))
        set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
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    i = vfp_exceptbits_to_host(val);
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    set_float_exception_flags(i, &env->vfp.fp_status);
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    set_float_exception_flags(0, &env->vfp.standard_fp_status);
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}

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void vfp_set_fpscr(CPUState *env, uint32_t val)
{
    HELPER(vfp_set_fpscr)(env, val);
}

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#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))

#define VFP_BINOP(name) \
float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
{ \
    return float32_ ## name (a, b, &env->vfp.fp_status); \
} \
float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
{ \
    return float64_ ## name (a, b, &env->vfp.fp_status); \
}
VFP_BINOP(add)
VFP_BINOP(sub)
VFP_BINOP(mul)
VFP_BINOP(div)
#undef VFP_BINOP

float32 VFP_HELPER(neg, s)(float32 a)
{
    return float32_chs(a);
}

float64 VFP_HELPER(neg, d)(float64 a)
{
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    return float64_chs(a);
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}

float32 VFP_HELPER(abs, s)(float32 a)
{
    return float32_abs(a);
}

float64 VFP_HELPER(abs, d)(float64 a)
{
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    return float64_abs(a);
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}

float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
{
    return float32_sqrt(a, &env->vfp.fp_status);
}

float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
{
    return float64_sqrt(a, &env->vfp.fp_status);
}

/* XXX: check quiet/signaling case */
#define DO_VFP_cmp(p, type) \
void VFP_HELPER(cmp, p)(type a, type b, CPUState *env)  \
{ \
    uint32_t flags; \
    switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
    case 0: flags = 0x6; break; \
    case -1: flags = 0x8; break; \
    case 1: flags = 0x2; break; \
    default: case 2: flags = 0x3; break; \
    } \
    env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
        | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
} \
void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
{ \
    uint32_t flags; \
    switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
    case 0: flags = 0x6; break; \
    case -1: flags = 0x8; break; \
    case 1: flags = 0x2; break; \
    default: case 2: flags = 0x3; break; \
    } \
    env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
        | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
}
DO_VFP_cmp(s, float32)
DO_VFP_cmp(d, float64)
#undef DO_VFP_cmp

/* Helper routines to perform bitwise copies between float and int.  */
static inline float32 vfp_itos(uint32_t i)
{
    union {
        uint32_t i;
        float32 s;
    } v;

    v.i = i;
    return v.s;
}

static inline uint32_t vfp_stoi(float32 s)
{
    union {
        uint32_t i;
        float32 s;
    } v;

    v.s = s;
    return v.i;
}

static inline float64 vfp_itod(uint64_t i)
{
    union {
        uint64_t i;
        float64 d;
    } v;

    v.i = i;
    return v.d;
}

static inline uint64_t vfp_dtoi(float64 d)
{
    union {
        uint64_t i;
        float64 d;
    } v;

    v.d = d;
    return v.i;
}

/* Integer to float conversion.  */
float32 VFP_HELPER(uito, s)(float32 x, CPUState *env)
{
    return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
}

float64 VFP_HELPER(uito, d)(float32 x, CPUState *env)
{
    return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
}

float32 VFP_HELPER(sito, s)(float32 x, CPUState *env)
{
    return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
}

float64 VFP_HELPER(sito, d)(float32 x, CPUState *env)
{
    return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
}

/* Float to integer conversion.  */
float32 VFP_HELPER(toui, s)(float32 x, CPUState *env)
{
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    if (float32_is_any_nan(x)) {
        return float32_zero;
    }
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    return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
}

float32 VFP_HELPER(toui, d)(float64 x, CPUState *env)
{
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    if (float64_is_any_nan(x)) {
        return float32_zero;
    }
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    return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
}

float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env)
{
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    if (float32_is_any_nan(x)) {
        return float32_zero;
    }
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    return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
}

float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env)
{
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    if (float64_is_any_nan(x)) {
        return float32_zero;
    }
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    return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
}

float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env)
{
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    if (float32_is_any_nan(x)) {
        return float32_zero;
    }
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    return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
}

float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env)
{
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    if (float64_is_any_nan(x)) {
        return float32_zero;
    }
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    return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
}

float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
{
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    if (float32_is_any_nan(x)) {
        return float32_zero;
    }
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    return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
}

float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
{
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    if (float64_is_any_nan(x)) {
        return float32_zero;
    }
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    return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
}

/* floating point conversion */
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
{
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    float64 r = float32_to_float64(x, &env->vfp.fp_status);
    /* ARM requires that S<->D conversion of any kind of NaN generates
     * a quiet NaN by forcing the most significant frac bit to 1.
     */
    return float64_maybe_silence_nan(r);
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}

float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
{
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    float32 r =  float64_to_float32(x, &env->vfp.fp_status);
    /* ARM requires that S<->D conversion of any kind of NaN generates
     * a quiet NaN by forcing the most significant frac bit to 1.
     */
    return float32_maybe_silence_nan(r);
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}

/* VFP3 fixed point conversion.  */
#define VFP_CONV_FIX(name, p, ftype, itype, sign) \
ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
{ \
    ftype tmp; \
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    tmp = sign##int32_to_##ftype ((itype##_t)vfp_##p##toi(x), \
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                                  &env->vfp.fp_status); \
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    return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
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} \
ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
{ \
    ftype tmp; \
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    if (ftype##_is_any_nan(x)) { \
        return ftype##_zero; \
    } \
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    tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
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    return vfp_ito##p(ftype##_to_##itype##_round_to_zero(tmp, \
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        &env->vfp.fp_status)); \
}

VFP_CONV_FIX(sh, d, float64, int16, )
VFP_CONV_FIX(sl, d, float64, int32, )
VFP_CONV_FIX(uh, d, float64, uint16, u)
VFP_CONV_FIX(ul, d, float64, uint32, u)
VFP_CONV_FIX(sh, s, float32, int16, )
VFP_CONV_FIX(sl, s, float32, int32, )
VFP_CONV_FIX(uh, s, float32, uint16, u)
VFP_CONV_FIX(ul, s, float32, uint32, u)
#undef VFP_CONV_FIX

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/* Half precision conversions.  */
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
{
    float_status *s = &env->vfp.fp_status;
    int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
    return float16_to_float32(a, ieee, s);
}

uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
{
    float_status *s = &env->vfp.fp_status;
    int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
    return float32_to_float16(a, ieee, s);
}

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float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
{
    float_status *s = &env->vfp.fp_status;
    float32 two = int32_to_float32(2, s);
    return float32_sub(two, float32_mul(a, b, s), s);
}

float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
{
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    float_status *s = &env->vfp.standard_fp_status;
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    float32 two = int32_to_float32(2, s);
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    float32 three = int32_to_float32(3, s);
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    float32 product;
    if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
        (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
        product = float32_zero;
    } else {
        product = float32_mul(a, b, s);
    }
    return float32_div(float32_sub(three, product, s), two, s);
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}

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/* NEON helpers.  */

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/* TODO: The architecture specifies the value that the estimate functions
   should return.  We return the exact reciprocal/root instead.  */
float32 HELPER(recpe_f32)(float32 a, CPUState *env)
{
    float_status *s = &env->vfp.fp_status;
    float32 one = int32_to_float32(1, s);
    return float32_div(one, a, s);
}

float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
{
    float_status *s = &env->vfp.fp_status;
    float32 one = int32_to_float32(1, s);
    return float32_div(one, float32_sqrt(a, s), s);
}

uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
{
    float_status *s = &env->vfp.fp_status;
    float32 tmp;
    tmp = int32_to_float32(a, s);
    tmp = float32_scalbn(tmp, -32, s);
    tmp = helper_recpe_f32(tmp, env);
    tmp = float32_scalbn(tmp, 31, s);
    return float32_to_int32(tmp, s);
}

uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
{
    float_status *s = &env->vfp.fp_status;
    float32 tmp;
    tmp = int32_to_float32(a, s);
    tmp = float32_scalbn(tmp, -32, s);
    tmp = helper_rsqrte_f32(tmp, env);
    tmp = float32_scalbn(tmp, 31, s);
    return float32_to_int32(tmp, s);
}
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void HELPER(set_teecr)(CPUState *env, uint32_t val)
{
    val &= 1;
    if (env->teecr != val) {
        env->teecr = val;
        tb_flush(env);
    }
}