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提交 c227f099 编写于 作者: A Anthony Liguori
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Revert "Get rid of _t suffix" 

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b.
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
上级 99a0949b
展开全部 隐藏空白更改
内联 并排
Showing with 3334 addition and 3327 deletion
CODING_STYLE
浏览文件 @ c227f099
......@@ -40,10 +40,14 @@ Rationale:
3. Naming
Variables are lower_case_with_underscores; easy to type and read.
Structured type names are in CamelCase; harder to type but standing
out. Scalar type names are a_lower_case_beginning_with_an a or an.
Do not use _t suffix if you are including any headers.
Variables are lower_case_with_underscores; easy to type and read. Structured
type names are in CamelCase; harder to type but standing out. Scalar type
names are lower_case_with_underscores_ending_with_a_t, like the POSIX
uint64_t and family. Note that this last convention contradicts POSIX
and is therefore likely to be changed.
Typedefs are used to eliminate the redundant 'struct' keyword. It is the
QEMU coding style.
4. Block structure
......
balloon.h
浏览文件 @ c227f099
......@@ -16,12 +16,12 @@
#include "cpu-defs.h"
typedef a_ram_addr (QEMUBalloonEvent)(void *opaque, a_ram_addr target);
typedef ram_addr_t (QEMUBalloonEvent)(void *opaque, ram_addr_t target);
void qemu_add_balloon_handler(QEMUBalloonEvent *func, void *opaque);
void qemu_balloon(a_ram_addr target);
void qemu_balloon(ram_addr_t target);
a_ram_addr qemu_balloon_status(void);
ram_addr_t qemu_balloon_status(void);
#endif
block/vvfat.c
浏览文件 @ c227f099
此差异已折叠。
console.c
浏览文件 @ c227f099
......@@ -110,12 +110,12 @@ typedef enum {
GRAPHIC_CONSOLE,
TEXT_CONSOLE,
TEXT_CONSOLE_FIXED_SIZE
} e_console_type;
} console_type_t;
/* ??? This is mis-named.
It is used for both text and graphical consoles. */
struct TextConsole {
e_console_type console_type;
console_type_t console_type;
DisplayState *ds;
/* Graphic console state. */
vga_hw_update_ptr hw_update;
......@@ -183,7 +183,7 @@ void vga_hw_screen_dump(const char *filename)
active_console = previous_active_console;
}
void vga_hw_text_update(a_console_ch *chardata)
void vga_hw_text_update(console_ch_t *chardata)
{
if (active_console && active_console->hw_text_update)
active_console->hw_text_update(active_console->hw, chardata);
......@@ -1197,7 +1197,7 @@ static void text_console_invalidate(void *opaque)
console_refresh(s);
}
static void text_console_update(void *opaque, a_console_ch *chardata)
static void text_console_update(void *opaque, console_ch_t *chardata)
{
TextConsole *s = (TextConsole *) opaque;
int i, j, src;
......@@ -1236,7 +1236,7 @@ static TextConsole *get_graphic_console(DisplayState *ds)
return NULL;
}
static TextConsole *new_console(DisplayState *ds, e_console_type console_type)
static TextConsole *new_console(DisplayState *ds, console_type_t console_type)
{
TextConsole *s;
int i;
......
console.h
浏览文件 @ c227f099
......@@ -279,8 +279,8 @@ static inline int ds_get_bytes_per_pixel(DisplayState *ds)
return ds->surface->pf.bytes_per_pixel;
}
typedef unsigned long a_console_ch;
static inline void console_write_ch(a_console_ch *dest, uint32_t ch)
typedef unsigned long console_ch_t;
static inline void console_write_ch(console_ch_t *dest, uint32_t ch)
{
cpu_to_le32wu((uint32_t *) dest, ch);
}
......@@ -288,7 +288,7 @@ static inline void console_write_ch(a_console_ch *dest, uint32_t ch)
typedef void (*vga_hw_update_ptr)(void *);
typedef void (*vga_hw_invalidate_ptr)(void *);
typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
typedef void (*vga_hw_text_update_ptr)(void *, a_console_ch *);
typedef void (*vga_hw_text_update_ptr)(void *, console_ch_t *);
DisplayState *graphic_console_init(vga_hw_update_ptr update,
vga_hw_invalidate_ptr invalidate,
......@@ -299,7 +299,7 @@ DisplayState *graphic_console_init(vga_hw_update_ptr update,
void vga_hw_update(void);
void vga_hw_invalidate(void);
void vga_hw_screen_dump(const char *filename);
void vga_hw_text_update(a_console_ch *chardata);
void vga_hw_text_update(console_ch_t *chardata);
int is_graphic_console(void);
int is_fixedsize_console(void);
......
cpu-all.h
浏览文件 @ c227f099
......@@ -814,7 +814,7 @@ void cpu_reset(CPUState *s);
/* Return the physical page corresponding to a virtual one. Use it
only for debugging because no protection checks are done. Return -1
if no page found. */
a_target_phys_addr cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
#define CPU_LOG_TB_OUT_ASM (1 << 0)
#define CPU_LOG_TB_IN_ASM (1 << 1)
......@@ -847,8 +847,8 @@ int cpu_str_to_log_mask(const char *str);
extern int phys_ram_fd;
extern uint8_t *phys_ram_dirty;
extern a_ram_addr ram_size;
extern a_ram_addr last_ram_offset;
extern ram_addr_t ram_size;
extern ram_addr_t last_ram_offset;
/* physical memory access */
......@@ -876,23 +876,23 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
#define MIGRATION_DIRTY_FLAG 0x08
/* read dirty bit (return 0 or 1) */
static inline int cpu_physical_memory_is_dirty(a_ram_addr addr)
static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
{
return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
}
static inline int cpu_physical_memory_get_dirty(a_ram_addr addr,
static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
int dirty_flags)
{
return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
}
static inline void cpu_physical_memory_set_dirty(a_ram_addr addr)
static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
{
phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
}
void cpu_physical_memory_reset_dirty(a_ram_addr start, a_ram_addr end,
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
int dirty_flags);
void cpu_tlb_update_dirty(CPUState *env);
......@@ -900,8 +900,8 @@ int cpu_physical_memory_set_dirty_tracking(int enable);
int cpu_physical_memory_get_dirty_tracking(void);
int cpu_physical_sync_dirty_bitmap(a_target_phys_addr start_addr,
a_target_phys_addr end_addr);
int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
target_phys_addr_t end_addr);
void dump_exec_info(FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
......@@ -911,9 +911,9 @@ void dump_exec_info(FILE *f,
* batching which can make a major impact on performance when using
* virtualization.
*/
void qemu_register_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size);
void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
void qemu_unregister_coalesced_mmio(a_target_phys_addr addr, a_ram_addr size);
void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
/*******************************************/
/* host CPU ticks (if available) */
......
cpu-common.h
浏览文件 @ c227f099
......@@ -10,69 +10,69 @@
#include "bswap.h"
/* address in the RAM (different from a physical address) */
typedef unsigned long a_ram_addr;
typedef unsigned long ram_addr_t;
/* memory API */
typedef void CPUWriteMemoryFunc(void *opaque, a_target_phys_addr addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, a_target_phys_addr addr);
typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
void cpu_register_physical_memory_offset(a_target_phys_addr start_addr,
a_ram_addr size,
a_ram_addr phys_offset,
a_ram_addr region_offset);
static inline void cpu_register_physical_memory(a_target_phys_addr start_addr,
a_ram_addr size,
a_ram_addr phys_offset)
void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset,
ram_addr_t region_offset);
static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
ram_addr_t size,
ram_addr_t phys_offset)
{
cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
}
a_ram_addr cpu_get_physical_page_desc(a_target_phys_addr addr);
a_ram_addr qemu_ram_alloc(a_ram_addr);
void qemu_ram_free(a_ram_addr addr);
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc(ram_addr_t);
void qemu_ram_free(ram_addr_t addr);
/* This should only be used for ram local to a device. */
void *qemu_get_ram_ptr(a_ram_addr addr);
void *qemu_get_ram_ptr(ram_addr_t addr);
/* This should not be used by devices. */
a_ram_addr qemu_ram_addr_from_host(void *ptr);
ram_addr_t qemu_ram_addr_from_host(void *ptr);
int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write,
void *opaque);
void cpu_unregister_io_memory(int table_address);
void cpu_physical_memory_rw(a_target_phys_addr addr, uint8_t *buf,
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
int len, int is_write);
static inline void cpu_physical_memory_read(a_target_phys_addr addr,
static inline void cpu_physical_memory_read(target_phys_addr_t addr,
uint8_t *buf, int len)
{
cpu_physical_memory_rw(addr, buf, len, 0);
}
static inline void cpu_physical_memory_write(a_target_phys_addr addr,
static inline void cpu_physical_memory_write(target_phys_addr_t addr,
const uint8_t *buf, int len)
{
cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
}
void *cpu_physical_memory_map(a_target_phys_addr addr,
a_target_phys_addr *plen,
void *cpu_physical_memory_map(target_phys_addr_t addr,
target_phys_addr_t *plen,
int is_write);
void cpu_physical_memory_unmap(void *buffer, a_target_phys_addr len,
int is_write, a_target_phys_addr access_len);
void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
int is_write, target_phys_addr_t access_len);
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
void cpu_unregister_map_client(void *cookie);
uint32_t ldub_phys(a_target_phys_addr addr);
uint32_t lduw_phys(a_target_phys_addr addr);
uint32_t ldl_phys(a_target_phys_addr addr);
uint64_t ldq_phys(a_target_phys_addr addr);
void stl_phys_notdirty(a_target_phys_addr addr, uint32_t val);
void stq_phys_notdirty(a_target_phys_addr addr, uint64_t val);
void stb_phys(a_target_phys_addr addr, uint32_t val);
void stw_phys(a_target_phys_addr addr, uint32_t val);
void stl_phys(a_target_phys_addr addr, uint32_t val);
void stq_phys(a_target_phys_addr addr, uint64_t val);
void cpu_physical_memory_write_rom(a_target_phys_addr addr,
uint32_t ldub_phys(target_phys_addr_t addr);
uint32_t lduw_phys(target_phys_addr_t addr);
uint32_t ldl_phys(target_phys_addr_t addr);
uint64_t ldq_phys(target_phys_addr_t addr);
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
void stb_phys(target_phys_addr_t addr, uint32_t val);
void stw_phys(target_phys_addr_t addr, uint32_t val);
void stl_phys(target_phys_addr_t addr, uint32_t val);
void stq_phys(target_phys_addr_t addr, uint64_t val);
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
const uint8_t *buf, int len);
#define IO_MEM_SHIFT 3
......
cpu-defs.h
浏览文件 @ c227f099
......@@ -95,15 +95,15 @@ typedef struct CPUTLBEntry {
use the corresponding iotlb value. */
#if TARGET_PHYS_ADDR_BITS == 64
/* on i386 Linux make sure it is aligned */
a_target_phys_addr addend __attribute__((aligned(8)));
target_phys_addr_t addend __attribute__((aligned(8)));
#else
a_target_phys_addr addend;
target_phys_addr_t addend;
#endif
/* padding to get a power of two size */
uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
(sizeof(target_ulong) * 3 +
((-sizeof(target_ulong) * 3) & (sizeof(a_target_phys_addr) - 1)) +
sizeof(a_target_phys_addr))];
((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
sizeof(target_phys_addr_t))];
} CPUTLBEntry;
#ifdef HOST_WORDS_BIGENDIAN
......@@ -152,7 +152,7 @@ typedef struct CPUWatchpoint {
volatile sig_atomic_t exit_request; \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
a_target_phys_addr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
/* buffer for temporaries in the code generator */ \
long temp_buf[CPU_TEMP_BUF_NLONGS]; \
......
curses.c
浏览文件 @ c227f099
......@@ -40,7 +40,7 @@
#define FONT_HEIGHT 16
#define FONT_WIDTH 8
static a_console_ch screen[160 * 100];
static console_ch_t screen[160 * 100];
static WINDOW *screenpad = NULL;
static int width, height, gwidth, gheight, invalidate;
static int px, py, sminx, sminy, smaxx, smaxy;
......@@ -158,7 +158,7 @@ static void curses_cursor_position(DisplayState *ds, int x, int y)
#include "curses_keys.h"
static a_kbd_layout *kbd_layout = NULL;
static kbd_layout_t *kbd_layout = NULL;
static int keycode2keysym[CURSES_KEYS];
static void curses_refresh(DisplayState *ds)
......
curses_keys.h
浏览文件 @ c227f099
......@@ -243,7 +243,7 @@ static const int curses2keysym[CURSES_KEYS] = {
};
static const a_name2keysym name2keysym[] = {
static const name2keysym_t name2keysym[] = {
/* Plain ASCII */
{ "space", 0x020 },
{ "exclam", 0x021 },
......
darwin-user/commpage.c
浏览文件 @ c227f099
......@@ -109,7 +109,7 @@ static struct commpage_entry commpage_entries[] =
COMMPAGE_ENTRY(add_atomic_word64, 0, 0x1c0, unimpl_commpage, CALL_INDIRECT | HAS_PTR),
COMMPAGE_ENTRY(mach_absolute_time, 0, 0x200, unimpl_commpage, CALL_INDIRECT),
COMMPAGE_ENTRY(a_spinlockry, 1, 0x220, unimpl_commpage, CALL_INDIRECT),
COMMPAGE_ENTRY(spinlock_try, 1, 0x220, unimpl_commpage, CALL_INDIRECT),
COMMPAGE_ENTRY(spinlock_lock, 1, 0x260, OSSpinLockLock, CALL_DIRECT),
COMMPAGE_ENTRY(spinlock_unlock, 1, 0x2a0, OSSpinLockUnlock, CALL_DIRECT),
COMMPAGE_ENTRY(pthread_getspecific, 0, 0x2c0, unimpl_commpage, CALL_INDIRECT),
......
darwin-user/machload.c
浏览文件 @ c227f099
......@@ -101,7 +101,7 @@ typedef struct mach_i386_thread_state {
unsigned int es;
unsigned int fs;
unsigned int gs;
};
} mach_i386_thread_state_t;
void bswap_i386_thread_state(struct mach_i386_thread_state *ts)
{
......
darwin-user/qemu.h
浏览文件 @ c227f099
......@@ -10,7 +10,7 @@
#include "gdbstub.h"
typedef siginfo_t a_target_siginfo;
typedef siginfo_t target_siginfo_t;
#define target_sigaction sigaction
#ifdef TARGET_I386
struct target_pt_regs {
......
disas.h
浏览文件 @ c227f099
......@@ -22,7 +22,7 @@ struct syminfo;
struct elf32_sym;
struct elf64_sym;
typedef const char *(*lookup_symbol_t)(struct syminfo *s, a_target_phys_addr orig_addr);
typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_phys_addr_t orig_addr);
struct syminfo {
lookup_symbol_t lookup_symbol;
......
dma-helpers.c
浏览文件 @ c227f099
......@@ -18,8 +18,8 @@ void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint)
qsg->size = 0;
}
void qemu_sglist_add(QEMUSGList *qsg, a_target_phys_addr base,
a_target_phys_addr len)
void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base,
target_phys_addr_t len)
{
if (qsg->nsg == qsg->nalloc) {
qsg->nalloc = 2 * qsg->nalloc + 1;
......@@ -44,7 +44,7 @@ typedef struct {
uint64_t sector_num;
int is_write;
int sg_cur_index;
a_target_phys_addr sg_cur_byte;
target_phys_addr_t sg_cur_byte;
QEMUIOVector iov;
QEMUBH *bh;
} DMAAIOCB;
......@@ -82,7 +82,7 @@ static void dma_bdrv_unmap(DMAAIOCB *dbs)
static void dma_bdrv_cb(void *opaque, int ret)
{
DMAAIOCB *dbs = (DMAAIOCB *)opaque;
a_target_phys_addr cur_addr, cur_len;
target_phys_addr_t cur_addr, cur_len;
void *mem;
dbs->acb = NULL;
......
dma.h
浏览文件 @ c227f099
......@@ -16,20 +16,20 @@
#include "block.h"
typedef struct {
a_target_phys_addr base;
a_target_phys_addr len;
target_phys_addr_t base;
target_phys_addr_t len;
} ScatterGatherEntry;
typedef struct {
ScatterGatherEntry *sg;
int nsg;
int nalloc;
a_target_phys_addr size;
target_phys_addr_t size;
} QEMUSGList;
void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint);
void qemu_sglist_add(QEMUSGList *qsg, a_target_phys_addr base,
a_target_phys_addr len);
void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base,
target_phys_addr_t len);
void qemu_sglist_destroy(QEMUSGList *qsg);
BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs,
......
dyngen-exec.h
浏览文件 @ c227f099
......@@ -37,7 +37,7 @@
#endif
/* XXX: This may be wrong for 64-bit ILP32 hosts. */
typedef void * a_host_reg;
typedef void * host_reg_t;
#ifdef CONFIG_BSD
typedef struct __sFILE FILE;
......
exec-all.h
浏览文件 @ c227f099
......@@ -81,16 +81,16 @@ TranslationBlock *tb_gen_code(CPUState *env,
void cpu_exec_init(CPUState *env);
void QEMU_NORETURN cpu_loop_exit(void);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(a_target_phys_addr start, a_target_phys_addr end,
void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
a_target_phys_addr paddr, int prot,
target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu);
static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
a_target_phys_addr paddr, int prot,
target_phys_addr_t paddr, int prot,
int mmu_idx, int is_softmmu)
{
if (prot & PAGE_READ)
......@@ -269,7 +269,7 @@ extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
#include "qemu-lock.h"
extern a_spinlock tb_lock;
extern spinlock_t tb_lock;
extern int tb_invalidated_flag;
......
exec.c
浏览文件 @ c227f099
此差异已折叠。
hostregs_helper.h
浏览文件 @ c227f099
......@@ -27,8 +27,8 @@
#if defined(DECLARE_HOST_REGS)
#define DO_REG(REG) \
register a_host_reg reg_AREG##REG asm(AREG##REG); \
volatile a_host_reg saved_AREG##REG;
register host_reg_t reg_AREG##REG asm(AREG##REG); \
volatile host_reg_t saved_AREG##REG;
#elif defined(SAVE_HOST_REGS)
......
hw/an5206.c
浏览文件 @ c227f099
......@@ -29,7 +29,7 @@ void irq_info(Monitor *mon)
/* Board init. */
static void an5206_init(a_ram_addr ram_size,
static void an5206_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
......@@ -37,7 +37,7 @@ static void an5206_init(a_ram_addr ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
a_target_phys_addr entry;
target_phys_addr_t entry;
if (!cpu_model)
cpu_model = "m5206";
......
hw/apb_pci.c
浏览文件 @ c227f099
......@@ -39,7 +39,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
#define APB_DPRINTF(fmt, ...)
#endif
typedef a_target_phys_addr a_pci_addr;
typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"
typedef struct APBState {
......@@ -47,7 +47,7 @@ typedef struct APBState {
PCIHostState host_state;
} APBState;
static void pci_apb_config_writel (void *opaque, a_target_phys_addr addr,
static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
APBState *s = opaque;
......@@ -61,7 +61,7 @@ static void pci_apb_config_writel (void *opaque, a_target_phys_addr addr,
}
static uint32_t pci_apb_config_readl (void *opaque,
a_target_phys_addr addr)
target_phys_addr_t addr)
{
APBState *s = opaque;
uint32_t val;
......@@ -87,7 +87,7 @@ static CPUReadMemoryFunc * const pci_apb_config_read[] = {
&pci_apb_config_readl,
};
static void apb_config_writel (void *opaque, a_target_phys_addr addr,
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
//PCIBus *s = opaque;
......@@ -105,7 +105,7 @@ static void apb_config_writel (void *opaque, a_target_phys_addr addr,
}
static uint32_t apb_config_readl (void *opaque,
a_target_phys_addr addr)
target_phys_addr_t addr)
{
//PCIBus *s = opaque;
uint32_t val;
......@@ -148,25 +148,25 @@ static CPUReadMemoryFunc * const pci_apb_read[] = {
&pci_host_data_readl,
};
static void pci_apb_iowriteb (void *opaque, a_target_phys_addr addr,
static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
static void pci_apb_iowritew (void *opaque, a_target_phys_addr addr,
static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, val);
}
static void pci_apb_iowritel (void *opaque, a_target_phys_addr addr,
static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, val);
}
static uint32_t pci_apb_ioreadb (void *opaque, a_target_phys_addr addr)
static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
......@@ -174,7 +174,7 @@ static uint32_t pci_apb_ioreadb (void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t pci_apb_ioreadw (void *opaque, a_target_phys_addr addr)
static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
......@@ -182,7 +182,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t pci_apb_ioreadl (void *opaque, a_target_phys_addr addr)
static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
{
uint32_t val;
......@@ -226,8 +226,8 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(pic[irq_num], level);
}
PCIBus *pci_apb_init(a_target_phys_addr special_base,
a_target_phys_addr mem_base,
PCIBus *pci_apb_init(target_phys_addr_t special_base,
target_phys_addr_t mem_base,
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
DeviceState *dev;
......
hw/apic.c
浏览文件 @ c227f099
......@@ -661,25 +661,25 @@ static void apic_timer(void *opaque)
apic_timer_update(s, s->next_time);
}
static uint32_t apic_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
{
return 0;
}
static uint32_t apic_mem_readw(void *opaque, a_target_phys_addr addr)
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
{
return 0;
}
static void apic_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
}
static void apic_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
}
static uint32_t apic_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
{
CPUState *env;
APICState *s;
......@@ -760,7 +760,7 @@ static uint32_t apic_mem_readl(void *opaque, a_target_phys_addr addr)
return val;
}
static void apic_send_msi(a_target_phys_addr addr, uint32 data)
static void apic_send_msi(target_phys_addr_t addr, uint32 data)
{
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
......@@ -771,7 +771,7 @@ static void apic_send_msi(a_target_phys_addr addr, uint32 data)
apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
}
static void apic_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CPUState *env;
APICState *s;
......
hw/arm-misc.h
浏览文件 @ c227f099
......@@ -26,8 +26,8 @@ struct arm_boot_info {
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
a_target_phys_addr loader_start;
a_target_phys_addr smp_loader_start;
target_phys_addr_t loader_start;
target_phys_addr_t smp_loader_start;
int nb_cpus;
int board_id;
int (*atag_board)(struct arm_boot_info *info, void *p);
......
hw/arm_boot.c
浏览文件 @ c227f099
......@@ -61,9 +61,9 @@ static void main_cpu_reset(void *opaque)
} while (0)
static void set_kernel_args(struct arm_boot_info *info,
int initrd_size, a_target_phys_addr base)
int initrd_size, target_phys_addr_t base)
{
a_target_phys_addr p;
target_phys_addr_t p;
p = base + KERNEL_ARGS_ADDR;
/* ATAG_CORE */
......@@ -114,9 +114,9 @@ static void set_kernel_args(struct arm_boot_info *info,
}
static void set_kernel_args_old(struct arm_boot_info *info,
int initrd_size, a_target_phys_addr base)
int initrd_size, target_phys_addr_t base)
{
a_target_phys_addr p;
target_phys_addr_t p;
const char *s;
......@@ -193,7 +193,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
int n;
int is_linux = 0;
uint64_t elf_entry;
a_target_phys_addr entry;
target_phys_addr_t entry;
int big_endian;
/* Load the kernel. */
......
hw/arm_gic.c
浏览文件 @ c227f099
......@@ -238,7 +238,7 @@ static void gic_complete_irq(gic_state * s, int cpu, int irq)
}
}
static uint32_t gic_dist_readb(void *opaque, a_target_phys_addr offset)
static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
{
gic_state *s = (gic_state *)opaque;
uint32_t res;
......@@ -348,7 +348,7 @@ bad_reg:
return 0;
}
static uint32_t gic_dist_readw(void *opaque, a_target_phys_addr offset)
static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
{
uint32_t val;
val = gic_dist_readb(opaque, offset);
......@@ -356,7 +356,7 @@ static uint32_t gic_dist_readw(void *opaque, a_target_phys_addr offset)
return val;
}
static uint32_t gic_dist_readl(void *opaque, a_target_phys_addr offset)
static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
{
uint32_t val;
#ifdef NVIC
......@@ -371,7 +371,7 @@ static uint32_t gic_dist_readl(void *opaque, a_target_phys_addr offset)
return val;
}
static void gic_dist_writeb(void *opaque, a_target_phys_addr offset,
static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
......@@ -509,14 +509,14 @@ bad_reg:
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
static void gic_dist_writew(void *opaque, a_target_phys_addr offset,
static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
gic_dist_writeb(opaque, offset, value & 0xff);
gic_dist_writeb(opaque, offset + 1, value >> 8);
}
static void gic_dist_writel(void *opaque, a_target_phys_addr offset,
static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
......
hw/arm_sysctl.c
浏览文件 @ c227f099
......@@ -27,7 +27,7 @@ typedef struct {
uint32_t resetlevel;
} arm_sysctl_state;
static uint32_t arm_sysctl_read(void *opaque, a_target_phys_addr offset)
static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
......@@ -104,7 +104,7 @@ static uint32_t arm_sysctl_read(void *opaque, a_target_phys_addr offset)
}
}
static void arm_sysctl_write(void *opaque, a_target_phys_addr offset,
static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
uint32_t val)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
......
hw/arm_timer.c
浏览文件 @ c227f099
......@@ -42,7 +42,7 @@ static void arm_timer_update(arm_timer_state *s)
}
}
static uint32_t arm_timer_read(void *opaque, a_target_phys_addr offset)
static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;
......@@ -84,7 +84,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload)
ptimer_set_limit(s->timer, limit, reload);
}
static void arm_timer_write(void *opaque, a_target_phys_addr offset,
static void arm_timer_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
arm_timer_state *s = (arm_timer_state *)opaque;
......@@ -199,7 +199,7 @@ static void sp804_set_irq(void *opaque, int irq, int level)
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
static uint32_t sp804_read(void *opaque, a_target_phys_addr offset)
static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
{
sp804_state *s = (sp804_state *)opaque;
......@@ -211,7 +211,7 @@ static uint32_t sp804_read(void *opaque, a_target_phys_addr offset)
}
}
static void sp804_write(void *opaque, a_target_phys_addr offset,
static void sp804_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
sp804_state *s = (sp804_state *)opaque;
......@@ -283,7 +283,7 @@ typedef struct {
arm_timer_state *timer[3];
} icp_pit_state;
static uint32_t icp_pit_read(void *opaque, a_target_phys_addr offset)
static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
{
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
......@@ -297,7 +297,7 @@ static uint32_t icp_pit_read(void *opaque, a_target_phys_addr offset)
return arm_timer_read(s->timer[n], offset & 0xff);
}
static void icp_pit_write(void *opaque, a_target_phys_addr offset,
static void icp_pit_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
icp_pit_state *s = (icp_pit_state *)opaque;
......
hw/armv7m.c
浏览文件 @ c227f099
......@@ -26,14 +26,14 @@ static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
}
static uint32_t bitband_readb(void *opaque, a_target_phys_addr offset)
static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
{
uint8_t v;
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
static void bitband_writeb(void *opaque, a_target_phys_addr offset,
static void bitband_writeb(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
uint32_t addr;
......@@ -49,7 +49,7 @@ static void bitband_writeb(void *opaque, a_target_phys_addr offset,
cpu_physical_memory_write(addr, &v, 1);
}
static uint32_t bitband_readw(void *opaque, a_target_phys_addr offset)
static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
{
uint32_t addr;
uint16_t mask;
......@@ -61,7 +61,7 @@ static uint32_t bitband_readw(void *opaque, a_target_phys_addr offset)
return (v & mask) != 0;
}
static void bitband_writew(void *opaque, a_target_phys_addr offset,
static void bitband_writew(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
uint32_t addr;
......@@ -78,7 +78,7 @@ static void bitband_writew(void *opaque, a_target_phys_addr offset,
cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}
static uint32_t bitband_readl(void *opaque, a_target_phys_addr offset)
static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
{
uint32_t addr;
uint32_t mask;
......@@ -90,7 +90,7 @@ static uint32_t bitband_readl(void *opaque, a_target_phys_addr offset)
return (v & mask) != 0;
}
static void bitband_writel(void *opaque, a_target_phys_addr offset,
static void bitband_writel(void *opaque, target_phys_addr_t offset,
uint32_t value)
{
uint32_t addr;
......
hw/axis_dev88.c
浏览文件 @ c227f099
......@@ -44,7 +44,7 @@ struct nand_state_t
};
static struct nand_state_t nand_state;
static uint32_t nand_readl (void *opaque, a_target_phys_addr addr)
static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
{
struct nand_state_t *s = opaque;
uint32_t r;
......@@ -59,7 +59,7 @@ static uint32_t nand_readl (void *opaque, a_target_phys_addr addr)
}
static void
nand_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct nand_state_t *s = opaque;
int rdy;
......@@ -168,7 +168,7 @@ static struct gpio_state_t
uint32_t regs[0x5c / 4];
} gpio_state;
static uint32_t gpio_readl (void *opaque, a_target_phys_addr addr)
static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
......@@ -197,7 +197,7 @@ static uint32_t gpio_readl (void *opaque, a_target_phys_addr addr)
D(printf("%s %x=%x\n", __func__, addr, r));
}
static void gpio_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct gpio_state_t *s = opaque;
D(printf("%s %x=%x\n", __func__, addr, value));
......@@ -250,7 +250,7 @@ static void main_cpu_reset(void *opaque)
}
static
void axisdev88_init (a_ram_addr ram_size,
void axisdev88_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
......@@ -265,8 +265,8 @@ void axisdev88_init (a_ram_addr ram_size,
int i;
int nand_regs;
int gpio_regs;
a_ram_addr phys_ram;
a_ram_addr phys_intmem;
ram_addr_t phys_ram;
ram_addr_t phys_intmem;
/* init CPUs */
if (cpu_model == NULL) {
......
hw/boards.h
浏览文件 @ c227f099
......@@ -5,7 +5,7 @@
#include "qdev.h"
typedef void QEMUMachineInitFunc(a_ram_addr ram_size,
typedef void QEMUMachineInitFunc(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
......
hw/bt-hci-csr.c
浏览文件 @ c227f099
......@@ -44,7 +44,7 @@ struct csrhci_s {
QEMUTimer *out_tm;
int64_t baud_delay;
a_bdaddr bd_addr;
bdaddr_t bd_addr;
struct HCIInfo *hci;
};
......@@ -398,7 +398,7 @@ static void csrhci_reset(struct csrhci_s *s)
/* After a while... (but sooner than 10ms) */
s->modem_state |= CHR_TIOCM_CTS;
memset(&s->bd_addr, 0, sizeof(a_bdaddr));
memset(&s->bd_addr, 0, sizeof(bdaddr_t));
}
static void csrhci_out_tick(void *opaque)
......
hw/bt-hci.c
浏览文件 @ c227f099
......@@ -62,7 +62,7 @@ struct bt_hci_s {
uint32_t role_bmp;
int last_handle;
int connecting;
a_bdaddr awaiting_bdaddr[HCI_HANDLES_MAX];
bdaddr_t awaiting_bdaddr[HCI_HANDLES_MAX];
} lm;
uint8_t event_mask[8];
......@@ -672,7 +672,7 @@ static void bt_hci_lmp_link_teardown(struct bt_hci_s *hci, uint16_t handle)
}
}
static int bt_hci_connect(struct bt_hci_s *hci, a_bdaddr *bdaddr)
static int bt_hci_connect(struct bt_hci_s *hci, bdaddr_t *bdaddr)
{
struct bt_device_s *slave;
struct bt_link_s link;
......@@ -706,7 +706,7 @@ static void bt_hci_connection_reject(struct bt_hci_s *hci,
}
static void bt_hci_connection_reject_event(struct bt_hci_s *hci,
a_bdaddr *bdaddr)
bdaddr_t *bdaddr)
{
evt_conn_complete params;
......@@ -808,7 +808,7 @@ static void bt_hci_conn_accept_timeout(void *opaque)
* that's been cancelled by the host in the meantime and immediately
* try to detach the link and send a Connection Complete. */
static int bt_hci_lmp_connection_ready(struct bt_hci_s *hci,
a_bdaddr *bdaddr)
bdaddr_t *bdaddr)
{
int i;
......@@ -939,7 +939,7 @@ static void bt_hci_lmp_disconnect_slave(struct bt_link_s *btlink)
&params, EVT_DISCONN_COMPLETE_SIZE);
}
static int bt_hci_name_req(struct bt_hci_s *hci, a_bdaddr *bdaddr)
static int bt_hci_name_req(struct bt_hci_s *hci, bdaddr_t *bdaddr)
{
struct bt_device_s *slave;
evt_remote_name_req_complete params;
......@@ -1290,7 +1290,7 @@ static inline void bt_hci_event_complete_status(struct bt_hci_s *hci,
}
static inline void bt_hci_event_complete_conn_cancel(struct bt_hci_s *hci,
uint8_t status, a_bdaddr *bd_addr)
uint8_t status, bdaddr_t *bd_addr)
{
create_conn_cancel_rp params = {
.status = status,
......@@ -1324,7 +1324,7 @@ static inline void bt_hci_event_encrypt_change(struct bt_hci_s *hci,
}
static inline void bt_hci_event_complete_name_cancel(struct bt_hci_s *hci,
a_bdaddr *bd_addr)
bdaddr_t *bd_addr)
{
remote_name_req_cancel_rp params = {
.status = HCI_INVALID_PARAMETERS,
......@@ -2134,7 +2134,7 @@ static int bt_hci_bdaddr_set(struct HCIInfo *info, const uint8_t *bd_addr)
{
struct bt_hci_s *hci = hci_from_info(info);
bacpy(&hci->device.bd_addr, (const a_bdaddr *) bd_addr);
bacpy(&hci->device.bd_addr, (const bdaddr_t *) bd_addr);
return 0;
}
......
hw/bt.h
浏览文件 @ c227f099
......@@ -26,20 +26,20 @@
/* BD Address */
typedef struct {
uint8_t b[6];
} __attribute__((packed)) a_bdaddr;
} __attribute__((packed)) bdaddr_t;
#define BDADDR_ANY (&(a_bdaddr) {{0, 0, 0, 0, 0, 0}})
#define BDADDR_ALL (&(a_bdaddr) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}})
#define BDADDR_LOCAL (&(a_bdaddr) {{0, 0, 0, 0xff, 0xff, 0xff}})
#define BDADDR_ANY (&(bdaddr_t) {{0, 0, 0, 0, 0, 0}})
#define BDADDR_ALL (&(bdaddr_t) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}})
#define BDADDR_LOCAL (&(bdaddr_t) {{0, 0, 0, 0xff, 0xff, 0xff}})
/* Copy, swap, convert BD Address */
static inline int bacmp(const a_bdaddr *ba1, const a_bdaddr *ba2)
static inline int bacmp(const bdaddr_t *ba1, const bdaddr_t *ba2)
{
return memcmp(ba1, ba2, sizeof(a_bdaddr));
return memcmp(ba1, ba2, sizeof(bdaddr_t));
}
static inline void bacpy(a_bdaddr *dst, const a_bdaddr *src)
static inline void bacpy(bdaddr_t *dst, const bdaddr_t *src)
{
memcpy(dst, src, sizeof(a_bdaddr));
memcpy(dst, src, sizeof(bdaddr_t));
}
#define BAINIT(orig) { .b = { \
......@@ -71,7 +71,7 @@ struct bt_link_s {
struct bt_device_s {
int lt_addr;
a_bdaddr bd_addr;
bdaddr_t bd_addr;
int mtu;
int setup;
struct bt_scatternet_s *net;
......@@ -451,7 +451,7 @@ typedef struct {
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) status_bdaddr_rp;
#define STATUS_BDADDR_RP_SIZE 7
......@@ -471,7 +471,7 @@ typedef struct {
#define OCF_CREATE_CONN 0x0005
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint16_t pkt_type;
uint8_t pscan_rep_mode;
uint8_t pscan_mode;
......@@ -497,33 +497,33 @@ typedef struct {
#define OCF_CREATE_CONN_CANCEL 0x0008
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) create_conn_cancel_cp;
#define CREATE_CONN_CANCEL_CP_SIZE 6
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) create_conn_cancel_rp;
#define CREATE_CONN_CANCEL_RP_SIZE 7
#define OCF_ACCEPT_CONN_REQ 0x0009
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t role;
} __attribute__ ((packed)) accept_conn_req_cp;
#define ACCEPT_CONN_REQ_CP_SIZE 7
#define OCF_REJECT_CONN_REQ 0x000A
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t reason;
} __attribute__ ((packed)) reject_conn_req_cp;
#define REJECT_CONN_REQ_CP_SIZE 7
#define OCF_LINK_KEY_REPLY 0x000B
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t link_key[16];
} __attribute__ ((packed)) link_key_reply_cp;
#define LINK_KEY_REPLY_CP_SIZE 22
......@@ -532,7 +532,7 @@ typedef struct {
#define OCF_PIN_CODE_REPLY 0x000D
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pin_len;
uint8_t pin_code[16];
} __attribute__ ((packed)) pin_code_reply_cp;
......@@ -574,7 +574,7 @@ typedef struct {
#define OCF_REMOTE_NAME_REQ 0x0019
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_mode;
uint16_t clock_offset;
......@@ -583,13 +583,13 @@ typedef struct {
#define OCF_REMOTE_NAME_REQ_CANCEL 0x001A
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) remote_name_req_cancel_cp;
#define REMOTE_NAME_REQ_CANCEL_CP_SIZE 6
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) remote_name_req_cancel_rp;
#define REMOTE_NAME_REQ_CANCEL_RP_SIZE 7
......@@ -646,7 +646,7 @@ typedef struct {
#define OCF_ACCEPT_SYNC_CONN_REQ 0x0029
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint32_t tx_bandwith;
uint32_t rx_bandwith;
uint16_t max_latency;
......@@ -658,7 +658,7 @@ typedef struct {
#define OCF_REJECT_SYNC_CONN_REQ 0x002A
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t reason;
} __attribute__ ((packed)) reject_sync_conn_req_cp;
#define REJECT_SYNC_CONN_REQ_CP_SIZE 7
......@@ -734,7 +734,7 @@ typedef struct {
#define OCF_SWITCH_ROLE 0x000B
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t role;
} __attribute__ ((packed)) switch_role_cp;
#define SWITCH_ROLE_CP_SIZE 7
......@@ -847,7 +847,7 @@ typedef struct {
#define OCF_READ_STORED_LINK_KEY 0x000D
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t read_all;
} __attribute__ ((packed)) read_stored_link_key_cp;
#define READ_STORED_LINK_KEY_CP_SIZE 7
......@@ -872,7 +872,7 @@ typedef struct {
#define OCF_DELETE_STORED_LINK_KEY 0x0012
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t delete_all;
} __attribute__ ((packed)) delete_stored_link_key_cp;
#define DELETE_STORED_LINK_KEY_CP_SIZE 7
......@@ -1238,7 +1238,7 @@ typedef struct {
#define OCF_READ_BD_ADDR 0x0009
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) read_bd_addr_rp;
#define READ_BD_ADDR_RP_SIZE 7
......@@ -1317,7 +1317,7 @@ typedef struct {
#define EVT_INQUIRY_RESULT 0x02
typedef struct {
uint8_t num_responses;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t pscan_mode;
......@@ -1330,7 +1330,7 @@ typedef struct {
typedef struct {
uint8_t status;
uint16_t handle;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t link_type;
uint8_t encr_mode;
} __attribute__ ((packed)) evt_conn_complete;
......@@ -1338,7 +1338,7 @@ typedef struct {
#define EVT_CONN_REQUEST 0x04
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t dev_class[3];
uint8_t link_type;
} __attribute__ ((packed)) evt_conn_request;
......@@ -1362,7 +1362,7 @@ typedef struct {
#define EVT_REMOTE_NAME_REQ_COMPLETE 0x07
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
char name[248];
} __attribute__ ((packed)) evt_remote_name_req_complete;
#define EVT_REMOTE_NAME_REQ_COMPLETE_SIZE 255
......@@ -1447,7 +1447,7 @@ typedef struct {
#define EVT_ROLE_CHANGE 0x12
typedef struct {
uint8_t status;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t role;
} __attribute__ ((packed)) evt_role_change;
#define EVT_ROLE_CHANGE_SIZE 8
......@@ -1480,19 +1480,19 @@ typedef struct {
#define EVT_PIN_CODE_REQ 0x16
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) evt_pin_code_req;
#define EVT_PIN_CODE_REQ_SIZE 6
#define EVT_LINK_KEY_REQ 0x17
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
} __attribute__ ((packed)) evt_link_key_req;
#define EVT_LINK_KEY_REQ_SIZE 6
#define EVT_LINK_KEY_NOTIFY 0x18
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t link_key[16];
uint8_t key_type;
} __attribute__ ((packed)) evt_link_key_notify;
......@@ -1537,7 +1537,7 @@ typedef struct {
#define EVT_PSCAN_REP_MODE_CHANGE 0x20
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
} __attribute__ ((packed)) evt_pscan_rep_mode_change;
#define EVT_PSCAN_REP_MODE_CHANGE_SIZE 7
......@@ -1555,7 +1555,7 @@ typedef struct {
#define EVT_INQUIRY_RESULT_WITH_RSSI 0x22
typedef struct {
uint8_t num_responses;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t dev_class[3];
......@@ -1565,7 +1565,7 @@ typedef struct {
#define INQUIRY_INFO_WITH_RSSI_SIZE 15
typedef struct {
uint8_t num_responses;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t pscan_mode;
......@@ -1589,7 +1589,7 @@ typedef struct {
typedef struct {
uint8_t status;
uint16_t handle;
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t link_type;
uint8_t trans_interval;
uint8_t retrans_window;
......@@ -1623,7 +1623,7 @@ typedef struct {
#define EVT_EXTENDED_INQUIRY_RESULT 0x2F
typedef struct {
a_bdaddr bdaddr;
bdaddr_t bdaddr;
uint8_t pscan_rep_mode;
uint8_t pscan_period_mode;
uint8_t dev_class[3];
......
hw/cirrus_vga.c
浏览文件 @ c227f099
......@@ -1214,7 +1214,7 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
/* Thinking about changing bank base? First, drop the dirty bitmap information
* on the current location, otherwise we lose this pointer forever */
if (s->vga.lfb_vram_mapped) {
a_target_phys_addr base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
}
s->cirrus_bank_base[bank_index] = offset;
......@@ -1988,7 +1988,7 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
*
***************************************/
static uint32_t cirrus_vga_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
{
CirrusVGAState *s = opaque;
unsigned bank_index;
......@@ -2032,7 +2032,7 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t cirrus_vga_mem_readw(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2045,7 +2045,7 @@ static uint32_t cirrus_vga_mem_readw(void *opaque, a_target_phys_addr addr)
return v;
}
static uint32_t cirrus_vga_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2062,7 +2062,7 @@ static uint32_t cirrus_vga_mem_readl(void *opaque, a_target_phys_addr addr)
return v;
}
static void cirrus_vga_mem_writeb(void *opaque, a_target_phys_addr addr,
static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
CirrusVGAState *s = opaque;
......@@ -2127,7 +2127,7 @@ static void cirrus_vga_mem_writeb(void *opaque, a_target_phys_addr addr,
}
}
static void cirrus_vga_mem_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
......@@ -2138,7 +2138,7 @@ static void cirrus_vga_mem_writew(void *opaque, a_target_phys_addr addr, uint32_
#endif
}
static void cirrus_vga_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
......@@ -2341,7 +2341,7 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
*
***************************************/
static uint32_t cirrus_linear_readb(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
{
CirrusVGAState *s = opaque;
uint32_t ret;
......@@ -2369,7 +2369,7 @@ static uint32_t cirrus_linear_readb(void *opaque, a_target_phys_addr addr)
return ret;
}
static uint32_t cirrus_linear_readw(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2382,7 +2382,7 @@ static uint32_t cirrus_linear_readw(void *opaque, a_target_phys_addr addr)
return v;
}
static uint32_t cirrus_linear_readl(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2399,7 +2399,7 @@ static uint32_t cirrus_linear_readl(void *opaque, a_target_phys_addr addr)
return v;
}
static void cirrus_linear_writeb(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
......@@ -2440,7 +2440,7 @@ static void cirrus_linear_writeb(void *opaque, a_target_phys_addr addr,
}
}
static void cirrus_linear_writew(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2452,7 +2452,7 @@ static void cirrus_linear_writew(void *opaque, a_target_phys_addr addr,
#endif
}
static void cirrus_linear_writel(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2488,7 +2488,7 @@ static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
***************************************/
static uint32_t cirrus_linear_bitblt_readb(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
{
uint32_t ret;
......@@ -2497,7 +2497,7 @@ static uint32_t cirrus_linear_bitblt_readb(void *opaque, a_target_phys_addr addr
return ret;
}
static uint32_t cirrus_linear_bitblt_readw(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2510,7 +2510,7 @@ static uint32_t cirrus_linear_bitblt_readw(void *opaque, a_target_phys_addr addr
return v;
}
static uint32_t cirrus_linear_bitblt_readl(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2527,7 +2527,7 @@ static uint32_t cirrus_linear_bitblt_readl(void *opaque, a_target_phys_addr addr
return v;
}
static void cirrus_linear_bitblt_writeb(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
......@@ -2541,7 +2541,7 @@ static void cirrus_linear_bitblt_writeb(void *opaque, a_target_phys_addr addr,
}
}
static void cirrus_linear_bitblt_writew(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2553,7 +2553,7 @@ static void cirrus_linear_bitblt_writew(void *opaque, a_target_phys_addr addr,
#endif
}
static void cirrus_linear_bitblt_writel(void *opaque, a_target_phys_addr addr,
static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2855,7 +2855,7 @@ static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
*
***************************************/
static uint32_t cirrus_mmio_readb(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
{
CirrusVGAState *s = opaque;
......@@ -2868,7 +2868,7 @@ static uint32_t cirrus_mmio_readb(void *opaque, a_target_phys_addr addr)
}
}
static uint32_t cirrus_mmio_readw(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2881,7 +2881,7 @@ static uint32_t cirrus_mmio_readw(void *opaque, a_target_phys_addr addr)
return v;
}
static uint32_t cirrus_mmio_readl(void *opaque, a_target_phys_addr addr)
static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2898,7 +2898,7 @@ static uint32_t cirrus_mmio_readl(void *opaque, a_target_phys_addr addr)
return v;
}
static void cirrus_mmio_writeb(void *opaque, a_target_phys_addr addr,
static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
CirrusVGAState *s = opaque;
......@@ -2912,7 +2912,7 @@ static void cirrus_mmio_writeb(void *opaque, a_target_phys_addr addr,
}
}
static void cirrus_mmio_writew(void *opaque, a_target_phys_addr addr,
static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
......@@ -2924,7 +2924,7 @@ static void cirrus_mmio_writew(void *opaque, a_target_phys_addr addr,
#endif
}
static void cirrus_mmio_writel(void *opaque, a_target_phys_addr addr,
static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
......
hw/cs4231.c
浏览文件 @ c227f099
......@@ -64,7 +64,7 @@ static void cs_reset(void *opaque)
s->dregs[25] = CS_VER;
}
static uint32_t cs_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
{
CSState *s = opaque;
uint32_t saddr, ret;
......@@ -90,7 +90,7 @@ static uint32_t cs_mem_readl(void *opaque, a_target_phys_addr addr)
return ret;
}
static void cs_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CSState *s = opaque;
uint32_t saddr;
......
hw/cuda.c
浏览文件 @ c227f099
......@@ -250,7 +250,7 @@ static void cuda_timer1(void *opaque)
cuda_update_irq(s);
}
static uint32_t cuda_readb(void *opaque, a_target_phys_addr addr)
static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
{
CUDAState *s = opaque;
uint32_t val;
......@@ -321,7 +321,7 @@ static uint32_t cuda_readb(void *opaque, a_target_phys_addr addr)
return val;
}
static void cuda_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CUDAState *s = opaque;
......@@ -612,20 +612,20 @@ static void cuda_receive_packet_from_host(CUDAState *s,
}
}
static void cuda_writew (void *opaque, a_target_phys_addr addr, uint32_t value)
static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}
static void cuda_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}
static uint32_t cuda_readw (void *opaque, a_target_phys_addr addr)
static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
{
return 0;
}
static uint32_t cuda_readl (void *opaque, a_target_phys_addr addr)
static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
{
return 0;
}
......
hw/dma.c
浏览文件 @ c227f099
......@@ -401,7 +401,7 @@ void DMA_register_channel (int nchan,
int DMA_read_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
a_target_phys_addr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
......@@ -423,7 +423,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len)
int DMA_write_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
a_target_phys_addr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
......
hw/dp8393x.c
浏览文件 @ c227f099
......@@ -166,7 +166,7 @@ typedef struct dp8393xState {
int loopback_packet;
/* Memory access */
void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write);
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
void* mem_opaque;
} dp8393xState;
......@@ -601,7 +601,7 @@ static void dp8393x_watchdog(void *opaque)
dp8393x_update_irq(s);
}
static uint32_t dp8393x_readw(void *opaque, a_target_phys_addr addr)
static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
{
dp8393xState *s = opaque;
int reg;
......@@ -614,13 +614,13 @@ static uint32_t dp8393x_readw(void *opaque, a_target_phys_addr addr)
return read_register(s, reg);
}
static uint32_t dp8393x_readb(void *opaque, a_target_phys_addr addr)
static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr)
{
uint16_t v = dp8393x_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
static uint32_t dp8393x_readl(void *opaque, a_target_phys_addr addr)
static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = dp8393x_readw(opaque, addr);
......@@ -628,7 +628,7 @@ static uint32_t dp8393x_readl(void *opaque, a_target_phys_addr addr)
return v;
}
static void dp8393x_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
dp8393xState *s = opaque;
int reg;
......@@ -642,7 +642,7 @@ static void dp8393x_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
write_register(s, reg, (uint16_t)val);
}
static void dp8393x_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1);
......@@ -657,7 +657,7 @@ static void dp8393x_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
dp8393x_writew(opaque, addr & ~0x1, val);
}
static void dp8393x_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
dp8393x_writew(opaque, addr, val & 0xffff);
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
......@@ -872,9 +872,9 @@ static void nic_cleanup(VLANClientState *vc)
qemu_free(s);
}
void dp83932_init(NICInfo *nd, a_target_phys_addr base, int it_shift,
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, a_target_phys_addr addr, uint8_t *buf, int len, int is_write))
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;
......
hw/ds1225y.c
浏览文件 @ c227f099
......@@ -34,12 +34,12 @@ typedef struct ds1225y_t
QEMUFile *file;
uint8_t *contents;
uint8_t protection;
} a_ds1225y;
} ds1225y_t;
static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
a_ds1225y *s = opaque;
ds1225y_t *s = opaque;
uint32_t val;
val = s->contents[addr];
......@@ -50,7 +50,7 @@ static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr)
return val;
}
static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
......@@ -58,7 +58,7 @@ static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr)
return v;
}
static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
uint32_t v;
v = nvram_readb(opaque, addr);
......@@ -68,9 +68,9 @@ static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr)
return v;
}
static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
{
a_ds1225y *s = opaque;
ds1225y_t *s = opaque;
#ifdef DEBUG_NVRAM
printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr);
......@@ -84,13 +84,13 @@ static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
}
static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb(opaque, addr, val & 0xff);
nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
......@@ -98,9 +98,9 @@ static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t val)
nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}
static void nvram_writeb_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
{
a_ds1225y *s = opaque;
ds1225y_t *s = opaque;
if (s->protection != 7) {
#ifdef DEBUG_NVRAM
......@@ -112,13 +112,13 @@ static void nvram_writeb_protected (void *opaque, a_target_phys_addr addr, uint3
nvram_writeb(opaque, addr, val);
}
static void nvram_writew_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb_protected(opaque, addr, val & 0xff);
nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
}
static void nvram_writel_protected (void *opaque, a_target_phys_addr addr, uint32_t val)
static void nvram_writel_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
{
nvram_writeb_protected(opaque, addr, val & 0xff);
nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
......@@ -145,13 +145,13 @@ static CPUWriteMemoryFunc * const nvram_write_protected[] = {
};
/* Initialisation routine */
void *ds1225y_init(a_target_phys_addr mem_base, const char *filename)
void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
{
a_ds1225y *s;
ds1225y_t *s;
int mem_indexRW, mem_indexRP;
QEMUFile *file;
s = qemu_mallocz(sizeof(a_ds1225y));
s = qemu_mallocz(sizeof(ds1225y_t));
s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
s->contents = qemu_mallocz(s->chip_size);
s->protection = 7;
......
hw/dummy_m68k.c
浏览文件 @ c227f099
......@@ -16,7 +16,7 @@
/* Board init. */
static void dummy_m68k_init(a_ram_addr ram_size,
static void dummy_m68k_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
......@@ -24,7 +24,7 @@ static void dummy_m68k_init(a_ram_addr ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
a_target_phys_addr entry;
target_phys_addr_t entry;
if (!cpu_model)
cpu_model = "cfv4e";
......
hw/e1000.c
浏览文件 @ c227f099
......@@ -478,7 +478,7 @@ process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
}
static uint32_t
txdesc_writeback(a_target_phys_addr base, struct e1000_tx_desc *dp)
txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
{
uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
......@@ -495,7 +495,7 @@ txdesc_writeback(a_target_phys_addr base, struct e1000_tx_desc *dp)
static void
start_xmit(E1000State *s)
{
a_target_phys_addr base;
target_phys_addr_t base;
struct e1000_tx_desc desc;
uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
......@@ -613,7 +613,7 @@ e1000_receive(VLANClientState *vc, const uint8_t *buf, size_t size)
{
E1000State *s = vc->opaque;
struct e1000_rx_desc desc;
a_target_phys_addr base;
target_phys_addr_t base;
unsigned int n, rdt;
uint32_t rdh_start;
uint16_t vlan_special = 0;
......@@ -814,7 +814,7 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
e1000_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
......@@ -832,7 +832,7 @@ e1000_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
}
static void
e1000_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
// emulate hw without byte enables: no RMW
e1000_mmio_writel(opaque, addr & ~3,
......@@ -840,7 +840,7 @@ e1000_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
}
static void
e1000_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
// emulate hw without byte enables: no RMW
e1000_mmio_writel(opaque, addr & ~3,
......@@ -848,7 +848,7 @@ e1000_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
}
static uint32_t
e1000_mmio_readl(void *opaque, a_target_phys_addr addr)
e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
......@@ -866,14 +866,14 @@ e1000_mmio_readl(void *opaque, a_target_phys_addr addr)
}
static uint32_t
e1000_mmio_readb(void *opaque, a_target_phys_addr addr)
e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
{
return ((e1000_mmio_readl(opaque, addr & ~3)) >>
(8 * (addr & 3))) & 0xff;
}
static uint32_t
e1000_mmio_readw(void *opaque, a_target_phys_addr addr)
e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
{
return ((e1000_mmio_readl(opaque, addr & ~3)) >>
(8 * (addr & 3))) & 0xffff;
......
hw/eccmemctl.c
浏览文件 @ c227f099
......@@ -133,7 +133,7 @@ typedef struct ECCState {
uint32_t version;
} ECCState;
static void ecc_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
ECCState *s = opaque;
......@@ -175,7 +175,7 @@ static void ecc_mem_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
static uint32_t ecc_mem_readl(void *opaque, a_target_phys_addr addr)
static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
{
ECCState *s = opaque;
uint32_t ret = 0;
......@@ -233,7 +233,7 @@ static CPUWriteMemoryFunc * const ecc_mem_write[3] = {
ecc_mem_writel,
};
static void ecc_diag_mem_writeb(void *opaque, a_target_phys_addr addr,
static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
ECCState *s = opaque;
......@@ -242,7 +242,7 @@ static void ecc_diag_mem_writeb(void *opaque, a_target_phys_addr addr,
s->diag[addr & ECC_DIAG_MASK] = val;
}
static uint32_t ecc_diag_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
{
ECCState *s = opaque;
uint32_t ret = s->diag[(int)addr];
......
hw/eepro100.c
浏览文件 @ c227f099
......@@ -144,7 +144,7 @@ typedef struct {
//~ int32_t tx_buf_size0; /* Length of Tx hdr. */
//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
//~ int32_t tx_buf_size1; /* Length of Tx data. */
} a_eepro100_tx;
} eepro100_tx_t;
/* Receive frame descriptor. */
typedef struct {
......@@ -155,7 +155,7 @@ typedef struct {
uint16_t count;
uint16_t size;
char packet[MAX_ETH_FRAME_SIZE + 4];
} a_eepro100_rx;
} eepro100_rx_t;
typedef struct {
uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
......@@ -167,7 +167,7 @@ typedef struct {
uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
uint16_t xmt_tco_frames, rcv_tco_frames;
uint32_t complete;
} a_eepro100_stats;
} eepro100_stats_t;
typedef enum {
cu_idle = 0,
......@@ -175,14 +175,14 @@ typedef enum {
cu_active = 2,
cu_lpq_active = 2,
cu_hqp_active = 3
} a_cu_state;
} cu_state_t;
typedef enum {
ru_idle = 0,
ru_suspended = 1,
ru_no_resources = 2,
ru_ready = 4
} a_ru_state;
} ru_state_t;
typedef struct {
PCIDevice dev;
......@@ -213,7 +213,7 @@ typedef struct {
uint8_t macaddr[6];
uint32_t statcounter[19];
uint16_t mdimem[32];
a_eeprom *eeprom;
eeprom_t *eeprom;
uint32_t device; /* device variant */
uint32_t pointer;
/* (cu_base + cu_offset) address the next command block in the command block list. */
......@@ -222,8 +222,8 @@ typedef struct {
/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
uint32_t ru_base; /* RU base address */
uint32_t ru_offset; /* RU address offset */
uint32_t statsaddr; /* pointer to a_eepro100_stats */
a_eepro100_stats statistics; /* statistical counters */
uint32_t statsaddr; /* pointer to eepro100_stats_t */
eepro100_stats_t statistics; /* statistical counters */
#if 0
uint16_t status;
#endif
......@@ -600,22 +600,22 @@ enum commands {
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
};
static a_cu_state get_cu_state(EEPRO100State * s)
static cu_state_t get_cu_state(EEPRO100State * s)
{
return ((s->mem[SCBStatus] >> 6) & 0x03);
}
static void set_cu_state(EEPRO100State * s, a_cu_state state)
static void set_cu_state(EEPRO100State * s, cu_state_t state)
{
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
}
static a_ru_state get_ru_state(EEPRO100State * s)
static ru_state_t get_ru_state(EEPRO100State * s)
{
return ((s->mem[SCBStatus] >> 2) & 0x0f);
}
static void set_ru_state(EEPRO100State * s, a_ru_state state)
static void set_ru_state(EEPRO100State * s, ru_state_t state)
{
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
}
......@@ -639,7 +639,7 @@ static void dump_statistics(EEPRO100State * s)
static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
{
a_eepro100_tx tx;
eepro100_tx_t tx;
uint32_t cb_address;
switch (val) {
case CU_NOP:
......@@ -915,7 +915,7 @@ static uint16_t eepro100_read_eeprom(EEPRO100State * s)
return val;
}
static void eepro100_write_eeprom(a_eeprom * eeprom, uint8_t val)
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
{
TRACE(EEPROM, logout("val=0x%02x\n", val));
......@@ -1099,7 +1099,7 @@ static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
typedef struct {
uint32_t st_sign; /* Self Test Signature */
uint32_t st_result; /* Self Test Results */
} a_eepro100_selftest;
} eepro100_selftest_t;
static uint32_t eepro100_read_port(EEPRO100State * s)
{
......@@ -1117,7 +1117,7 @@ static void eepro100_write_port(EEPRO100State * s, uint32_t val)
break;
case PORT_SELFTEST:
TRACE(OTHER, logout("selftest address=0x%08x\n", address));
a_eepro100_selftest data;
eepro100_selftest_t data;
cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
data.st_sign = 0xffffffff;
data.st_result = 0;
......@@ -1398,42 +1398,42 @@ static void pci_map(PCIDevice * pci_dev, int region_num,
*
****************************************************************************/
static void pci_mmio_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write1(s, addr, val);
}
static void pci_mmio_writew(void *opaque, a_target_phys_addr addr, uint32_t val)
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write2(s, addr, val);
}
static void pci_mmio_writel(void *opaque, a_target_phys_addr addr, uint32_t val)
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
eepro100_write4(s, addr, val);
}
static uint32_t pci_mmio_readb(void *opaque, a_target_phys_addr addr)
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
return eepro100_read1(s, addr);
}
static uint32_t pci_mmio_readw(void *opaque, a_target_phys_addr addr)
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
return eepro100_read2(s, addr);
}
static uint32_t pci_mmio_readl(void *opaque, a_target_phys_addr addr)
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
{
EEPRO100State *s = opaque;
//~ logout("addr=%s\n", regname(addr));
......@@ -1541,9 +1541,9 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
}
//~ !!!
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
a_eepro100_rx rx;
eepro100_rx_t rx;
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
offsetof(a_eepro100_rx, packet));
offsetof(eepro100_rx_t, packet));
uint16_t rfd_command = le16_to_cpu(rx.command);
uint16_t rfd_size = le16_to_cpu(rx.size);
assert(size <= rfd_size);
......@@ -1552,9 +1552,9 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
}
TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, status),
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
rfd_status);
stw_phys(s->ru_base + s->ru_offset + offsetof(a_eepro100_rx, count), size);
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
/* Early receive interrupt not supported. */
//~ eepro100_er_interrupt(s);
/* Receive CRC Transfer not supported. */
......@@ -1562,7 +1562,7 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size
/* TODO: check stripping enable bit. */
//~ assert(!(s->configuration[17] & 1));
cpu_physical_memory_write(s->ru_base + s->ru_offset +
offsetof(a_eepro100_rx, packet), buf, size);
offsetof(eepro100_rx_t, packet), buf, size);
s->statistics.rx_good_frames++;
eepro100_fr_interrupt(s);
s->ru_offset = le32_to_cpu(rx.link);
......
hw/eeprom93xx.c
浏览文件 @ c227f099
......@@ -71,7 +71,7 @@ static const char *opstring[] = {
};
#endif
struct eeprom {
struct _eeprom_t {
uint8_t tick;
uint8_t address;
uint8_t command;
......@@ -93,7 +93,7 @@ static void eeprom_save(QEMUFile *f, void *opaque)
{
/* Save EEPROM data. */
unsigned address;
a_eeprom *eeprom = (a_eeprom *)opaque;
eeprom_t *eeprom = (eeprom_t *)opaque;
qemu_put_byte(f, eeprom->tick);
qemu_put_byte(f, eeprom->address);
......@@ -116,7 +116,7 @@ static int eeprom_load(QEMUFile *f, void *opaque, int version_id)
{
/* Load EEPROM data from saved data if version and EEPROM size
of data and current EEPROM are identical. */
a_eeprom *eeprom = (a_eeprom *)opaque;
eeprom_t *eeprom = (eeprom_t *)opaque;
int result = -EINVAL;
if (version_id >= OLD_EEPROM_VERSION) {
unsigned address;
......@@ -150,7 +150,7 @@ static int eeprom_load(QEMUFile *f, void *opaque, int version_id)
return result;
}
void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi)
void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi)
{
uint8_t tick = eeprom->tick;
uint8_t eedo = eeprom->eedo;
......@@ -275,7 +275,7 @@ void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi)
eeprom->command = command;
}
uint16_t eeprom93xx_read(a_eeprom *eeprom)
uint16_t eeprom93xx_read(eeprom_t *eeprom)
{
/* Return status of pin DO (0 or 1). */
logout("CS=%u DO=%u\n", eeprom->eecs, eeprom->eedo);
......@@ -292,10 +292,10 @@ void eeprom93xx_reset(eeprom_t *eeprom)
}
#endif
a_eeprom *eeprom93xx_new(uint16_t nwords)
eeprom_t *eeprom93xx_new(uint16_t nwords)
{
/* Add a new EEPROM (with 16, 64 or 256 words). */
a_eeprom *eeprom;
eeprom_t *eeprom;
uint8_t addrbits;
switch (nwords) {
......@@ -313,7 +313,7 @@ a_eeprom *eeprom93xx_new(uint16_t nwords)
addrbits = 6;
}
eeprom = (a_eeprom *)qemu_mallocz(sizeof(*eeprom) + nwords * 2);
eeprom = (eeprom_t *)qemu_mallocz(sizeof(*eeprom) + nwords * 2);
eeprom->size = nwords;
eeprom->addrbits = addrbits;
/* Output DO is tristate, read results in 1. */
......@@ -324,7 +324,7 @@ a_eeprom *eeprom93xx_new(uint16_t nwords)
return eeprom;
}
void eeprom93xx_free(a_eeprom *eeprom)
void eeprom93xx_free(eeprom_t *eeprom)
{
/* Destroy EEPROM. */
logout("eeprom = 0x%p\n", eeprom);
......@@ -332,7 +332,7 @@ void eeprom93xx_free(a_eeprom *eeprom)
qemu_free(eeprom);
}
uint16_t *eeprom93xx_data(a_eeprom *eeprom)
uint16_t *eeprom93xx_data(eeprom_t *eeprom)
{
/* Get EEPROM data array. */
return &eeprom->contents[0];
......
hw/eeprom93xx.h
浏览文件 @ c227f099
......@@ -20,21 +20,21 @@
#ifndef EEPROM93XX_H
#define EEPROM93XX_H
typedef struct eeprom a_eeprom;
typedef struct _eeprom_t eeprom_t;
/* Create a new EEPROM with (nwords * 2) bytes. */
a_eeprom *eeprom93xx_new(uint16_t nwords);
eeprom_t *eeprom93xx_new(uint16_t nwords);
/* Destroy an existing EEPROM. */
void eeprom93xx_free(a_eeprom *eeprom);
void eeprom93xx_free(eeprom_t *eeprom);
/* Read from the EEPROM. */
uint16_t eeprom93xx_read(a_eeprom *eeprom);
uint16_t eeprom93xx_read(eeprom_t *eeprom);
/* Write to the EEPROM. */
void eeprom93xx_write(a_eeprom *eeprom, int eecs, int eesk, int eedi);
void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi);
/* Get EEPROM data array. */
uint16_t *eeprom93xx_data(a_eeprom *eeprom);
uint16_t *eeprom93xx_data(eeprom_t *eeprom);
#endif /* EEPROM93XX_H */
hw/elf_ops.h
浏览文件 @ c227f099
......@@ -74,7 +74,7 @@ static int glue(symfind, SZ)(const void *s0, const void *s1)
}
static const char *glue(lookup_symbol, SZ)(struct syminfo *s,
a_target_phys_addr orig_addr)
target_phys_addr_t orig_addr)
{
struct elf_sym *syms = glue(s->disas_symtab.elf, SZ);
struct elf_sym key;
......
hw/escc.c
浏览文件 @ c227f099
......@@ -84,13 +84,13 @@
typedef enum {
chn_a, chn_b,
} e_chn_id;
} chn_id_t;
#define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
typedef enum {
ser, kbd, mouse,
} e_chn_type;
} chn_type_t;
#define SERIO_QUEUE_SIZE 256
......@@ -104,8 +104,8 @@ typedef struct ChannelState {
qemu_irq irq;
uint32_t reg;
uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
e_chn_id chn; // this channel, A (base+4) or B (base+0)
e_chn_type type;
chn_id_t chn; // this channel, A (base+4) or B (base+0)
chn_type_t type;
struct ChannelState *otherchn;
uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS];
SERIOQueue queue;
......@@ -481,7 +481,7 @@ static void escc_update_parameters(ChannelState *s)
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
static void escc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void escc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
SerialState *serial = opaque;
ChannelState *s;
......@@ -578,7 +578,7 @@ static void escc_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
}
}
static uint32_t escc_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t escc_mem_readb(void *opaque, target_phys_addr_t addr)
{
SerialState *serial = opaque;
ChannelState *s;
......@@ -725,7 +725,7 @@ static int escc_load(QEMUFile *f, void *opaque, int version_id)
}
int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB,
int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift)
{
......@@ -890,7 +890,7 @@ static void sunmouse_event(void *opaque,
put_queue(s, 0);
}
void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq,
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
int disabled, int clock, int it_shift)
{
DeviceState *dev;
......
hw/escc.h
浏览文件 @ c227f099
/* escc.c */
#define ESCC_SIZE 4
int escc_init(a_target_phys_addr base, qemu_irq irqA, qemu_irq irqB,
int escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift);
void slavio_serial_ms_kbd_init(a_target_phys_addr base, qemu_irq irq,
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
int disabled, int clock, int it_shift);
hw/esp.c
浏览文件 @ c227f099
......@@ -439,7 +439,7 @@ static void parent_esp_reset(void *opaque, int irq, int level)
esp_reset(opaque);
}
static uint32_t esp_mem_readb(void *opaque, a_target_phys_addr addr)
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
{
ESPState *s = opaque;
uint32_t saddr, old_val;
......@@ -480,7 +480,7 @@ static uint32_t esp_mem_readb(void *opaque, a_target_phys_addr addr)
return s->rregs[saddr];
}
static void esp_mem_writeb(void *opaque, a_target_phys_addr addr, uint32_t val)
static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
ESPState *s = opaque;
uint32_t saddr;
......@@ -632,7 +632,7 @@ static const VMStateDescription vmstate_esp = {
}
};
void esp_init(a_target_phys_addr espaddr, int it_shift,
void esp_init(target_phys_addr_t espaddr, int it_shift,
espdma_memory_read_write dma_memory_read,
espdma_memory_read_write dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset)
......
hw/etraxfs.c
浏览文件 @ c227f099
......@@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque)
}
static
void bareetraxfs_init (a_ram_addr ram_size,
void bareetraxfs_init (ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
......@@ -59,9 +59,9 @@ void bareetraxfs_init (a_ram_addr ram_size,
int kernel_size;
DriveInfo *dinfo;
int i;
a_ram_addr phys_ram;
a_ram_addr phys_flash;
a_ram_addr phys_intmem;
ram_addr_t phys_ram;
ram_addr_t phys_flash;
ram_addr_t phys_intmem;
/* init CPUs */
if (cpu_model == NULL) {
......
hw/etraxfs.h
浏览文件 @ c227f099
......@@ -25,4 +25,4 @@
#include "etraxfs_dma.h"
qemu_irq *cris_pic_init_cpu(CPUState *env);
void *etraxfs_eth_init(NICInfo *nd, a_target_phys_addr base, int phyaddr);
void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr);
hw/etraxfs_dma.c
浏览文件 @ c227f099
......@@ -211,7 +211,7 @@ static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
&& ctrl->channels[c].client;
}
static inline int fs_channel(a_target_phys_addr addr)
static inline int fs_channel(target_phys_addr_t addr)
{
/* Every channel has a 0x2000 ctrl register map. */
return addr >> 13;
......@@ -220,7 +220,7 @@ static inline int fs_channel(a_target_phys_addr addr)
#ifdef USE_THIS_DEAD_CODE
static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
{
a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP);
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
......@@ -252,7 +252,7 @@ static void dump_d(int ch, struct dma_descr_data *d)
static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
{
a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
......@@ -269,7 +269,7 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
a_target_phys_addr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Load and decode. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
......@@ -283,7 +283,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
a_target_phys_addr addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
......@@ -295,7 +295,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
a_target_phys_addr addr = channel_reg(ctrl, c, RW_SAVED_DATA);
target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
......@@ -556,14 +556,14 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
return 0;
}
static uint32_t dma_rinvalid (void *opaque, a_target_phys_addr addr)
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
{
hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
return 0;
}
static uint32_t
dma_readl (void *opaque, a_target_phys_addr addr)
dma_readl (void *opaque, target_phys_addr_t addr)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
......@@ -591,7 +591,7 @@ dma_readl (void *opaque, a_target_phys_addr addr)
}
static void
dma_winvalid (void *opaque, a_target_phys_addr addr, uint32_t value)
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
{
hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
}
......@@ -608,7 +608,7 @@ dma_update_state(struct fs_dma_ctrl *ctrl, int c)
}
static void
dma_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
......@@ -739,7 +739,7 @@ static void DMA_run(void *opaque)
qemu_bh_schedule_idle(etraxfs_dmac->bh);
}
void *etraxfs_dmac_init(a_target_phys_addr base, int nr_channels)
void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
{
struct fs_dma_ctrl *ctrl = NULL;
......
hw/etraxfs_dma.h
浏览文件 @ c227f099
......@@ -13,7 +13,7 @@ struct etraxfs_dma_client
} client;
};
void *etraxfs_dmac_init(a_target_phys_addr base, int nr_channels);
void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels);
void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line,
int input);
void etraxfs_dmac_connect_client(void *opaque, int c,
......
hw/etraxfs_eth.c
浏览文件 @ c227f099
......@@ -365,7 +365,7 @@ static void eth_validate_duplex(struct fs_eth *eth)
}
}
static uint32_t eth_readl (void *opaque, a_target_phys_addr addr)
static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
{
struct fs_eth *eth = opaque;
uint32_t r = 0;
......@@ -409,7 +409,7 @@ static void eth_update_ma(struct fs_eth *eth, int ma)
}
static void
eth_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct fs_eth *eth = opaque;
......@@ -564,7 +564,7 @@ static void eth_cleanup(VLANClientState *vc)
qemu_free(eth);
}
void *etraxfs_eth_init(NICInfo *nd, a_target_phys_addr base, int phyaddr)
void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr)
{
struct etraxfs_dma_client *dma = NULL;
struct fs_eth *eth = NULL;
......
hw/etraxfs_pic.c
浏览文件 @ c227f099
......@@ -77,7 +77,7 @@ static void pic_update(struct etrax_pic *fs)
qemu_set_irq(fs->parent_irq, !!vector);
}
static uint32_t pic_readl (void *opaque, a_target_phys_addr addr)
static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
{
struct etrax_pic *fs = opaque;
uint32_t rval;
......@@ -88,7 +88,7 @@ static uint32_t pic_readl (void *opaque, a_target_phys_addr addr)
}
static void
pic_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_pic *fs = opaque;
D(printf("%s addr=%x val=%x\n", __func__, addr, value));
......
hw/etraxfs_ser.c
浏览文件 @ c227f099
......@@ -65,7 +65,7 @@ static void ser_update_irq(struct etrax_serial *s)
s->regs[RW_ACK_INTR] = 0;
}
static uint32_t ser_readl (void *opaque, a_target_phys_addr addr)
static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
{
struct etrax_serial *s = opaque;
D(CPUState *env = s->env);
......@@ -91,7 +91,7 @@ static uint32_t ser_readl (void *opaque, a_target_phys_addr addr)
}
static void
ser_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_serial *s = opaque;
unsigned char ch = value;
......
hw/etraxfs_timer.c
浏览文件 @ c227f099
......@@ -72,7 +72,7 @@ struct etrax_timer {
uint32_t r_masked_intr;
};
static uint32_t timer_readl (void *opaque, a_target_phys_addr addr)
static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
{
struct etrax_timer *t = opaque;
uint32_t r = 0;
......@@ -243,7 +243,7 @@ static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
}
static void
timer_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct etrax_timer *t = opaque;
......
hw/fdc.c
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hw/fdc.h
浏览文件 @ c227f099
/* fdc.c */
#define MAX_FD 2
typedef struct fdctrl a_fdctrl;
typedef struct fdctrl_t fdctrl_t;
a_fdctrl *fdctrl_init_isa(BlockDriverState **fds);
a_fdctrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a_target_phys_addr mmio_base,
fdctrl_t *fdctrl_init_isa(BlockDriverState **fds);
fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
target_phys_addr_t mmio_base,
BlockDriverState **fds);
a_fdctrl *sun4m_fdctrl_init (qemu_irq irq, a_target_phys_addr io_base,
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
BlockDriverState **fds, qemu_irq *fdc_tc);
int fdctrl_get_drive_type(a_fdctrl *fdctrl, int drive_num);
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
hw/flash.h
浏览文件 @ c227f099
/* NOR flash devices */
typedef struct pflash a_pflash;
typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */
a_pflash *pflash_cfi01_register(a_target_phys_addr base, a_ram_addr off,
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3);
/* pflash_cfi02.c */
a_pflash *pflash_cfi02_register(a_target_phys_addr base, a_ram_addr off,
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
......@@ -36,7 +36,7 @@ uint8_t nand_getio(NANDFlashState *s);
#define NAND_MFR_MICRON 0x2c
/* onenand.c */
void onenand_base_update(void *opaque, a_target_phys_addr new);
void onenand_base_update(void *opaque, target_phys_addr_t new);
void onenand_base_unmap(void *opaque);
void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
void *onenand_raw_otp(void *opaque);
......
hw/framebuffer.c
浏览文件 @ c227f099
......@@ -22,7 +22,7 @@
void framebuffer_update_display(
DisplayState *ds,
a_target_phys_addr base,
target_phys_addr_t base,
int cols, /* Width in pixels. */
int rows, /* Leight in pixels. */
int src_width, /* Length of source line, in bytes. */
......@@ -34,16 +34,16 @@ void framebuffer_update_display(
int *first_row, /* Input and output. */
int *last_row /* Output only */)
{
a_target_phys_addr src_len;
target_phys_addr_t src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;
int first, last = 0;
int dirty;
int i;
a_ram_addr addr;
a_ram_addr pd;
a_ram_addr pd2;
ram_addr_t addr;
ram_addr_t pd;
ram_addr_t pd2;
i = *first_row;
*first_row = -1;
......@@ -86,7 +86,7 @@ void framebuffer_update_display(
dest += i * dest_row_pitch;
for (; i < rows; i++) {
a_target_phys_addr dirty_offset;
target_phys_addr_t dirty_offset;
dirty = 0;
dirty_offset = 0;
while (addr + dirty_offset < TARGET_PAGE_ALIGN(addr + src_width)) {
......
hw/framebuffer.h
浏览文件 @ c227f099
......@@ -7,7 +7,7 @@ typedef void (*drawfn)(void *, uint8_t *, const uint8_t *, int, int);
void framebuffer_update_display(
DisplayState *ds,
a_target_phys_addr base,
target_phys_addr_t base,
int cols,
int rows,
int src_width,
......
hw/fw_cfg.c
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hw/fw_cfg.h
浏览文件 @ c227f099
......@@ -35,7 +35,7 @@ int fw_cfg_add_i64(void *opaque, uint16_t key, uint64_t value);
int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback,
void *callback_opaque, uint8_t *data, size_t len);
void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
a_target_phys_addr crl_addr, a_target_phys_addr data_addr);
target_phys_addr_t crl_addr, target_phys_addr_t data_addr);
#endif /* NO_QEMU_PROTOS */
......
hw/g364fb.c
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hw/grackle_pci.c
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hw/gt64xxx.c
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hw/gumstix.c
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hw/heathrow_pic.c
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hw/hpet.c
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hw/ide.h
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hw/isa.h
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hw/mips.h
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hw/nvram.h
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hw/omap.h
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hw/omap1.c
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hw/openpic.c
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hw/pci_host.h
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hw/pckbd.c
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hw/pcnet.c
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hw/petalogix_s3adsp1800_mmu.c
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hw/pflash_cfi01.c
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hw/pflash_cfi02.c
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hw/piix_pci.c
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hw/ppc405_boards.c
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hw/ppc440_bamboo.c
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hw/ppc4xx_devs.c
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hw/ppc4xx_pci.c
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hw/ppc_mac.h
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hw/ppc_newworld.c
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hw/ppce500_mpc8544ds.c
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hw/ppce500_pci.c
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hw/prep_pci.c
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hw/pxa2xx_gpio.c
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hw/pxa2xx_keypad.c
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hw/pxa2xx_lcd.c
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hw/pxa2xx_mmci.c
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hw/pxa2xx_pcmcia.c
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hw/pxa2xx_pic.c
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hw/pxa2xx_timer.c
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hw/realview_gic.c
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hw/rtl8139.c
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hw/sd.c
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hw/serial.c
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hw/sh7750_regnames.c
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hw/slavio_intctl.c
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hw/slavio_misc.c
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hw/sm501.c
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hw/smc91c111.c
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hw/soc_dma.c
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hw/sparc32_dma.c
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hw/spitz.c
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hw/stellaris.c
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hw/stellaris_enet.c
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hw/sun4c_intctl.c
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hw/syborg_fb.c
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hw/syborg_interrupt.c
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hw/syborg_keyboard.c
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hw/syborg_pointer.c
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hw/syborg_rtc.c
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hw/syborg_serial.c
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hw/syborg_virtio.c
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hw/tcx.c
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hw/vmware_vga.c
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hw/wdt_i6300esb.c
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hw/xen_machine_pv.c
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hw/xilinx_ethlite.c
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hw/zaurus.c
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ioport-user.c
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ioport.c
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ioport.h
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keymaps.c
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keymaps.h
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kvm-all.c
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kvm.h
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linux-user/alpha/target_signal.h
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linux-user/m68k/target_signal.h
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linux-user/main.c
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linux-user/mips64/target_signal.h
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linux-user/mipsn32/target_signal.h
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linux-user/sh4/target_signal.h
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linux-user/signal.c
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linux-user/sparc/target_signal.h
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linux-user/sparc64/target_signal.h
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linux-user/syscall_defs.h
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m68k-semi.c
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monitor.c
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qemu-img.c
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qemu-lock.h
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sdl.c
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sdl_keysym.h
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softmmu_template.h
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tap-win32.c
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target-alpha/cpu.h
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target-alpha/helper.c
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target-alpha/op_helper.c
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target-arm/helper.c
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target-arm/op_helper.c
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target-cris/helper.c
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target-i386/helper.c
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target-i386/op_helper.c
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target-m68k/helper.c
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target-microblaze/cpu.h
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target-microblaze/helper.c
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target-microblaze/op_helper.c
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target-mips/cpu.h
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target-mips/helper.c
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target-mips/op_helper.c
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target-mips/translate.c
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target-mips/translate_init.c
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target-ppc/cpu.h
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target-ppc/helper.h
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target-ppc/op_helper.c
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target-ppc/translate.c
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target-ppc/translate_init.c
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target-sh4/cpu.h
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targphys.h
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uboot_image.h
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vl.c
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vnc.h
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vnc_keysym.h
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