- 01 7月, 2020 40 次提交
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由 Aric Cyr 提交于
Signed-off-by: NAric Cyr <aric.cyr@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Stylon Wang 提交于
[Why] Regression was introduced where setting max bpc property has no effect on the atomic check and final commit. It has the same effect as max bpc being stuck at 8. [How] Correctly propagate max bpc with the new connector state. Signed-off-by: NStylon Wang <stylon.wang@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Anthony Koo 提交于
[Header Changes] - Add debug flag for psr to use hw locking mgr state machine Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wenjing Liu 提交于
[why] DP link layer CTS specs updated to change the test parameters in test 4.2.1.1. Before it requires source to delay 400us on aux no reply. With the specs updates Errata5, it requires source to delay 3.2ms (based on LTTPR aux timeout) This causes our test to fail after updating with the latest test equipment firmware. [how] the change is to allow LTTPR 3.2ms aux timeout delay by default. And set back to 400us if LTTPR feature is not enabled. We will set 3.2ms and always enable LTTPR non transparent mode if LTTPR feature is enabled and LTTPR is present. Signed-off-by: NWenjing Liu <wenjing.liu@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NKrunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wenjing Liu 提交于
[why] Two issues: 1. Add read only operation support for query ddc data over aux. 2. Fix a bug where if read size is multiple of 16, mot of the last read transaction will not be set to 0. Signed-off-by: NWenjing Liu <wenjing.liu@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 David Galiffi 提交于
[Why] If the front porch of the two timings differ, then there may not be enough time while both streams are in vertical blank to perform a memory clock change. This can hang the system. [How] Check the each streams timing.v_front_porch when determining if the two streams are synchronizable. Signed-off-by: NDavid Galiffi <David.Galiffi@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Martin Leung 提交于
why: seamless boots requires split of init_hw into hw and pipes to work. This was implemented in dcn10_init_hw but did not apply yet to dcn30. how: Copy over dcn10_init_hw and adapt it to dcn30 using recent changes to dcn3. Behavior will be different in init sequence. Signed-off-by: NMartin Leung <martin.leung@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Peikang Zhang 提交于
[Why] We try to to change new_clocks->dppclk_khz to 100000 when new_clocks->dppclk_khz is 0 [How] Don't change new_clocks->dppclk_khz value when new_clocks->dppclk_khz is 0 Signed-off-by: NPeikang Zhang <peikang.zhang@amd.com> Reviewed-by: NYongqiang Sun <yongqiang.sun@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Chris Park 提交于
[Why] 10K YCbCr420 does not need ODM 4:1, but it requires MPC 4 split indicated on the flags. [How] Make pixel encoding and resolution size specific workaround to enable ODM combine on YCbCr420 high resolution modes. Signed-off-by: NChris Park <Chris.Park@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Derek Lai 提交于
[why] If a typeC to HDMI dongle supports YCbCr420 pass through and VSC colorimetry and pixel encoding formats in the Extended Receiver Capability, we shall allow VSC SDP to be used. [How] The Extended Receiver Capability field shall check the EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT bit in the TRAINING_AUX_RD_INTERVAL register. Removed DPCD rev checking for VSC SDP. Signed-off-by: NDerek Lai <Derek.Lai@amd.com> Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: NTony Cheng <Tony.Cheng@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nicholas Kazlauskas 提交于
[Why] DMCUB firmware version is now available from firmware metadata block. We should be passing this into dmub_srv so we can know when to apply firmware version specific functionality like using CW4 only instead of the REGION4. [How] We don't have the helpers for DM to actually extract out firmware metadata block themselves. We could add that and add helpers in DM to grab this, but not every creation sequence has firmware instruction before dmub_srv_create. Easiest way to handle this is to fill this in automatically per DM in the place we do have it - when calculating the region parameters. But only fill it in if DM already hasn't in case we need to override with a specific version. We aren't do anything firmware version specific in dmub_srv_create today that does require fw_version, so while it's a little unituitive to do it when calculating region parameters it works for now. Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Stylon Wang 提交于
[Why] Connector property output_bpc is available on DP/eDP only. New IGT tests would benifit if this property works on HDMI. [How] Enable this read-only property on all types of connectors. Signed-off-by: NStylon Wang <stylon.wang@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Chris Park 提交于
[Why] All YCbCr420 resolutions 5K and above have tiling and discoloration issues. The issue can be remedied by forcing ODM combine from 5K to 8K. 10K resolution requires ODM 4:1. The mechanism of what the real problem is, that is inherent in ODM combine programming, doesn't seem to be pointed at singular register programming (CLK, MPC, DCSURF, etc.), and needs more in-depth programming sequence review for these new use case scenarios. Until then, workaround to enable ODM combine is proposed. While it is not our policy, HW spreadsheet also recommends turning on ODM for these scenario to lower the voltage. [How] Make pixel encoding and resolution size specific workaround to enable ODM combine on YCbCr420 high resolution modes. Signed-off-by: NChris Park <Chris.Park@amd.com> Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dmytro Laktyushkin 提交于
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: NChris Park <Chris.Park@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Brandon Syu 提交于
[Why] There is using pixelclk AVFS for dppclk, that would cause issue. [How] To use dispclk AVFS for both dispclk and dppclk. There would choose dppclk for request voltage when dispclk wouldn't be updated case. If dispclk need to be updated, then it'll choose the bigger one from dppclk and dispclk for request voltage. Signed-off-by: NBrandon Syu <Brandon.Syu@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Yang 提交于
[Why] If optimized init is done in FW. DCN init be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Reviewed-by: NTony Cheng <Tony.Cheng@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Dale Zhao 提交于
[WHY] Check max_tmds_clk_mhz firstly will restrict pixel clock under HDMI 1.4, thus HDMI2.0 port can't correctly support 4K 60Hz. [HOW] Fine tune the logic to check max_forum_tmds_clk_mhz firstly. Signed-off-by: NDale Zhao <dale.zhao@amd.com> Reviewed-by: NChris Park <Chris.Park@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jake Wang 提交于
[Why & How] Need to check if local_sink is NULL before accessing. Signed-off-by: NJake Wang <haonan.wang2@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aurabindo Pillai 提交于
[Why] DC global validation can fail when userspace requests to draw large plane without performing the clipping themselves. This is observed in the IGT kms_plane panning tests for 4K displays where they draw an 8K plane without any clipping while expecting only the top 4K to be drawn. [How] DRM already has helpers to take care of the clipping necessary and to mark whether a plane is visible or not, so make use of these helpers in DM before passing the plane to DC. Signed-off-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
Signed-off-by: NAric Cyr <aric.cyr@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Anthony Koo 提交于
[Header Changes] - Update scratch information for boot status Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Camille Cho 提交于
[Why] dc_link_set_psr_allow_active() always returns true, even in the case that PSR is not supported. [How] Hook up the return value of dc_link_set_psr_allow_active(). Signed-off-by: NCamille Cho <Camille.Cho@amd.com> Reviewed-by: NJosip Pavic <Josip.Pavic@amd.com> Acked-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Nicholas Kazlauskas 提交于
[Why] Side-by-side and Top-and-bottom stereo configurations fail DML mode validation due to Viewport exceeded. This is because we consider the planes as being pipe split in pipe population so we end up doubling the viewport width, eg. from 4k to 8k. [How] These pipes technically aren't hsplit, so add a check for determining whether is_hsplit should be set. Signed-off-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Bhawanpreet Lakha 提交于
[Why] assr is content protection for eDP, in order to use it we need to call psp ta (dtm) [How] We have a enable_assr callback, hook into this and call the correct psp cmd id to enable assr. Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: NHersen Wu <hersenxs.wu@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Michael Strauss 提交于
[WHY] Currently DC doesn't check requested pixel clock against an EDID specified TMDS max clock if it exists, passing modes that should fail [HOW] Add max TMDS clk to edid caps and perform check during validation Signed-off-by: NMichael Strauss <michael.strauss@amd.com> Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Anthony Koo 提交于
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yi-Ling Chen 提交于
[why] dc->hwss->edp_backlight_control is null, it would casue it only be off main-link of eDP. It is not worng behavior for eDP power sequence off. [how] Must use hwseq->funcs.edp_backlight_control finction pointer for edp backlight. Signed-off-by: NYi-Ling Chen <Yi-Ling.Chen2@amd.com> Reviewed-by: NSung Lee <Sung.Lee@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Mikita Lipski 提交于
[why] The calculation of virtual channel payload would not take link settings in account. As we calculate VCPI slots needed both PBN for stream and also PBN per time slot. Before we would use generic PBN per time slot, which would not change with link settings causing wrong Payload allocation. [how] Provide PBN per time slot for each Virtual channel payload calculation. Signed-off-by: NMikita Lipski <mikita.lipski@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Anthony Koo 提交于
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wyatt Wood 提交于
[Why] Hw lock manager adds the ability to lock pipe, cursor, and dig in fw. [How] Send hw lock command to fw to lock pipe, cursor, and dig. Signed-off-by: NWyatt Wood <wyatt.wood@amd.com> Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sonny Jiang 提交于
Enable asic Verde, Tahiti and Pitcairn UVD block. Signed-off-by: NSonny Jiang <sonny.jiang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sonny Jiang 提交于
Enable Oland UVD block. Signed-off-by: NSonny Jiang <sonny.jiang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sonny Jiang 提交于
Signed-off-by: NSonny Jiang <sonny.jiang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sonny Jiang 提交于
Implement SI uvd_ctx_rreg/wreg functions. Signed-off-by: NSonny Jiang <sonny.jiang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sonny Jiang 提交于
Implement SI UVD. The SI UVD firmware requires validation. v2: squash in missing brace fix (Colin Ian King) Signed-off-by: NSonny Jiang <sonny.jiang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sonny Jiang 提交于
Add SI UVD registers files. Signed-off-by: NSonny Jiang <sonny.jiang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sonny Jiang 提交于
Fix packet_type0 definition in sid. Signed-off-by: NSonny Jiang <sonny.jiang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sonny Jiang 提交于
For implement UVD on SI asic, add Oland, Pitcairn, Verde, Tahiti firmwares. Signed-off-by: NSonny Jiang <sonny.jiang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
drop the duplicate register macros from sid.h and use the standard ones in the oss register headers. Acked-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Qingqing Zhuo 提交于
when compiled with allmodconfig option, there are error messages as below: ERROR: modpost: "mod_color_is_table_init" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "mod_color_get_table" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "mod_color_set_table_init_state" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! To fix the issue, this commits removes CONFIG_DRM_AMD_DC_DCN guard in color/makefile. Signed-off-by: NQingqing Zhuo <qingqing.zhuo@amd.com> CC: Lewis Huang <Lewis.Huang@amd.com> CC: Aric Cyr <Aric.Cyr@amd.com> CC: Alexander Deucher <Alexander.Deucher@amd.com> CC: Harry Wentland <hwentlan@amd.com> CC: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> CC: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> CC: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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