drm/amd/display: fine tune logic of edid max TMDS clock check

[WHY]
Check max_tmds_clk_mhz firstly will restrict pixel clock under HDMI
1.4, thus HDMI2.0 port can't correctly support 4K 60Hz.

[HOW]
Fine tune the logic to check max_forum_tmds_clk_mhz firstly.
Signed-off-by: NDale Zhao <dale.zhao@amd.com>
Reviewed-by: NChris Park <Chris.Park@amd.com>
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dc_types.h

@@ -255,15 +255,14 @@ struct dc_edid_caps {
 	uint8_t qs_bit;
 	uint8_t qy_bit;
 
+	uint32_t max_tmds_clk_mhz;
+
 	/*HDMI 2.0 caps*/
 	bool lte_340mcsc_scramble;
 
 	bool edid_hdmi;
 	bool hdr_supported;
 
-	uint32_t max_tmds_clk_mhz;
-	uint32_t max_forum_tmds_clk_mhz;
-
 	struct dc_panel_patch panel_patch;
 };
 

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

@@ -629,9 +629,6 @@ static bool dcn10_link_encoder_validate_hdmi_output(
 	if (edid_caps->max_tmds_clk_mhz != 0 &&
 			adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000)
 		return false;
-	if (edid_caps->max_forum_tmds_clk_mhz != 0 &&
-			adjusted_pix_clk_100hz > edid_caps->max_forum_tmds_clk_mhz * 10000)
-		return false;
 
 	if (max_deep_color < crtc_timing->display_color_depth)
 		return false;