We introduced a new compatible for the NMI or R_INTC interrupt
controller. This new compatible has the register region aligned
to the boundary listed in the SoC's memory map.

This patch converts the NMI/R_INTC node to using the new compatible,
and fixes up the register region and device node name.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add SoC specific compatibles for all sunXi crypto nodes, in addition to
the one already used (allwinner,sun4i-a10-crypto).
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

tcon0 contains a muxing register used to mux tcon output to downstream
hdmi or mipi dsi encoders. tcon0 must be available for the mux to be
configured.

Whether the display subsystem is enabled or not is now solely controlled
by the display-engine node.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The Allwinner A31/A31s SoCs have 2 display pipelines, as in 2 display
frontends, backends, and tcons each. The relationship between the
backends and tcons are 1:1, but the frontends can feed either backend.

Add device nodes and of graph nodes describing this relationship.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

All dts files for the sunxi platform have been switched to the generic
pinconf bindings. As a result, the sunxi specific pinctrl macros are
no longer used.

Remove the #include entry with the following command:

    sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \
	arch/arm/boot/dts/sun?i*.*

arch/arm/boot/dts/sun9i-a80.dtsi was then edited to remove the extra
empty line.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.

Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).

In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.
Acked-by: NShawn Guo <shawnguo@kernel.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NSantosh Shilimkar <ssantosh@kernel.org>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add the SPDIF transceiver controller block to the A31 dtsi.
Signed-off-by: NMarcus Cooper <codekipper@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add the SPDIF TX pin to the A31 dtsi.
Signed-off-by: NMarcus Cooper <codekipper@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

In the past, all the MMC pins had

	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;

which was actually a no-op. We were relying on U-boot to set the bias
pull up for us. These properties were removed as part of the fix up to
actually support no bias on the pins. During the transition some boards
experienced regular MMC time-outs during normal operation, while others
completely failed to initialize the SD card.

Given that MMC starts in open-drain mode and the pull-ups are required,
it's best to enable it for all the pin settings.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

While we now support the internal display pipeline found on sun6i, it
is possible that we are unable to enable the display for some boards,
due to a lack of drivers for the panels or bridges found on them. If
the display pipeline is enabled, the driver will try to enable, and
possibly screw up the simple framebuffer U-boot had configured.

Disable the display pipeline by default.

Fixes: 6d0e5b70 ("ARM: dts: sun6i: Add device nodes for first
		      display pipeline")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now that we can handle the generic pinctrl bindings, convert our DT to it.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>

The allwinner,pull property set to NO_PULL was really considered our
default (and wasn't even changing the default value in the code).

Remove these properties to make it obvious that we do not set anything in
such a case.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>

The allwinner,drive property set to 10mA was really considered as our
default. Remove all those properties entirely to make that obvious.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>

The pin controllers also use the two oscillators for debouncing. Add them
to the DTs.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NChen-Yu Tsai <wens@csie.org>

The A31 SoC includes the Allwinner audio codec, capable of 24-bit
playback up to 192 kHz and 24-bit capture up to 48 kHz.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The LCD0 controller on the A31 can do RGB output up to 8 bits per
channel. Add the pins for RGB888 output.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The A31 has 2 parallel display pipelines, which can be intermixed.
However the driver currently only supports one of them.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The pinmux setting nodes for the A31 were added out of alphabetical
order. Sort them.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i
and newer.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Now that we have a different clock representation, switch to it.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

mmc2 and mmc3 are available on the same pins, with different mux values.
However, only mmc3 supports 8 bit DDR transfer modes.

Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
set the drive strength to 40mA, which is needed for DDR.

This pinmux setting also includes the hardware reset pin for emmc.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some boards, such as tablets, have regulators providing power to parts
of the display pipeline, like signal converters and LCD panels.

Add labels to the simplefb device nodes so that we can reference them
in the board dts files to add regulator supply properties.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add a pinmux setting for using mmc2 in regular 4 bit mode.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

When the gpio interrupt bindings where changed to add a bank to the
specifier list, the r_pio nodes of A23/A31/A33 where not updated to
match and neither was the pio node of the A80, this fixes this.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This also includes the reset pin for emmc.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

sun6i also has the LRADC for tablet buttons.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

A31/A31s have the same "Security System" crypto engine as A10/A20,
but with a separate reset control.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The A31 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The current DTs were setting the cell size to 2, but used the default xlate
function that was assuming an interrupt cell size of 1, leading to the
second part of the cell (the flags) being ignored, while we were having an
inconsistent binding between the interrupts and gpio (that could also be
used as interrupts).

That "binding" doesn't work either with newer SoCs that have multiple irq
banks.

Now that we fixed the pinctrl driver to handle this like it should always
have been handled, convert the DT users, and while we're at it, remove the
size-cells property of PIO that is completely useless.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Add a node for the otg/drc usb controller to sun6i-a31.dtsi.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

A few lines (probably copy pasted) have an indentation mixing tabs and
spaces that triggers a checkpatch warning.

Fix those, and while we're at it, fix the space-indented sections.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

A few lines in our DTSIs are over the 80 characters limit, making
checkpatch complain about that.

If possible (and relevant), wrap these lines to 80 characters.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The FSF address triggers a warning on checkpatch, saying that the FSF
license is already present in the Linux source code, and that it has
already changed in the past.

Remove it from our DT, as suggested.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

On sun6i we already have PLL6 as AHB1 clock's parent. However this was
previously set in the dma controller node, which takes effect when the
dma controller is probed.

We want this to take effect as soon as possible, so hrtimer rate
calculation is correct, and to be sure the AHB1 clock rate remains as
stable as possible.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The core temperature sensor now supports thermal zones. Add a thermal
zone mapping for the cpus with passive cooling (cpufreq throttling).
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The cpu core is clocked from the "cpu" clock. Add a reference to it
in the first cpu node. Also add "cpu0" label to the node.

The operating points were taken from the a list compiled by Maxime Ripard,
which is based on A31 FEX files from the sunxi-boards repository. Not all
boards have the same settings. The settings in this patch are the ones
shared by A/B/C revisions, plus the default clock setting from u-boot.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

mmc1 is used to connect to the WiFi chip on the Hummingbird A31.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
[maxime: Changed the drive and pull values for their defines]
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Sometimes we need to specify non-probably information for sdio devices in the
devicetree, this is done through child nodes addressed by the reg property,
whereby the reg property refers to the sdio function number, see;
Documentation/devicetree/bindings/mmc/mmc.txt

This commit adds the necessary address- and size-cells properties to the mmc
controller nodes in the dtsi files, so that dts files needing such a child
node do not need to specify these themselves.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The p2wi controller has only one possible pinmux setting. Use it by
default in the dtsi, instead of having to set it in each board's dts.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
[wens@csie.org: reformat commit title; rename p2wi pins and use as default]
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Commit f77d55a3 ("serial: 8250_dw: get index of serial line from DT
aliases") made the serial driver now use the serial aliases to get the tty
number, pointing out that our aliases have been wrong all along.

Remove them from the DTSI and add custom ones in the relevant boards.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>