提交 f89f2a37 编写于 作者: C Chen-Yu Tsai 提交者: Maxime Ripard

ARM: dts: sun6i: Enable tcon0 by default

tcon0 contains a muxing register used to mux tcon output to downstream
hdmi or mipi dsi encoders. tcon0 must be available for the mux to be
configured.

Whether the display subsystem is enabled or not is now solely controlled
by the display-engine node.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
上级 9a26882a
......@@ -319,7 +319,6 @@
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd0_rgb888_pins>;
status = "okay";
};
&tcon0_out {
......
......@@ -264,7 +264,6 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon0-pixel-clock";
status = "disabled";
ports {
#address-cells = <1>;
......
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