This patch adds the mux/divider clocks for CMU_CDREX (DRAM Express
Controller) which generates the clocks for DRAM and NoC (Network on Chip)
bus.  There is differnet source of MUX_MX_MSPLL_CCORE between exynos5420
and exynos5422, so each MUX_MX_MSPLL_CCORE uses the different parent source
group.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

The aclk333 clock needs to be ungated during the MFC power domain switch,
so set the clock ID to allow the Exynos power domain logic to lookup this
clock if is defined in the MFC PD device tree node.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

The exynos5420_clk_sleep_init() function and arrays with initialization
data of PLLs can be moved to init section because they are referenced
only from other init-level symbols.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

All of initialization data can be made const.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

The samsung_clk_init() cannot return NULL. Either it returns allocated
memory or it panics.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds the clock id for ACLK clock which is source clock
of AMBA AXI bus. This clock should be handled in the bus frequency
scaling driver.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Tested-by: NMarkus Reichl <m.reichl@fivetechno.de>
Tested-by: NAnand Moon <linux.amoon@gmail.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This flag is a no-op now. Remove usage of the flag.
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Proper source for MFC block is mout_user_aclk333 (in datasheet named
USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).

Based on Hardkernel's kernel for ODROID-XU3 board.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.

Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds clocks, which are required for preserving parent clock
configuration on GSCL power domain on/off.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are
using it. The clkdev.h header isn't always used either, so remove
it and add in slab.h where files were relying on it to include
slab for them.

Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add missing static to local (file-scope only) symbols.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Commit ae43b328 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power
Management support v12") added pm support for the pl330 dma driver but
it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
during suspend and this in turn makes its parent clock aclk266_g2d to
be gated. But the clock needs to be ungated prior suspend to allow the
system to be suspend and resumed correctly.

Add GATE_BUS_TOP register to the list of registers to be restored when
the system enters into a suspend state so aclk266_g2d will be ungated.

Thanks to Abhilash Kesavan for figuring out that this was the issue.

Fixes: ae43b328 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12")
Cc: stable@vger.kernel.org # 3.19+
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: NKevin Hilman <khilman@linaro.org>
Tested-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.

So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:

ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)

Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.

Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NAmit Daniel Kachhap <amit.daniel@samsung.com>
Tested-by: NArjun K.V <arjun.kv@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Prior to suspending the system, we need to ensure that certain
clock source and gate registers are unmasked.

while at it, add these clks to save/restore list also.
Signed-off-by: NVikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Array of struct of_device_id may be be const as expected by
of_match_table field and of_find_matching_node_and_match() function.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Ensure the clock provider is not registered until after all its related
clocks were created and are ready to use. Currently there are races
possible and any (of_)clk_get() call right after a clock provider's
clk_init_cb callback call may fail.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

The "aclk66_peric" clock is a gate clock with a whole bunch of gates
underneath it.  This big gate isn't very useful to include in our
clock tree.  If any of the children need to be turned on then the big
gate will need to be on anyway.  ...and there are plenty of other "big
gates" that aren't described in our clock tree, some of which shut off
collections of clocks that have no relationship in the hierarchy so
are hard to model.

"aclk66_peric" is causing earlyprintk problems since it gets disabled
as part of the boot process, so let's just remove it.

Strangely (and for no good reason) this clock is exported as part of
the common clock bindings.  Remove it since there are no in-kernel
device trees using it and no reason anyone out of tree should refer to
it either.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Exynos5800 clock structure is mostly similar to 5420 with only
a small delta changes. So the 5420 clock file is re-used for
5800 also. The common clocks for both are seggreagated and few
clocks which are different for both are separately initialized.
Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds more register offsets to the list for
preserving their values during S2R.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds some missing miscellaneous clocks specific
to exynos5420.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds the missing MAU block specific clocks.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch fixes the wrong register offset for sclk_bpll clock.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Reviewed-by: NAlim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch corrects the wrong parent-child relationship
between sysmmu-mfc clocks.
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds more clocks from FSYS and FSYS2 blocks
and uses GATE_IP_* registers for gating IPs.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds missing clocks for WCORE block.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch fixes some parent-child relationships according
to the latest datasheet and adds more clocks related to
PERIS and GEN blocks.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch includes,
    1] renaming of the HSI2C clocks
    2] renaming of spi clocks according to the datasheet
    3] fixes for child-parent relationships
    4] adding of more clocks related to PERIC block
    5] use GATE_IP_* offsets instead of GATE_BUS_*
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch corrects some child-parent clock relationships,
and updates the clocks according to the latest datasheet.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds missing clocks of G2D block. It also removes
the aclkg3d alias from G3D block clocks.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch fixes the parent clocks for mscl sysmmu.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds the missing GSCL and MSCL block clocks
and corrects some wrong parent-child relationships.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds minimum set of clocks to gate ISP block for
power saving.
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch renames the mux parent arrays as per the naming
convension followed by the other exynos specific clock drivers.
And it also renames "mout_cpu_kfc" clock to "mout_kfc".
Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Adds IDs for the clocks needed by the ARM Mali GPU
in exynos5420.
Signed-off-by: NArun Kumar K <arun.kk@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

Set it as per the user manual.
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>

This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.
Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com>
[t.figa: Fixed sort order and group name.]
Signed-off-by: NTomasz Figa <t.figa@samsung.com>