Right now we are passing a pointer to a pointer to the structure that
will be used to fetch the clk hw, which gets casted later to a pointer
to the structure, thus getting garbage in the hw structs.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Fixes: a8b6e85d ("clk: rk808: Migrate to clk_hw based OF and
registration APIs")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds code instantiating the EPLL, which is used as the
audio subsystem's root clock.
The requirement to specify the external root clock in clocks property
is documented.  Having the consumer 'clocks' property ensures proper
initialization order by explicitly specifying dependencies in DT.
It prevents situations when the SoC's clock controller driver has
initialized, the external oscillator clock is not yet registered
and setting clock frequencies through assigned-clock-rates property
doesn't work properly due to unknown external oscillator frequency.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>

There is no need to log probe() completion in normal conditions
so the "setup completed" log is removed.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Exynos5410 Audio Subsystem Clock Controller, comparing to the already
supported IP block revisions, has additionally an I2S_MST divider
so a new compatible string is added.
It is not clear from the Exynos5410 User's Manual released on 2012.03.09
where in the clock tree the I2S_MST clock divider can be found exactly
so this clock is left unimplemented for now.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

Then variant handling is reworked to make the code simpler when
more variants are added.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

There is no such significant differences in pll2550x PLL type
to justify a separate registration function.  This patch adapts
exynos5440 driver to use the common function and removes
samsung_clk_register_pll2550x().
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NChanwoo Choi <cw00.choi@samsung.com>

These clocks are needed in order to use the PL330 peripheral
DMA controllers.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch adds the mux/divider clocks for CMU_CDREX (DRAM Express
Controller) which generates the clocks for DRAM and NoC (Network on Chip)
bus.  There is differnet source of MUX_MX_MSPLL_CCORE between exynos5420
and exynos5422, so each MUX_MX_MSPLL_CCORE uses the different parent source
group.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch uses the samsung_cmu_register_one() to simplify code
and move the pll/mux/div/gate data to initconst section.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

This patch moves the samsung_cmu_info struct instances to initconst
section, this decreases the kernel image size by 784 bytes, which makes
zImage smaller by 480 bytes.

The patch increases .init.rodata section size by 780 bytes but decreases
.init.text section size by 1564 bytes.

Size of the drivers/clk/samsung/clk-exynos5260.o object file is 29100
bytes without the patch and 28316 after applying the patch.

The section size differences are as below:
15c15
<   3 .init.text    000006b8  00000000  00000000  00000034  2**2
---
>   3 .init.text    0000009c  00000000  00000000  00000034  2**2
25c25
<   8 .init.rodata  00003f6c  00000000  00000000  00002f20  2**2
---
>   8 .init.rodata  00004278  00000000  00000000  00002904  2**2
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>

If the firmware had set up a clock to source from PLLC, go along with
it.  But if we're looking for a new parent, we don't want to switch it
to PLLC because the firmware will force PLLC (and thus the AXI bus
clock) to different frequencies during over-temp/under-voltage,
without notification to Linux.

On my system, this moves the Linux-enabled HDMI state machine and DSI1
escape clock over to plld_per from pllc_per.  EMMC still ends up on
pllc_per, because the firmware had set it up to use that.
Signed-off-by: NEric Anholt <eric@anholt.net>
Fixes: 41691b88 ("clk: bcm2835: Add support for programming the audio domain clocks")
Acked-by: NMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

While the SDRAM is being driven by its dedicated PLL most of the time,
there is a little loop running in the firmware that periodically turns
on the CM SDRAM clock (using its pre-initialized parent) and switches
SDRAM to using the CM clock to do PVT recalibration.

This avoids system hangs if we choose SDRAM's parent for some other
clock, then disable that clock.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

These divide off of PLLD_PER and are used for the ethernet and wifi
PHYs source PLLs.  Neither of them is currently represented by a phy
device that would grab the clock for us.

This keeps other drivers from killing the networking PHYs when they
disable their own clocks and trigger PLLD_PER's refcount going to 0.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The VPU clock is also the clock for our AXI bus, so we really can't
disable it.  This might have happened during boot if, for example,
uart1 (aux_uart clock) probed and was then disabled before the other
consumers of the VPU clock had probed.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NMartin Sperl <kernel@martin.sperl.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Export the dclk_vop_frac out, so we can set the dclk_vop as the
child of dclk_vop_frac, and then we can start to take use of
the fractional dividers.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Currently the fractional divider clock time can't handle the
CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers,
there is no clk_divider_bestdiv() function to try speeding up the parent
to see if it helps things.

Eventually someone could try to figure out how to make fractional
dividers able to use CLK_SET_RATE_PARENT, but until they do let's not
confuse the common clock framework (and anyone using it) by setting the
flag.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

We would prefer the 2016M as 2.0G than 1992M which seems odd, adding
it to big cpu clk rate table then we can set 2016M in dts.
Signed-off-by: NShunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: NXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add the PWM related clocks in order to be referenced as PWM source
clocks.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com

This patch adds support for the meson8b clock gates. Most of
them are disabled by Amlogic U-Boot, but need to be enabled
for ethernet, USB and many other components.
Signed-off-by: NAlexander Müller <serveralex@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-7-git-send-email-serveralex@gmail.com

The macro used gxbb_ prefix for clock definitions. In order
to share the macro between gxbb and meson8b, the prefix must
be moved to gxbb.c.
Signed-off-by: NAlexander Müller <serveralex@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-6-git-send-email-serveralex@gmail.com

Only expose future CLKID constants if necessary. This patch
removes CLK_NR_CLKS from the DT bindings but leaves all previously
defined CLKIDs there to keep backward compatibility.
Signed-off-by: NAlexander Müller <serveralex@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-5-git-send-email-serveralex@gmail.com

Signed-off-by: NAlexander Müller <serveralex@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-4-git-send-email-serveralex@gmail.com

Move the register definitions into a separate header file
to reflect the gxbb implementation.
Signed-off-by: NAlexander Müller <serveralex@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-3-git-send-email-serveralex@gmail.com

Signed-off-by: NAlexander Müller <serveralex@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1472319654-59048-2-git-send-email-serveralex@gmail.com

Changing the rate of the DDR clock needs special care, as the DDR
is of course in use and will react badly if the rate changes under it.

Over time different approaches to handle that were used.

Past SoCs like the rk3288 and before would store some code in SRAM
while the rk3368 used a SCPI variant and let a coprocessor handle that.

New rockchip platforms like the rk3399 have a dcf controller to do ddr
frequency scaling, and support for this controller will be implemented
in the arm-trusted-firmware.

This new clock-type should over time handle all these methods for
handling DDR rate changes, but right now it will concentrate on the
SIP interface used to talk to ARM trusted firmware.

The SIP interface counterpart was merged from pull-request #684 [0]
into the upstream arm-trusted-firmware codebase.

[0] https://github.com/ARM-software/arm-trusted-firmware/pull/684Signed-off-by: NLin Huang <hl@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Currently we see the following error when using the SAI audio
driver on mx7:

Division by zero in kernel.
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0-rc3-next-20160823
Hardware name: Freescale i.MX7 Dual (Device Tree)
Backtrace:
[<c010b70c>] (dump_backtrace) from [<c010b8a8>] (show_stack+0x18)
r6:60000013 r5:ffffffff r4:00000000 r3:00000000
[<c010b890>] (show_stack) from [<c03e9324>] (dump_stack+0xb0/0xe)
[<c03e9274>] (dump_stack) from [<c010b578>] (__div0+0x18/0x20)
r8:00000000 r7:ffffffff r6:ffffffff r5:00000000 r4:00000000 r3:0
[<c010b560>] (__div0) from [<c03e795c>] (Ldiv0_64+0x8/0x18)
[<c06cd860>] (divider_get_val) from [<c06cda28>] (clk_divider_se)

This error happens due to the lack of definition of the
IMX7D_PLL_AUDIO_TEST_DIV/IMX7D_PLL_AUDIO_POST_DIV clocks.

Add support for them.

Tested on a imx7s-warp board.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch reverts commit 023bd716 ("clk: skip unnecessary
set_phase if nothing to do"), fixing two problems:

* in some SoCs, the hardware phase delay depends on the rate ratio of
  the clock and its parent. So, changing this ratio may imply to set
  new hardware values, even if the logical delay is the same.

* when the delay was the same as previously, an error was returned.
Signed-off-by: NJean-Francois Moine <moinejf@free.fr>
Fixes: 023bd716 ("clk: skip unnecessary set_phase if nothing to do")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This adds support for the two ICST525-based clocks on the
Integrator/AP baseboard, as documented in the board manual
"Integrator/AP ASIC Development Motherboard", ARM DUI0098 B,
pages 3-15 thru 3-18.

Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
[sboyd@codeaurora.org: fixed uninitialized val warning]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The reset register offsets for UART*, I2C* and SCR were off by a few bytes.
Signed-off-by: NJorik Jonker <jorik@kippendief.biz>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

__of_clk_get_hw_from_provider() is confusing because it will
return EPROBE_DEFER if there isn't a ->get() or ->get_hw()
function pointer in a provider. That's just a bug though, and we
used to NULL pointer exception when ->get() was missing anyway,
so let's make this more obvious that they're not optional. The
assumption is that most providers will implement ->get_hw() so we
only fallback to the ->get() function if necessary. This
clarifies the intent and removes any possibility of probe defer
happening if clk providers are buggy.
Reported-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The Integrator/AP and Integrator/CP have special derivatives
of the ICST525 control registers, where some bits have been
hardwired but others are possible to adjust, resulting in a
control register that makes it possible to set an even,
desired megahertz value.

The Integrator/AP and Integrator/CP have slightly different
layout so we support them using different compatible
strings.

After adding these clocks, the Integrator-specific cpufreq
driver can be switched over to use the generic operating
point device tree cpufreq driver.

Instead of simply writing a value to the oscillator control
register we switch to the more elaborate method of providing
a bitmask and use regmap_update_bits() to poke the right bits
for the desired frequency, this is needed since these control
registers sometimes control more than one clock.

Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds missing 2 PCIE common reset lines.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch corrects the register offset for pcie2 pipe clock.
Offset according to datasheet is 0x6e018 instead of 0x6e108.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: b1e010c0 ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch selects QCOM_GDSC Kconfig for msm8996 GCC and MMCC clock
controllers, as these provide some of the gdscs on the SOC.

Also selecting this config will make it align with other drivers which
do the same.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 52111672 ("clk: qcom: gdsc: Add GDSCs in msm8996 GCC")
Fixes: 7e824d50 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers in this driver, allowing us to
move closer to a clear split of consumer and provider clk APIs.
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>