Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.

Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NAmit Daniel Kachhap <amit.daniel@samsung.com>
Tested-by: NArjun K.V <arjun.kv@samsung.com>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>