smu_v11_0.c 45.0 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
/*
 * Copyright 2019 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/firmware.h>
24
#include <linux/module.h>
25
#include <linux/pci.h>
26 27

#include "pp_debug.h"
28 29
#include "amdgpu.h"
#include "amdgpu_smu.h"
30
#include "atomfirmware.h"
31
#include "amdgpu_atomfirmware.h"
32
#include "smu_v11_0.h"
33
#include "soc15_common.h"
34
#include "atom.h"
35
#include "vega20_ppt.h"
36
#include "navi10_ppt.h"
37 38 39

#include "asic_reg/thm/thm_11_0_2_offset.h"
#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
40 41
#include "asic_reg/mp/mp_11_0_offset.h"
#include "asic_reg/mp/mp_11_0_sh_mask.h"
42
#include "asic_reg/nbio/nbio_7_4_offset.h"
43 44
#include "asic_reg/smuio/smuio_11_0_0_offset.h"
#include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
45

46
MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
47
MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
48

49
#define SMU11_VOLTAGE_SCALE 4
50

51 52 53 54 55 56 57 58
static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
					      uint16_t msg)
{
	struct amdgpu_device *adev = smu->adev;
	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
	return 0;
}

59 60 61 62 63 64 65 66
static int smu_v11_0_read_arg(struct smu_context *smu, uint32_t *arg)
{
	struct amdgpu_device *adev = smu->adev;

	*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
	return 0;
}

67 68 69
static int smu_v11_0_wait_for_response(struct smu_context *smu)
{
	struct amdgpu_device *adev = smu->adev;
70
	uint32_t cur_value, i, timeout = adev->usec_timeout * 10;
71

72
	for (i = 0; i < timeout; i++) {
73 74 75 76 77 78 79
		cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
		if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
			break;
		udelay(1);
	}

	/* timeout means wrong logic */
80
	if (i == timeout)
81 82
		return -ETIME;

83
	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
84 85 86 87 88
}

static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
{
	struct amdgpu_device *adev = smu->adev;
89 90 91 92 93
	int ret = 0, index = 0;

	index = smu_msg_get_index(smu, msg);
	if (index < 0)
		return index;
94 95 96 97 98

	smu_v11_0_wait_for_response(smu);

	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

99
	smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
100 101 102 103

	ret = smu_v11_0_wait_for_response(smu);

	if (ret)
104
		pr_err("Failed to send message 0x%x, response 0x%x\n", index,
105 106 107 108 109 110 111 112 113 114 115 116
		       ret);

	return ret;

}

static int
smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
			      uint32_t param)
{

	struct amdgpu_device *adev = smu->adev;
117 118 119 120 121
	int ret = 0, index = 0;

	index = smu_msg_get_index(smu, msg);
	if (index < 0)
		return index;
122 123 124

	ret = smu_v11_0_wait_for_response(smu);
	if (ret)
125 126
		pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
		       index, ret, param);
127 128 129 130 131

	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);

132
	smu_v11_0_send_msg_without_waiting(smu, (uint16_t)index);
133 134 135

	ret = smu_v11_0_wait_for_response(smu);
	if (ret)
136 137
		pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
		       index, ret, param);
138 139 140 141

	return ret;
}

142 143 144
static int smu_v11_0_init_microcode(struct smu_context *smu)
{
	struct amdgpu_device *adev = smu->adev;
145 146 147 148 149 150
	const char *chip_name;
	char fw_name[30];
	int err = 0;
	const struct smc_firmware_header_v1_0 *hdr;
	const struct common_firmware_header *header;
	struct amdgpu_firmware_info *ucode = NULL;
151

152 153 154 155
	switch (adev->asic_type) {
	case CHIP_VEGA20:
		chip_name = "vega20";
		break;
156 157 158
	case CHIP_NAVI10:
		chip_name = "navi10";
		break;
159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192
	default:
		BUG();
	}

	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);

	err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
	if (err)
		goto out;
	err = amdgpu_ucode_validate(adev->pm.fw);
	if (err)
		goto out;

	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
	amdgpu_ucode_print_smc_hdr(&hdr->header);
	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);

	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
		ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
		ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
		ucode->fw = adev->pm.fw;
		header = (const struct common_firmware_header *)ucode->fw->data;
		adev->firmware.fw_size +=
			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
	}

out:
	if (err) {
		DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
			  fw_name);
		release_firmware(adev->pm.fw);
		adev->pm.fw = NULL;
	}
	return err;
193 194
}

195 196
static int smu_v11_0_load_microcode(struct smu_context *smu)
{
197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229
	struct amdgpu_device *adev = smu->adev;
	const uint32_t *src;
	const struct smc_firmware_header_v1_0 *hdr;
	uint32_t addr_start = MP1_SRAM;
	uint32_t i;
	uint32_t mp1_fw_flags;

	hdr = (const struct smc_firmware_header_v1_0 *)	adev->pm.fw->data;
	src = (const uint32_t *)(adev->pm.fw->data +
		le32_to_cpu(hdr->header.ucode_array_offset_bytes));

	for (i = 1; i < MP1_SMC_SIZE/4 - 1; i++) {
		WREG32_PCIE(addr_start, src[i]);
		addr_start += 4;
	}

	WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
		1 & MP1_SMN_PUB_CTRL__RESET_MASK);
	WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
		1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);

	for (i = 0; i < adev->usec_timeout; i++) {
		mp1_fw_flags = RREG32_PCIE(MP1_Public |
			(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
		if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
			MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
			break;
		udelay(1);
	}

	if (i == adev->usec_timeout)
		return -ETIME;

230 231 232
	return 0;
}

233 234
static int smu_v11_0_check_fw_status(struct smu_context *smu)
{
235 236 237
	struct amdgpu_device *adev = smu->adev;
	uint32_t mp1_fw_flags;

238 239
	mp1_fw_flags = RREG32_PCIE(MP1_Public |
				   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
240 241 242 243

	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
	    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
		return 0;
244

245
	return -EIO;
246 247
}

248 249
static int smu_v11_0_check_fw_version(struct smu_context *smu)
{
250 251 252
	uint32_t if_version = 0xff, smu_version = 0xff;
	uint16_t smu_major;
	uint8_t smu_minor, smu_debug;
253 254
	int ret = 0;

255
	ret = smu_get_smc_version(smu, &if_version, &smu_version);
256
	if (ret)
257
		return ret;
258

259 260 261 262
	smu_major = (smu_version >> 16) & 0xffff;
	smu_minor = (smu_version >> 8) & 0xff;
	smu_debug = (smu_version >> 0) & 0xff;

263

264
	if (if_version != smu->smc_if_version) {
265 266 267 268
		pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
			"smu fw version = 0x%08x (%d.%d.%d)\n",
			smu->smc_if_version, if_version,
			smu_version, smu_major, smu_minor, smu_debug);
269
		pr_err("SMU driver if version not matched\n");
270
		ret = -EINVAL;
271 272
	}

273 274 275
	return ret;
}

276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317
static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
{
	struct amdgpu_device *adev = smu->adev;
	uint32_t ppt_offset_bytes;
	const struct smc_firmware_header_v2_0 *v2;

	v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;

	ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
	*size = le32_to_cpu(v2->ppt_size_bytes);
	*table = (uint8_t *)v2 + ppt_offset_bytes;

	return 0;
}

static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
{
	struct amdgpu_device *adev = smu->adev;
	const struct smc_firmware_header_v2_1 *v2_1;
	struct smc_soft_pptable_entry *entries;
	uint32_t pptable_count = 0;
	int i = 0;

	v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
	entries = (struct smc_soft_pptable_entry *)
		((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
	pptable_count = le32_to_cpu(v2_1->pptable_count);
	for (i = 0; i < pptable_count; i++) {
		if (le32_to_cpu(entries[i].id) == pptable_id) {
			*table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
			*size = le32_to_cpu(entries[i].ppt_size_bytes);
			break;
		}
	}

	if (i == pptable_count)
		return -EINVAL;

	return 0;
}

static int smu_v11_0_setup_pptable(struct smu_context *smu)
318
{
319 320
	struct amdgpu_device *adev = smu->adev;
	const struct smc_firmware_header_v1_0 *hdr;
321
	int ret, index;
322
	uint32_t size;
323
	uint8_t frev, crev;
324
	void *table;
325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344
	uint16_t version_major, version_minor;

	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
	version_major = le16_to_cpu(hdr->header.header_version_major);
	version_minor = le16_to_cpu(hdr->header.header_version_minor);
	if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
		switch (version_minor) {
		case 0:
			ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
			break;
		case 1:
			ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
							 smu->smu_table.boot_values.pp_table_id);
			break;
		default:
			ret = -EINVAL;
			break;
		}
		if (ret)
			return ret;
345

346 347 348
	} else {
		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
						    powerplayinfo);
349

350
		ret = smu_get_atom_data_table(smu, index, (uint16_t *)&size, &frev, &crev,
351 352 353 354
					      (uint8_t **)&table);
		if (ret)
			return ret;
	}
355

356 357 358 359
	if (!smu->smu_table.power_play_table)
		smu->smu_table.power_play_table = table;
	if (!smu->smu_table.power_play_table_size)
		smu->smu_table.power_play_table_size = size;
360 361 362 363

	return 0;
}

364 365 366 367 368 369 370
static int smu_v11_0_init_dpm_context(struct smu_context *smu)
{
	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;

	if (smu_dpm->dpm_context || smu_dpm->dpm_context_size != 0)
		return -EINVAL;

371
	return smu_alloc_dpm_context(smu);
372 373 374 375 376 377 378 379 380 381
}

static int smu_v11_0_fini_dpm_context(struct smu_context *smu)
{
	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;

	if (!smu_dpm->dpm_context || smu_dpm->dpm_context_size == 0)
		return -EINVAL;

	kfree(smu_dpm->dpm_context);
382
	kfree(smu_dpm->golden_dpm_context);
383 384
	kfree(smu_dpm->dpm_current_power_state);
	kfree(smu_dpm->dpm_request_power_state);
385
	smu_dpm->dpm_context = NULL;
386
	smu_dpm->golden_dpm_context = NULL;
387
	smu_dpm->dpm_context_size = 0;
388 389
	smu_dpm->dpm_current_power_state = NULL;
	smu_dpm->dpm_request_power_state = NULL;
390 391 392 393

	return 0;
}

394 395 396 397
static int smu_v11_0_init_smc_tables(struct smu_context *smu)
{
	struct smu_table_context *smu_table = &smu->smu_table;
	struct smu_table *tables = NULL;
398
	int ret = 0;
399

400
	if (smu_table->tables || smu_table->table_count == 0)
401 402
		return -EINVAL;

403 404
	tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
			 GFP_KERNEL);
405 406 407 408 409
	if (!tables)
		return -ENOMEM;

	smu_table->tables = tables;

410 411 412
	ret = smu_tables_init(smu, tables);
	if (ret)
		return ret;
413

414 415 416 417
	ret = smu_v11_0_init_dpm_context(smu);
	if (ret)
		return ret;

418 419 420 421 422 423
	return 0;
}

static int smu_v11_0_fini_smc_tables(struct smu_context *smu)
{
	struct smu_table_context *smu_table = &smu->smu_table;
424
	int ret = 0;
425 426 427 428 429

	if (!smu_table->tables || smu_table->table_count == 0)
		return -EINVAL;

	kfree(smu_table->tables);
430
	kfree(smu_table->metrics_table);
431 432
	smu_table->tables = NULL;
	smu_table->table_count = 0;
433 434
	smu_table->metrics_table = NULL;
	smu_table->metrics_time = 0;
435

436 437 438
	ret = smu_v11_0_fini_dpm_context(smu);
	if (ret)
		return ret;
439 440
	return 0;
}
441 442 443 444 445

static int smu_v11_0_init_power(struct smu_context *smu)
{
	struct smu_power_context *smu_power = &smu->smu_power;

446 447
	if (!smu->pm_enabled)
		return 0;
448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463
	if (smu_power->power_context || smu_power->power_context_size != 0)
		return -EINVAL;

	smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
					   GFP_KERNEL);
	if (!smu_power->power_context)
		return -ENOMEM;
	smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);

	return 0;
}

static int smu_v11_0_fini_power(struct smu_context *smu)
{
	struct smu_power_context *smu_power = &smu->smu_power;

464 465
	if (!smu->pm_enabled)
		return 0;
466 467 468 469 470 471 472 473 474 475
	if (!smu_power->power_context || smu_power->power_context_size == 0)
		return -EINVAL;

	kfree(smu_power->power_context);
	smu_power->power_context = NULL;
	smu_power->power_context_size = 0;

	return 0;
}

476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533
int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
{
	int ret, index;
	uint16_t size;
	uint8_t frev, crev;
	struct atom_common_table_header *header;
	struct atom_firmware_info_v3_3 *v_3_3;
	struct atom_firmware_info_v3_1 *v_3_1;

	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
					    firmwareinfo);

	ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
				      (uint8_t **)&header);
	if (ret)
		return ret;

	if (header->format_revision != 3) {
		pr_err("unknown atom_firmware_info version! for smu11\n");
		return -EINVAL;
	}

	switch (header->content_revision) {
	case 0:
	case 1:
	case 2:
		v_3_1 = (struct atom_firmware_info_v3_1 *)header;
		smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
		smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
		smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
		smu->smu_table.boot_values.socclk = 0;
		smu->smu_table.boot_values.dcefclk = 0;
		smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
		smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
		smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
		smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
		smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
		smu->smu_table.boot_values.pp_table_id = 0;
		break;
	case 3:
	default:
		v_3_3 = (struct atom_firmware_info_v3_3 *)header;
		smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
		smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
		smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
		smu->smu_table.boot_values.socclk = 0;
		smu->smu_table.boot_values.dcefclk = 0;
		smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
		smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
		smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
		smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
		smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
		smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
	}

	return 0;
}

534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567
static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
{
	int ret, index;
	struct amdgpu_device *adev = smu->adev;
	struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
	struct atom_get_smu_clock_info_output_parameters_v3_1 *output;

	input.clk_id = SMU11_SYSPLL0_SOCCLK_ID;
	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
					    getsmuclockinfo);

	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
					(uint32_t *)&input);
	if (ret)
		return -EINVAL;

	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
	smu->smu_table.boot_values.socclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;

	memset(&input, 0, sizeof(input));
	input.clk_id = SMU11_SYSPLL0_DCEFCLK_ID;
	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
					    getsmuclockinfo);

	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
					(uint32_t *)&input);
	if (ret)
		return -EINVAL;

	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
	smu->smu_table.boot_values.dcefclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;

568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609
	memset(&input, 0, sizeof(input));
	input.clk_id = SMU11_SYSPLL0_ECLK_ID;
	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
					    getsmuclockinfo);

	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
					(uint32_t *)&input);
	if (ret)
		return -EINVAL;

	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
	smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;

	memset(&input, 0, sizeof(input));
	input.clk_id = SMU11_SYSPLL0_VCLK_ID;
	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
					    getsmuclockinfo);

	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
					(uint32_t *)&input);
	if (ret)
		return -EINVAL;

	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
	smu->smu_table.boot_values.vclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;

	memset(&input, 0, sizeof(input));
	input.clk_id = SMU11_SYSPLL0_DCLK_ID;
	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
					    getsmuclockinfo);

	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
					(uint32_t *)&input);
	if (ret)
		return -EINVAL;

	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
	smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;

610 611 612
	return 0;
}

613 614 615 616 617 618 619 620 621 622 623
static int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
{
	struct smu_table_context *smu_table = &smu->smu_table;
	struct smu_table *memory_pool = &smu_table->memory_pool;
	int ret = 0;
	uint64_t address;
	uint32_t address_low, address_high;

	if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
		return ret;

624
	address = (uintptr_t)memory_pool->cpu_addr;
625 626 627 628
	address_high = (uint32_t)upper_32_bits(address);
	address_low  = (uint32_t)lower_32_bits(address);

	ret = smu_send_smc_msg_with_param(smu,
629
					  SMU_MSG_SetSystemVirtualDramAddrHigh,
630 631 632 633
					  address_high);
	if (ret)
		return ret;
	ret = smu_send_smc_msg_with_param(smu,
634
					  SMU_MSG_SetSystemVirtualDramAddrLow,
635 636 637 638 639 640 641 642
					  address_low);
	if (ret)
		return ret;

	address = memory_pool->mc_address;
	address_high = (uint32_t)upper_32_bits(address);
	address_low  = (uint32_t)lower_32_bits(address);

643
	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
644 645 646
					  address_high);
	if (ret)
		return ret;
647
	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
648 649 650
					  address_low);
	if (ret)
		return ret;
651
	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
652 653 654 655 656 657 658
					  (uint32_t)memory_pool->size);
	if (ret)
		return ret;

	return ret;
}

659 660 661 662 663 664 665 666
static int smu_v11_0_check_pptable(struct smu_context *smu)
{
	int ret;

	ret = smu_check_powerplay_table(smu);
	return ret;
}

667 668 669 670 671
static int smu_v11_0_parse_pptable(struct smu_context *smu)
{
	int ret;

	struct smu_table_context *table_context = &smu->smu_table;
672
	struct smu_table *table = &table_context->tables[SMU_TABLE_PPTABLE];
673 674 675 676

	if (table_context->driver_pptable)
		return -EINVAL;

677
	table_context->driver_pptable = kzalloc(table->size, GFP_KERNEL);
678 679 680 681 682

	if (!table_context->driver_pptable)
		return -ENOMEM;

	ret = smu_store_powerplay_table(smu);
683 684 685 686
	if (ret)
		return -EINVAL;

	ret = smu_append_powerplay_table(smu);
687 688 689 690

	return ret;
}

691 692
static int smu_v11_0_populate_smc_pptable(struct smu_context *smu)
{
693
	int ret;
694

695
	ret = smu_set_default_dpm_table(smu);
696

697
	return ret;
698 699
}

700 701
static int smu_v11_0_write_pptable(struct smu_context *smu)
{
702
	struct smu_table_context *table_context = &smu->smu_table;
703 704
	int ret = 0;

705 706
	ret = smu_update_table(smu, SMU_TABLE_PPTABLE,
			       table_context->driver_pptable, true);
707 708 709 710

	return ret;
}

711 712
static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
{
713 714 715 716 717 718 719 720 721 722 723 724
	int ret = 0;
	struct smu_table_context *smu_table = &smu->smu_table;
	struct smu_table *table = NULL;

	table = &smu_table->tables[SMU_TABLE_WATERMARKS];
	if (!table)
		return -EINVAL;

	if (!table->cpu_addr)
		return -EINVAL;

	ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr,
725
				true);
726 727

	return ret;
728 729
}

730 731 732 733 734 735 736 737 738 739 740 741
static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
{
	int ret;

	ret = smu_send_smc_msg_with_param(smu,
					  SMU_MSG_SetMinDeepSleepDcefclk, clk);
	if (ret)
		pr_err("SMU11 attempt to set divider for DCEFCLK Failed!");

	return ret;
}

742 743 744 745
static int smu_v11_0_set_min_dcef_deep_sleep(struct smu_context *smu)
{
	struct smu_table_context *table_context = &smu->smu_table;

746 747
	if (!smu->pm_enabled)
		return 0;
748 749 750
	if (!table_context)
		return -EINVAL;

751
	return smu_set_deep_sleep_dcefclk(smu,
752 753 754
					  table_context->boot_values.dcefclk / 100);
}

755 756 757
static int smu_v11_0_set_tool_table_location(struct smu_context *smu)
{
	int ret = 0;
758
	struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
759 760 761

	if (tool_table->mc_address) {
		ret = smu_send_smc_msg_with_param(smu,
762
				SMU_MSG_SetToolsDramAddrHigh,
763 764 765
				upper_32_bits(tool_table->mc_address));
		if (!ret)
			ret = smu_send_smc_msg_with_param(smu,
766
				SMU_MSG_SetToolsDramAddrLow,
767 768 769 770 771 772
				lower_32_bits(tool_table->mc_address));
	}

	return ret;
}

773
static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
774 775
{
	int ret = 0;
776 777 778

	if (!smu->pm_enabled)
		return ret;
779

780
	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
781 782 783
	return ret;
}

784 785 786 787 788
static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
{
	uint32_t feature_low = 0, feature_high = 0;
	int ret = 0;

789 790
	if (!smu->pm_enabled)
		return ret;
791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822
	if (feature_id >= 0 && feature_id < 31)
		feature_low = (1 << feature_id);
	else if (feature_id > 31 && feature_id < 63)
		feature_high = (1 << feature_id);
	else
		return -EINVAL;

	if (enabled) {
		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
						  feature_low);
		if (ret)
			return ret;
		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
						  feature_high);
		if (ret)
			return ret;

	} else {
		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
						  feature_low);
		if (ret)
			return ret;
		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
						  feature_high);
		if (ret)
			return ret;

	}

	return ret;
}

823 824 825 826 827 828
static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
{
	struct smu_feature *feature = &smu->smu_feature;
	int ret = 0;
	uint32_t feature_mask[2];

829
	mutex_lock(&feature->mutex);
830
	if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
831
		goto failed;
832 833 834 835 836 837

	bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);

	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
					  feature_mask[1]);
	if (ret)
838
		goto failed;
839 840 841 842

	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
					  feature_mask[0]);
	if (ret)
843
		goto failed;
844

845 846
failed:
	mutex_unlock(&feature->mutex);
847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878
	return ret;
}

static int smu_v11_0_get_enabled_mask(struct smu_context *smu,
				      uint32_t *feature_mask, uint32_t num)
{
	uint32_t feature_mask_high = 0, feature_mask_low = 0;
	int ret = 0;

	if (!feature_mask || num < 2)
		return -EINVAL;

	ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh);
	if (ret)
		return ret;
	ret = smu_read_smc_arg(smu, &feature_mask_high);
	if (ret)
		return ret;

	ret = smu_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow);
	if (ret)
		return ret;
	ret = smu_read_smc_arg(smu, &feature_mask_low);
	if (ret)
		return ret;

	feature_mask[0] = feature_mask_low;
	feature_mask[1] = feature_mask_high;

	return ret;
}

879 880
static int smu_v11_0_system_features_control(struct smu_context *smu,
					     bool en)
881 882 883 884 885
{
	struct smu_feature *feature = &smu->smu_feature;
	uint32_t feature_mask[2];
	int ret = 0;

886 887 888 889 890 891 892
	if (smu->pm_enabled) {
		ret = smu_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
					     SMU_MSG_DisableAllSmuFeatures));
		if (ret)
			return ret;
	}

893 894 895 896 897 898 899 900 901 902 903 904
	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
	if (ret)
		return ret;

	bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
		    feature->feature_num);
	bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
		    feature->feature_num);

	return ret;
}

905 906 907 908
static int smu_v11_0_notify_display_change(struct smu_context *smu)
{
	int ret = 0;

909 910
	if (!smu->pm_enabled)
		return ret;
911 912 913
	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
	    smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1);
914 915 916 917

	return ret;
}

918 919
static int
smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
920
				    enum smu_clk_type clock_select)
921 922 923
{
	int ret = 0;

924 925
	if (!smu->pm_enabled)
		return ret;
926
	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
927
					  smu_clk_get_index(smu, clock_select) << 16);
928 929 930 931 932 933 934 935 936 937 938 939 940 941
	if (ret) {
		pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
		return ret;
	}

	ret = smu_read_smc_arg(smu, clock);
	if (ret)
		return ret;

	if (*clock != 0)
		return 0;

	/* if DC limit is zero, return AC limit */
	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
942
					  smu_clk_get_index(smu, clock_select) << 16);
943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968
	if (ret) {
		pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
		return ret;
	}

	ret = smu_read_smc_arg(smu, clock);

	return ret;
}

static int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
{
	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
	int ret = 0;

	max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
					 GFP_KERNEL);
	smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;

	max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
	max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
	max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
	max_sustainable_clocks->display_clock = 0xFFFFFFFF;
	max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
	max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;

969
	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
970 971
		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->uclock),
972
							  SMU_UCLK);
973 974 975 976 977 978 979
		if (ret) {
			pr_err("[%s] failed to get max UCLK from SMC!",
			       __func__);
			return ret;
		}
	}

980
	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
981 982
		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->soc_clock),
983
							  SMU_SOCCLK);
984 985 986 987 988 989 990
		if (ret) {
			pr_err("[%s] failed to get max SOCCLK from SMC!",
			       __func__);
			return ret;
		}
	}

991
	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
992 993
		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->dcef_clock),
994
							  SMU_DCEFCLK);
995 996 997 998 999 1000 1001 1002
		if (ret) {
			pr_err("[%s] failed to get max DCEFCLK from SMC!",
			       __func__);
			return ret;
		}

		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->display_clock),
1003
							  SMU_DISPCLK);
1004 1005 1006 1007 1008 1009 1010
		if (ret) {
			pr_err("[%s] failed to get max DISPCLK from SMC!",
			       __func__);
			return ret;
		}
		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->phy_clock),
1011
							  SMU_PHYCLK);
1012 1013 1014 1015 1016 1017 1018
		if (ret) {
			pr_err("[%s] failed to get max PHYCLK from SMC!",
			       __func__);
			return ret;
		}
		ret = smu_v11_0_get_max_sustainable_clock(smu,
							  &(max_sustainable_clocks->pixel_clock),
1019
							  SMU_PIXCLK);
1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032
		if (ret) {
			pr_err("[%s] failed to get max PIXCLK from SMC!",
			       __func__);
			return ret;
		}
	}

	if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
		max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;

	return 0;
}

1033 1034 1035
static int smu_v11_0_get_power_limit(struct smu_context *smu,
				     uint32_t *limit,
				     bool get_default)
1036
{
1037
	int ret = 0;
1038

1039 1040 1041
	if (get_default) {
		mutex_lock(&smu->mutex);
		*limit = smu->default_power_limit;
1042 1043 1044 1045
		if (smu->od_enabled) {
			*limit *= (100 + smu->smu_table.TDPODLimit);
			*limit /= 100;
		}
1046 1047 1048
		mutex_unlock(&smu->mutex);
	} else {
		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1049
			smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);
1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062
		if (ret) {
			pr_err("[%s] get PPT limit failed!", __func__);
			return ret;
		}
		smu_read_smc_arg(smu, limit);
		smu->power_limit = *limit;
	}

	return ret;
}

static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
{
1063
	uint32_t max_power_limit;
1064 1065
	int ret = 0;

1066 1067 1068 1069 1070 1071 1072 1073 1074 1075
	if (n == 0)
		n = smu->default_power_limit;

	max_power_limit = smu->default_power_limit;

	if (smu->od_enabled) {
		max_power_limit *= (100 + smu->smu_table.TDPODLimit);
		max_power_limit /= 100;
	}

1076
	if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1077
		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
1078
	if (ret) {
1079
		pr_err("[%s] Set power limit Failed!", __func__);
1080 1081 1082
		return ret;
	}

1083
	return ret;
1084 1085
}

1086 1087 1088
static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
					  enum smu_clk_type clk_id,
					  uint32_t *value)
1089 1090 1091 1092
{
	int ret = 0;
	uint32_t freq;

1093
	if (clk_id >= SMU_CLK_COUNT || !value)
1094 1095
		return -EINVAL;

1096 1097
	/* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
	if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0)
1098 1099 1100 1101 1102 1103
		ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
	else {
		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
						  (smu_clk_get_index(smu, clk_id) << 16));
		if (ret)
			return ret;
1104

1105 1106 1107 1108
		ret = smu_read_smc_arg(smu, &freq);
		if (ret)
			return ret;
	}
1109 1110 1111 1112 1113 1114 1115

	freq *= 100;
	*value = freq;

	return ret;
}

1116
static int smu_v11_0_set_thermal_range(struct smu_context *smu,
1117
				       struct smu_temperature_range *range)
1118 1119
{
	struct amdgpu_device *adev = smu->adev;
1120 1121 1122 1123
	int low = SMU_THERMAL_MINIMUM_ALERT_TEMP *
		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
	int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP *
		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1124 1125
	uint32_t val;

1126 1127 1128
	if (!range)
		return -EINVAL;

1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139
	if (low < range->min)
		low = range->min;
	if (high > range->max)
		high = range->max;

	if (low > high)
		return -EINVAL;

	val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1140 1141
	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1142 1143
	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
1144 1145 1146 1147 1148 1149 1150
	val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);

	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);

	return 0;
}

1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164
static int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
{
	struct amdgpu_device *adev = smu->adev;
	uint32_t val = 0;

	val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
	val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
	val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);

	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);

	return 0;
}

1165 1166 1167
static int smu_v11_0_start_thermal_control(struct smu_context *smu)
{
	int ret = 0;
1168
	struct smu_temperature_range range = {
1169 1170 1171 1172 1173 1174 1175 1176 1177
		TEMP_RANGE_MIN,
		TEMP_RANGE_MAX,
		TEMP_RANGE_MAX,
		TEMP_RANGE_MIN,
		TEMP_RANGE_MAX,
		TEMP_RANGE_MAX,
		TEMP_RANGE_MIN,
		TEMP_RANGE_MAX,
		TEMP_RANGE_MAX};
1178 1179
	struct amdgpu_device *adev = smu->adev;

1180 1181
	if (!smu->pm_enabled)
		return ret;
1182
	ret = smu_get_thermal_temperature_range(smu, &range);
1183 1184 1185 1186 1187 1188 1189 1190 1191

	if (smu->smu_table.thermal_controller_type) {
		ret = smu_v11_0_set_thermal_range(smu, &range);
		if (ret)
			return ret;

		ret = smu_v11_0_enable_thermal_alert(smu);
		if (ret)
			return ret;
1192

1193
		ret = smu_set_thermal_fan_table(smu);
1194 1195 1196 1197 1198 1199
		if (ret)
			return ret;
	}

	adev->pm.dpm.thermal.min_temp = range.min;
	adev->pm.dpm.thermal.max_temp = range.max;
1200 1201 1202 1203 1204 1205 1206
	adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
	adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
	adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
	adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
	adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
	adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
	adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
1207 1208 1209 1210

	return ret;
}

1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234
static uint16_t convert_to_vddc(uint8_t vid)
{
	return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
}

static int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
{
	struct amdgpu_device *adev = smu->adev;
	uint32_t vdd = 0, val_vid = 0;

	if (!value)
		return -EINVAL;
	val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
		SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
		SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;

	vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);

	*value = vdd;

	return 0;

}

1235 1236 1237 1238 1239 1240
static int smu_v11_0_read_sensor(struct smu_context *smu,
				 enum amd_pp_sensors sensor,
				 void *data, uint32_t *size)
{
	int ret = 0;
	switch (sensor) {
1241
	case AMDGPU_PP_SENSOR_GFX_MCLK:
1242
		ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
1243 1244 1245
		*size = 4;
		break;
	case AMDGPU_PP_SENSOR_GFX_SCLK:
1246
		ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t *)data);
1247
		*size = 4;
1248
		break;
1249 1250 1251
	case AMDGPU_PP_SENSOR_VDDGFX:
		ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
		*size = 4;
1252
		break;
1253 1254 1255 1256
	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
		*(uint32_t *)data = 0;
		*size = 4;
		break;
1257
	default:
1258
		ret = smu_common_read_sensor(smu, sensor, data, size);
1259 1260 1261
		break;
	}

1262 1263 1264 1265
	/* try get sensor data by asic */
	if (ret)
		ret = smu_asic_read_sensor(smu, sensor, data, size);

1266 1267 1268 1269 1270 1271
	if (ret)
		*size = 0;

	return ret;
}

1272 1273 1274 1275 1276 1277 1278
static int
smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
					struct pp_display_clock_request
					*clock_req)
{
	enum amd_pp_clock_type clk_type = clock_req->clock_type;
	int ret = 0;
1279
	enum smu_clk_type clk_select = 0;
1280 1281
	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;

1282 1283
	if (!smu->pm_enabled)
		return -EINVAL;
1284

1285
	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1286
		smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1287 1288
		switch (clk_type) {
		case amd_pp_dcef_clock:
1289
			clk_select = SMU_DCEFCLK;
1290 1291
			break;
		case amd_pp_disp_clock:
1292
			clk_select = SMU_DISPCLK;
1293 1294
			break;
		case amd_pp_pixel_clock:
1295
			clk_select = SMU_PIXCLK;
1296 1297
			break;
		case amd_pp_phy_clock:
1298
			clk_select = SMU_PHYCLK;
1299
			break;
1300 1301 1302
		case amd_pp_mem_clock:
			clk_select = SMU_UCLK;
			break;
1303 1304 1305 1306 1307 1308 1309 1310 1311
		default:
			pr_info("[%s] Invalid Clock Type!", __func__);
			ret = -EINVAL;
			break;
		}

		if (ret)
			goto failed;

1312
		mutex_lock(&smu->mutex);
1313
		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1314
			(smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
1315
		mutex_unlock(&smu->mutex);
1316 1317 1318 1319 1320 1321
	}

failed:
	return ret;
}

1322 1323 1324 1325 1326 1327
static int
smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct
					  dm_pp_wm_sets_with_clock_ranges_soc15
					  *clock_ranges)
{
	int ret = 0;
1328
	struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS];
1329
	void *table = watermarks->cpu_addr;
1330 1331

	if (!smu->disable_watermark &&
1332 1333
	    smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
	    smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1334
		smu_set_watermarks_table(smu, table, clock_ranges);
1335 1336 1337 1338 1339 1340 1341
		smu->watermarks_bitmap |= WATERMARKS_EXIST;
		smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
	}

	return ret;
}

1342 1343 1344
static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
{
	int ret = 0;
1345
	struct amdgpu_device *adev = smu->adev;
1346

1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362
	switch (adev->asic_type) {
	case CHIP_VEGA20:
		break;
	case CHIP_NAVI10:
		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
			return 0;
		mutex_lock(&smu->mutex);
		if (enable)
			ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
		else
			ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
		mutex_unlock(&smu->mutex);
		break;
	default:
		break;
	}
1363 1364 1365 1366

	return ret;
}

1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383
static int smu_v11_0_get_current_rpm(struct smu_context *smu,
				     uint32_t *current_rpm)
{
	int ret;

	ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm);

	if (ret) {
		pr_err("Attempt to get current RPM from SMC Failed!\n");
		return ret;
	}

	smu_read_smc_arg(smu, current_rpm);

	return 0;
}

1384 1385 1386
static uint32_t
smu_v11_0_get_fan_control_mode(struct smu_context *smu)
{
1387
	if (!smu_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1388 1389 1390 1391 1392 1393 1394 1395 1396 1397
		return AMD_FAN_CTRL_MANUAL;
	else
		return AMD_FAN_CTRL_AUTO;
}

static int
smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
{
	int ret = 0;

1398
	if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1399 1400
		return 0;

1401
	ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453
	if (ret)
		pr_err("[%s]%s smc FAN CONTROL feature failed!",
		       __func__, (start ? "Start" : "Stop"));

	return ret;
}

static int
smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
{
	struct amdgpu_device *adev = smu->adev;

	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
				   CG_FDO_CTRL2, TMIN, 0));
	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
				   CG_FDO_CTRL2, FDO_PWM_MODE, mode));

	return 0;
}

static int
smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
{
	struct amdgpu_device *adev = smu->adev;
	uint32_t duty100;
	uint32_t duty;
	uint64_t tmp64;
	bool stop = 0;

	if (speed > 100)
		speed = 100;

	if (smu_v11_0_smc_fan_control(smu, stop))
		return -EINVAL;
	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
				CG_FDO_CTRL1, FMAX_DUTY100);
	if (!duty100)
		return -EINVAL;

	tmp64 = (uint64_t)speed * duty100;
	do_div(tmp64, 100);
	duty = (uint32_t)tmp64;

	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
				   CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));

	return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
}

1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476
static int
smu_v11_0_set_fan_control_mode(struct smu_context *smu,
			       uint32_t mode)
{
	int ret = 0;
	bool start = 1;
	bool stop  = 0;

	switch (mode) {
	case AMD_FAN_CTRL_NONE:
		ret = smu_v11_0_set_fan_speed_percent(smu, 100);
		break;
	case AMD_FAN_CTRL_MANUAL:
		ret = smu_v11_0_smc_fan_control(smu, stop);
		break;
	case AMD_FAN_CTRL_AUTO:
		ret = smu_v11_0_smc_fan_control(smu, start);
		break;
	default:
		break;
	}

	if (ret) {
1477
		pr_err("[%s]Set fan control mode failed!", __func__);
1478 1479 1480 1481 1482 1483
		return -EINVAL;
	}

	return ret;
}

1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513
static int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
				       uint32_t speed)
{
	struct amdgpu_device *adev = smu->adev;
	int ret;
	uint32_t tach_period, crystal_clock_freq;
	bool stop = 0;

	if (!speed)
		return -EINVAL;

	mutex_lock(&(smu->mutex));
	ret = smu_v11_0_smc_fan_control(smu, stop);
	if (ret)
		goto set_fan_speed_rpm_failed;

	crystal_clock_freq = amdgpu_asic_get_xclk(adev);
	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
	WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
		     REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
				   CG_TACH_CTRL, TARGET_PERIOD,
				   tach_period));

	ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);

set_fan_speed_rpm_failed:
	mutex_unlock(&(smu->mutex));
	return ret;
}

1514 1515 1516
#define XGMI_STATE_D0 1
#define XGMI_STATE_D3 0

1517 1518 1519
static int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
				     uint32_t pstate)
{
1520 1521 1522 1523 1524 1525 1526
	int ret = 0;
	mutex_lock(&(smu->mutex));
	ret = smu_send_smc_msg_with_param(smu,
					  SMU_MSG_SetXgmiMode,
					  pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
	mutex_unlock(&(smu->mutex));
	return ret;
1527 1528
}

1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603
#define THM_11_0__SRCID__THM_DIG_THERM_L2H		0		/* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
#define THM_11_0__SRCID__THM_DIG_THERM_H2L		1		/* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */

static int smu_v11_0_irq_process(struct amdgpu_device *adev,
				 struct amdgpu_irq_src *source,
				 struct amdgpu_iv_entry *entry)
{
	uint32_t client_id = entry->client_id;
	uint32_t src_id = entry->src_id;

	if (client_id == SOC15_IH_CLIENTID_THM) {
		switch (src_id) {
		case THM_11_0__SRCID__THM_DIG_THERM_L2H:
			pr_warn("GPU over temperature range detected on PCIe %d:%d.%d!\n",
				PCI_BUS_NUM(adev->pdev->devfn),
				PCI_SLOT(adev->pdev->devfn),
				PCI_FUNC(adev->pdev->devfn));
		break;
		case THM_11_0__SRCID__THM_DIG_THERM_H2L:
			pr_warn("GPU under temperature range detected on PCIe %d:%d.%d!\n",
				PCI_BUS_NUM(adev->pdev->devfn),
				PCI_SLOT(adev->pdev->devfn),
				PCI_FUNC(adev->pdev->devfn));
		break;
		default:
			pr_warn("GPU under temperature range unknown src id (%d), detected on PCIe %d:%d.%d!\n",
				src_id,
				PCI_BUS_NUM(adev->pdev->devfn),
				PCI_SLOT(adev->pdev->devfn),
				PCI_FUNC(adev->pdev->devfn));
		break;

		}
	}

	return 0;
}

static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
{
	.process = smu_v11_0_irq_process,
};

static int smu_v11_0_register_irq_handler(struct smu_context *smu)
{
	struct amdgpu_device *adev = smu->adev;
	struct amdgpu_irq_src *irq_src = smu->irq_source;
	int ret = 0;

	/* already register */
	if (irq_src)
		return 0;

	irq_src = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
	if (!irq_src)
		return -ENOMEM;
	smu->irq_source = irq_src;

	irq_src->funcs = &smu_v11_0_irq_funcs;

	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
				THM_11_0__SRCID__THM_DIG_THERM_L2H,
				irq_src);
	if (ret)
		return ret;

	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
				THM_11_0__SRCID__THM_DIG_THERM_H2L,
				irq_src);
	if (ret)
		return ret;

	return ret;
}

1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
		struct pp_smu_nv_clock_table *max_clocks)
{
	struct smu_table_context *table_context = &smu->smu_table;
	struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;

	if (!max_clocks || !table_context->max_sustainable_clocks)
		return -EINVAL;

	sustainable_clocks = table_context->max_sustainable_clocks;

	max_clocks->dcfClockInKhz =
			(unsigned int) sustainable_clocks->dcef_clock * 1000;
	max_clocks->displayClockInKhz =
			(unsigned int) sustainable_clocks->display_clock * 1000;
	max_clocks->phyClockInKhz =
			(unsigned int) sustainable_clocks->phy_clock * 1000;
	max_clocks->pixelClockInKhz =
			(unsigned int) sustainable_clocks->pixel_clock * 1000;
	max_clocks->uClockInKhz =
			(unsigned int) sustainable_clocks->uclock * 1000;
	max_clocks->socClockInKhz =
			(unsigned int) sustainable_clocks->soc_clock * 1000;
	max_clocks->dscClockInKhz = 0;
	max_clocks->dppClockInKhz = 0;
	max_clocks->fabricClockInKhz = 0;

	return 0;
}

1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644
static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
{
	int ret = 0;

	mutex_lock(&smu->mutex);
	ret = smu_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME);
	mutex_unlock(&smu->mutex);

	return ret;
}

1645 1646
static const struct smu_funcs smu_v11_0_funcs = {
	.init_microcode = smu_v11_0_init_microcode,
1647
	.load_microcode = smu_v11_0_load_microcode,
1648
	.check_fw_status = smu_v11_0_check_fw_status,
1649
	.check_fw_version = smu_v11_0_check_fw_version,
1650 1651
	.send_smc_msg = smu_v11_0_send_msg,
	.send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
1652
	.read_smc_arg = smu_v11_0_read_arg,
1653
	.setup_pptable = smu_v11_0_setup_pptable,
1654 1655
	.init_smc_tables = smu_v11_0_init_smc_tables,
	.fini_smc_tables = smu_v11_0_fini_smc_tables,
1656 1657
	.init_power = smu_v11_0_init_power,
	.fini_power = smu_v11_0_fini_power,
1658
	.get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
1659
	.get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
1660
	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
1661
	.check_pptable = smu_v11_0_check_pptable,
1662
	.parse_pptable = smu_v11_0_parse_pptable,
1663
	.populate_smc_pptable = smu_v11_0_populate_smc_pptable,
1664
	.write_pptable = smu_v11_0_write_pptable,
1665
	.write_watermarks_table = smu_v11_0_write_watermarks_table,
1666
	.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
1667
	.set_tool_table_location = smu_v11_0_set_tool_table_location,
1668
	.init_display_count = smu_v11_0_init_display_count,
1669 1670
	.set_allowed_mask = smu_v11_0_set_allowed_mask,
	.get_enabled_mask = smu_v11_0_get_enabled_mask,
1671
	.system_features_control = smu_v11_0_system_features_control,
1672
	.update_feature_enable_state = smu_v11_0_update_feature_enable_state,
1673
	.notify_display_change = smu_v11_0_notify_display_change,
1674
	.get_power_limit = smu_v11_0_get_power_limit,
1675
	.set_power_limit = smu_v11_0_set_power_limit,
1676
	.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
1677
	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
1678
	.start_thermal_control = smu_v11_0_start_thermal_control,
1679
	.read_sensor = smu_v11_0_read_sensor,
1680
	.set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
1681
	.display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
1682
	.set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges,
1683
	.get_current_rpm = smu_v11_0_get_current_rpm,
1684
	.get_fan_control_mode = smu_v11_0_get_fan_control_mode,
1685
	.set_fan_control_mode = smu_v11_0_set_fan_control_mode,
1686
	.set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
1687
	.set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
1688
	.set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
1689
	.gfx_off_control = smu_v11_0_gfx_off_control,
1690
	.register_irq_handler = smu_v11_0_register_irq_handler,
1691
	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
1692
	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
1693 1694 1695 1696
};

void smu_v11_0_set_smu_funcs(struct smu_context *smu)
{
1697 1698
	struct amdgpu_device *adev = smu->adev;

1699
	smu->funcs = &smu_v11_0_funcs;
1700 1701 1702 1703
	switch (adev->asic_type) {
	case CHIP_VEGA20:
		vega20_set_ppt_funcs(smu);
		break;
1704 1705 1706
	case CHIP_NAVI10:
		navi10_set_ppt_funcs(smu);
		break;
1707
	default:
1708
		pr_warn("Unknown asic for smu11\n");
1709
	}
1710
}