i915_debugfs.c 100.7 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/seq_file.h>
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#include <linux/circ_buf.h>
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#include <linux/ctype.h>
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#include <linux/debugfs.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/list_sort.h>
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#include <asm/msr-index.h>
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include "intel_ringbuffer.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

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enum {
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	ACTIVE_LIST,
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	INACTIVE_LIST,
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	PINNED_LIST,
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};
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static const char *yesno(int v)
{
	return v ? "yes" : "no";
}

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/* As the drm_debugfs_init() routines are called before dev->dev_private is
 * allocated we need to hook into the minor for release. */
static int
drm_add_fake_info_node(struct drm_minor *minor,
		       struct dentry *ent,
		       const void *key)
{
	struct drm_info_node *node;

	node = kmalloc(sizeof(*node), GFP_KERNEL);
	if (node == NULL) {
		debugfs_remove(ent);
		return -ENOMEM;
	}

	node->minor = minor;
	node->dent = ent;
	node->info_ent = (void *) key;

	mutex_lock(&minor->debugfs_lock);
	list_add(&node->list, &minor->debugfs_list);
	mutex_unlock(&minor->debugfs_lock);

	return 0;
}

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static int i915_capabilities(struct seq_file *m, void *data)
{
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	struct drm_info_node *node = m->private;
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	struct drm_device *dev = node->minor->dev;
	const struct intel_device_info *info = INTEL_INFO(dev);

	seq_printf(m, "gen: %d\n", info->gen);
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	seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
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#define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
#define SEP_SEMICOLON ;
	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
#undef PRINT_FLAG
#undef SEP_SEMICOLON
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	return 0;
}
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static const char *get_pin_flag(struct drm_i915_gem_object *obj)
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{
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	if (obj->user_pin_count > 0)
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		return "P";
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	else if (i915_gem_obj_is_pinned(obj))
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		return "p";
	else
		return " ";
}

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static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
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{
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	switch (obj->tiling_mode) {
	default:
	case I915_TILING_NONE: return " ";
	case I915_TILING_X: return "X";
	case I915_TILING_Y: return "Y";
	}
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}

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static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
{
	return obj->has_global_gtt_mapping ? "g" : " ";
}

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static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
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	struct i915_vma *vma;
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	int pin_count = 0;

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	seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
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		   &obj->base,
		   get_pin_flag(obj),
		   get_tiling_flag(obj),
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		   get_global_flag(obj),
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		   obj->base.size / 1024,
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		   obj->base.read_domains,
		   obj->base.write_domain,
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		   obj->last_read_seqno,
		   obj->last_write_seqno,
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		   obj->last_fenced_seqno,
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		   i915_cache_level_str(obj->cache_level),
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		   obj->dirty ? " dirty" : "",
		   obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
	if (obj->base.name)
		seq_printf(m, " (name: %d)", obj->base.name);
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	list_for_each_entry(vma, &obj->vma_list, vma_link)
		if (vma->pin_count > 0)
			pin_count++;
		seq_printf(m, " (pinned x %d)", pin_count);
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	if (obj->pin_display)
		seq_printf(m, " (display)");
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	if (obj->fence_reg != I915_FENCE_REG_NONE)
		seq_printf(m, " (fence: %d)", obj->fence_reg);
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	list_for_each_entry(vma, &obj->vma_list, vma_link) {
		if (!i915_is_ggtt(vma->vm))
			seq_puts(m, " (pp");
		else
			seq_puts(m, " (g");
		seq_printf(m, "gtt offset: %08lx, size: %08lx)",
			   vma->node.start, vma->node.size);
	}
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	if (obj->stolen)
		seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
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	if (obj->pin_mappable || obj->fault_mappable) {
		char s[3], *t = s;
		if (obj->pin_mappable)
			*t++ = 'p';
		if (obj->fault_mappable)
			*t++ = 'f';
		*t = '\0';
		seq_printf(m, " (%s mappable)", s);
	}
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	if (obj->ring != NULL)
		seq_printf(m, " (%s)", obj->ring->name);
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}

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static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
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{
	seq_putc(m, ctx->is_initialized ? 'I' : 'i');
	seq_putc(m, ctx->remap_slice ? 'R' : 'r');
	seq_putc(m, ' ');
}

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static int i915_gem_object_list_info(struct seq_file *m, void *data)
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{
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	struct drm_info_node *node = m->private;
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	uintptr_t list = (uintptr_t) node->info_ent->data;
	struct list_head *head;
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	struct drm_device *dev = node->minor->dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_address_space *vm = &dev_priv->gtt.base;
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	struct i915_vma *vma;
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	size_t total_obj_size, total_gtt_size;
	int count, ret;
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	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
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	/* FIXME: the user of this interface might want more than just GGTT */
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	switch (list) {
	case ACTIVE_LIST:
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		seq_puts(m, "Active:\n");
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		head = &vm->active_list;
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		break;
	case INACTIVE_LIST:
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		seq_puts(m, "Inactive:\n");
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		head = &vm->inactive_list;
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		break;
	default:
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		mutex_unlock(&dev->struct_mutex);
		return -EINVAL;
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	}

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	total_obj_size = total_gtt_size = count = 0;
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	list_for_each_entry(vma, head, mm_list) {
		seq_printf(m, "   ");
		describe_obj(m, vma->obj);
		seq_printf(m, "\n");
		total_obj_size += vma->obj->base.size;
		total_gtt_size += vma->node.size;
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		count++;
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	}
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	mutex_unlock(&dev->struct_mutex);
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	seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
		   count, total_obj_size, total_gtt_size);
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	return 0;
}

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static int obj_rank_by_stolen(void *priv,
			      struct list_head *A, struct list_head *B)
{
	struct drm_i915_gem_object *a =
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		container_of(A, struct drm_i915_gem_object, obj_exec_link);
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	struct drm_i915_gem_object *b =
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		container_of(B, struct drm_i915_gem_object, obj_exec_link);
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	return a->stolen->start - b->stolen->start;
}

static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
{
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	struct drm_info_node *node = m->private;
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	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	size_t total_obj_size, total_gtt_size;
	LIST_HEAD(stolen);
	int count, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	total_obj_size = total_gtt_size = count = 0;
	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
		if (obj->stolen == NULL)
			continue;

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		list_add(&obj->obj_exec_link, &stolen);
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		total_obj_size += obj->base.size;
		total_gtt_size += i915_gem_obj_ggtt_size(obj);
		count++;
	}
	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
		if (obj->stolen == NULL)
			continue;

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		list_add(&obj->obj_exec_link, &stolen);
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		total_obj_size += obj->base.size;
		count++;
	}
	list_sort(NULL, &stolen, obj_rank_by_stolen);
	seq_puts(m, "Stolen:\n");
	while (!list_empty(&stolen)) {
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		obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
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		seq_puts(m, "   ");
		describe_obj(m, obj);
		seq_putc(m, '\n');
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		list_del_init(&obj->obj_exec_link);
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	}
	mutex_unlock(&dev->struct_mutex);

	seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
		   count, total_obj_size, total_gtt_size);
	return 0;
}

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#define count_objects(list, member) do { \
	list_for_each_entry(obj, list, member) { \
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		size += i915_gem_obj_ggtt_size(obj); \
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		++count; \
		if (obj->map_and_fenceable) { \
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			mappable_size += i915_gem_obj_ggtt_size(obj); \
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			++mappable_count; \
		} \
	} \
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} while (0)
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struct file_stats {
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	struct drm_i915_file_private *file_priv;
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	int count;
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	size_t total, unbound;
	size_t global, shared;
	size_t active, inactive;
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};

static int per_file_stats(int id, void *ptr, void *data)
{
	struct drm_i915_gem_object *obj = ptr;
	struct file_stats *stats = data;
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	struct i915_vma *vma;
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	stats->count++;
	stats->total += obj->base.size;

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	if (obj->base.name || obj->base.dma_buf)
		stats->shared += obj->base.size;

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	if (USES_FULL_PPGTT(obj->base.dev)) {
		list_for_each_entry(vma, &obj->vma_list, vma_link) {
			struct i915_hw_ppgtt *ppgtt;

			if (!drm_mm_node_allocated(&vma->node))
				continue;

			if (i915_is_ggtt(vma->vm)) {
				stats->global += obj->base.size;
				continue;
			}

			ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
			if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
				continue;

			if (obj->ring) /* XXX per-vma statistic */
				stats->active += obj->base.size;
			else
				stats->inactive += obj->base.size;

			return 0;
		}
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	} else {
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		if (i915_gem_obj_ggtt_bound(obj)) {
			stats->global += obj->base.size;
			if (obj->ring)
				stats->active += obj->base.size;
			else
				stats->inactive += obj->base.size;
			return 0;
		}
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	}

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	if (!list_empty(&obj->global_list))
		stats->unbound += obj->base.size;

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	return 0;
}

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#define count_vmas(list, member) do { \
	list_for_each_entry(vma, list, member) { \
		size += i915_gem_obj_ggtt_size(vma->obj); \
		++count; \
		if (vma->obj->map_and_fenceable) { \
			mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
			++mappable_count; \
		} \
	} \
} while (0)

static int i915_gem_object_info(struct seq_file *m, void* data)
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{
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	struct drm_info_node *node = m->private;
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	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	u32 count, mappable_count, purgeable_count;
	size_t size, mappable_size, purgeable_size;
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	struct drm_i915_gem_object *obj;
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	struct i915_address_space *vm = &dev_priv->gtt.base;
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	struct drm_file *file;
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	struct i915_vma *vma;
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	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

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	seq_printf(m, "%u objects, %zu bytes\n",
		   dev_priv->mm.object_count,
		   dev_priv->mm.object_memory);

	size = count = mappable_size = mappable_count = 0;
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	count_objects(&dev_priv->mm.bound_list, global_list);
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	seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
		   count, mappable_count, size, mappable_size);

	size = count = mappable_size = mappable_count = 0;
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	count_vmas(&vm->active_list, mm_list);
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	seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
		   count, mappable_count, size, mappable_size);

	size = count = mappable_size = mappable_count = 0;
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	count_vmas(&vm->inactive_list, mm_list);
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	seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
		   count, mappable_count, size, mappable_size);

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	size = count = purgeable_size = purgeable_count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
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		size += obj->base.size, ++count;
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		if (obj->madv == I915_MADV_DONTNEED)
			purgeable_size += obj->base.size, ++purgeable_count;
	}
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	seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);

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	size = count = mappable_size = mappable_count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
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		if (obj->fault_mappable) {
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			size += i915_gem_obj_ggtt_size(obj);
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			++count;
		}
		if (obj->pin_mappable) {
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			mappable_size += i915_gem_obj_ggtt_size(obj);
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			++mappable_count;
		}
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		if (obj->madv == I915_MADV_DONTNEED) {
			purgeable_size += obj->base.size;
			++purgeable_count;
		}
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	}
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	seq_printf(m, "%u purgeable objects, %zu bytes\n",
		   purgeable_count, purgeable_size);
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	seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
		   mappable_count, mappable_size);
	seq_printf(m, "%u fault mappable objects, %zu bytes\n",
		   count, size);

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	seq_printf(m, "%zu [%lu] gtt total\n",
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		   dev_priv->gtt.base.total,
		   dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
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	seq_putc(m, '\n');
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	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct file_stats stats;
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		struct task_struct *task;
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		memset(&stats, 0, sizeof(stats));
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		stats.file_priv = file->driver_priv;
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		idr_for_each(&file->object_idr, per_file_stats, &stats);
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		/*
		 * Although we have a valid reference on file->pid, that does
		 * not guarantee that the task_struct who called get_pid() is
		 * still alive (e.g. get_pid(current) => fork() => exit()).
		 * Therefore, we need to protect this ->comm access using RCU.
		 */
		rcu_read_lock();
		task = pid_task(file->pid, PIDTYPE_PID);
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		seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
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			   task ? task->comm : "<unknown>",
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			   stats.count,
			   stats.total,
			   stats.active,
			   stats.inactive,
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			   stats.global,
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			   stats.shared,
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			   stats.unbound);
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		rcu_read_unlock();
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	}

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	mutex_unlock(&dev->struct_mutex);

	return 0;
}

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static int i915_gem_gtt_info(struct seq_file *m, void *data)
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{
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	struct drm_info_node *node = m->private;
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	struct drm_device *dev = node->minor->dev;
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	uintptr_t list = (uintptr_t) node->info_ent->data;
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	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj;
	size_t total_obj_size, total_gtt_size;
	int count, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	total_obj_size = total_gtt_size = count = 0;
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	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
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		if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
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			continue;

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		seq_puts(m, "   ");
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		describe_obj(m, obj);
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		seq_putc(m, '\n');
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		total_obj_size += obj->base.size;
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		total_gtt_size += i915_gem_obj_ggtt_size(obj);
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		count++;
	}

	mutex_unlock(&dev->struct_mutex);

	seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
		   count, total_obj_size, total_gtt_size);

	return 0;
}

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static int i915_gem_pageflip_info(struct seq_file *m, void *data)
{
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	struct drm_info_node *node = m->private;
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	struct drm_device *dev = node->minor->dev;
	unsigned long flags;
	struct intel_crtc *crtc;

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	for_each_intel_crtc(dev, crtc) {
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		const char pipe = pipe_name(crtc->pipe);
		const char plane = plane_name(crtc->plane);
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		struct intel_unpin_work *work;

		spin_lock_irqsave(&dev->event_lock, flags);
		work = crtc->unpin_work;
		if (work == NULL) {
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			seq_printf(m, "No flip due on pipe %c (plane %c)\n",
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				   pipe, plane);
		} else {
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			if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
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				seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
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					   pipe, plane);
			} else {
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				seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
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					   pipe, plane);
			}
			if (work->enable_stall_check)
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				seq_puts(m, "Stall check enabled, ");
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			else
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				seq_puts(m, "Stall check waiting for page flip ioctl, ");
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			seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
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			if (work->old_fb_obj) {
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				struct drm_i915_gem_object *obj = work->old_fb_obj;
				if (obj)
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					seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
						   i915_gem_obj_ggtt_offset(obj));
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			}
			if (work->pending_flip_obj) {
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				struct drm_i915_gem_object *obj = work->pending_flip_obj;
				if (obj)
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					seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
						   i915_gem_obj_ggtt_offset(obj));
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			}
		}
		spin_unlock_irqrestore(&dev->event_lock, flags);
	}

	return 0;
}

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static int i915_gem_request_info(struct seq_file *m, void *data)
{
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	struct drm_info_node *node = m->private;
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	struct drm_device *dev = node->minor->dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_engine_cs *ring;
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	struct drm_i915_gem_request *gem_request;
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	int ret, count, i;
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	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
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	count = 0;
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	for_each_ring(ring, dev_priv, i) {
		if (list_empty(&ring->request_list))
			continue;

		seq_printf(m, "%s requests:\n", ring->name);
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		list_for_each_entry(gem_request,
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				    &ring->request_list,
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				    list) {
			seq_printf(m, "    %d @ %d\n",
				   gem_request->seqno,
				   (int) (jiffies - gem_request->emitted_jiffies));
		}
		count++;
587
	}
588 589
	mutex_unlock(&dev->struct_mutex);

590
	if (count == 0)
591
		seq_puts(m, "No requests\n");
592

593 594 595
	return 0;
}

596
static void i915_ring_seqno_info(struct seq_file *m,
597
				 struct intel_engine_cs *ring)
598 599
{
	if (ring->get_seqno) {
600
		seq_printf(m, "Current sequence (%s): %u\n",
601
			   ring->name, ring->get_seqno(ring, false));
602 603 604
	}
}

605 606
static int i915_gem_seqno_info(struct seq_file *m, void *data)
{
607
	struct drm_info_node *node = m->private;
608
	struct drm_device *dev = node->minor->dev;
609
	struct drm_i915_private *dev_priv = dev->dev_private;
610
	struct intel_engine_cs *ring;
611
	int ret, i;
612 613 614 615

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
616
	intel_runtime_pm_get(dev_priv);
617

618 619
	for_each_ring(ring, dev_priv, i)
		i915_ring_seqno_info(m, ring);
620

621
	intel_runtime_pm_put(dev_priv);
622 623
	mutex_unlock(&dev->struct_mutex);

624 625 626 627 628 629
	return 0;
}


static int i915_interrupt_info(struct seq_file *m, void *data)
{
630
	struct drm_info_node *node = m->private;
631
	struct drm_device *dev = node->minor->dev;
632
	struct drm_i915_private *dev_priv = dev->dev_private;
633
	struct intel_engine_cs *ring;
634
	int ret, i, pipe;
635 636 637 638

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
639
	intel_runtime_pm_get(dev_priv);
640

641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681
	if (IS_CHERRYVIEW(dev)) {
		int i;
		seq_printf(m, "Master Interrupt Control:\t%08x\n",
			   I915_READ(GEN8_MASTER_IRQ));

		seq_printf(m, "Display IER:\t%08x\n",
			   I915_READ(VLV_IER));
		seq_printf(m, "Display IIR:\t%08x\n",
			   I915_READ(VLV_IIR));
		seq_printf(m, "Display IIR_RW:\t%08x\n",
			   I915_READ(VLV_IIR_RW));
		seq_printf(m, "Display IMR:\t%08x\n",
			   I915_READ(VLV_IMR));
		for_each_pipe(pipe)
			seq_printf(m, "Pipe %c stat:\t%08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));

		seq_printf(m, "Port hotplug:\t%08x\n",
			   I915_READ(PORT_HOTPLUG_EN));
		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
			   I915_READ(VLV_DPFLIPSTAT));
		seq_printf(m, "DPINVGTT:\t%08x\n",
			   I915_READ(DPINVGTT));

		for (i = 0; i < 4; i++) {
			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IMR(i)));
			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IIR(i)));
			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IER(i)));
		}

		seq_printf(m, "PCU interrupt mask:\t%08x\n",
			   I915_READ(GEN8_PCU_IMR));
		seq_printf(m, "PCU interrupt identity:\t%08x\n",
			   I915_READ(GEN8_PCU_IIR));
		seq_printf(m, "PCU interrupt enable:\t%08x\n",
			   I915_READ(GEN8_PCU_IER));
	} else if (INTEL_INFO(dev)->gen >= 8) {
682 683 684 685 686 687 688 689 690 691 692 693
		seq_printf(m, "Master Interrupt Control:\t%08x\n",
			   I915_READ(GEN8_MASTER_IRQ));

		for (i = 0; i < 4; i++) {
			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IMR(i)));
			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IIR(i)));
			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
				   i, I915_READ(GEN8_GT_IER(i)));
		}

694
		for_each_pipe(pipe) {
695
			seq_printf(m, "Pipe %c IMR:\t%08x\n",
696 697
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
698
			seq_printf(m, "Pipe %c IIR:\t%08x\n",
699 700
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
701
			seq_printf(m, "Pipe %c IER:\t%08x\n",
702 703
				   pipe_name(pipe),
				   I915_READ(GEN8_DE_PIPE_IER(pipe)));
704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726
		}

		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IMR));
		seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IIR));
		seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
			   I915_READ(GEN8_DE_PORT_IER));

		seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IMR));
		seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IIR));
		seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
			   I915_READ(GEN8_DE_MISC_IER));

		seq_printf(m, "PCU interrupt mask:\t%08x\n",
			   I915_READ(GEN8_PCU_IMR));
		seq_printf(m, "PCU interrupt identity:\t%08x\n",
			   I915_READ(GEN8_PCU_IIR));
		seq_printf(m, "PCU interrupt enable:\t%08x\n",
			   I915_READ(GEN8_PCU_IER));
	} else if (IS_VALLEYVIEW(dev)) {
727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764
		seq_printf(m, "Display IER:\t%08x\n",
			   I915_READ(VLV_IER));
		seq_printf(m, "Display IIR:\t%08x\n",
			   I915_READ(VLV_IIR));
		seq_printf(m, "Display IIR_RW:\t%08x\n",
			   I915_READ(VLV_IIR_RW));
		seq_printf(m, "Display IMR:\t%08x\n",
			   I915_READ(VLV_IMR));
		for_each_pipe(pipe)
			seq_printf(m, "Pipe %c stat:\t%08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));

		seq_printf(m, "Master IER:\t%08x\n",
			   I915_READ(VLV_MASTER_IER));

		seq_printf(m, "Render IER:\t%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Render IIR:\t%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Render IMR:\t%08x\n",
			   I915_READ(GTIMR));

		seq_printf(m, "PM IER:\t\t%08x\n",
			   I915_READ(GEN6_PMIER));
		seq_printf(m, "PM IIR:\t\t%08x\n",
			   I915_READ(GEN6_PMIIR));
		seq_printf(m, "PM IMR:\t\t%08x\n",
			   I915_READ(GEN6_PMIMR));

		seq_printf(m, "Port hotplug:\t%08x\n",
			   I915_READ(PORT_HOTPLUG_EN));
		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
			   I915_READ(VLV_DPFLIPSTAT));
		seq_printf(m, "DPINVGTT:\t%08x\n",
			   I915_READ(DPINVGTT));

	} else if (!HAS_PCH_SPLIT(dev)) {
765 766 767 768 769 770
		seq_printf(m, "Interrupt enable:    %08x\n",
			   I915_READ(IER));
		seq_printf(m, "Interrupt identity:  %08x\n",
			   I915_READ(IIR));
		seq_printf(m, "Interrupt mask:      %08x\n",
			   I915_READ(IMR));
771 772 773 774
		for_each_pipe(pipe)
			seq_printf(m, "Pipe %c stat:         %08x\n",
				   pipe_name(pipe),
				   I915_READ(PIPESTAT(pipe)));
775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794
	} else {
		seq_printf(m, "North Display Interrupt enable:		%08x\n",
			   I915_READ(DEIER));
		seq_printf(m, "North Display Interrupt identity:	%08x\n",
			   I915_READ(DEIIR));
		seq_printf(m, "North Display Interrupt mask:		%08x\n",
			   I915_READ(DEIMR));
		seq_printf(m, "South Display Interrupt enable:		%08x\n",
			   I915_READ(SDEIER));
		seq_printf(m, "South Display Interrupt identity:	%08x\n",
			   I915_READ(SDEIIR));
		seq_printf(m, "South Display Interrupt mask:		%08x\n",
			   I915_READ(SDEIMR));
		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
			   I915_READ(GTIER));
		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
			   I915_READ(GTIIR));
		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
			   I915_READ(GTIMR));
	}
795
	for_each_ring(ring, dev_priv, i) {
796
		if (INTEL_INFO(dev)->gen >= 6) {
797 798 799
			seq_printf(m,
				   "Graphics Interrupt mask (%s):	%08x\n",
				   ring->name, I915_READ_IMR(ring));
800
		}
801
		i915_ring_seqno_info(m, ring);
802
	}
803
	intel_runtime_pm_put(dev_priv);
804 805
	mutex_unlock(&dev->struct_mutex);

806 807 808
	return 0;
}

809 810
static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
{
811
	struct drm_info_node *node = m->private;
812
	struct drm_device *dev = node->minor->dev;
813
	struct drm_i915_private *dev_priv = dev->dev_private;
814 815 816 817 818
	int i, ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
819 820 821 822

	seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
	for (i = 0; i < dev_priv->num_fence_regs; i++) {
823
		struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
824

825 826
		seq_printf(m, "Fence %d, pin count = %d, object = ",
			   i, dev_priv->fence_regs[i].pin_count);
827
		if (obj == NULL)
828
			seq_puts(m, "unused");
829
		else
830
			describe_obj(m, obj);
831
		seq_putc(m, '\n');
832 833
	}

834
	mutex_unlock(&dev->struct_mutex);
835 836 837
	return 0;
}

838 839
static int i915_hws_info(struct seq_file *m, void *data)
{
840
	struct drm_info_node *node = m->private;
841
	struct drm_device *dev = node->minor->dev;
842
	struct drm_i915_private *dev_priv = dev->dev_private;
843
	struct intel_engine_cs *ring;
844
	const u32 *hws;
845 846
	int i;

847
	ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
848
	hws = ring->status_page.page_addr;
849 850 851 852 853 854 855 856 857 858 859
	if (hws == NULL)
		return 0;

	for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
		seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
			   i * 4,
			   hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
	}
	return 0;
}

860 861 862 863 864 865
static ssize_t
i915_error_state_write(struct file *filp,
		       const char __user *ubuf,
		       size_t cnt,
		       loff_t *ppos)
{
866
	struct i915_error_state_file_priv *error_priv = filp->private_data;
867
	struct drm_device *dev = error_priv->dev;
868
	int ret;
869 870 871

	DRM_DEBUG_DRIVER("Resetting error state\n");

872 873 874 875
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892
	i915_destroy_error_state(dev);
	mutex_unlock(&dev->struct_mutex);

	return cnt;
}

static int i915_error_state_open(struct inode *inode, struct file *file)
{
	struct drm_device *dev = inode->i_private;
	struct i915_error_state_file_priv *error_priv;

	error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
	if (!error_priv)
		return -ENOMEM;

	error_priv->dev = dev;

893
	i915_error_state_get(dev, error_priv);
894

895 896 897
	file->private_data = error_priv;

	return 0;
898 899 900 901
}

static int i915_error_state_release(struct inode *inode, struct file *file)
{
902
	struct i915_error_state_file_priv *error_priv = file->private_data;
903

904
	i915_error_state_put(error_priv);
905 906
	kfree(error_priv);

907 908 909
	return 0;
}

910 911 912 913 914 915 916 917 918 919 920 921
static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
				     size_t count, loff_t *pos)
{
	struct i915_error_state_file_priv *error_priv = file->private_data;
	struct drm_i915_error_state_buf error_str;
	loff_t tmp_pos = 0;
	ssize_t ret_count = 0;
	int ret;

	ret = i915_error_state_buf_init(&error_str, count, *pos);
	if (ret)
		return ret;
922

923
	ret = i915_error_state_to_str(&error_str, error_priv);
924 925 926 927 928 929 930 931 932 933 934 935
	if (ret)
		goto out;

	ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
					    error_str.buf,
					    error_str.bytes);

	if (ret_count < 0)
		ret = ret_count;
	else
		*pos = error_str.start + ret_count;
out:
936
	i915_error_state_buf_release(&error_str);
937
	return ret ?: ret_count;
938 939 940 941 942
}

static const struct file_operations i915_error_state_fops = {
	.owner = THIS_MODULE,
	.open = i915_error_state_open,
943
	.read = i915_error_state_read,
944 945 946 947 948
	.write = i915_error_state_write,
	.llseek = default_llseek,
	.release = i915_error_state_release,
};

949 950
static int
i915_next_seqno_get(void *data, u64 *val)
951
{
952
	struct drm_device *dev = data;
953
	struct drm_i915_private *dev_priv = dev->dev_private;
954 955 956 957 958 959
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

960
	*val = dev_priv->next_seqno;
961 962
	mutex_unlock(&dev->struct_mutex);

963
	return 0;
964 965
}

966 967 968 969
static int
i915_next_seqno_set(void *data, u64 val)
{
	struct drm_device *dev = data;
970 971 972 973 974 975
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

976
	ret = i915_gem_set_seqno(dev, val);
977 978
	mutex_unlock(&dev->struct_mutex);

979
	return ret;
980 981
}

982 983
DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
			i915_next_seqno_get, i915_next_seqno_set,
984
			"0x%llx\n");
985

986 987
static int i915_rstdby_delays(struct seq_file *m, void *unused)
{
988
	struct drm_info_node *node = m->private;
989
	struct drm_device *dev = node->minor->dev;
990
	struct drm_i915_private *dev_priv = dev->dev_private;
991 992 993 994 995 996
	u16 crstanddelay;
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
997
	intel_runtime_pm_get(dev_priv);
998 999 1000

	crstanddelay = I915_READ16(CRSTANDVID);

1001
	intel_runtime_pm_put(dev_priv);
1002
	mutex_unlock(&dev->struct_mutex);
1003 1004 1005 1006 1007 1008

	seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));

	return 0;
}

1009
static int i915_frequency_info(struct seq_file *m, void *unused)
1010
{
1011
	struct drm_info_node *node = m->private;
1012
	struct drm_device *dev = node->minor->dev;
1013
	struct drm_i915_private *dev_priv = dev->dev_private;
1014 1015 1016
	int ret = 0;

	intel_runtime_pm_get(dev_priv);
1017

1018 1019
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

1020 1021 1022 1023 1024 1025 1026 1027 1028 1029
	if (IS_GEN5(dev)) {
		u16 rgvswctl = I915_READ16(MEMSWCTL);
		u16 rgvstat = I915_READ16(MEMSTAT_ILK);

		seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
		seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
		seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
			   MEMSTAT_VID_SHIFT);
		seq_printf(m, "Current P-state: %d\n",
			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1030 1031
	} else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
		   IS_BROADWELL(dev)) {
1032 1033 1034
		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1035
		u32 rpmodectl, rpinclimit, rpdeclimit;
1036
		u32 rpstat, cagf, reqf;
1037 1038
		u32 rpupei, rpcurup, rpprevup;
		u32 rpdownei, rpcurdown, rpprevdown;
1039 1040 1041
		int max_freq;

		/* RPSTAT1 is in the GT power well */
1042 1043
		ret = mutex_lock_interruptible(&dev->struct_mutex);
		if (ret)
1044
			goto out;
1045

1046
		gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1047

1048 1049
		reqf = I915_READ(GEN6_RPNSWREQ);
		reqf &= ~GEN6_TURBO_DISABLE;
1050
		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1051 1052 1053 1054 1055
			reqf >>= 24;
		else
			reqf >>= 25;
		reqf *= GT_FREQUENCY_MULTIPLIER;

1056 1057 1058 1059
		rpmodectl = I915_READ(GEN6_RP_CONTROL);
		rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
		rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);

1060 1061 1062 1063 1064 1065 1066
		rpstat = I915_READ(GEN6_RPSTAT1);
		rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
		rpcurup = I915_READ(GEN6_RP_CUR_UP);
		rpprevup = I915_READ(GEN6_RP_PREV_UP);
		rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
		rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
		rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1067
		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
B
Ben Widawsky 已提交
1068 1069 1070 1071
			cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
		else
			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
		cagf *= GT_FREQUENCY_MULTIPLIER;
1072

1073
		gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1074 1075
		mutex_unlock(&dev->struct_mutex);

1076 1077 1078 1079 1080 1081
		seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
			   I915_READ(GEN6_PMIER),
			   I915_READ(GEN6_PMIMR),
			   I915_READ(GEN6_PMISR),
			   I915_READ(GEN6_PMIIR),
			   I915_READ(GEN6_PMINTRMSK));
1082 1083 1084 1085 1086 1087 1088
		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
		seq_printf(m, "Render p-state ratio: %d\n",
			   (gt_perf_status & 0xff00) >> 8);
		seq_printf(m, "Render p-state VID: %d\n",
			   gt_perf_status & 0xff);
		seq_printf(m, "Render p-state limit: %d\n",
			   rp_state_limits & 0xff);
1089 1090 1091 1092
		seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
		seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
		seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
		seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1093
		seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
B
Ben Widawsky 已提交
1094
		seq_printf(m, "CAGF: %dMHz\n", cagf);
1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106
		seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
			   GEN6_CURICONT_MASK);
		seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
			   GEN6_CURBSYTAVG_MASK);
		seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
			   GEN6_CURBSYTAVG_MASK);
		seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
			   GEN6_CURIAVG_MASK);
		seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
			   GEN6_CURBSYTAVG_MASK);
		seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
			   GEN6_CURBSYTAVG_MASK);
1107 1108 1109

		max_freq = (rp_state_cap & 0xff0000) >> 16;
		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1110
			   max_freq * GT_FREQUENCY_MULTIPLIER);
1111 1112 1113

		max_freq = (rp_state_cap & 0xff00) >> 8;
		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1114
			   max_freq * GT_FREQUENCY_MULTIPLIER);
1115 1116 1117

		max_freq = rp_state_cap & 0xff;
		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1118
			   max_freq * GT_FREQUENCY_MULTIPLIER);
1119 1120

		seq_printf(m, "Max overclocked frequency: %dMHz\n",
1121
			   dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1122 1123 1124
	} else if (IS_VALLEYVIEW(dev)) {
		u32 freq_sts, val;

1125
		mutex_lock(&dev_priv->rps.hw_lock);
1126
		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1127 1128 1129
		seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);

1130
		val = valleyview_rps_max_freq(dev_priv);
1131
		seq_printf(m, "max GPU freq: %d MHz\n",
1132
			   vlv_gpu_freq(dev_priv, val));
1133

1134
		val = valleyview_rps_min_freq(dev_priv);
1135
		seq_printf(m, "min GPU freq: %d MHz\n",
1136
			   vlv_gpu_freq(dev_priv, val));
1137 1138

		seq_printf(m, "current GPU freq: %d MHz\n",
1139
			   vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1140
		mutex_unlock(&dev_priv->rps.hw_lock);
1141
	} else {
1142
		seq_puts(m, "no P-state info available\n");
1143
	}
1144

1145 1146 1147
out:
	intel_runtime_pm_put(dev_priv);
	return ret;
1148 1149 1150 1151
}

static int i915_delayfreq_table(struct seq_file *m, void *unused)
{
1152
	struct drm_info_node *node = m->private;
1153
	struct drm_device *dev = node->minor->dev;
1154
	struct drm_i915_private *dev_priv = dev->dev_private;
1155
	u32 delayfreq;
1156 1157 1158 1159 1160
	int ret, i;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1161
	intel_runtime_pm_get(dev_priv);
1162 1163 1164

	for (i = 0; i < 16; i++) {
		delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1165 1166
		seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
			   (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1167 1168
	}

1169 1170
	intel_runtime_pm_put(dev_priv);

1171 1172
	mutex_unlock(&dev->struct_mutex);

1173 1174 1175 1176 1177 1178 1179 1180 1181 1182
	return 0;
}

static inline int MAP_TO_MV(int map)
{
	return 1250 - (map * 25);
}

static int i915_inttoext_table(struct seq_file *m, void *unused)
{
1183
	struct drm_info_node *node = m->private;
1184
	struct drm_device *dev = node->minor->dev;
1185
	struct drm_i915_private *dev_priv = dev->dev_private;
1186
	u32 inttoext;
1187 1188 1189 1190 1191
	int ret, i;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1192
	intel_runtime_pm_get(dev_priv);
1193 1194 1195 1196 1197 1198

	for (i = 1; i <= 32; i++) {
		inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
		seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
	}

1199
	intel_runtime_pm_put(dev_priv);
1200 1201
	mutex_unlock(&dev->struct_mutex);

1202 1203 1204
	return 0;
}

1205
static int ironlake_drpc_info(struct seq_file *m)
1206
{
1207
	struct drm_info_node *node = m->private;
1208
	struct drm_device *dev = node->minor->dev;
1209
	struct drm_i915_private *dev_priv = dev->dev_private;
1210 1211 1212 1213 1214 1215 1216
	u32 rgvmodectl, rstdbyctl;
	u16 crstandvid;
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1217
	intel_runtime_pm_get(dev_priv);
1218 1219 1220 1221 1222

	rgvmodectl = I915_READ(MEMMODECTL);
	rstdbyctl = I915_READ(RSTDBYCTL);
	crstandvid = I915_READ16(CRSTANDVID);

1223
	intel_runtime_pm_put(dev_priv);
1224
	mutex_unlock(&dev->struct_mutex);
1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238

	seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
		   "yes" : "no");
	seq_printf(m, "Boost freq: %d\n",
		   (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
		   MEMMODE_BOOST_FREQ_SHIFT);
	seq_printf(m, "HW control enabled: %s\n",
		   rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
	seq_printf(m, "SW control enabled: %s\n",
		   rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
	seq_printf(m, "Gated voltage change: %s\n",
		   rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
	seq_printf(m, "Starting frequency: P%d\n",
		   (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1239
	seq_printf(m, "Max P-state: P%d\n",
1240
		   (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1241 1242 1243 1244 1245
	seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
	seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
	seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
	seq_printf(m, "Render standby enabled: %s\n",
		   (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1246
	seq_puts(m, "Current RS state: ");
1247 1248
	switch (rstdbyctl & RSX_STATUS_MASK) {
	case RSX_STATUS_ON:
1249
		seq_puts(m, "on\n");
1250 1251
		break;
	case RSX_STATUS_RC1:
1252
		seq_puts(m, "RC1\n");
1253 1254
		break;
	case RSX_STATUS_RC1E:
1255
		seq_puts(m, "RC1E\n");
1256 1257
		break;
	case RSX_STATUS_RS1:
1258
		seq_puts(m, "RS1\n");
1259 1260
		break;
	case RSX_STATUS_RS2:
1261
		seq_puts(m, "RS2 (RC6)\n");
1262 1263
		break;
	case RSX_STATUS_RS3:
1264
		seq_puts(m, "RC3 (RC6+)\n");
1265 1266
		break;
	default:
1267
		seq_puts(m, "unknown\n");
1268 1269
		break;
	}
1270 1271 1272 1273

	return 0;
}

1274 1275 1276
static int vlv_drpc_info(struct seq_file *m)
{

1277
	struct drm_info_node *node = m->private;
1278 1279 1280 1281 1282
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 rpmodectl1, rcctl1;
	unsigned fw_rendercount = 0, fw_mediacount = 0;

1283 1284
	intel_runtime_pm_get(dev_priv);

1285 1286 1287
	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
	rcctl1 = I915_READ(GEN6_RC_CONTROL);

1288 1289
	intel_runtime_pm_put(dev_priv);

1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308
	seq_printf(m, "Video Turbo Mode: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
	seq_printf(m, "Turbo enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "HW control enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "SW control enabled: %s\n",
		   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
			  GEN6_RP_MEDIA_SW_MODE));
	seq_printf(m, "RC6 Enabled: %s\n",
		   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
					GEN6_RC_CTL_EI_MODE(1))));
	seq_printf(m, "Render Power Well: %s\n",
			(I915_READ(VLV_GTLC_PW_STATUS) &
				VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
	seq_printf(m, "Media Power Well: %s\n",
			(I915_READ(VLV_GTLC_PW_STATUS) &
				VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");

1309 1310 1311 1312 1313
	seq_printf(m, "Render RC6 residency since boot: %u\n",
		   I915_READ(VLV_GT_RENDER_RC6));
	seq_printf(m, "Media RC6 residency since boot: %u\n",
		   I915_READ(VLV_GT_MEDIA_RC6));

1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326
	spin_lock_irq(&dev_priv->uncore.lock);
	fw_rendercount = dev_priv->uncore.fw_rendercount;
	fw_mediacount = dev_priv->uncore.fw_mediacount;
	spin_unlock_irq(&dev_priv->uncore.lock);

	seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
	seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);


	return 0;
}


1327 1328 1329
static int gen6_drpc_info(struct seq_file *m)
{

1330
	struct drm_info_node *node = m->private;
1331 1332
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1333
	u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1334
	unsigned forcewake_count;
1335
	int count = 0, ret;
1336 1337 1338 1339

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1340
	intel_runtime_pm_get(dev_priv);
1341

1342 1343 1344
	spin_lock_irq(&dev_priv->uncore.lock);
	forcewake_count = dev_priv->uncore.forcewake_count;
	spin_unlock_irq(&dev_priv->uncore.lock);
1345 1346

	if (forcewake_count) {
1347 1348
		seq_puts(m, "RC information inaccurate because somebody "
			    "holds a forcewake reference \n");
1349 1350 1351 1352 1353 1354 1355 1356
	} else {
		/* NB: we cannot use forcewake, else we read the wrong values */
		while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
			udelay(10);
		seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
	}

	gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1357
	trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1358 1359 1360 1361

	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
	rcctl1 = I915_READ(GEN6_RC_CONTROL);
	mutex_unlock(&dev->struct_mutex);
1362 1363 1364
	mutex_lock(&dev_priv->rps.hw_lock);
	sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
	mutex_unlock(&dev_priv->rps.hw_lock);
1365

1366 1367
	intel_runtime_pm_put(dev_priv);

1368 1369 1370 1371 1372 1373 1374
	seq_printf(m, "Video Turbo Mode: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
	seq_printf(m, "HW control enabled: %s\n",
		   yesno(rpmodectl1 & GEN6_RP_ENABLE));
	seq_printf(m, "SW control enabled: %s\n",
		   yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
			  GEN6_RP_MEDIA_SW_MODE));
1375
	seq_printf(m, "RC1e Enabled: %s\n",
1376 1377 1378 1379 1380 1381 1382
		   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
	seq_printf(m, "RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
	seq_printf(m, "Deep RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
	seq_printf(m, "Deepest RC6 Enabled: %s\n",
		   yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1383
	seq_puts(m, "Current RC state: ");
1384 1385 1386
	switch (gt_core_status & GEN6_RCn_MASK) {
	case GEN6_RC0:
		if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1387
			seq_puts(m, "Core Power Down\n");
1388
		else
1389
			seq_puts(m, "on\n");
1390 1391
		break;
	case GEN6_RC3:
1392
		seq_puts(m, "RC3\n");
1393 1394
		break;
	case GEN6_RC6:
1395
		seq_puts(m, "RC6\n");
1396 1397
		break;
	case GEN6_RC7:
1398
		seq_puts(m, "RC7\n");
1399 1400
		break;
	default:
1401
		seq_puts(m, "Unknown\n");
1402 1403 1404 1405 1406
		break;
	}

	seq_printf(m, "Core Power Down: %s\n",
		   yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417

	/* Not exactly sure what this is */
	seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6_LOCKED));
	seq_printf(m, "RC6 residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6));
	seq_printf(m, "RC6+ residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6p));
	seq_printf(m, "RC6++ residency since boot: %u\n",
		   I915_READ(GEN6_GT_GFX_RC6pp));

1418 1419 1420 1421 1422 1423
	seq_printf(m, "RC6   voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
	seq_printf(m, "RC6+  voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
	seq_printf(m, "RC6++ voltage: %dmV\n",
		   GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1424 1425 1426 1427 1428
	return 0;
}

static int i915_drpc_info(struct seq_file *m, void *unused)
{
1429
	struct drm_info_node *node = m->private;
1430 1431
	struct drm_device *dev = node->minor->dev;

1432 1433 1434
	if (IS_VALLEYVIEW(dev))
		return vlv_drpc_info(m);
	else if (IS_GEN6(dev) || IS_GEN7(dev))
1435 1436 1437 1438 1439
		return gen6_drpc_info(m);
	else
		return ironlake_drpc_info(m);
}

1440 1441
static int i915_fbc_status(struct seq_file *m, void *unused)
{
1442
	struct drm_info_node *node = m->private;
1443
	struct drm_device *dev = node->minor->dev;
1444
	struct drm_i915_private *dev_priv = dev->dev_private;
1445

1446
	if (!HAS_FBC(dev)) {
1447
		seq_puts(m, "FBC unsupported on this chipset\n");
1448 1449 1450
		return 0;
	}

1451 1452
	intel_runtime_pm_get(dev_priv);

1453
	if (intel_fbc_enabled(dev)) {
1454
		seq_puts(m, "FBC enabled\n");
1455
	} else {
1456
		seq_puts(m, "FBC disabled: ");
1457
		switch (dev_priv->fbc.no_fbc_reason) {
1458 1459 1460 1461 1462 1463
		case FBC_OK:
			seq_puts(m, "FBC actived, but currently disabled in hardware");
			break;
		case FBC_UNSUPPORTED:
			seq_puts(m, "unsupported by this chipset");
			break;
C
Chris Wilson 已提交
1464
		case FBC_NO_OUTPUT:
1465
			seq_puts(m, "no outputs");
C
Chris Wilson 已提交
1466
			break;
1467
		case FBC_STOLEN_TOO_SMALL:
1468
			seq_puts(m, "not enough stolen memory");
1469 1470
			break;
		case FBC_UNSUPPORTED_MODE:
1471
			seq_puts(m, "mode not supported");
1472 1473
			break;
		case FBC_MODE_TOO_LARGE:
1474
			seq_puts(m, "mode too large");
1475 1476
			break;
		case FBC_BAD_PLANE:
1477
			seq_puts(m, "FBC unsupported on plane");
1478 1479
			break;
		case FBC_NOT_TILED:
1480
			seq_puts(m, "scanout buffer not tiled");
1481
			break;
1482
		case FBC_MULTIPLE_PIPES:
1483
			seq_puts(m, "multiple pipes are enabled");
1484
			break;
1485
		case FBC_MODULE_PARAM:
1486
			seq_puts(m, "disabled per module param (default off)");
1487
			break;
1488
		case FBC_CHIP_DEFAULT:
1489
			seq_puts(m, "disabled per chip default");
1490
			break;
1491
		default:
1492
			seq_puts(m, "unknown reason");
1493
		}
1494
		seq_putc(m, '\n');
1495
	}
1496 1497 1498

	intel_runtime_pm_put(dev_priv);

1499 1500 1501
	return 0;
}

1502 1503
static int i915_ips_status(struct seq_file *m, void *unused)
{
1504
	struct drm_info_node *node = m->private;
1505 1506 1507
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

1508
	if (!HAS_IPS(dev)) {
1509 1510 1511 1512
		seq_puts(m, "not supported\n");
		return 0;
	}

1513 1514
	intel_runtime_pm_get(dev_priv);

1515
	if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
1516 1517 1518 1519
		seq_puts(m, "enabled\n");
	else
		seq_puts(m, "disabled\n");

1520 1521
	intel_runtime_pm_put(dev_priv);

1522 1523 1524
	return 0;
}

1525 1526
static int i915_sr_status(struct seq_file *m, void *unused)
{
1527
	struct drm_info_node *node = m->private;
1528
	struct drm_device *dev = node->minor->dev;
1529
	struct drm_i915_private *dev_priv = dev->dev_private;
1530 1531
	bool sr_enabled = false;

1532 1533
	intel_runtime_pm_get(dev_priv);

1534
	if (HAS_PCH_SPLIT(dev))
1535
		sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1536
	else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1537 1538 1539 1540 1541 1542
		sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
	else if (IS_I915GM(dev))
		sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
	else if (IS_PINEVIEW(dev))
		sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;

1543 1544
	intel_runtime_pm_put(dev_priv);

1545 1546
	seq_printf(m, "self-refresh: %s\n",
		   sr_enabled ? "enabled" : "disabled");
1547 1548 1549 1550

	return 0;
}

1551 1552
static int i915_emon_status(struct seq_file *m, void *unused)
{
1553
	struct drm_info_node *node = m->private;
1554
	struct drm_device *dev = node->minor->dev;
1555
	struct drm_i915_private *dev_priv = dev->dev_private;
1556
	unsigned long temp, chipset, gfx;
1557 1558
	int ret;

1559 1560 1561
	if (!IS_GEN5(dev))
		return -ENODEV;

1562 1563 1564
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1565 1566 1567 1568

	temp = i915_mch_val(dev_priv);
	chipset = i915_chipset_val(dev_priv);
	gfx = i915_gfx_val(dev_priv);
1569
	mutex_unlock(&dev->struct_mutex);
1570 1571 1572 1573 1574 1575 1576 1577 1578

	seq_printf(m, "GMCH temp: %ld\n", temp);
	seq_printf(m, "Chipset power: %ld\n", chipset);
	seq_printf(m, "GFX power: %ld\n", gfx);
	seq_printf(m, "Total power: %ld\n", chipset + gfx);

	return 0;
}

1579 1580
static int i915_ring_freq_table(struct seq_file *m, void *unused)
{
1581
	struct drm_info_node *node = m->private;
1582
	struct drm_device *dev = node->minor->dev;
1583
	struct drm_i915_private *dev_priv = dev->dev_private;
1584
	int ret = 0;
1585 1586
	int gpu_freq, ia_freq;

1587
	if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1588
		seq_puts(m, "unsupported on this chipset\n");
1589 1590 1591
		return 0;
	}

1592 1593
	intel_runtime_pm_get(dev_priv);

1594 1595
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

1596
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1597
	if (ret)
1598
		goto out;
1599

1600
	seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1601

1602 1603
	for (gpu_freq = dev_priv->rps.min_freq_softlimit;
	     gpu_freq <= dev_priv->rps.max_freq_softlimit;
1604
	     gpu_freq++) {
1605 1606 1607 1608
		ia_freq = gpu_freq;
		sandybridge_pcode_read(dev_priv,
				       GEN6_PCODE_READ_MIN_FREQ_TABLE,
				       &ia_freq);
1609 1610 1611 1612
		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
			   gpu_freq * GT_FREQUENCY_MULTIPLIER,
			   ((ia_freq >> 0) & 0xff) * 100,
			   ((ia_freq >> 8) & 0xff) * 100);
1613 1614
	}

1615
	mutex_unlock(&dev_priv->rps.hw_lock);
1616

1617 1618 1619
out:
	intel_runtime_pm_put(dev_priv);
	return ret;
1620 1621
}

1622 1623
static int i915_gfxec(struct seq_file *m, void *unused)
{
1624
	struct drm_info_node *node = m->private;
1625
	struct drm_device *dev = node->minor->dev;
1626
	struct drm_i915_private *dev_priv = dev->dev_private;
1627 1628 1629 1630 1631
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1632
	intel_runtime_pm_get(dev_priv);
1633 1634

	seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1635
	intel_runtime_pm_put(dev_priv);
1636

1637 1638
	mutex_unlock(&dev->struct_mutex);

1639 1640 1641
	return 0;
}

1642 1643
static int i915_opregion(struct seq_file *m, void *unused)
{
1644
	struct drm_info_node *node = m->private;
1645
	struct drm_device *dev = node->minor->dev;
1646
	struct drm_i915_private *dev_priv = dev->dev_private;
1647
	struct intel_opregion *opregion = &dev_priv->opregion;
1648
	void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1649 1650
	int ret;

1651 1652 1653
	if (data == NULL)
		return -ENOMEM;

1654 1655
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
1656
		goto out;
1657

1658 1659 1660 1661
	if (opregion->header) {
		memcpy_fromio(data, opregion->header, OPREGION_SIZE);
		seq_write(m, data, OPREGION_SIZE);
	}
1662 1663 1664

	mutex_unlock(&dev->struct_mutex);

1665 1666
out:
	kfree(data);
1667 1668 1669
	return 0;
}

1670 1671
static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
{
1672
	struct drm_info_node *node = m->private;
1673
	struct drm_device *dev = node->minor->dev;
1674
	struct intel_fbdev *ifbdev = NULL;
1675 1676
	struct intel_framebuffer *fb;

1677 1678
#ifdef CONFIG_DRM_I915_FBDEV
	struct drm_i915_private *dev_priv = dev->dev_private;
1679 1680 1681 1682

	ifbdev = dev_priv->fbdev;
	fb = to_intel_framebuffer(ifbdev->helper.fb);

1683
	seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1684 1685 1686
		   fb->base.width,
		   fb->base.height,
		   fb->base.depth,
1687 1688
		   fb->base.bits_per_pixel,
		   atomic_read(&fb->base.refcount.refcount));
1689
	describe_obj(m, fb->obj);
1690
	seq_putc(m, '\n');
1691
#endif
1692

1693
	mutex_lock(&dev->mode_config.fb_lock);
1694
	list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1695
		if (ifbdev && &fb->base == ifbdev->helper.fb)
1696 1697
			continue;

1698
		seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1699 1700 1701
			   fb->base.width,
			   fb->base.height,
			   fb->base.depth,
1702 1703
			   fb->base.bits_per_pixel,
			   atomic_read(&fb->base.refcount.refcount));
1704
		describe_obj(m, fb->obj);
1705
		seq_putc(m, '\n');
1706
	}
1707
	mutex_unlock(&dev->mode_config.fb_lock);
1708 1709 1710 1711

	return 0;
}

1712 1713
static int i915_context_status(struct seq_file *m, void *unused)
{
1714
	struct drm_info_node *node = m->private;
1715
	struct drm_device *dev = node->minor->dev;
1716
	struct drm_i915_private *dev_priv = dev->dev_private;
1717
	struct intel_engine_cs *ring;
1718
	struct intel_context *ctx;
1719
	int ret, i;
1720

1721
	ret = mutex_lock_interruptible(&dev->struct_mutex);
1722 1723 1724
	if (ret)
		return ret;

1725
	if (dev_priv->ips.pwrctx) {
1726
		seq_puts(m, "power context ");
1727
		describe_obj(m, dev_priv->ips.pwrctx);
1728
		seq_putc(m, '\n');
1729
	}
1730

1731
	if (dev_priv->ips.renderctx) {
1732
		seq_puts(m, "render context ");
1733
		describe_obj(m, dev_priv->ips.renderctx);
1734
		seq_putc(m, '\n');
1735
	}
1736

1737
	list_for_each_entry(ctx, &dev_priv->context_list, link) {
1738 1739 1740
		if (ctx->obj == NULL)
			continue;

1741
		seq_puts(m, "HW context ");
1742
		describe_ctx(m, ctx);
1743 1744 1745 1746 1747 1748
		for_each_ring(ring, dev_priv, i)
			if (ring->default_context == ctx)
				seq_printf(m, "(default context %s) ", ring->name);

		describe_obj(m, ctx->obj);
		seq_putc(m, '\n');
1749 1750
	}

1751
	mutex_unlock(&dev->struct_mutex);
1752 1753 1754 1755

	return 0;
}

1756 1757
static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
{
1758
	struct drm_info_node *node = m->private;
1759 1760
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1761
	unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1762

1763
	spin_lock_irq(&dev_priv->uncore.lock);
1764 1765 1766 1767 1768
	if (IS_VALLEYVIEW(dev)) {
		fw_rendercount = dev_priv->uncore.fw_rendercount;
		fw_mediacount = dev_priv->uncore.fw_mediacount;
	} else
		forcewake_count = dev_priv->uncore.forcewake_count;
1769
	spin_unlock_irq(&dev_priv->uncore.lock);
1770

1771 1772 1773 1774 1775
	if (IS_VALLEYVIEW(dev)) {
		seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
		seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
	} else
		seq_printf(m, "forcewake count = %u\n", forcewake_count);
1776 1777 1778 1779

	return 0;
}

1780 1781
static const char *swizzle_string(unsigned swizzle)
{
1782
	switch (swizzle) {
1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797
	case I915_BIT_6_SWIZZLE_NONE:
		return "none";
	case I915_BIT_6_SWIZZLE_9:
		return "bit9";
	case I915_BIT_6_SWIZZLE_9_10:
		return "bit9/bit10";
	case I915_BIT_6_SWIZZLE_9_11:
		return "bit9/bit11";
	case I915_BIT_6_SWIZZLE_9_10_11:
		return "bit9/bit10/bit11";
	case I915_BIT_6_SWIZZLE_9_17:
		return "bit9/bit17";
	case I915_BIT_6_SWIZZLE_9_10_17:
		return "bit9/bit10/bit17";
	case I915_BIT_6_SWIZZLE_UNKNOWN:
1798
		return "unknown";
1799 1800 1801 1802 1803 1804 1805
	}

	return "bug";
}

static int i915_swizzle_info(struct seq_file *m, void *data)
{
1806
	struct drm_info_node *node = m->private;
1807 1808
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1809 1810 1811 1812 1813
	int ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1814
	intel_runtime_pm_get(dev_priv);
1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827

	seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
		   swizzle_string(dev_priv->mm.bit_6_swizzle_x));
	seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));

	if (IS_GEN3(dev) || IS_GEN4(dev)) {
		seq_printf(m, "DDC = 0x%08x\n",
			   I915_READ(DCC));
		seq_printf(m, "C0DRB3 = 0x%04x\n",
			   I915_READ16(C0DRB3));
		seq_printf(m, "C1DRB3 = 0x%04x\n",
			   I915_READ16(C1DRB3));
1828
	} else if (INTEL_INFO(dev)->gen >= 6) {
1829 1830 1831 1832 1833 1834 1835 1836
		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C0));
		seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C1));
		seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
			   I915_READ(MAD_DIMM_C2));
		seq_printf(m, "TILECTL = 0x%08x\n",
			   I915_READ(TILECTL));
1837 1838 1839 1840 1841 1842
		if (IS_GEN8(dev))
			seq_printf(m, "GAMTARBMODE = 0x%08x\n",
				   I915_READ(GAMTARBMODE));
		else
			seq_printf(m, "ARB_MODE = 0x%08x\n",
				   I915_READ(ARB_MODE));
1843 1844
		seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
			   I915_READ(DISP_ARB_CTL));
1845
	}
1846
	intel_runtime_pm_put(dev_priv);
1847 1848 1849 1850 1851
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

B
Ben Widawsky 已提交
1852 1853
static int per_file_ctx(int id, void *ptr, void *data)
{
1854
	struct intel_context *ctx = ptr;
B
Ben Widawsky 已提交
1855 1856 1857
	struct seq_file *m = data;
	struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);

1858 1859 1860 1861
	if (i915_gem_context_is_default(ctx))
		seq_puts(m, "  default context:\n");
	else
		seq_printf(m, "  context %d:\n", ctx->id);
B
Ben Widawsky 已提交
1862 1863 1864 1865 1866
	ppgtt->debug_dump(ppgtt, m);

	return 0;
}

1867
static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1868 1869
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1870
	struct intel_engine_cs *ring;
1871 1872
	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
	int unused, i;
1873

1874 1875 1876 1877
	if (!ppgtt)
		return;

	seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1878
	seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
1879 1880 1881 1882 1883 1884 1885
	for_each_ring(ring, dev_priv, unused) {
		seq_printf(m, "%s\n", ring->name);
		for (i = 0; i < 4; i++) {
			u32 offset = 0x270 + i * 8;
			u64 pdp = I915_READ(ring->mmio_base + offset + 4);
			pdp <<= 32;
			pdp |= I915_READ(ring->mmio_base + offset);
1886
			seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1887 1888 1889 1890 1891 1892 1893
		}
	}
}

static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1894
	struct intel_engine_cs *ring;
B
Ben Widawsky 已提交
1895
	struct drm_file *file;
1896
	int i;
1897 1898 1899 1900

	if (INTEL_INFO(dev)->gen == 6)
		seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));

1901
	for_each_ring(ring, dev_priv, i) {
1902 1903 1904 1905 1906 1907 1908 1909 1910 1911
		seq_printf(m, "%s\n", ring->name);
		if (INTEL_INFO(dev)->gen == 7)
			seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
		seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
		seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
		seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
	}
	if (dev_priv->mm.aliasing_ppgtt) {
		struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;

1912
		seq_puts(m, "aliasing PPGTT:\n");
1913
		seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
B
Ben Widawsky 已提交
1914

B
Ben Widawsky 已提交
1915
		ppgtt->debug_dump(ppgtt, m);
B
Ben Widawsky 已提交
1916 1917 1918 1919 1920 1921 1922 1923 1924
	} else
		return;

	list_for_each_entry_reverse(file, &dev->filelist, lhead) {
		struct drm_i915_file_private *file_priv = file->driver_priv;

		seq_printf(m, "proc: %s\n",
			   get_pid_task(file->pid, PIDTYPE_PID)->comm);
		idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1925 1926
	}
	seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1927 1928 1929 1930
}

static int i915_ppgtt_info(struct seq_file *m, void *data)
{
1931
	struct drm_info_node *node = m->private;
1932
	struct drm_device *dev = node->minor->dev;
1933
	struct drm_i915_private *dev_priv = dev->dev_private;
1934 1935 1936 1937

	int ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
1938
	intel_runtime_pm_get(dev_priv);
1939 1940 1941 1942 1943 1944

	if (INTEL_INFO(dev)->gen >= 8)
		gen8_ppgtt_info(m, dev);
	else if (INTEL_INFO(dev)->gen >= 6)
		gen6_ppgtt_info(m, dev);

1945
	intel_runtime_pm_put(dev_priv);
1946 1947 1948 1949 1950
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

1951 1952
static int i915_llc(struct seq_file *m, void *data)
{
1953
	struct drm_info_node *node = m->private;
1954 1955 1956 1957 1958 1959 1960 1961 1962 1963
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* Size calculation for LLC is a bit of a pain. Ignore for now. */
	seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
	seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);

	return 0;
}

1964 1965 1966 1967 1968
static int i915_edp_psr_status(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1969 1970
	u32 psrperf = 0;
	bool enabled = false;
1971

1972 1973
	intel_runtime_pm_get(dev_priv);

1974 1975
	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
	seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1976

1977 1978 1979
	enabled = HAS_PSR(dev) &&
		I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
	seq_printf(m, "Enabled: %s\n", yesno(enabled));
1980

1981 1982 1983 1984
	if (HAS_PSR(dev))
		psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
			EDP_PSR_PERF_CNT_MASK;
	seq_printf(m, "Performance_Counter: %u\n", psrperf);
1985

1986
	intel_runtime_pm_put(dev_priv);
1987 1988 1989
	return 0;
}

1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006
static int i915_sink_crc(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct intel_encoder *encoder;
	struct intel_connector *connector;
	struct intel_dp *intel_dp = NULL;
	int ret;
	u8 crc[6];

	drm_modeset_lock_all(dev);
	list_for_each_entry(connector, &dev->mode_config.connector_list,
			    base.head) {

		if (connector->base.dpms != DRM_MODE_DPMS_ON)
			continue;

2007 2008 2009
		if (!connector->base.encoder)
			continue;

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030
		encoder = to_intel_encoder(connector->base.encoder);
		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);

		ret = intel_dp_sink_crc(intel_dp, crc);
		if (ret)
			goto out;

		seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
			   crc[0], crc[1], crc[2],
			   crc[3], crc[4], crc[5]);
		goto out;
	}
	ret = -ENODEV;
out:
	drm_modeset_unlock_all(dev);
	return ret;
}

2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041
static int i915_energy_uJ(struct seq_file *m, void *data)
{
	struct drm_info_node *node = m->private;
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u64 power;
	u32 units;

	if (INTEL_INFO(dev)->gen < 6)
		return -ENODEV;

2042 2043
	intel_runtime_pm_get(dev_priv);

2044 2045 2046 2047 2048 2049
	rdmsrl(MSR_RAPL_POWER_UNIT, power);
	power = (power & 0x1f00) >> 8;
	units = 1000000 / (1 << power); /* convert to uJ */
	power = I915_READ(MCH_SECP_NRG_STTS);
	power *= units;

2050 2051
	intel_runtime_pm_put(dev_priv);

2052
	seq_printf(m, "%llu", (long long unsigned)power);
2053 2054 2055 2056 2057 2058

	return 0;
}

static int i915_pc8_status(struct seq_file *m, void *unused)
{
2059
	struct drm_info_node *node = m->private;
2060 2061 2062
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

2063
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2064 2065 2066 2067
		seq_puts(m, "not supported\n");
		return 0;
	}

2068
	seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2069
	seq_printf(m, "IRQs disabled: %s\n",
2070
		   yesno(dev_priv->pm.irqs_disabled));
2071

2072 2073 2074
	return 0;
}

2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097
static const char *power_domain_str(enum intel_display_power_domain domain)
{
	switch (domain) {
	case POWER_DOMAIN_PIPE_A:
		return "PIPE_A";
	case POWER_DOMAIN_PIPE_B:
		return "PIPE_B";
	case POWER_DOMAIN_PIPE_C:
		return "PIPE_C";
	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
		return "PIPE_A_PANEL_FITTER";
	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
		return "PIPE_B_PANEL_FITTER";
	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
		return "PIPE_C_PANEL_FITTER";
	case POWER_DOMAIN_TRANSCODER_A:
		return "TRANSCODER_A";
	case POWER_DOMAIN_TRANSCODER_B:
		return "TRANSCODER_B";
	case POWER_DOMAIN_TRANSCODER_C:
		return "TRANSCODER_C";
	case POWER_DOMAIN_TRANSCODER_EDP:
		return "TRANSCODER_EDP";
2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119
	case POWER_DOMAIN_PORT_DDI_A_2_LANES:
		return "PORT_DDI_A_2_LANES";
	case POWER_DOMAIN_PORT_DDI_A_4_LANES:
		return "PORT_DDI_A_4_LANES";
	case POWER_DOMAIN_PORT_DDI_B_2_LANES:
		return "PORT_DDI_B_2_LANES";
	case POWER_DOMAIN_PORT_DDI_B_4_LANES:
		return "PORT_DDI_B_4_LANES";
	case POWER_DOMAIN_PORT_DDI_C_2_LANES:
		return "PORT_DDI_C_2_LANES";
	case POWER_DOMAIN_PORT_DDI_C_4_LANES:
		return "PORT_DDI_C_4_LANES";
	case POWER_DOMAIN_PORT_DDI_D_2_LANES:
		return "PORT_DDI_D_2_LANES";
	case POWER_DOMAIN_PORT_DDI_D_4_LANES:
		return "PORT_DDI_D_4_LANES";
	case POWER_DOMAIN_PORT_DSI:
		return "PORT_DSI";
	case POWER_DOMAIN_PORT_CRT:
		return "PORT_CRT";
	case POWER_DOMAIN_PORT_OTHER:
		return "PORT_OTHER";
2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133
	case POWER_DOMAIN_VGA:
		return "VGA";
	case POWER_DOMAIN_AUDIO:
		return "AUDIO";
	case POWER_DOMAIN_INIT:
		return "INIT";
	default:
		WARN_ON(1);
		return "?";
	}
}

static int i915_power_domain_info(struct seq_file *m, void *unused)
{
2134
	struct drm_info_node *node = m->private;
2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166
	struct drm_device *dev = node->minor->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct i915_power_domains *power_domains = &dev_priv->power_domains;
	int i;

	mutex_lock(&power_domains->lock);

	seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
	for (i = 0; i < power_domains->power_well_count; i++) {
		struct i915_power_well *power_well;
		enum intel_display_power_domain power_domain;

		power_well = &power_domains->power_wells[i];
		seq_printf(m, "%-25s %d\n", power_well->name,
			   power_well->count);

		for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
		     power_domain++) {
			if (!(BIT(power_domain) & power_well->domains))
				continue;

			seq_printf(m, "  %-23s %d\n",
				 power_domain_str(power_domain),
				 power_domains->domain_use_count[power_domain]);
		}
	}

	mutex_unlock(&power_domains->lock);

	return 0;
}

2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188
static void intel_seq_print_mode(struct seq_file *m, int tabs,
				 struct drm_display_mode *mode)
{
	int i;

	for (i = 0; i < tabs; i++)
		seq_putc(m, '\t');

	seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
		   mode->base.id, mode->name,
		   mode->vrefresh, mode->clock,
		   mode->hdisplay, mode->hsync_start,
		   mode->hsync_end, mode->htotal,
		   mode->vdisplay, mode->vsync_start,
		   mode->vsync_end, mode->vtotal,
		   mode->type, mode->flags);
}

static void intel_encoder_info(struct seq_file *m,
			       struct intel_crtc *intel_crtc,
			       struct intel_encoder *intel_encoder)
{
2189
	struct drm_info_node *node = m->private;
2190 2191 2192 2193 2194 2195 2196
	struct drm_device *dev = node->minor->dev;
	struct drm_crtc *crtc = &intel_crtc->base;
	struct intel_connector *intel_connector;
	struct drm_encoder *encoder;

	encoder = &intel_encoder->base;
	seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2197
		   encoder->base.id, encoder->name);
2198 2199 2200 2201
	for_each_connector_on_encoder(dev, encoder, intel_connector) {
		struct drm_connector *connector = &intel_connector->base;
		seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
			   connector->base.id,
2202
			   connector->name,
2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215
			   drm_get_connector_status_name(connector->status));
		if (connector->status == connector_status_connected) {
			struct drm_display_mode *mode = &crtc->mode;
			seq_printf(m, ", mode:\n");
			intel_seq_print_mode(m, 2, mode);
		} else {
			seq_putc(m, '\n');
		}
	}
}

static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
{
2216
	struct drm_info_node *node = m->private;
2217 2218 2219 2220 2221
	struct drm_device *dev = node->minor->dev;
	struct drm_crtc *crtc = &intel_crtc->base;
	struct intel_encoder *intel_encoder;

	seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2222 2223
		   crtc->primary->fb->base.id, crtc->x, crtc->y,
		   crtc->primary->fb->width, crtc->primary->fb->height);
2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269
	for_each_encoder_on_crtc(dev, crtc, intel_encoder)
		intel_encoder_info(m, intel_crtc, intel_encoder);
}

static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
{
	struct drm_display_mode *mode = panel->fixed_mode;

	seq_printf(m, "\tfixed mode:\n");
	intel_seq_print_mode(m, 2, mode);
}

static void intel_dp_info(struct seq_file *m,
			  struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
	seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
		   "no");
	if (intel_encoder->type == INTEL_OUTPUT_EDP)
		intel_panel_info(m, &intel_connector->panel);
}

static void intel_hdmi_info(struct seq_file *m,
			    struct intel_connector *intel_connector)
{
	struct intel_encoder *intel_encoder = intel_connector->encoder;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);

	seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
		   "no");
}

static void intel_lvds_info(struct seq_file *m,
			    struct intel_connector *intel_connector)
{
	intel_panel_info(m, &intel_connector->panel);
}

static void intel_connector_info(struct seq_file *m,
				 struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct intel_encoder *intel_encoder = intel_connector->encoder;
2270
	struct drm_display_mode *mode;
2271 2272

	seq_printf(m, "connector %d: type %s, status: %s\n",
2273
		   connector->base.id, connector->name,
2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292
		   drm_get_connector_status_name(connector->status));
	if (connector->status == connector_status_connected) {
		seq_printf(m, "\tname: %s\n", connector->display_info.name);
		seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
			   connector->display_info.width_mm,
			   connector->display_info.height_mm);
		seq_printf(m, "\tsubpixel order: %s\n",
			   drm_get_subpixel_order_name(connector->display_info.subpixel_order));
		seq_printf(m, "\tCEA rev: %d\n",
			   connector->display_info.cea_rev);
	}
	if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
	    intel_encoder->type == INTEL_OUTPUT_EDP)
		intel_dp_info(m, intel_connector);
	else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
		intel_hdmi_info(m, intel_connector);
	else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
		intel_lvds_info(m, intel_connector);

2293 2294 2295
	seq_printf(m, "\tmodes:\n");
	list_for_each_entry(mode, &connector->modes, head)
		intel_seq_print_mode(m, 2, mode);
2296 2297
}

2298 2299 2300 2301 2302 2303 2304 2305
static bool cursor_active(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 state;

	if (IS_845G(dev) || IS_I865G(dev))
		state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
	else
2306
		state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2307 2308 2309 2310 2311 2312 2313 2314 2315

	return state;
}

static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pos;

2316
	pos = I915_READ(CURPOS(pipe));
2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328

	*x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
	if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
		*x = -*x;

	*y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
	if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
		*y = -*y;

	return cursor_active(dev, pipe);
}

2329 2330
static int i915_display_info(struct seq_file *m, void *unused)
{
2331
	struct drm_info_node *node = m->private;
2332
	struct drm_device *dev = node->minor->dev;
2333
	struct drm_i915_private *dev_priv = dev->dev_private;
2334
	struct intel_crtc *crtc;
2335 2336
	struct drm_connector *connector;

2337
	intel_runtime_pm_get(dev_priv);
2338 2339 2340
	drm_modeset_lock_all(dev);
	seq_printf(m, "CRTC info\n");
	seq_printf(m, "---------\n");
2341
	for_each_intel_crtc(dev, crtc) {
2342 2343
		bool active;
		int x, y;
2344 2345

		seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2346 2347
			   crtc->base.base.id, pipe_name(crtc->pipe),
			   yesno(crtc->active));
2348
		if (crtc->active) {
2349 2350
			intel_crtc_info(m, crtc);

2351 2352
			active = cursor_position(dev, crtc->pipe, &x, &y);
			seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2353
				   yesno(crtc->cursor_base),
2354 2355 2356
				   x, y, crtc->cursor_addr,
				   yesno(active));
		}
2357 2358 2359 2360

		seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
			   yesno(!crtc->cpu_fifo_underrun_disabled),
			   yesno(!crtc->pch_fifo_underrun_disabled));
2361 2362 2363 2364 2365 2366 2367 2368 2369
	}

	seq_printf(m, "\n");
	seq_printf(m, "Connector info\n");
	seq_printf(m, "--------------\n");
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		intel_connector_info(m, connector);
	}
	drm_modeset_unlock_all(dev);
2370
	intel_runtime_pm_put(dev_priv);
2371 2372 2373 2374

	return 0;
}

2375 2376 2377 2378 2379 2380 2381 2382
struct pipe_crc_info {
	const char *name;
	struct drm_device *dev;
	enum pipe pipe;
};

static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
{
2383 2384 2385 2386
	struct pipe_crc_info *info = inode->i_private;
	struct drm_i915_private *dev_priv = info->dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];

2387 2388 2389
	if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
		return -ENODEV;

2390 2391 2392 2393
	spin_lock_irq(&pipe_crc->lock);

	if (pipe_crc->opened) {
		spin_unlock_irq(&pipe_crc->lock);
2394 2395 2396
		return -EBUSY; /* already open */
	}

2397
	pipe_crc->opened = true;
2398 2399
	filep->private_data = inode->i_private;

2400 2401
	spin_unlock_irq(&pipe_crc->lock);

2402 2403 2404 2405 2406
	return 0;
}

static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
{
2407 2408 2409 2410
	struct pipe_crc_info *info = inode->i_private;
	struct drm_i915_private *dev_priv = info->dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];

2411 2412 2413
	spin_lock_irq(&pipe_crc->lock);
	pipe_crc->opened = false;
	spin_unlock_irq(&pipe_crc->lock);
2414

2415 2416 2417 2418 2419 2420 2421 2422 2423
	return 0;
}

/* (6 fields, 8 chars each, space separated (5) + '\n') */
#define PIPE_CRC_LINE_LEN	(6 * 8 + 5 + 1)
/* account for \'0' */
#define PIPE_CRC_BUFFER_LEN	(PIPE_CRC_LINE_LEN + 1)

static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2424
{
2425 2426 2427
	assert_spin_locked(&pipe_crc->lock);
	return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
			INTEL_PIPE_CRC_ENTRIES_NR);
2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449
}

static ssize_t
i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
		   loff_t *pos)
{
	struct pipe_crc_info *info = filep->private_data;
	struct drm_device *dev = info->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
	char buf[PIPE_CRC_BUFFER_LEN];
	int head, tail, n_entries, n;
	ssize_t bytes_read;

	/*
	 * Don't allow user space to provide buffers not big enough to hold
	 * a line of data.
	 */
	if (count < PIPE_CRC_LINE_LEN)
		return -EINVAL;

	if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2450
		return 0;
2451 2452

	/* nothing to read */
2453
	spin_lock_irq(&pipe_crc->lock);
2454
	while (pipe_crc_data_count(pipe_crc) == 0) {
2455 2456 2457 2458
		int ret;

		if (filep->f_flags & O_NONBLOCK) {
			spin_unlock_irq(&pipe_crc->lock);
2459
			return -EAGAIN;
2460
		}
2461

2462 2463 2464 2465 2466 2467
		ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
				pipe_crc_data_count(pipe_crc), pipe_crc->lock);
		if (ret) {
			spin_unlock_irq(&pipe_crc->lock);
			return ret;
		}
2468 2469
	}

2470
	/* We now have one or more entries to read */
2471 2472
	head = pipe_crc->head;
	tail = pipe_crc->tail;
2473 2474
	n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
			count / PIPE_CRC_LINE_LEN);
2475 2476
	spin_unlock_irq(&pipe_crc->lock);

2477 2478 2479
	bytes_read = 0;
	n = 0;
	do {
2480
		struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2481
		int ret;
2482

2483 2484 2485 2486 2487 2488 2489 2490 2491 2492
		bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
				       "%8u %8x %8x %8x %8x %8x\n",
				       entry->frame, entry->crc[0],
				       entry->crc[1], entry->crc[2],
				       entry->crc[3], entry->crc[4]);

		ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
				   buf, PIPE_CRC_LINE_LEN);
		if (ret == PIPE_CRC_LINE_LEN)
			return -EFAULT;
2493 2494 2495

		BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
		tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2496 2497
		n++;
	} while (--n_entries);
2498

2499 2500 2501 2502
	spin_lock_irq(&pipe_crc->lock);
	pipe_crc->tail = tail;
	spin_unlock_irq(&pipe_crc->lock);

2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537
	return bytes_read;
}

static const struct file_operations i915_pipe_crc_fops = {
	.owner = THIS_MODULE,
	.open = i915_pipe_crc_open,
	.read = i915_pipe_crc_read,
	.release = i915_pipe_crc_release,
};

static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
	{
		.name = "i915_pipe_A_crc",
		.pipe = PIPE_A,
	},
	{
		.name = "i915_pipe_B_crc",
		.pipe = PIPE_B,
	},
	{
		.name = "i915_pipe_C_crc",
		.pipe = PIPE_C,
	},
};

static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
				enum pipe pipe)
{
	struct drm_device *dev = minor->dev;
	struct dentry *ent;
	struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];

	info->dev = dev;
	ent = debugfs_create_file(info->name, S_IRUGO, root, info,
				  &i915_pipe_crc_fops);
2538 2539
	if (!ent)
		return -ENOMEM;
2540 2541

	return drm_add_fake_info_node(minor, ent, info);
2542 2543
}

D
Daniel Vetter 已提交
2544
static const char * const pipe_crc_sources[] = {
2545 2546 2547 2548
	"none",
	"plane1",
	"plane2",
	"pf",
2549
	"pipe",
2550 2551 2552 2553
	"TV",
	"DP-B",
	"DP-C",
	"DP-D",
2554
	"auto",
2555 2556 2557 2558 2559 2560 2561 2562
};

static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
{
	BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
	return pipe_crc_sources[source];
}

2563
static int display_crc_ctl_show(struct seq_file *m, void *data)
2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575
{
	struct drm_device *dev = m->private;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	for (i = 0; i < I915_MAX_PIPES; i++)
		seq_printf(m, "%c %s\n", pipe_name(i),
			   pipe_crc_source_name(dev_priv->pipe_crc[i].source));

	return 0;
}

2576
static int display_crc_ctl_open(struct inode *inode, struct file *file)
2577 2578 2579
{
	struct drm_device *dev = inode->i_private;

2580
	return single_open(file, display_crc_ctl_show, dev);
2581 2582
}

2583
static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2584 2585
				 uint32_t *val)
{
2586 2587 2588 2589
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PIPE;

	switch (*source) {
2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
		break;
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

2603 2604 2605 2606 2607
static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
				     enum intel_pipe_crc_source *source)
{
	struct intel_encoder *encoder;
	struct intel_crtc *crtc;
2608
	struct intel_digital_port *dig_port;
2609 2610 2611 2612
	int ret = 0;

	*source = INTEL_PIPE_CRC_SOURCE_PIPE;

2613
	drm_modeset_lock_all(dev);
2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		if (!encoder->base.crtc)
			continue;

		crtc = to_intel_crtc(encoder->base.crtc);

		if (crtc->pipe != pipe)
			continue;

		switch (encoder->type) {
		case INTEL_OUTPUT_TVOUT:
			*source = INTEL_PIPE_CRC_SOURCE_TV;
			break;
		case INTEL_OUTPUT_DISPLAYPORT:
		case INTEL_OUTPUT_EDP:
2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645
			dig_port = enc_to_dig_port(&encoder->base);
			switch (dig_port->port) {
			case PORT_B:
				*source = INTEL_PIPE_CRC_SOURCE_DP_B;
				break;
			case PORT_C:
				*source = INTEL_PIPE_CRC_SOURCE_DP_C;
				break;
			case PORT_D:
				*source = INTEL_PIPE_CRC_SOURCE_DP_D;
				break;
			default:
				WARN(1, "nonexisting DP port %c\n",
				     port_name(dig_port->port));
				break;
			}
2646 2647 2648
			break;
		}
	}
2649
	drm_modeset_unlock_all(dev);
2650 2651 2652 2653 2654 2655 2656

	return ret;
}

static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
				enum pipe pipe,
				enum intel_pipe_crc_source *source,
2657 2658
				uint32_t *val)
{
2659 2660 2661
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool need_stable_symbols = false;

2662 2663 2664 2665 2666 2667 2668
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
		int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
		if (ret)
			return ret;
	}

	switch (*source) {
2669 2670 2671 2672 2673
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_B:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2674
		need_stable_symbols = true;
2675 2676 2677
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_C:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2678
		need_stable_symbols = true;
2679 2680 2681 2682 2683 2684 2685 2686
		break;
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707
	/*
	 * When the pipe CRC tap point is after the transcoders we need
	 * to tweak symbol-level features to produce a deterministic series of
	 * symbols for a given frame. We need to reset those features only once
	 * a frame (instead of every nth symbol):
	 *   - DC-balance: used to ensure a better clock recovery from the data
	 *     link (SDVO)
	 *   - DisplayPort scrambling: used for EMI reduction
	 */
	if (need_stable_symbols) {
		uint32_t tmp = I915_READ(PORT_DFT2_G4X);

		tmp |= DC_BALANCE_RESET_VLV;
		if (pipe == PIPE_A)
			tmp |= PIPE_A_SCRAMBLE_RESET;
		else
			tmp |= PIPE_B_SCRAMBLE_RESET;

		I915_WRITE(PORT_DFT2_G4X, tmp);
	}

2708 2709 2710
	return 0;
}

2711
static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2712 2713
				 enum pipe pipe,
				 enum intel_pipe_crc_source *source,
2714 2715
				 uint32_t *val)
{
2716 2717 2718
	struct drm_i915_private *dev_priv = dev->dev_private;
	bool need_stable_symbols = false;

2719 2720 2721 2722 2723 2724 2725
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
		int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
		if (ret)
			return ret;
	}

	switch (*source) {
2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
		break;
	case INTEL_PIPE_CRC_SOURCE_TV:
		if (!SUPPORTS_TV(dev))
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_B:
		if (!IS_G4X(dev))
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2738
		need_stable_symbols = true;
2739 2740 2741 2742 2743
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_C:
		if (!IS_G4X(dev))
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2744
		need_stable_symbols = true;
2745 2746 2747 2748 2749
		break;
	case INTEL_PIPE_CRC_SOURCE_DP_D:
		if (!IS_G4X(dev))
			return -EINVAL;
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2750
		need_stable_symbols = true;
2751 2752 2753 2754 2755 2756 2757 2758
		break;
	case INTEL_PIPE_CRC_SOURCE_NONE:
		*val = 0;
		break;
	default:
		return -EINVAL;
	}

2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783
	/*
	 * When the pipe CRC tap point is after the transcoders we need
	 * to tweak symbol-level features to produce a deterministic series of
	 * symbols for a given frame. We need to reset those features only once
	 * a frame (instead of every nth symbol):
	 *   - DC-balance: used to ensure a better clock recovery from the data
	 *     link (SDVO)
	 *   - DisplayPort scrambling: used for EMI reduction
	 */
	if (need_stable_symbols) {
		uint32_t tmp = I915_READ(PORT_DFT2_G4X);

		WARN_ON(!IS_G4X(dev));

		I915_WRITE(PORT_DFT_I9XX,
			   I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);

		if (pipe == PIPE_A)
			tmp |= PIPE_A_SCRAMBLE_RESET;
		else
			tmp |= PIPE_B_SCRAMBLE_RESET;

		I915_WRITE(PORT_DFT2_G4X, tmp);
	}

2784 2785 2786
	return 0;
}

2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802
static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
					 enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp = I915_READ(PORT_DFT2_G4X);

	if (pipe == PIPE_A)
		tmp &= ~PIPE_A_SCRAMBLE_RESET;
	else
		tmp &= ~PIPE_B_SCRAMBLE_RESET;
	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
		tmp &= ~DC_BALANCE_RESET_VLV;
	I915_WRITE(PORT_DFT2_G4X, tmp);

}

2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820
static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
					 enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t tmp = I915_READ(PORT_DFT2_G4X);

	if (pipe == PIPE_A)
		tmp &= ~PIPE_A_SCRAMBLE_RESET;
	else
		tmp &= ~PIPE_B_SCRAMBLE_RESET;
	I915_WRITE(PORT_DFT2_G4X, tmp);

	if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
		I915_WRITE(PORT_DFT_I9XX,
			   I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
	}
}

2821
static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2822 2823
				uint32_t *val)
{
2824 2825 2826 2827
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PIPE;

	switch (*source) {
2828 2829 2830 2831 2832 2833 2834 2835 2836
	case INTEL_PIPE_CRC_SOURCE_PLANE1:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
		break;
	case INTEL_PIPE_CRC_SOURCE_PLANE2:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
		break;
	case INTEL_PIPE_CRC_SOURCE_PIPE:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
		break;
2837
	case INTEL_PIPE_CRC_SOURCE_NONE:
2838 2839
		*val = 0;
		break;
2840 2841
	default:
		return -EINVAL;
2842 2843 2844 2845 2846
	}

	return 0;
}

2847
static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2848 2849
				uint32_t *val)
{
2850 2851 2852 2853
	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
		*source = INTEL_PIPE_CRC_SOURCE_PF;

	switch (*source) {
2854 2855 2856 2857 2858 2859 2860 2861 2862
	case INTEL_PIPE_CRC_SOURCE_PLANE1:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
		break;
	case INTEL_PIPE_CRC_SOURCE_PLANE2:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
		break;
	case INTEL_PIPE_CRC_SOURCE_PF:
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
		break;
2863
	case INTEL_PIPE_CRC_SOURCE_NONE:
2864 2865
		*val = 0;
		break;
2866 2867
	default:
		return -EINVAL;
2868 2869 2870 2871 2872
	}

	return 0;
}

2873 2874 2875 2876
static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
			       enum intel_pipe_crc_source source)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2877
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2878
	u32 val = 0; /* shut up gcc */
2879
	int ret;
2880

2881 2882 2883
	if (pipe_crc->source == source)
		return 0;

2884 2885 2886 2887
	/* forbid changing the source without going back to 'none' */
	if (pipe_crc->source && source)
		return -EINVAL;

2888
	if (IS_GEN2(dev))
2889
		ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2890
	else if (INTEL_INFO(dev)->gen < 5)
2891
		ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2892
	else if (IS_VALLEYVIEW(dev))
2893
		ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2894
	else if (IS_GEN5(dev) || IS_GEN6(dev))
2895
		ret = ilk_pipe_crc_ctl_reg(&source, &val);
2896
	else
2897
		ret = ivb_pipe_crc_ctl_reg(&source, &val);
2898 2899 2900 2901

	if (ret != 0)
		return ret;

2902 2903
	/* none -> real source transition */
	if (source) {
2904 2905 2906
		DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
				 pipe_name(pipe), pipe_crc_source_name(source));

2907 2908 2909 2910 2911 2912
		pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
					    INTEL_PIPE_CRC_ENTRIES_NR,
					    GFP_KERNEL);
		if (!pipe_crc->entries)
			return -ENOMEM;

2913 2914 2915 2916
		spin_lock_irq(&pipe_crc->lock);
		pipe_crc->head = 0;
		pipe_crc->tail = 0;
		spin_unlock_irq(&pipe_crc->lock);
2917 2918
	}

2919
	pipe_crc->source = source;
2920 2921 2922 2923

	I915_WRITE(PIPE_CRC_CTL(pipe), val);
	POSTING_READ(PIPE_CRC_CTL(pipe));

2924 2925
	/* real source -> none transition */
	if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2926
		struct intel_pipe_crc_entry *entries;
2927 2928
		struct intel_crtc *crtc =
			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2929

2930 2931 2932
		DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
				 pipe_name(pipe));

2933 2934 2935 2936
		drm_modeset_lock(&crtc->base.mutex, NULL);
		if (crtc->active)
			intel_wait_for_vblank(dev, pipe);
		drm_modeset_unlock(&crtc->base.mutex);
2937

2938 2939
		spin_lock_irq(&pipe_crc->lock);
		entries = pipe_crc->entries;
2940
		pipe_crc->entries = NULL;
2941 2942 2943
		spin_unlock_irq(&pipe_crc->lock);

		kfree(entries);
2944 2945 2946

		if (IS_G4X(dev))
			g4x_undo_pipe_scramble_reset(dev, pipe);
2947 2948
		else if (IS_VALLEYVIEW(dev))
			vlv_undo_pipe_scramble_reset(dev, pipe);
2949 2950
	}

2951 2952 2953 2954 2955
	return 0;
}

/*
 * Parse pipe CRC command strings:
2956 2957 2958
 *   command: wsp* object wsp+ name wsp+ source wsp*
 *   object: 'pipe'
 *   name: (A | B | C)
2959 2960 2961 2962
 *   source: (none | plane1 | plane2 | pf)
 *   wsp: (#0x20 | #0x9 | #0xA)+
 *
 * eg.:
2963 2964
 *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
 *  "pipe A none"    ->  Stop CRC
2965
 */
2966
static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996
{
	int n_words = 0;

	while (*buf) {
		char *end;

		/* skip leading white space */
		buf = skip_spaces(buf);
		if (!*buf)
			break;	/* end of buffer */

		/* find end of word */
		for (end = buf; *end && !isspace(*end); end++)
			;

		if (n_words == max_words) {
			DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
					 max_words);
			return -EINVAL;	/* ran out of words[] before bytes */
		}

		if (*end)
			*end++ = '\0';
		words[n_words++] = buf;
		buf = end;
	}

	return n_words;
}

2997 2998 2999 3000
enum intel_pipe_crc_object {
	PIPE_CRC_OBJECT_PIPE,
};

D
Daniel Vetter 已提交
3001
static const char * const pipe_crc_objects[] = {
3002 3003 3004 3005
	"pipe",
};

static int
3006
display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3007 3008 3009 3010 3011
{
	int i;

	for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
		if (!strcmp(buf, pipe_crc_objects[i])) {
3012
			*o = i;
3013 3014 3015 3016 3017 3018
			return 0;
		    }

	return -EINVAL;
}

3019
static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031
{
	const char name = buf[0];

	if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
		return -EINVAL;

	*pipe = name - 'A';

	return 0;
}

static int
3032
display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3033 3034 3035 3036 3037
{
	int i;

	for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
		if (!strcmp(buf, pipe_crc_sources[i])) {
3038
			*s = i;
3039 3040 3041 3042 3043 3044
			return 0;
		    }

	return -EINVAL;
}

3045
static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3046
{
3047
#define N_WORDS 3
3048
	int n_words;
3049
	char *words[N_WORDS];
3050
	enum pipe pipe;
3051
	enum intel_pipe_crc_object object;
3052 3053
	enum intel_pipe_crc_source source;

3054
	n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3055 3056 3057 3058 3059 3060
	if (n_words != N_WORDS) {
		DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
				 N_WORDS);
		return -EINVAL;
	}

3061
	if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3062
		DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3063 3064 3065
		return -EINVAL;
	}

3066
	if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3067
		DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3068 3069 3070
		return -EINVAL;
	}

3071
	if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3072
		DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3073 3074 3075 3076 3077 3078
		return -EINVAL;
	}

	return pipe_crc_set_source(dev, pipe, source);
}

3079 3080
static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
				     size_t len, loff_t *offp)
3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105
{
	struct seq_file *m = file->private_data;
	struct drm_device *dev = m->private;
	char *tmpbuf;
	int ret;

	if (len == 0)
		return 0;

	if (len > PAGE_SIZE - 1) {
		DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
				 PAGE_SIZE);
		return -E2BIG;
	}

	tmpbuf = kmalloc(len + 1, GFP_KERNEL);
	if (!tmpbuf)
		return -ENOMEM;

	if (copy_from_user(tmpbuf, ubuf, len)) {
		ret = -EFAULT;
		goto out;
	}
	tmpbuf[len] = '\0';

3106
	ret = display_crc_ctl_parse(dev, tmpbuf, len);
3107 3108 3109 3110 3111 3112 3113 3114 3115 3116

out:
	kfree(tmpbuf);
	if (ret < 0)
		return ret;

	*offp += len;
	return len;
}

3117
static const struct file_operations i915_display_crc_ctl_fops = {
3118
	.owner = THIS_MODULE,
3119
	.open = display_crc_ctl_open,
3120 3121 3122
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
3123
	.write = display_crc_ctl_write
3124 3125
};

3126 3127 3128
static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
{
	struct drm_device *dev = m->private;
3129
	int num_levels = ilk_wm_max_level(dev) + 1;
3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211
	int level;

	drm_modeset_lock_all(dev);

	for (level = 0; level < num_levels; level++) {
		unsigned int latency = wm[level];

		/* WM1+ latency values in 0.5us units */
		if (level > 0)
			latency *= 5;

		seq_printf(m, "WM%d %u (%u.%u usec)\n",
			   level, wm[level],
			   latency / 10, latency % 10);
	}

	drm_modeset_unlock_all(dev);
}

static int pri_wm_latency_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;

	wm_latency_show(m, to_i915(dev)->wm.pri_latency);

	return 0;
}

static int spr_wm_latency_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;

	wm_latency_show(m, to_i915(dev)->wm.spr_latency);

	return 0;
}

static int cur_wm_latency_show(struct seq_file *m, void *data)
{
	struct drm_device *dev = m->private;

	wm_latency_show(m, to_i915(dev)->wm.cur_latency);

	return 0;
}

static int pri_wm_latency_open(struct inode *inode, struct file *file)
{
	struct drm_device *dev = inode->i_private;

	if (!HAS_PCH_SPLIT(dev))
		return -ENODEV;

	return single_open(file, pri_wm_latency_show, dev);
}

static int spr_wm_latency_open(struct inode *inode, struct file *file)
{
	struct drm_device *dev = inode->i_private;

	if (!HAS_PCH_SPLIT(dev))
		return -ENODEV;

	return single_open(file, spr_wm_latency_show, dev);
}

static int cur_wm_latency_open(struct inode *inode, struct file *file)
{
	struct drm_device *dev = inode->i_private;

	if (!HAS_PCH_SPLIT(dev))
		return -ENODEV;

	return single_open(file, cur_wm_latency_show, dev);
}

static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
				size_t len, loff_t *offp, uint16_t wm[5])
{
	struct seq_file *m = file->private_data;
	struct drm_device *dev = m->private;
	uint16_t new[5] = { 0 };
3212
	int num_levels = ilk_wm_max_level(dev) + 1;
3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293
	int level;
	int ret;
	char tmp[32];

	if (len >= sizeof(tmp))
		return -EINVAL;

	if (copy_from_user(tmp, ubuf, len))
		return -EFAULT;

	tmp[len] = '\0';

	ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
	if (ret != num_levels)
		return -EINVAL;

	drm_modeset_lock_all(dev);

	for (level = 0; level < num_levels; level++)
		wm[level] = new[level];

	drm_modeset_unlock_all(dev);

	return len;
}


static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
	struct drm_device *dev = m->private;

	return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
}

static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
	struct drm_device *dev = m->private;

	return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
}

static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
				    size_t len, loff_t *offp)
{
	struct seq_file *m = file->private_data;
	struct drm_device *dev = m->private;

	return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
}

static const struct file_operations i915_pri_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = pri_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = pri_wm_latency_write
};

static const struct file_operations i915_spr_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = spr_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = spr_wm_latency_write
};

static const struct file_operations i915_cur_wm_latency_fops = {
	.owner = THIS_MODULE,
	.open = cur_wm_latency_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
	.write = cur_wm_latency_write
};

3294 3295
static int
i915_wedged_get(void *data, u64 *val)
3296
{
3297
	struct drm_device *dev = data;
3298
	struct drm_i915_private *dev_priv = dev->dev_private;
3299

3300
	*val = atomic_read(&dev_priv->gpu_error.reset_counter);
3301

3302
	return 0;
3303 3304
}

3305 3306
static int
i915_wedged_set(void *data, u64 val)
3307
{
3308
	struct drm_device *dev = data;
3309 3310 3311
	struct drm_i915_private *dev_priv = dev->dev_private;

	intel_runtime_pm_get(dev_priv);
3312

3313 3314
	i915_handle_error(dev, val,
			  "Manually setting wedged to %llu", val);
3315 3316 3317

	intel_runtime_pm_put(dev_priv);

3318
	return 0;
3319 3320
}

3321 3322
DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
			i915_wedged_get, i915_wedged_set,
3323
			"%llu\n");
3324

3325 3326
static int
i915_ring_stop_get(void *data, u64 *val)
3327
{
3328
	struct drm_device *dev = data;
3329
	struct drm_i915_private *dev_priv = dev->dev_private;
3330

3331
	*val = dev_priv->gpu_error.stop_rings;
3332

3333
	return 0;
3334 3335
}

3336 3337
static int
i915_ring_stop_set(void *data, u64 val)
3338
{
3339
	struct drm_device *dev = data;
3340
	struct drm_i915_private *dev_priv = dev->dev_private;
3341
	int ret;
3342

3343
	DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3344

3345 3346 3347 3348
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

3349
	dev_priv->gpu_error.stop_rings = val;
3350 3351
	mutex_unlock(&dev->struct_mutex);

3352
	return 0;
3353 3354
}

3355 3356 3357
DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
			i915_ring_stop_get, i915_ring_stop_set,
			"0x%08llx\n");
3358

3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424
static int
i915_ring_missed_irq_get(void *data, u64 *val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = dev->dev_private;

	*val = dev_priv->gpu_error.missed_irq_rings;
	return 0;
}

static int
i915_ring_missed_irq_set(void *data, u64 val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	/* Lock against concurrent debugfs callers */
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
	dev_priv->gpu_error.missed_irq_rings = val;
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
			i915_ring_missed_irq_get, i915_ring_missed_irq_set,
			"0x%08llx\n");

static int
i915_ring_test_irq_get(void *data, u64 *val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = dev->dev_private;

	*val = dev_priv->gpu_error.test_irq_rings;

	return 0;
}

static int
i915_ring_test_irq_set(void *data, u64 val)
{
	struct drm_device *dev = data;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);

	/* Lock against concurrent debugfs callers */
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	dev_priv->gpu_error.test_irq_rings = val;
	mutex_unlock(&dev->struct_mutex);

	return 0;
}

DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
			i915_ring_test_irq_get, i915_ring_test_irq_set,
			"0x%08llx\n");

3425 3426 3427 3428 3429 3430 3431 3432
#define DROP_UNBOUND 0x1
#define DROP_BOUND 0x2
#define DROP_RETIRE 0x4
#define DROP_ACTIVE 0x8
#define DROP_ALL (DROP_UNBOUND | \
		  DROP_BOUND | \
		  DROP_RETIRE | \
		  DROP_ACTIVE)
3433 3434
static int
i915_drop_caches_get(void *data, u64 *val)
3435
{
3436
	*val = DROP_ALL;
3437

3438
	return 0;
3439 3440
}

3441 3442
static int
i915_drop_caches_set(void *data, u64 val)
3443
{
3444
	struct drm_device *dev = data;
3445 3446
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_i915_gem_object *obj, *next;
3447 3448
	struct i915_address_space *vm;
	struct i915_vma *vma, *x;
3449
	int ret;
3450

3451
	DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468

	/* No need to check and wait for gpu resets, only libdrm auto-restarts
	 * on ioctls on -EAGAIN. */
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

	if (val & DROP_ACTIVE) {
		ret = i915_gpu_idle(dev);
		if (ret)
			goto unlock;
	}

	if (val & (DROP_RETIRE | DROP_ACTIVE))
		i915_gem_retire_requests(dev);

	if (val & DROP_BOUND) {
3469 3470 3471
		list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
			list_for_each_entry_safe(vma, x, &vm->inactive_list,
						 mm_list) {
3472
				if (vma->pin_count)
3473 3474 3475 3476 3477 3478
					continue;

				ret = i915_vma_unbind(vma);
				if (ret)
					goto unlock;
			}
3479
		}
3480 3481 3482
	}

	if (val & DROP_UNBOUND) {
3483 3484
		list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
					 global_list)
3485 3486 3487 3488 3489 3490 3491 3492 3493 3494
			if (obj->pages_pin_count == 0) {
				ret = i915_gem_object_put_pages(obj);
				if (ret)
					goto unlock;
			}
	}

unlock:
	mutex_unlock(&dev->struct_mutex);

3495
	return ret;
3496 3497
}

3498 3499 3500
DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
			i915_drop_caches_get, i915_drop_caches_set,
			"0x%08llx\n");
3501

3502 3503
static int
i915_max_freq_get(void *data, u64 *val)
3504
{
3505
	struct drm_device *dev = data;
3506
	struct drm_i915_private *dev_priv = dev->dev_private;
3507
	int ret;
3508

3509
	if (INTEL_INFO(dev)->gen < 6)
3510 3511
		return -ENODEV;

3512 3513
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

3514
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3515 3516
	if (ret)
		return ret;
3517

3518
	if (IS_VALLEYVIEW(dev))
3519
		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
3520
	else
3521
		*val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3522
	mutex_unlock(&dev_priv->rps.hw_lock);
3523

3524
	return 0;
3525 3526
}

3527 3528
static int
i915_max_freq_set(void *data, u64 val)
3529
{
3530
	struct drm_device *dev = data;
3531
	struct drm_i915_private *dev_priv = dev->dev_private;
3532
	u32 rp_state_cap, hw_max, hw_min;
3533
	int ret;
3534

3535
	if (INTEL_INFO(dev)->gen < 6)
3536
		return -ENODEV;
3537

3538 3539
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

3540
	DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3541

3542
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3543 3544 3545
	if (ret)
		return ret;

3546 3547 3548
	/*
	 * Turbo will still be enabled, but won't go above the set value.
	 */
3549
	if (IS_VALLEYVIEW(dev)) {
3550
		val = vlv_freq_opcode(dev_priv, val);
3551 3552 3553

		hw_max = valleyview_rps_max_freq(dev_priv);
		hw_min = valleyview_rps_min_freq(dev_priv);
3554 3555
	} else {
		do_div(val, GT_FREQUENCY_MULTIPLIER);
3556 3557

		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3558
		hw_max = dev_priv->rps.max_freq;
3559 3560 3561
		hw_min = (rp_state_cap >> 16) & 0xff;
	}

3562
	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
3563 3564
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
3565 3566
	}

3567
	dev_priv->rps.max_freq_softlimit = val;
3568 3569 3570 3571 3572 3573

	if (IS_VALLEYVIEW(dev))
		valleyview_set_rps(dev, val);
	else
		gen6_set_rps(dev, val);

3574
	mutex_unlock(&dev_priv->rps.hw_lock);
3575

3576
	return 0;
3577 3578
}

3579 3580
DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
			i915_max_freq_get, i915_max_freq_set,
3581
			"%llu\n");
3582

3583 3584
static int
i915_min_freq_get(void *data, u64 *val)
3585
{
3586
	struct drm_device *dev = data;
3587
	struct drm_i915_private *dev_priv = dev->dev_private;
3588
	int ret;
3589

3590
	if (INTEL_INFO(dev)->gen < 6)
3591 3592
		return -ENODEV;

3593 3594
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

3595
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3596 3597
	if (ret)
		return ret;
3598

3599
	if (IS_VALLEYVIEW(dev))
3600
		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
3601
	else
3602
		*val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3603
	mutex_unlock(&dev_priv->rps.hw_lock);
3604

3605
	return 0;
3606 3607
}

3608 3609
static int
i915_min_freq_set(void *data, u64 val)
3610
{
3611
	struct drm_device *dev = data;
3612
	struct drm_i915_private *dev_priv = dev->dev_private;
3613
	u32 rp_state_cap, hw_max, hw_min;
3614
	int ret;
3615

3616
	if (INTEL_INFO(dev)->gen < 6)
3617
		return -ENODEV;
3618

3619 3620
	flush_delayed_work(&dev_priv->rps.delayed_resume_work);

3621
	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3622

3623
	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3624 3625 3626
	if (ret)
		return ret;

3627 3628 3629
	/*
	 * Turbo will still be enabled, but won't go below the set value.
	 */
3630
	if (IS_VALLEYVIEW(dev)) {
3631
		val = vlv_freq_opcode(dev_priv, val);
3632 3633 3634

		hw_max = valleyview_rps_max_freq(dev_priv);
		hw_min = valleyview_rps_min_freq(dev_priv);
3635 3636
	} else {
		do_div(val, GT_FREQUENCY_MULTIPLIER);
3637 3638

		rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3639
		hw_max = dev_priv->rps.max_freq;
3640 3641 3642
		hw_min = (rp_state_cap >> 16) & 0xff;
	}

3643
	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
3644 3645
		mutex_unlock(&dev_priv->rps.hw_lock);
		return -EINVAL;
3646
	}
3647

3648
	dev_priv->rps.min_freq_softlimit = val;
3649 3650 3651 3652 3653 3654

	if (IS_VALLEYVIEW(dev))
		valleyview_set_rps(dev, val);
	else
		gen6_set_rps(dev, val);

3655
	mutex_unlock(&dev_priv->rps.hw_lock);
3656

3657
	return 0;
3658 3659
}

3660 3661
DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
			i915_min_freq_get, i915_min_freq_set,
3662
			"%llu\n");
3663

3664 3665
static int
i915_cache_sharing_get(void *data, u64 *val)
3666
{
3667
	struct drm_device *dev = data;
3668
	struct drm_i915_private *dev_priv = dev->dev_private;
3669
	u32 snpcr;
3670
	int ret;
3671

3672 3673 3674
	if (!(IS_GEN6(dev) || IS_GEN7(dev)))
		return -ENODEV;

3675 3676 3677
	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;
3678
	intel_runtime_pm_get(dev_priv);
3679

3680
	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3681 3682

	intel_runtime_pm_put(dev_priv);
3683 3684
	mutex_unlock(&dev_priv->dev->struct_mutex);

3685
	*val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3686

3687
	return 0;
3688 3689
}

3690 3691
static int
i915_cache_sharing_set(void *data, u64 val)
3692
{
3693
	struct drm_device *dev = data;
3694 3695 3696
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 snpcr;

3697 3698 3699
	if (!(IS_GEN6(dev) || IS_GEN7(dev)))
		return -ENODEV;

3700
	if (val > 3)
3701 3702
		return -EINVAL;

3703
	intel_runtime_pm_get(dev_priv);
3704
	DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3705 3706 3707 3708 3709 3710 3711

	/* Update the cache sharing policy here as well */
	snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
	snpcr &= ~GEN6_MBC_SNPCR_MASK;
	snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);

3712
	intel_runtime_pm_put(dev_priv);
3713
	return 0;
3714 3715
}

3716 3717 3718
DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
			i915_cache_sharing_get, i915_cache_sharing_set,
			"%llu\n");
3719

3720 3721 3722 3723 3724
static int i915_forcewake_open(struct inode *inode, struct file *file)
{
	struct drm_device *dev = inode->i_private;
	struct drm_i915_private *dev_priv = dev->dev_private;

3725
	if (INTEL_INFO(dev)->gen < 6)
3726 3727
		return 0;

3728
	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3729 3730 3731 3732

	return 0;
}

3733
static int i915_forcewake_release(struct inode *inode, struct file *file)
3734 3735 3736 3737
{
	struct drm_device *dev = inode->i_private;
	struct drm_i915_private *dev_priv = dev->dev_private;

3738
	if (INTEL_INFO(dev)->gen < 6)
3739 3740
		return 0;

3741
	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757

	return 0;
}

static const struct file_operations i915_forcewake_fops = {
	.owner = THIS_MODULE,
	.open = i915_forcewake_open,
	.release = i915_forcewake_release,
};

static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
{
	struct drm_device *dev = minor->dev;
	struct dentry *ent;

	ent = debugfs_create_file("i915_forcewake_user",
3758
				  S_IRUSR,
3759 3760
				  root, dev,
				  &i915_forcewake_fops);
3761 3762
	if (!ent)
		return -ENOMEM;
3763

3764
	return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3765 3766
}

3767 3768 3769 3770
static int i915_debugfs_create(struct dentry *root,
			       struct drm_minor *minor,
			       const char *name,
			       const struct file_operations *fops)
3771 3772 3773 3774
{
	struct drm_device *dev = minor->dev;
	struct dentry *ent;

3775
	ent = debugfs_create_file(name,
3776 3777
				  S_IRUGO | S_IWUSR,
				  root, dev,
3778
				  fops);
3779 3780
	if (!ent)
		return -ENOMEM;
3781

3782
	return drm_add_fake_info_node(minor, ent, fops);
3783 3784
}

3785
static const struct drm_info_list i915_debugfs_list[] = {
3786
	{"i915_capabilities", i915_capabilities, 0},
3787
	{"i915_gem_objects", i915_gem_object_info, 0},
3788
	{"i915_gem_gtt", i915_gem_gtt_info, 0},
3789
	{"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3790 3791
	{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
	{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3792
	{"i915_gem_stolen", i915_gem_stolen_list_info },
3793
	{"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3794 3795
	{"i915_gem_request", i915_gem_request_info, 0},
	{"i915_gem_seqno", i915_gem_seqno_info, 0},
3796
	{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3797
	{"i915_gem_interrupt", i915_interrupt_info, 0},
3798 3799 3800
	{"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
	{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
	{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3801
	{"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3802
	{"i915_rstdby_delays", i915_rstdby_delays, 0},
3803
	{"i915_frequency_info", i915_frequency_info, 0},
3804 3805 3806
	{"i915_delayfreq_table", i915_delayfreq_table, 0},
	{"i915_inttoext_table", i915_inttoext_table, 0},
	{"i915_drpc_info", i915_drpc_info, 0},
3807
	{"i915_emon_status", i915_emon_status, 0},
3808
	{"i915_ring_freq_table", i915_ring_freq_table, 0},
3809
	{"i915_gfxec", i915_gfxec, 0},
3810
	{"i915_fbc_status", i915_fbc_status, 0},
3811
	{"i915_ips_status", i915_ips_status, 0},
3812
	{"i915_sr_status", i915_sr_status, 0},
3813
	{"i915_opregion", i915_opregion, 0},
3814
	{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3815
	{"i915_context_status", i915_context_status, 0},
3816
	{"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3817
	{"i915_swizzle_info", i915_swizzle_info, 0},
3818
	{"i915_ppgtt_info", i915_ppgtt_info, 0},
3819
	{"i915_llc", i915_llc, 0},
3820
	{"i915_edp_psr_status", i915_edp_psr_status, 0},
3821
	{"i915_sink_crc_eDP1", i915_sink_crc, 0},
3822
	{"i915_energy_uJ", i915_energy_uJ, 0},
3823
	{"i915_pc8_status", i915_pc8_status, 0},
3824
	{"i915_power_domain_info", i915_power_domain_info, 0},
3825
	{"i915_display_info", i915_display_info, 0},
3826
};
3827
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3828

3829
static const struct i915_debugfs_files {
3830 3831 3832 3833 3834 3835 3836 3837
	const char *name;
	const struct file_operations *fops;
} i915_debugfs_files[] = {
	{"i915_wedged", &i915_wedged_fops},
	{"i915_max_freq", &i915_max_freq_fops},
	{"i915_min_freq", &i915_min_freq_fops},
	{"i915_cache_sharing", &i915_cache_sharing_fops},
	{"i915_ring_stop", &i915_ring_stop_fops},
3838 3839
	{"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
	{"i915_ring_test_irq", &i915_ring_test_irq_fops},
3840 3841 3842
	{"i915_gem_drop_caches", &i915_drop_caches_fops},
	{"i915_error_state", &i915_error_state_fops},
	{"i915_next_seqno", &i915_next_seqno_fops},
3843
	{"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3844 3845 3846
	{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
	{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
	{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3847 3848
};

3849 3850 3851
void intel_display_crc_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3852
	enum pipe pipe;
3853

3854 3855
	for_each_pipe(pipe) {
		struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3856

3857 3858
		pipe_crc->opened = false;
		spin_lock_init(&pipe_crc->lock);
3859 3860 3861 3862
		init_waitqueue_head(&pipe_crc->wq);
	}
}

3863
int i915_debugfs_init(struct drm_minor *minor)
3864
{
3865
	int ret, i;
3866

3867
	ret = i915_forcewake_create(minor->debugfs_root, minor);
3868 3869
	if (ret)
		return ret;
3870

3871 3872 3873 3874 3875 3876
	for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
		ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
		if (ret)
			return ret;
	}

3877 3878 3879 3880 3881 3882 3883
	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
		ret = i915_debugfs_create(minor->debugfs_root, minor,
					  i915_debugfs_files[i].name,
					  i915_debugfs_files[i].fops);
		if (ret)
			return ret;
	}
3884

3885 3886
	return drm_debugfs_create_files(i915_debugfs_list,
					I915_DEBUGFS_ENTRIES,
3887 3888 3889
					minor->debugfs_root, minor);
}

3890
void i915_debugfs_cleanup(struct drm_minor *minor)
3891
{
3892 3893
	int i;

3894 3895
	drm_debugfs_remove_files(i915_debugfs_list,
				 I915_DEBUGFS_ENTRIES, minor);
3896

3897 3898
	drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
				 1, minor);
3899

3900
	for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3901 3902 3903 3904 3905 3906
		struct drm_info_list *info_list =
			(struct drm_info_list *)&i915_pipe_crc_data[i];

		drm_debugfs_remove_files(info_list, 1, minor);
	}

3907 3908 3909 3910 3911 3912
	for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
		struct drm_info_list *info_list =
			(struct drm_info_list *) i915_debugfs_files[i].fops;

		drm_debugfs_remove_files(info_list, 1, minor);
	}
3913
}
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