amdgpu_dm.c 250.8 KB
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/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

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/* The caprices of the preprocessor require that this be declared right here */
#define CREATE_TRACE_POINTS

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#include "dm_services_types.h"
#include "dc.h"
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#include "dc/inc/core_types.h"
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#include "dal_asic_id.h"
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#include "dmub/dmub_srv.h"
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#include "dc/inc/hw/dmcu.h"
#include "dc/inc/hw/abm.h"
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#include "dc/dc_dmub_srv.h"
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#include "vid.h"
#include "amdgpu.h"
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#include "amdgpu_display.h"
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#include "amdgpu_ucode.h"
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#include "atom.h"
#include "amdgpu_dm.h"
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#ifdef CONFIG_DRM_AMD_DC_HDCP
#include "amdgpu_dm_hdcp.h"
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#include <drm/drm_hdcp.h>
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#endif
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#include "amdgpu_pm.h"
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#include "amd_shared.h"
#include "amdgpu_dm_irq.h"
#include "dm_helpers.h"
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#include "amdgpu_dm_mst_types.h"
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#if defined(CONFIG_DEBUG_FS)
#include "amdgpu_dm_debugfs.h"
#endif
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#include "ivsrcid/ivsrcid_vislands30.h"

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/version.h>
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#include <linux/types.h>
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#include <linux/pm_runtime.h>
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#include <linux/pci.h>
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#include <linux/firmware.h>
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#include <linux/component.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_uapi.h>
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#include <drm/drm_atomic_helper.h>
#include <drm/drm_dp_mst_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_edid.h>
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#include <drm/drm_vblank.h>
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#include <drm/drm_audio_component.h>
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#include <drm/drm_hdcp.h>
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
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#include "dcn/dcn_1_0_offset.h"
#include "dcn/dcn_1_0_sh_mask.h"
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#include "soc15_hw_ip.h"
#include "vega10_ip_offset.h"
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#include "soc15_common.h"
#endif

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#include "modules/inc/mod_freesync.h"
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#include "modules/power/power_helpers.h"
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#include "modules/inc/mod_info_packet.h"
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#define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
#endif
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#define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
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#define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);

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/* Number of bytes in PSP header for firmware. */
#define PSP_HEADER_BYTES 0x100

/* Number of bytes in PSP footer for firmware. */
#define PSP_FOOTER_BYTES 0x100

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/**
 * DOC: overview
 *
 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
 * requests into DC requests, and DC responses into DRM responses.
 *
 * The root control structure is &struct amdgpu_display_manager.
 */

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/* basic init/fini API */
static int amdgpu_dm_init(struct amdgpu_device *adev);
static void amdgpu_dm_fini(struct amdgpu_device *adev);

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/*
 * initializes drm_device display related structures, based on the information
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 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 * drm_encoder, drm_mode_config
 *
 * Returns 0 on success
 */
static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
/* removes and deallocates the drm structures, created by the above function */
static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);

static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
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				struct drm_plane *plane,
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				unsigned long possible_crtcs,
				const struct dc_plane_cap *plane_cap);
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static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
			       struct drm_plane *plane,
			       uint32_t link_index);
static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
				    struct amdgpu_dm_connector *amdgpu_dm_connector,
				    uint32_t link_index,
				    struct amdgpu_encoder *amdgpu_encoder);
static int amdgpu_dm_encoder_init(struct drm_device *dev,
				  struct amdgpu_encoder *aencoder,
				  uint32_t link_index);

static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);

static int amdgpu_dm_atomic_commit(struct drm_device *dev,
				   struct drm_atomic_state *state,
				   bool nonblock);

static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);

static int amdgpu_dm_atomic_check(struct drm_device *dev,
				  struct drm_atomic_state *state);

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static void handle_cursor_update(struct drm_plane *plane,
				 struct drm_plane_state *old_plane_state);
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static void amdgpu_dm_set_psr_caps(struct dc_link *link);
static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);


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/*
 * dm_vblank_get_counter
 *
 * @brief
 * Get counter for number of vertical blanks
 *
 * @param
 * struct amdgpu_device *adev - [in] desired amdgpu device
 * int disp_idx - [in] which CRTC to get the counter from
 *
 * @return
 * Counter for vertical blanks
 */
static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
{
	if (crtc >= adev->mode_info.num_crtc)
		return 0;
	else {
		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
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		struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
				acrtc->base.state);
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		if (acrtc_state->stream == NULL) {
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			DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
				  crtc);
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			return 0;
		}

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		return dc_stream_get_vblank_counter(acrtc_state->stream);
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	}
}

static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
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				  u32 *vbl, u32 *position)
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{
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	uint32_t v_blank_start, v_blank_end, h_position, v_position;

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	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
		return -EINVAL;
	else {
		struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
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		struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
						acrtc->base.state);
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		if (acrtc_state->stream ==  NULL) {
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			DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
				  crtc);
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			return 0;
		}

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		/*
		 * TODO rework base driver to use values directly.
		 * for now parse it back into reg-format
		 */
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		dc_stream_get_scanoutpos(acrtc_state->stream,
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					 &v_blank_start,
					 &v_blank_end,
					 &h_position,
					 &v_position);

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		*position = v_position | (h_position << 16);
		*vbl = v_blank_start | (v_blank_end << 16);
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	}

	return 0;
}

static bool dm_is_idle(void *handle)
{
	/* XXX todo */
	return true;
}

static int dm_wait_for_idle(void *handle)
{
	/* XXX todo */
	return 0;
}

static bool dm_check_soft_reset(void *handle)
{
	return false;
}

static int dm_soft_reset(void *handle)
{
	/* XXX todo */
	return 0;
}

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static struct amdgpu_crtc *
get_crtc_by_otg_inst(struct amdgpu_device *adev,
		     int otg_inst)
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{
	struct drm_device *dev = adev->ddev;
	struct drm_crtc *crtc;
	struct amdgpu_crtc *amdgpu_crtc;

	if (otg_inst == -1) {
		WARN_ON(1);
		return adev->mode_info.crtcs[0];
	}

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		amdgpu_crtc = to_amdgpu_crtc(crtc);

		if (amdgpu_crtc->otg_inst == otg_inst)
			return amdgpu_crtc;
	}

	return NULL;
}

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static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
{
	return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
	       dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
}

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/**
 * dm_pflip_high_irq() - Handle pageflip interrupt
 * @interrupt_params: ignored
 *
 * Handles the pageflip interrupt by notifying all interested parties
 * that the pageflip has been completed.
 */
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static void dm_pflip_high_irq(void *interrupt_params)
{
	struct amdgpu_crtc *amdgpu_crtc;
	struct common_irq_params *irq_params = interrupt_params;
	struct amdgpu_device *adev = irq_params->adev;
	unsigned long flags;
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	struct drm_pending_vblank_event *e;
	struct dm_crtc_state *acrtc_state;
	uint32_t vpos, hpos, v_blank_start, v_blank_end;
	bool vrr_active;
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	amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);

	/* IRQ could occur when in initial stage */
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	/* TODO work and BO cleanup */
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	if (amdgpu_crtc == NULL) {
		DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
		return;
	}

	spin_lock_irqsave(&adev->ddev->event_lock, flags);

	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
						 amdgpu_crtc->pflip_status,
						 AMDGPU_FLIP_SUBMITTED,
						 amdgpu_crtc->crtc_id,
						 amdgpu_crtc);
		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
		return;
	}

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	/* page flip completed. */
	e = amdgpu_crtc->event;
	amdgpu_crtc->event = NULL;
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	if (!e)
		WARN_ON(1);
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	acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
	vrr_active = amdgpu_dm_vrr_active(acrtc_state);

	/* Fixed refresh rate, or VRR scanout position outside front-porch? */
	if (!vrr_active ||
	    !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
				      &v_blank_end, &hpos, &vpos) ||
	    (vpos < v_blank_start)) {
		/* Update to correct count and vblank timestamp if racing with
		 * vblank irq. This also updates to the correct vblank timestamp
		 * even in VRR mode, as scanout is past the front-porch atm.
		 */
		drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
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		/* Wake up userspace by sending the pageflip event with proper
		 * count and timestamp of vblank of flip completion.
		 */
		if (e) {
			drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);

			/* Event sent, so done with vblank for this flip */
			drm_crtc_vblank_put(&amdgpu_crtc->base);
		}
	} else if (e) {
		/* VRR active and inside front-porch: vblank count and
		 * timestamp for pageflip event will only be up to date after
		 * drm_crtc_handle_vblank() has been executed from late vblank
		 * irq handler after start of back-porch (vline 0). We queue the
		 * pageflip event for send-out by drm_crtc_handle_vblank() with
		 * updated timestamp and count, once it runs after us.
		 *
		 * We need to open-code this instead of using the helper
		 * drm_crtc_arm_vblank_event(), as that helper would
		 * call drm_crtc_accurate_vblank_count(), which we must
		 * not call in VRR mode while we are in front-porch!
		 */

		/* sequence will be replaced by real count during send-out. */
		e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
		e->pipe = amdgpu_crtc->crtc_id;

		list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
		e = NULL;
	}
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	/* Keep track of vblank of this flip for flip throttling. We use the
	 * cooked hw counter, as that one incremented at start of this vblank
	 * of pageflip completion, so last_flip_vblank is the forbidden count
	 * for queueing new pageflips if vsync + VRR is enabled.
	 */
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	amdgpu_crtc->last_flip_vblank =
		amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
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	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
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	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);

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	DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
			 amdgpu_crtc->crtc_id, amdgpu_crtc,
			 vrr_active, (int) !e);
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}

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static void dm_vupdate_high_irq(void *interrupt_params)
{
	struct common_irq_params *irq_params = interrupt_params;
	struct amdgpu_device *adev = irq_params->adev;
	struct amdgpu_crtc *acrtc;
	struct dm_crtc_state *acrtc_state;
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	unsigned long flags;
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	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);

	if (acrtc) {
		acrtc_state = to_dm_crtc_state(acrtc->base.state);

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		DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d\n",
			      acrtc->crtc_id,
			      amdgpu_dm_vrr_active(acrtc_state));
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		/* Core vblank handling is done here after end of front-porch in
		 * vrr mode, as vblank timestamping will give valid results
		 * while now done after front-porch. This will also deliver
		 * page-flip completion events that have been queued to us
		 * if a pageflip happened inside front-porch.
		 */
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		if (amdgpu_dm_vrr_active(acrtc_state)) {
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			drm_crtc_handle_vblank(&acrtc->base);
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			/* BTR processing for pre-DCE12 ASICs */
			if (acrtc_state->stream &&
			    adev->family < AMDGPU_FAMILY_AI) {
				spin_lock_irqsave(&adev->ddev->event_lock, flags);
				mod_freesync_handle_v_update(
				    adev->dm.freesync_module,
				    acrtc_state->stream,
				    &acrtc_state->vrr_params);

				dc_stream_adjust_vmin_vmax(
				    adev->dm.dc,
				    acrtc_state->stream,
				    &acrtc_state->vrr_params.adjust);
				spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
			}
		}
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	}
}

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/**
 * dm_crtc_high_irq() - Handles CRTC interrupt
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 * @interrupt_params: used for determining the CRTC instance
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 *
 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 * event handler.
 */
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static void dm_crtc_high_irq(void *interrupt_params)
{
	struct common_irq_params *irq_params = interrupt_params;
	struct amdgpu_device *adev = irq_params->adev;
	struct amdgpu_crtc *acrtc;
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	struct dm_crtc_state *acrtc_state;
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	unsigned long flags;
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	acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
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	if (!acrtc)
		return;

	acrtc_state = to_dm_crtc_state(acrtc->base.state);

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	DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
			 amdgpu_dm_vrr_active(acrtc_state),
			 acrtc_state->active_planes);
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	/**
	 * Core vblank handling at start of front-porch is only possible
	 * in non-vrr mode, as only there vblank timestamping will give
	 * valid results while done in front-porch. Otherwise defer it
	 * to dm_vupdate_high_irq after end of front-porch.
	 */
	if (!amdgpu_dm_vrr_active(acrtc_state))
		drm_crtc_handle_vblank(&acrtc->base);

	/**
	 * Following stuff must happen at start of vblank, for crc
	 * computation and below-the-range btr support in vrr mode.
	 */
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	amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
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	/* BTR updates need to happen before VUPDATE on Vega and above. */
	if (adev->family < AMDGPU_FAMILY_AI)
		return;
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	spin_lock_irqsave(&adev->ddev->event_lock, flags);

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	if (acrtc_state->stream && acrtc_state->vrr_params.supported &&
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	    acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
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		mod_freesync_handle_v_update(adev->dm.freesync_module,
					     acrtc_state->stream,
					     &acrtc_state->vrr_params);
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		dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc_state->stream,
					   &acrtc_state->vrr_params.adjust);
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	}

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	/*
	 * If there aren't any active_planes then DCH HUBP may be clock-gated.
	 * In that case, pageflip completion interrupts won't fire and pageflip
	 * completion events won't get delivered. Prevent this by sending
	 * pending pageflip events from here if a flip is still pending.
	 *
	 * If any planes are enabled, use dm_pflip_high_irq() instead, to
	 * avoid race conditions between flip programming and completion,
	 * which could cause too early flip completion events.
	 */
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	if (adev->family >= AMDGPU_FAMILY_RV &&
	    acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
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	    acrtc_state->active_planes == 0) {
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		if (acrtc->event) {
			drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
			acrtc->event = NULL;
			drm_crtc_vblank_put(&acrtc->base);
		}
		acrtc->pflip_status = AMDGPU_FLIP_NONE;
	}

	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
}

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static int dm_set_clockgating_state(void *handle,
		  enum amd_clockgating_state state)
{
	return 0;
}

static int dm_set_powergating_state(void *handle,
		  enum amd_powergating_state state)
{
	return 0;
}

/* Prototypes of private functions */
static int dm_early_init(void* handle);

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/* Allocate memory for FBC compressed data  */
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static void amdgpu_dm_fbc_init(struct drm_connector *connector)
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{
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	struct drm_device *dev = connector->dev;
	struct amdgpu_device *adev = dev->dev_private;
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	struct dm_comressor_info *compressor = &adev->dm.compressor;
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	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
	struct drm_display_mode *mode;
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	unsigned long max_size = 0;

	if (adev->dm.dc->fbc_compressor == NULL)
		return;
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	if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
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		return;

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	if (compressor->bo_ptr)
		return;
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	list_for_each_entry(mode, &connector->modes, head) {
		if (max_size < mode->htotal * mode->vtotal)
			max_size = mode->htotal * mode->vtotal;
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	}

	if (max_size) {
		int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
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			    AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
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			    &compressor->gpu_addr, &compressor->cpu_addr);
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		if (r)
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			DRM_ERROR("DM: Failed to initialize FBC\n");
		else {
			adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
			DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
		}

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	}

}

582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702
static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
					  int pipe, bool *enabled,
					  unsigned char *buf, int max_bytes)
{
	struct drm_device *dev = dev_get_drvdata(kdev);
	struct amdgpu_device *adev = dev->dev_private;
	struct drm_connector *connector;
	struct drm_connector_list_iter conn_iter;
	struct amdgpu_dm_connector *aconnector;
	int ret = 0;

	*enabled = false;

	mutex_lock(&adev->dm.audio_lock);

	drm_connector_list_iter_begin(dev, &conn_iter);
	drm_for_each_connector_iter(connector, &conn_iter) {
		aconnector = to_amdgpu_dm_connector(connector);
		if (aconnector->audio_inst != port)
			continue;

		*enabled = true;
		ret = drm_eld_size(connector->eld);
		memcpy(buf, connector->eld, min(max_bytes, ret));

		break;
	}
	drm_connector_list_iter_end(&conn_iter);

	mutex_unlock(&adev->dm.audio_lock);

	DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);

	return ret;
}

static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
	.get_eld = amdgpu_dm_audio_component_get_eld,
};

static int amdgpu_dm_audio_component_bind(struct device *kdev,
				       struct device *hda_kdev, void *data)
{
	struct drm_device *dev = dev_get_drvdata(kdev);
	struct amdgpu_device *adev = dev->dev_private;
	struct drm_audio_component *acomp = data;

	acomp->ops = &amdgpu_dm_audio_component_ops;
	acomp->dev = kdev;
	adev->dm.audio_component = acomp;

	return 0;
}

static void amdgpu_dm_audio_component_unbind(struct device *kdev,
					  struct device *hda_kdev, void *data)
{
	struct drm_device *dev = dev_get_drvdata(kdev);
	struct amdgpu_device *adev = dev->dev_private;
	struct drm_audio_component *acomp = data;

	acomp->ops = NULL;
	acomp->dev = NULL;
	adev->dm.audio_component = NULL;
}

static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
	.bind	= amdgpu_dm_audio_component_bind,
	.unbind	= amdgpu_dm_audio_component_unbind,
};

static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
{
	int i, ret;

	if (!amdgpu_audio)
		return 0;

	adev->mode_info.audio.enabled = true;

	adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;

	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
		adev->mode_info.audio.pin[i].channels = -1;
		adev->mode_info.audio.pin[i].rate = -1;
		adev->mode_info.audio.pin[i].bits_per_sample = -1;
		adev->mode_info.audio.pin[i].status_bits = 0;
		adev->mode_info.audio.pin[i].category_code = 0;
		adev->mode_info.audio.pin[i].connected = false;
		adev->mode_info.audio.pin[i].id =
			adev->dm.dc->res_pool->audios[i]->inst;
		adev->mode_info.audio.pin[i].offset = 0;
	}

	ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
	if (ret < 0)
		return ret;

	adev->dm.audio_registered = true;

	return 0;
}

static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
{
	if (!amdgpu_audio)
		return;

	if (!adev->mode_info.audio.enabled)
		return;

	if (adev->dm.audio_registered) {
		component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
		adev->dm.audio_registered = false;
	}

	/* TODO: Disable audio? */

	adev->mode_info.audio.enabled = false;
}

703
static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
704 705 706 707 708 709 710 711 712 713 714
{
	struct drm_audio_component *acomp = adev->dm.audio_component;

	if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
		DRM_DEBUG_KMS("Notify ELD: %d\n", pin);

		acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
						 pin, -1);
	}
}

715 716 717 718
static int dm_dmub_hw_init(struct amdgpu_device *adev)
{
	const struct dmcub_firmware_header_v1_0 *hdr;
	struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
719
	struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
720 721 722 723 724 725
	const struct firmware *dmub_fw = adev->dm.dmub_fw;
	struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
	struct abm *abm = adev->dm.dc->res_pool->abm;
	struct dmub_srv_hw_params hw_params;
	enum dmub_status status;
	const unsigned char *fw_inst_const, *fw_bss_data;
726
	uint32_t i, fw_inst_const_size, fw_bss_data_size;
727 728 729 730 731 732
	bool has_hw_support;

	if (!dmub_srv)
		/* DMUB isn't supported on the ASIC. */
		return 0;

733 734 735 736 737
	if (!fb_info) {
		DRM_ERROR("No framebuffer info for DMUB service.\n");
		return -EINVAL;
	}

738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758
	if (!dmub_fw) {
		/* Firmware required for DMUB support. */
		DRM_ERROR("No firmware provided for DMUB.\n");
		return -EINVAL;
	}

	status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
	if (status != DMUB_STATUS_OK) {
		DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
		return -EINVAL;
	}

	if (!has_hw_support) {
		DRM_INFO("DMUB unsupported on ASIC\n");
		return 0;
	}

	hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;

	fw_inst_const = dmub_fw->data +
			le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
759
			PSP_HEADER_BYTES;
760 761 762 763 764 765

	fw_bss_data = dmub_fw->data +
		      le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
		      le32_to_cpu(hdr->inst_const_bytes);

	/* Copy firmware and bios info into FB memory. */
766 767 768 769 770
	fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
			     PSP_HEADER_BYTES - PSP_FOOTER_BYTES;

	fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);

771 772 773 774 775 776 777 778 779 780
	/* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
	 * amdgpu_ucode_init_single_fw will load dmub firmware
	 * fw_inst_const part to cw0; otherwise, the firmware back door load
	 * will be done by dm_dmub_hw_init
	 */
	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
		memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
				fw_inst_const_size);
	}

781 782 783
	if (fw_bss_data_size)
		memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
		       fw_bss_data, fw_bss_data_size);
784 785

	/* Copy firmware bios info into FB memory. */
786 787 788 789 790 791 792 793 794 795 796 797
	memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
	       adev->bios_size);

	/* Reset regions that need to be reset. */
	memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
	fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);

	memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
	       fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);

	memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
	       fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
798 799 800 801 802 803

	/* Initialize hardware. */
	memset(&hw_params, 0, sizeof(hw_params));
	hw_params.fb_base = adev->gmc.fb_start;
	hw_params.fb_offset = adev->gmc.aper_base;

H
Hersen Wu 已提交
804 805 806 807
	/* backdoor load firmware and trigger dmub running */
	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
		hw_params.load_inst_const = true;

808 809 810
	if (dmcu)
		hw_params.psp_version = dmcu->psp_version;

811 812
	for (i = 0; i < fb_info->num_fb; ++i)
		hw_params.fb[i] = &fb_info->fb[i];
813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830

	status = dmub_srv_hw_init(dmub_srv, &hw_params);
	if (status != DMUB_STATUS_OK) {
		DRM_ERROR("Error initializing DMUB HW: %d\n", status);
		return -EINVAL;
	}

	/* Wait for firmware load to finish. */
	status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
	if (status != DMUB_STATUS_OK)
		DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);

	/* Init DMCU and ABM if available. */
	if (dmcu && abm) {
		dmcu->funcs->dmcu_init(dmcu);
		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
	}

831 832 833 834 835 836
	adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
	if (!adev->dm.dc->ctx->dmub_srv) {
		DRM_ERROR("Couldn't allocate DC DMUB server!\n");
		return -ENOMEM;
	}

837 838 839 840 841 842
	DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
		 adev->dm.dmcub_fw_version);

	return 0;
}

843
static int amdgpu_dm_init(struct amdgpu_device *adev)
844 845
{
	struct dc_init_data init_data;
846 847 848
#ifdef CONFIG_DRM_AMD_DC_HDCP
	struct dc_callback_init init_params;
#endif
849
	int r;
850

851 852 853 854 855
	adev->dm.ddev = adev->ddev;
	adev->dm.adev = adev;

	/* Zero all the fields */
	memset(&init_data, 0, sizeof(init_data));
856 857 858
#ifdef CONFIG_DRM_AMD_DC_HDCP
	memset(&init_params, 0, sizeof(init_params));
#endif
859

860
	mutex_init(&adev->dm.dc_lock);
861
	mutex_init(&adev->dm.audio_lock);
862

863 864 865 866 867 868 869
	if(amdgpu_dm_irq_init(adev)) {
		DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
		goto error;
	}

	init_data.asic_id.chip_family = adev->family;

870
	init_data.asic_id.pci_revision_id = adev->pdev->revision;
871 872
	init_data.asic_id.hw_internal_rev = adev->external_rev_id;

873
	init_data.asic_id.vram_width = adev->gmc.vram_width;
874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890
	/* TODO: initialize init_data.asic_id.vram_type here!!!! */
	init_data.asic_id.atombios_base_address =
		adev->mode_info.atom_context->bios;

	init_data.driver = adev;

	adev->dm.cgs_device = amdgpu_cgs_create_device(adev);

	if (!adev->dm.cgs_device) {
		DRM_ERROR("amdgpu: failed to create cgs device.\n");
		goto error;
	}

	init_data.cgs_device = adev->dm.cgs_device;

	init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;

891 892 893 894
	switch (adev->asic_type) {
	case CHIP_CARRIZO:
	case CHIP_STONEY:
	case CHIP_RAVEN:
895
	case CHIP_RENOIR:
896
		init_data.flags.gpu_vm_support = true;
897 898 899 900
		break;
	default:
		break;
	}
901

902 903 904
	if (amdgpu_dc_feature_mask & DC_FBC_MASK)
		init_data.flags.fbc_support = true;

905 906 907
	if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
		init_data.flags.multi_mon_pp_mclk_switch = true;

908 909 910
	if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
		init_data.flags.disable_fractional_pwm = true;

911
	init_data.flags.power_down_display_on_boot = true;
912

913
	init_data.soc_bounding_box = adev->dm.soc_bounding_box;
914

915 916 917
	/* Display Core create. */
	adev->dm.dc = dc_create(&init_data);

918
	if (adev->dm.dc) {
919
		DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
920
	} else {
921
		DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
922 923
		goto error;
	}
924

925 926 927 928 929
	if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
		adev->dm.dc->debug.force_single_disp_pipe_split = false;
		adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
	}

930 931 932
	if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
		adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;

933 934 935 936 937 938 939 940 941
	if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
		adev->dm.dc->debug.disable_stutter = true;

	if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
		adev->dm.dc->debug.disable_dsc = true;

	if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
		adev->dm.dc->debug.disable_clock_gate = true;

942 943 944 945 946 947
	r = dm_dmub_hw_init(adev);
	if (r) {
		DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
		goto error;
	}

948 949
	dc_hardware_init(adev->dm.dc);

950 951 952 953 954
	adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
	if (!adev->dm.freesync_module) {
		DRM_ERROR(
		"amdgpu: failed to initialize freesync_module.\n");
	} else
955
		DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
956 957
				adev->dm.freesync_module);

958 959
	amdgpu_dm_init_color_mod();

960
#ifdef CONFIG_DRM_AMD_DC_HDCP
961
	if (adev->asic_type >= CHIP_RAVEN) {
962
		adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
963

964 965 966 967
		if (!adev->dm.hdcp_workqueue)
			DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
		else
			DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
968

969 970
		dc_init_callbacks(adev->dm.dc, &init_params);
	}
971
#endif
972 973 974 975 976 977 978 979 980 981 982 983
	if (amdgpu_dm_initialize_drm_device(adev)) {
		DRM_ERROR(
		"amdgpu: failed to initialize sw for display support.\n");
		goto error;
	}

	/* Update the actual used number of crtc */
	adev->mode_info.num_crtc = adev->dm.display_indexes_num;

	/* TODO: Add_display_info? */

	/* TODO use dynamic cursor width */
984 985
	adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
	adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
986 987 988 989 990 991 992

	if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
		DRM_ERROR(
		"amdgpu: failed to initialize sw for display support.\n");
		goto error;
	}

993
	DRM_DEBUG_DRIVER("KMS initialized.\n");
994 995 996 997 998

	return 0;
error:
	amdgpu_dm_fini(adev);

999
	return -EINVAL;
1000 1001
}

1002
static void amdgpu_dm_fini(struct amdgpu_device *adev)
1003
{
1004 1005
	amdgpu_dm_audio_fini(adev);

1006
	amdgpu_dm_destroy_drm_device(&adev->dm);
E
Emily Deng 已提交
1007

1008 1009 1010 1011 1012 1013 1014 1015 1016
#ifdef CONFIG_DRM_AMD_DC_HDCP
	if (adev->dm.hdcp_workqueue) {
		hdcp_destroy(adev->dm.hdcp_workqueue);
		adev->dm.hdcp_workqueue = NULL;
	}

	if (adev->dm.dc)
		dc_deinit_callbacks(adev->dm.dc);
#endif
1017 1018 1019 1020 1021
	if (adev->dm.dc->ctx->dmub_srv) {
		dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
		adev->dm.dc->ctx->dmub_srv = NULL;
	}

1022 1023 1024 1025
	if (adev->dm.dmub_bo)
		amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
				      &adev->dm.dmub_bo_gpu_addr,
				      &adev->dm.dmub_bo_cpu_addr);
1026

E
Emily Deng 已提交
1027 1028 1029
	/* DC Destroy TODO: Replace destroy DAL */
	if (adev->dm.dc)
		dc_destroy(&adev->dm.dc);
1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043
	/*
	 * TODO: pageflip, vlank interrupt
	 *
	 * amdgpu_dm_irq_fini(adev);
	 */

	if (adev->dm.cgs_device) {
		amdgpu_cgs_destroy_device(adev->dm.cgs_device);
		adev->dm.cgs_device = NULL;
	}
	if (adev->dm.freesync_module) {
		mod_freesync_destroy(adev->dm.freesync_module);
		adev->dm.freesync_module = NULL;
	}
1044

1045
	mutex_destroy(&adev->dm.audio_lock);
1046 1047
	mutex_destroy(&adev->dm.dc_lock);

1048 1049 1050
	return;
}

D
David Francis 已提交
1051
static int load_dmcu_fw(struct amdgpu_device *adev)
1052
{
1053
	const char *fw_name_dmcu = NULL;
D
David Francis 已提交
1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073
	int r;
	const struct dmcu_firmware_header_v1_0 *hdr;

	switch(adev->asic_type) {
	case CHIP_BONAIRE:
	case CHIP_HAWAII:
	case CHIP_KAVERI:
	case CHIP_KABINI:
	case CHIP_MULLINS:
	case CHIP_TONGA:
	case CHIP_FIJI:
	case CHIP_CARRIZO:
	case CHIP_STONEY:
	case CHIP_POLARIS11:
	case CHIP_POLARIS10:
	case CHIP_POLARIS12:
	case CHIP_VEGAM:
	case CHIP_VEGA10:
	case CHIP_VEGA12:
	case CHIP_VEGA20:
1074
	case CHIP_NAVI10:
1075
	case CHIP_NAVI14:
1076
	case CHIP_RENOIR:
1077 1078 1079
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	case CHIP_SIENNA_CICHLID:
#endif
D
David Francis 已提交
1080
		return 0;
1081 1082 1083
	case CHIP_NAVI12:
		fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
		break;
D
David Francis 已提交
1084
	case CHIP_RAVEN:
1085 1086 1087 1088 1089 1090
		if (ASICREV_IS_PICASSO(adev->external_rev_id))
			fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
		else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
			fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
		else
			return 0;
D
David Francis 已提交
1091 1092 1093
		break;
	default:
		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1094
		return -EINVAL;
D
David Francis 已提交
1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134
	}

	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
		DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
		return 0;
	}

	r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
	if (r == -ENOENT) {
		/* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
		DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
		adev->dm.fw_dmcu = NULL;
		return 0;
	}
	if (r) {
		dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
			fw_name_dmcu);
		return r;
	}

	r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
	if (r) {
		dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
			fw_name_dmcu);
		release_firmware(adev->dm.fw_dmcu);
		adev->dm.fw_dmcu = NULL;
		return r;
	}

	hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
	adev->firmware.fw_size +=
		ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);

	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
	adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
	adev->firmware.fw_size +=
		ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);

1135 1136
	adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);

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1137 1138
	DRM_DEBUG_KMS("PSP loading DMCU firmware\n");

1139 1140 1141
	return 0;
}

1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159
static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
{
	struct amdgpu_device *adev = ctx;

	return dm_read_reg(adev->dm.dc->ctx, address);
}

static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
				     uint32_t value)
{
	struct amdgpu_device *adev = ctx;

	return dm_write_reg(adev->dm.dc->ctx, address, value);
}

static int dm_dmub_sw_init(struct amdgpu_device *adev)
{
	struct dmub_srv_create_params create_params;
1160 1161 1162 1163 1164
	struct dmub_srv_region_params region_params;
	struct dmub_srv_region_info region_info;
	struct dmub_srv_fb_params fb_params;
	struct dmub_srv_fb_info *fb_info;
	struct dmub_srv *dmub_srv;
1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
	const struct dmcub_firmware_header_v1_0 *hdr;
	const char *fw_name_dmub;
	enum dmub_asic dmub_asic;
	enum dmub_status status;
	int r;

	switch (adev->asic_type) {
	case CHIP_RENOIR:
		dmub_asic = DMUB_ASIC_DCN21;
		fw_name_dmub = FIRMWARE_RENOIR_DMUB;
		break;
1176 1177 1178 1179 1180 1181
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	case CHIP_SIENNA_CICHLID:
		dmub_asic = DMUB_ASIC_DCN30;
		fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
		break;
#endif
1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201

	default:
		/* ASIC doesn't support DMUB. */
		return 0;
	}

	r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
	if (r) {
		DRM_ERROR("DMUB firmware loading failed: %d\n", r);
		return 0;
	}

	r = amdgpu_ucode_validate(adev->dm.dmub_fw);
	if (r) {
		DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
		return 0;
	}

	hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;

1202 1203 1204 1205 1206 1207 1208
	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
		adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
			AMDGPU_UCODE_ID_DMCUB;
		adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
			adev->dm.dmub_fw;
		adev->firmware.fw_size +=
			ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
1209

1210 1211 1212 1213 1214
		DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
			 adev->dm.dmcub_fw_version);
	}

	adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
1215

1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243
	adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
	dmub_srv = adev->dm.dmub_srv;

	if (!dmub_srv) {
		DRM_ERROR("Failed to allocate DMUB service!\n");
		return -ENOMEM;
	}

	memset(&create_params, 0, sizeof(create_params));
	create_params.user_ctx = adev;
	create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
	create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
	create_params.asic = dmub_asic;

	/* Create the DMUB service. */
	status = dmub_srv_create(dmub_srv, &create_params);
	if (status != DMUB_STATUS_OK) {
		DRM_ERROR("Error creating DMUB service: %d\n", status);
		return -EINVAL;
	}

	/* Calculate the size of all the regions for the DMUB service. */
	memset(&region_params, 0, sizeof(region_params));

	region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
					PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
	region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
	region_params.vbios_size = adev->bios_size;
1244
	region_params.fw_bss_data = region_params.bss_data_size ?
1245 1246
		adev->dm.dmub_fw->data +
		le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1247
		le32_to_cpu(hdr->inst_const_bytes) : NULL;
1248 1249 1250 1251
	region_params.fw_inst_const =
		adev->dm.dmub_fw->data +
		le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
		PSP_HEADER_BYTES;
1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293

	status = dmub_srv_calc_region_info(dmub_srv, &region_params,
					   &region_info);

	if (status != DMUB_STATUS_OK) {
		DRM_ERROR("Error calculating DMUB region info: %d\n", status);
		return -EINVAL;
	}

	/*
	 * Allocate a framebuffer based on the total size of all the regions.
	 * TODO: Move this into GART.
	 */
	r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
				    AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
				    &adev->dm.dmub_bo_gpu_addr,
				    &adev->dm.dmub_bo_cpu_addr);
	if (r)
		return r;

	/* Rebase the regions on the framebuffer address. */
	memset(&fb_params, 0, sizeof(fb_params));
	fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
	fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
	fb_params.region_info = &region_info;

	adev->dm.dmub_fb_info =
		kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
	fb_info = adev->dm.dmub_fb_info;

	if (!fb_info) {
		DRM_ERROR(
			"Failed to allocate framebuffer info for DMUB service!\n");
		return -ENOMEM;
	}

	status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
	if (status != DMUB_STATUS_OK) {
		DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
		return -EINVAL;
	}

1294 1295 1296
	return 0;
}

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1297 1298 1299
static int dm_sw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1300 1301 1302 1303 1304
	int r;

	r = dm_dmub_sw_init(adev);
	if (r)
		return r;
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1305 1306 1307 1308

	return load_dmcu_fw(adev);
}

1309 1310
static int dm_sw_fini(void *handle)
{
D
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1311 1312
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

1313 1314 1315
	kfree(adev->dm.dmub_fb_info);
	adev->dm.dmub_fb_info = NULL;

1316 1317 1318 1319 1320 1321 1322 1323 1324 1325
	if (adev->dm.dmub_srv) {
		dmub_srv_destroy(adev->dm.dmub_srv);
		adev->dm.dmub_srv = NULL;
	}

	if (adev->dm.dmub_fw) {
		release_firmware(adev->dm.dmub_fw);
		adev->dm.dmub_fw = NULL;
	}

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1326 1327 1328 1329 1330
	if(adev->dm.fw_dmcu) {
		release_firmware(adev->dm.fw_dmcu);
		adev->dm.fw_dmcu = NULL;
	}

1331 1332 1333
	return 0;
}

1334
static int detect_mst_link_for_all_connectors(struct drm_device *dev)
1335
{
1336
	struct amdgpu_dm_connector *aconnector;
1337
	struct drm_connector *connector;
1338
	struct drm_connector_list_iter iter;
1339
	int ret = 0;
1340

1341 1342
	drm_connector_list_iter_begin(dev, &iter);
	drm_for_each_connector_iter(connector, &iter) {
1343
		aconnector = to_amdgpu_dm_connector(connector);
1344 1345
		if (aconnector->dc_link->type == dc_connection_mst_branch &&
		    aconnector->mst_mgr.aux) {
1346
			DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
1347 1348
					 aconnector,
					 aconnector->base.base.id);
1349 1350 1351 1352

			ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
			if (ret < 0) {
				DRM_ERROR("DM_MST: Failed to start MST\n");
1353 1354 1355
				aconnector->dc_link->type =
					dc_connection_single;
				break;
1356
			}
1357
		}
1358
	}
1359
	drm_connector_list_iter_end(&iter);
1360

1361 1362 1363 1364 1365
	return ret;
}

static int dm_late_init(void *handle)
{
1366
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1367

D
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1368 1369 1370
	struct dmcu_iram_parameters params;
	unsigned int linear_lut[16];
	int i;
1371
	struct dmcu *dmcu = NULL;
1372
	bool ret;
D
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1373

1374 1375 1376 1377 1378
	if (!adev->dm.fw_dmcu)
		return detect_mst_link_for_all_connectors(adev->ddev);

	dmcu = adev->dm.dc->res_pool->dmcu;

D
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1379 1380 1381 1382 1383 1384 1385 1386 1387
	for (i = 0; i < 16; i++)
		linear_lut[i] = 0xFFFF * i / 15;

	params.set = 0;
	params.backlight_ramping_start = 0xCCCC;
	params.backlight_ramping_reduction = 0xCCCCCCCC;
	params.backlight_lut_array_size = 16;
	params.backlight_lut_array = linear_lut;

1388 1389 1390 1391 1392
	/* Min backlight level after ABM reduction,  Don't allow below 1%
	 * 0xFFFF x 0.01 = 0x28F
	 */
	params.min_abm_backlight = 0x28F;

1393
	ret = dmcu_load_iram(dmcu, params);
D
David Francis 已提交
1394

1395 1396
	if (!ret)
		return -EINVAL;
D
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1397

1398
	return detect_mst_link_for_all_connectors(adev->ddev);
1399 1400 1401 1402
}

static void s3_handle_mst(struct drm_device *dev, bool suspend)
{
1403
	struct amdgpu_dm_connector *aconnector;
1404
	struct drm_connector *connector;
1405
	struct drm_connector_list_iter iter;
1406 1407 1408
	struct drm_dp_mst_topology_mgr *mgr;
	int ret;
	bool need_hotplug = false;
1409

1410 1411
	drm_connector_list_iter_begin(dev, &iter);
	drm_for_each_connector_iter(connector, &iter) {
1412 1413 1414 1415 1416 1417 1418 1419 1420 1421
		aconnector = to_amdgpu_dm_connector(connector);
		if (aconnector->dc_link->type != dc_connection_mst_branch ||
		    aconnector->mst_port)
			continue;

		mgr = &aconnector->mst_mgr;

		if (suspend) {
			drm_dp_mst_topology_mgr_suspend(mgr);
		} else {
1422
			ret = drm_dp_mst_topology_mgr_resume(mgr, true);
1423 1424 1425 1426 1427
			if (ret < 0) {
				drm_dp_mst_topology_mgr_set_mst(mgr, false);
				need_hotplug = true;
			}
		}
1428
	}
1429
	drm_connector_list_iter_end(&iter);
1430 1431 1432

	if (need_hotplug)
		drm_kms_helper_hotplug_event(dev);
1433 1434
}

1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501
static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
{
	struct smu_context *smu = &adev->smu;
	int ret = 0;

	if (!is_support_sw_smu(adev))
		return 0;

	/* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
	 * on window driver dc implementation.
	 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
	 * should be passed to smu during boot up and resume from s3.
	 * boot up: dc calculate dcn watermark clock settings within dc_create,
	 * dcn20_resource_construct
	 * then call pplib functions below to pass the settings to smu:
	 * smu_set_watermarks_for_clock_ranges
	 * smu_set_watermarks_table
	 * navi10_set_watermarks_table
	 * smu_write_watermarks_table
	 *
	 * For Renoir, clock settings of dcn watermark are also fixed values.
	 * dc has implemented different flow for window driver:
	 * dc_hardware_init / dc_set_power_state
	 * dcn10_init_hw
	 * notify_wm_ranges
	 * set_wm_ranges
	 * -- Linux
	 * smu_set_watermarks_for_clock_ranges
	 * renoir_set_watermarks_table
	 * smu_write_watermarks_table
	 *
	 * For Linux,
	 * dc_hardware_init -> amdgpu_dm_init
	 * dc_set_power_state --> dm_resume
	 *
	 * therefore, this function apply to navi10/12/14 but not Renoir
	 * *
	 */
	switch(adev->asic_type) {
	case CHIP_NAVI10:
	case CHIP_NAVI14:
	case CHIP_NAVI12:
		break;
	default:
		return 0;
	}

	mutex_lock(&smu->mutex);

	/* pass data to smu controller */
	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
			!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
		ret = smu_write_watermarks_table(smu);

		if (ret) {
			mutex_unlock(&smu->mutex);
			DRM_ERROR("Failed to update WMTABLE!\n");
			return ret;
		}
		smu->watermarks_bitmap |= WATERMARKS_LOADED;
	}

	mutex_unlock(&smu->mutex);

	return 0;
}

1502 1503
/**
 * dm_hw_init() - Initialize DC device
1504
 * @handle: The base driver device containing the amdgpu_dm device.
1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521
 *
 * Initialize the &struct amdgpu_display_manager device. This involves calling
 * the initializers of each DM component, then populating the struct with them.
 *
 * Although the function implies hardware initialization, both hardware and
 * software are initialized here. Splitting them out to their relevant init
 * hooks is a future TODO item.
 *
 * Some notable things that are initialized here:
 *
 * - Display Core, both software and hardware
 * - DC modules that we need (freesync and color management)
 * - DRM software states
 * - Interrupt sources and handlers
 * - Vblank support
 * - Debug FS entries, if enabled
 */
1522 1523 1524 1525 1526 1527 1528 1529 1530 1531
static int dm_hw_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
	/* Create DAL display manager */
	amdgpu_dm_init(adev);
	amdgpu_dm_hpd_init(adev);

	return 0;
}

1532 1533
/**
 * dm_hw_fini() - Teardown DC device
1534
 * @handle: The base driver device containing the amdgpu_dm device.
1535 1536 1537 1538 1539
 *
 * Teardown components within &struct amdgpu_display_manager that require
 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
 * were loaded. Also flush IRQ workqueues and disable them.
 */
1540 1541 1542 1543 1544 1545 1546
static int dm_hw_fini(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	amdgpu_dm_hpd_fini(adev);

	amdgpu_dm_irq_fini(adev);
1547
	amdgpu_dm_fini(adev);
1548 1549 1550
	return 0;
}

1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588

static int dm_enable_vblank(struct drm_crtc *crtc);
static void dm_disable_vblank(struct drm_crtc *crtc);

static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
				 struct dc_state *state, bool enable)
{
	enum dc_irq_source irq_source;
	struct amdgpu_crtc *acrtc;
	int rc = -EBUSY;
	int i = 0;

	for (i = 0; i < state->stream_count; i++) {
		acrtc = get_crtc_by_otg_inst(
				adev, state->stream_status[i].primary_otg_inst);

		if (acrtc && state->stream_status[i].plane_count != 0) {
			irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
			rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
			DRM_DEBUG("crtc %d - vupdate irq %sabling: r=%d\n",
				  acrtc->crtc_id, enable ? "en" : "dis", rc);
			if (rc)
				DRM_WARN("Failed to %s pflip interrupts\n",
					 enable ? "enable" : "disable");

			if (enable) {
				rc = dm_enable_vblank(&acrtc->base);
				if (rc)
					DRM_WARN("Failed to enable vblank interrupts\n");
			} else {
				dm_disable_vblank(&acrtc->base);
			}

		}
	}

}

1589
static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640
{
	struct dc_state *context = NULL;
	enum dc_status res = DC_ERROR_UNEXPECTED;
	int i;
	struct dc_stream_state *del_streams[MAX_PIPES];
	int del_streams_count = 0;

	memset(del_streams, 0, sizeof(del_streams));

	context = dc_create_state(dc);
	if (context == NULL)
		goto context_alloc_fail;

	dc_resource_state_copy_construct_current(dc, context);

	/* First remove from context all streams */
	for (i = 0; i < context->stream_count; i++) {
		struct dc_stream_state *stream = context->streams[i];

		del_streams[del_streams_count++] = stream;
	}

	/* Remove all planes for removed streams and then remove the streams */
	for (i = 0; i < del_streams_count; i++) {
		if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
			res = DC_FAIL_DETACH_SURFACES;
			goto fail;
		}

		res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
		if (res != DC_OK)
			goto fail;
	}


	res = dc_validate_global_state(dc, context, false);

	if (res != DC_OK) {
		DRM_ERROR("%s:resource validation failed, dc_status:%d\n", __func__, res);
		goto fail;
	}

	res = dc_commit_state(dc, context);

fail:
	dc_release_state(context);

context_alloc_fail:
	return res;
}

1641 1642 1643 1644
static int dm_suspend(void *handle)
{
	struct amdgpu_device *adev = handle;
	struct amdgpu_display_manager *dm = &adev->dm;
1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658
	int ret = 0;

	if (adev->in_gpu_reset) {
		mutex_lock(&dm->dc_lock);
		dm->cached_dc_state = dc_copy_state(dm->dc->current_state);

		dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);

		amdgpu_dm_commit_zero_streams(dm->dc);

		amdgpu_dm_irq_suspend(adev);

		return ret;
	}
1659

1660 1661 1662
	WARN_ON(adev->dm.cached_state);
	adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);

1663 1664 1665 1666
	s3_handle_mst(adev->ddev, true);

	amdgpu_dm_irq_suspend(adev);

1667

1668
	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1669

1670
	return 0;
1671 1672
}

1673 1674 1675
static struct amdgpu_dm_connector *
amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
					     struct drm_crtc *crtc)
1676 1677
{
	uint32_t i;
1678
	struct drm_connector_state *new_con_state;
1679 1680 1681
	struct drm_connector *connector;
	struct drm_crtc *crtc_from_state;

1682 1683
	for_each_new_connector_in_state(state, connector, new_con_state, i) {
		crtc_from_state = new_con_state->crtc;
1684 1685

		if (crtc_from_state == crtc)
1686
			return to_amdgpu_dm_connector(connector);
1687 1688 1689 1690 1691
	}

	return NULL;
}

1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760
static void emulated_link_detect(struct dc_link *link)
{
	struct dc_sink_init_data sink_init_data = { 0 };
	struct display_sink_capability sink_caps = { 0 };
	enum dc_edid_status edid_status;
	struct dc_context *dc_ctx = link->ctx;
	struct dc_sink *sink = NULL;
	struct dc_sink *prev_sink = NULL;

	link->type = dc_connection_none;
	prev_sink = link->local_sink;

	if (prev_sink != NULL)
		dc_sink_retain(prev_sink);

	switch (link->connector_signal) {
	case SIGNAL_TYPE_HDMI_TYPE_A: {
		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
		sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
		break;
	}

	case SIGNAL_TYPE_DVI_SINGLE_LINK: {
		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
		sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
		break;
	}

	case SIGNAL_TYPE_DVI_DUAL_LINK: {
		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
		sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
		break;
	}

	case SIGNAL_TYPE_LVDS: {
		sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
		sink_caps.signal = SIGNAL_TYPE_LVDS;
		break;
	}

	case SIGNAL_TYPE_EDP: {
		sink_caps.transaction_type =
			DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
		sink_caps.signal = SIGNAL_TYPE_EDP;
		break;
	}

	case SIGNAL_TYPE_DISPLAY_PORT: {
		sink_caps.transaction_type =
			DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
		sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
		break;
	}

	default:
		DC_ERROR("Invalid connector type! signal:%d\n",
			link->connector_signal);
		return;
	}

	sink_init_data.link = link;
	sink_init_data.sink_signal = sink_caps.signal;

	sink = dc_sink_create(&sink_init_data);
	if (!sink) {
		DC_ERROR("Failed to create sink!\n");
		return;
	}

1761
	/* dc_sink_create returns a new reference */
1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773
	link->local_sink = sink;

	edid_status = dm_helpers_read_local_edid(
			link->ctx,
			link,
			sink);

	if (edid_status != EDID_OK)
		DC_ERROR("Failed to read EDID");

}

1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813
static void dm_gpureset_commit_state(struct dc_state *dc_state,
				     struct amdgpu_display_manager *dm)
{
	struct {
		struct dc_surface_update surface_updates[MAX_SURFACES];
		struct dc_plane_info plane_infos[MAX_SURFACES];
		struct dc_scaling_info scaling_infos[MAX_SURFACES];
		struct dc_flip_addrs flip_addrs[MAX_SURFACES];
		struct dc_stream_update stream_update;
	} * bundle;
	int k, m;

	bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);

	if (!bundle) {
		dm_error("Failed to allocate update bundle\n");
		goto cleanup;
	}

	for (k = 0; k < dc_state->stream_count; k++) {
		bundle->stream_update.stream = dc_state->streams[k];

		for (m = 0; m < dc_state->stream_status->plane_count; m++) {
			bundle->surface_updates[m].surface =
				dc_state->stream_status->plane_states[m];
			bundle->surface_updates[m].surface->force_full_update =
				true;
		}
		dc_commit_updates_for_stream(
			dm->dc, bundle->surface_updates,
			dc_state->stream_status->plane_count,
			dc_state->streams[k], &bundle->stream_update, dc_state);
	}

cleanup:
	kfree(bundle);

	return;
}

1814 1815 1816 1817 1818
static int dm_resume(void *handle)
{
	struct amdgpu_device *adev = handle;
	struct drm_device *ddev = adev->ddev;
	struct amdgpu_display_manager *dm = &adev->dm;
1819
	struct amdgpu_dm_connector *aconnector;
1820
	struct drm_connector *connector;
1821
	struct drm_connector_list_iter iter;
1822
	struct drm_crtc *crtc;
1823
	struct drm_crtc_state *new_crtc_state;
1824 1825 1826 1827
	struct dm_crtc_state *dm_new_crtc_state;
	struct drm_plane *plane;
	struct drm_plane_state *new_plane_state;
	struct dm_plane_state *dm_new_plane_state;
1828
	struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
1829
	enum dc_connection_type new_connection_type = dc_connection_none;
1830 1831
	struct dc_state *dc_state;
	int i, r, j;
1832

1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867
	if (adev->in_gpu_reset) {
		dc_state = dm->cached_dc_state;

		r = dm_dmub_hw_init(adev);
		if (r)
			DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);

		dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
		dc_resume(dm->dc);

		amdgpu_dm_irq_resume_early(adev);

		for (i = 0; i < dc_state->stream_count; i++) {
			dc_state->streams[i]->mode_changed = true;
			for (j = 0; j < dc_state->stream_status->plane_count; j++) {
				dc_state->stream_status->plane_states[j]->update_flags.raw
					= 0xffffffff;
			}
		}

		WARN_ON(!dc_commit_state(dm->dc, dc_state));

		dm_gpureset_commit_state(dm->cached_dc_state, dm);

		dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);

		dc_release_state(dm->cached_dc_state);
		dm->cached_dc_state = NULL;

		amdgpu_dm_irq_resume_late(adev);

		mutex_unlock(&dm->dc_lock);

		return 0;
	}
1868 1869 1870 1871 1872 1873
	/* Recreate dc_state - DC invalidates it when setting power state to S3. */
	dc_release_state(dm_state->context);
	dm_state->context = dc_create_state(dm->dc);
	/* TODO: Remove dc_state->dccg, use dc->dccg directly. */
	dc_resource_state_construct(dm->dc, dm_state->context);

1874 1875 1876 1877 1878
	/* Before powering on DC we need to re-initialize DMUB. */
	r = dm_dmub_hw_init(adev);
	if (r)
		DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);

1879 1880 1881
	/* power on hardware */
	dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);

1882 1883 1884 1885 1886 1887 1888 1889 1890
	/* program HPD filter */
	dc_resume(dm->dc);

	/*
	 * early enable HPD Rx IRQ, should be done before set mode as short
	 * pulse interrupts are used for MST
	 */
	amdgpu_dm_irq_resume_early(adev);

1891
	/* On resume we need to rewrite the MSTM control bits to enable MST*/
1892 1893
	s3_handle_mst(ddev, false);

1894
	/* Do detection*/
1895 1896
	drm_connector_list_iter_begin(ddev, &iter);
	drm_for_each_connector_iter(connector, &iter) {
1897
		aconnector = to_amdgpu_dm_connector(connector);
1898 1899 1900 1901 1902 1903 1904 1905

		/*
		 * this is the case when traversing through already created
		 * MST connectors, should be skipped
		 */
		if (aconnector->mst_port)
			continue;

1906
		mutex_lock(&aconnector->hpd_lock);
1907 1908 1909 1910 1911 1912 1913
		if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
			DRM_ERROR("KMS: Failed to detect connector\n");

		if (aconnector->base.force && new_connection_type == dc_connection_none)
			emulated_link_detect(aconnector->dc_link);
		else
			dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
R
Roman Li 已提交
1914 1915 1916 1917

		if (aconnector->fake_enable && aconnector->dc_link->local_sink)
			aconnector->fake_enable = false;

1918 1919
		if (aconnector->dc_sink)
			dc_sink_release(aconnector->dc_sink);
1920 1921
		aconnector->dc_sink = NULL;
		amdgpu_dm_update_connector_after_detect(aconnector);
1922
		mutex_unlock(&aconnector->hpd_lock);
1923
	}
1924
	drm_connector_list_iter_end(&iter);
1925

1926
	/* Force mode set in atomic commit */
1927
	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
1928
		new_crtc_state->active_changed = true;
1929

1930 1931 1932 1933 1934
	/*
	 * atomic_check is expected to create the dc states. We need to release
	 * them here, since they were duplicated as part of the suspend
	 * procedure.
	 */
1935
	for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
1936 1937 1938 1939 1940 1941 1942 1943
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
		if (dm_new_crtc_state->stream) {
			WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
			dc_stream_release(dm_new_crtc_state->stream);
			dm_new_crtc_state->stream = NULL;
		}
	}

1944
	for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
1945 1946 1947 1948 1949 1950 1951 1952
		dm_new_plane_state = to_dm_plane_state(new_plane_state);
		if (dm_new_plane_state->dc_state) {
			WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
			dc_plane_state_release(dm_new_plane_state->dc_state);
			dm_new_plane_state->dc_state = NULL;
		}
	}

1953
	drm_atomic_helper_resume(ddev, dm->cached_state);
1954

1955
	dm->cached_state = NULL;
1956

1957
	amdgpu_dm_irq_resume_late(adev);
1958

1959 1960
	amdgpu_dm_smu_write_watermarks_table(adev);

1961
	return 0;
1962 1963
}

1964 1965 1966 1967 1968 1969 1970 1971 1972 1973
/**
 * DOC: DM Lifecycle
 *
 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
 * the base driver's device list to be initialized and torn down accordingly.
 *
 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
 */

1974 1975 1976
static const struct amd_ip_funcs amdgpu_dm_funcs = {
	.name = "dm",
	.early_init = dm_early_init,
1977
	.late_init = dm_late_init,
1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000
	.sw_init = dm_sw_init,
	.sw_fini = dm_sw_fini,
	.hw_init = dm_hw_init,
	.hw_fini = dm_hw_fini,
	.suspend = dm_suspend,
	.resume = dm_resume,
	.is_idle = dm_is_idle,
	.wait_for_idle = dm_wait_for_idle,
	.check_soft_reset = dm_check_soft_reset,
	.soft_reset = dm_soft_reset,
	.set_clockgating_state = dm_set_clockgating_state,
	.set_powergating_state = dm_set_powergating_state,
};

const struct amdgpu_ip_block_version dm_ip_block =
{
	.type = AMD_IP_BLOCK_TYPE_DCE,
	.major = 1,
	.minor = 0,
	.rev = 0,
	.funcs = &amdgpu_dm_funcs,
};

2001

2002 2003 2004 2005 2006
/**
 * DOC: atomic
 *
 * *WIP*
 */
2007

2008
static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2009
	.fb_create = amdgpu_display_user_framebuffer_create,
2010
	.output_poll_changed = drm_fb_helper_output_poll_changed,
2011
	.atomic_check = amdgpu_dm_atomic_check,
2012
	.atomic_commit = amdgpu_dm_atomic_commit,
2013 2014 2015 2016
};

static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
	.atomic_commit_tail = amdgpu_dm_atomic_commit_tail
2017 2018
};

2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073
static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
{
	u32 max_cll, min_cll, max, min, q, r;
	struct amdgpu_dm_backlight_caps *caps;
	struct amdgpu_display_manager *dm;
	struct drm_connector *conn_base;
	struct amdgpu_device *adev;
	static const u8 pre_computed_values[] = {
		50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
		71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};

	if (!aconnector || !aconnector->dc_link)
		return;

	conn_base = &aconnector->base;
	adev = conn_base->dev->dev_private;
	dm = &adev->dm;
	caps = &dm->backlight_caps;
	caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
	caps->aux_support = false;
	max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
	min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;

	if (caps->ext_caps->bits.oled == 1 ||
	    caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
	    caps->ext_caps->bits.hdr_aux_backlight_control == 1)
		caps->aux_support = true;

	/* From the specification (CTA-861-G), for calculating the maximum
	 * luminance we need to use:
	 *	Luminance = 50*2**(CV/32)
	 * Where CV is a one-byte value.
	 * For calculating this expression we may need float point precision;
	 * to avoid this complexity level, we take advantage that CV is divided
	 * by a constant. From the Euclids division algorithm, we know that CV
	 * can be written as: CV = 32*q + r. Next, we replace CV in the
	 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
	 * need to pre-compute the value of r/32. For pre-computing the values
	 * We just used the following Ruby line:
	 *	(0...32).each {|cv| puts (50*2**(cv/32.0)).round}
	 * The results of the above expressions can be verified at
	 * pre_computed_values.
	 */
	q = max_cll >> 5;
	r = max_cll % 32;
	max = (1 << q) * pre_computed_values[r];

	// min luminance: maxLum * (CV/255)^2 / 100
	q = DIV_ROUND_CLOSEST(min_cll, 255);
	min = max * DIV_ROUND_CLOSEST((q * q), 100);

	caps->aux_max_input_signal = max;
	caps->aux_min_input_signal = min;
}

2074 2075
void amdgpu_dm_update_connector_after_detect(
		struct amdgpu_dm_connector *aconnector)
2076 2077 2078
{
	struct drm_connector *connector = &aconnector->base;
	struct drm_device *dev = connector->dev;
2079
	struct dc_sink *sink;
2080 2081 2082 2083 2084 2085 2086

	/* MST handled by drm_mst framework */
	if (aconnector->mst_mgr.mst_state == true)
		return;


	sink = aconnector->dc_link->local_sink;
2087 2088
	if (sink)
		dc_sink_retain(sink);
2089

2090 2091
	/*
	 * Edid mgmt connector gets first update only in mode_valid hook and then
2092
	 * the connector sink is set to either fake or physical sink depends on link status.
2093
	 * Skip if already done during boot.
2094 2095 2096 2097
	 */
	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
			&& aconnector->dc_em_sink) {

2098 2099 2100
		/*
		 * For S3 resume with headless use eml_sink to fake stream
		 * because on resume connector->sink is set to NULL
2101 2102 2103 2104
		 */
		mutex_lock(&dev->mode_config.mutex);

		if (sink) {
2105
			if (aconnector->dc_sink) {
2106
				amdgpu_dm_update_freesync_caps(connector, NULL);
2107 2108 2109 2110
				/*
				 * retain and release below are used to
				 * bump up refcount for sink because the link doesn't point
				 * to it anymore after disconnect, so on next crtc to connector
2111 2112
				 * reshuffle by UMD we will get into unwanted dc_sink release
				 */
2113
				dc_sink_release(aconnector->dc_sink);
2114
			}
2115
			aconnector->dc_sink = sink;
2116
			dc_sink_retain(aconnector->dc_sink);
2117 2118
			amdgpu_dm_update_freesync_caps(connector,
					aconnector->edid);
2119
		} else {
2120
			amdgpu_dm_update_freesync_caps(connector, NULL);
2121
			if (!aconnector->dc_sink) {
2122
				aconnector->dc_sink = aconnector->dc_em_sink;
2123
				dc_sink_retain(aconnector->dc_sink);
2124
			}
2125 2126 2127
		}

		mutex_unlock(&dev->mode_config.mutex);
2128 2129 2130

		if (sink)
			dc_sink_release(sink);
2131 2132 2133 2134 2135 2136 2137
		return;
	}

	/*
	 * TODO: temporary guard to look for proper fix
	 * if this sink is MST sink, we should not do anything
	 */
2138 2139
	if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
		dc_sink_release(sink);
2140
		return;
2141
	}
2142 2143

	if (aconnector->dc_sink == sink) {
2144 2145 2146 2147
		/*
		 * We got a DP short pulse (Link Loss, DP CTS, etc...).
		 * Do nothing!!
		 */
2148
		DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2149
				aconnector->connector_id);
2150 2151
		if (sink)
			dc_sink_release(sink);
2152 2153 2154
		return;
	}

2155
	DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2156 2157 2158 2159
		aconnector->connector_id, aconnector->dc_sink, sink);

	mutex_lock(&dev->mode_config.mutex);

2160 2161 2162 2163
	/*
	 * 1. Update status of the drm connector
	 * 2. Send an event and let userspace tell us what to do
	 */
2164
	if (sink) {
2165 2166 2167 2168
		/*
		 * TODO: check if we still need the S3 mode update workaround.
		 * If yes, put it here.
		 */
2169
		if (aconnector->dc_sink)
2170
			amdgpu_dm_update_freesync_caps(connector, NULL);
2171 2172

		aconnector->dc_sink = sink;
2173
		dc_sink_retain(aconnector->dc_sink);
2174
		if (sink->dc_edid.length == 0) {
2175
			aconnector->edid = NULL;
2176 2177 2178 2179
			if (aconnector->dc_link->aux_mode) {
				drm_dp_cec_unset_edid(
					&aconnector->dm_dp_aux.aux);
			}
2180
		} else {
2181
			aconnector->edid =
2182
				(struct edid *)sink->dc_edid.raw_edid;
2183

2184
			drm_connector_update_edid_property(connector,
2185 2186 2187 2188 2189
							   aconnector->edid);

			if (aconnector->dc_link->aux_mode)
				drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
						    aconnector->edid);
2190
		}
2191

2192
		amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
2193
		update_connector_ext_caps(aconnector);
2194
	} else {
2195
		drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
2196
		amdgpu_dm_update_freesync_caps(connector, NULL);
2197
		drm_connector_update_edid_property(connector, NULL);
2198
		aconnector->num_modes = 0;
2199
		dc_sink_release(aconnector->dc_sink);
2200
		aconnector->dc_sink = NULL;
2201
		aconnector->edid = NULL;
2202 2203 2204 2205 2206
#ifdef CONFIG_DRM_AMD_DC_HDCP
		/* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
		if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
			connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
#endif
2207 2208 2209
	}

	mutex_unlock(&dev->mode_config.mutex);
2210 2211 2212

	if (sink)
		dc_sink_release(sink);
2213 2214 2215 2216
}

static void handle_hpd_irq(void *param)
{
2217
	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
2218 2219
	struct drm_connector *connector = &aconnector->base;
	struct drm_device *dev = connector->dev;
2220
	enum dc_connection_type new_connection_type = dc_connection_none;
2221 2222 2223
#ifdef CONFIG_DRM_AMD_DC_HDCP
	struct amdgpu_device *adev = dev->dev_private;
#endif
2224

2225 2226 2227
	/*
	 * In case of failure or MST no need to update connector status or notify the OS
	 * since (for MST case) MST does this in its own context.
2228 2229
	 */
	mutex_lock(&aconnector->hpd_lock);
2230

2231
#ifdef CONFIG_DRM_AMD_DC_HDCP
2232
	if (adev->dm.hdcp_workqueue)
2233
		hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
2234
#endif
2235 2236 2237
	if (aconnector->fake_enable)
		aconnector->fake_enable = false;

2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252
	if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
		DRM_ERROR("KMS: Failed to detect connector\n");

	if (aconnector->base.force && new_connection_type == dc_connection_none) {
		emulated_link_detect(aconnector->dc_link);


		drm_modeset_lock_all(dev);
		dm_restore_drm_connector_state(dev, connector);
		drm_modeset_unlock_all(dev);

		if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
			drm_kms_helper_hotplug_event(dev);

	} else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266
		amdgpu_dm_update_connector_after_detect(aconnector);


		drm_modeset_lock_all(dev);
		dm_restore_drm_connector_state(dev, connector);
		drm_modeset_unlock_all(dev);

		if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
			drm_kms_helper_hotplug_event(dev);
	}
	mutex_unlock(&aconnector->hpd_lock);

}

2267
static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302
{
	uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
	uint8_t dret;
	bool new_irq_handled = false;
	int dpcd_addr;
	int dpcd_bytes_to_read;

	const int max_process_count = 30;
	int process_count = 0;

	const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);

	if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
		dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
		/* DPCD 0x200 - 0x201 for downstream IRQ */
		dpcd_addr = DP_SINK_COUNT;
	} else {
		dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
		/* DPCD 0x2002 - 0x2005 for downstream IRQ */
		dpcd_addr = DP_SINK_COUNT_ESI;
	}

	dret = drm_dp_dpcd_read(
		&aconnector->dm_dp_aux.aux,
		dpcd_addr,
		esi,
		dpcd_bytes_to_read);

	while (dret == dpcd_bytes_to_read &&
		process_count < max_process_count) {
		uint8_t retry;
		dret = 0;

		process_count++;

2303
		DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327
		/* handle HPD short pulse irq */
		if (aconnector->mst_mgr.mst_state)
			drm_dp_mst_hpd_irq(
				&aconnector->mst_mgr,
				esi,
				&new_irq_handled);

		if (new_irq_handled) {
			/* ACK at DPCD to notify down stream */
			const int ack_dpcd_bytes_to_write =
				dpcd_bytes_to_read - 1;

			for (retry = 0; retry < 3; retry++) {
				uint8_t wret;

				wret = drm_dp_dpcd_write(
					&aconnector->dm_dp_aux.aux,
					dpcd_addr + 1,
					&esi[1],
					ack_dpcd_bytes_to_write);
				if (wret == ack_dpcd_bytes_to_write)
					break;
			}

2328
			/* check if there is new irq to be handled */
2329 2330 2331 2332 2333 2334 2335
			dret = drm_dp_dpcd_read(
				&aconnector->dm_dp_aux.aux,
				dpcd_addr,
				esi,
				dpcd_bytes_to_read);

			new_irq_handled = false;
2336
		} else {
2337
			break;
2338
		}
2339 2340 2341
	}

	if (process_count == max_process_count)
2342
		DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
2343 2344 2345 2346
}

static void handle_hpd_rx_irq(void *param)
{
2347
	struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
2348 2349
	struct drm_connector *connector = &aconnector->base;
	struct drm_device *dev = connector->dev;
2350
	struct dc_link *dc_link = aconnector->dc_link;
2351
	bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
2352
	enum dc_connection_type new_connection_type = dc_connection_none;
2353 2354 2355 2356 2357 2358
#ifdef CONFIG_DRM_AMD_DC_HDCP
	union hpd_irq_data hpd_irq_data;
	struct amdgpu_device *adev = dev->dev_private;

	memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
#endif
2359

2360 2361
	/*
	 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
2362 2363 2364
	 * conflict, after implement i2c helper, this mutex should be
	 * retired.
	 */
2365
	if (dc_link->type != dc_connection_mst_branch)
2366 2367
		mutex_lock(&aconnector->hpd_lock);

2368 2369 2370 2371

#ifdef CONFIG_DRM_AMD_DC_HDCP
	if (dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL) &&
#else
2372
	if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
2373
#endif
2374 2375
			!is_mst_root_connector) {
		/* Downstream Port status changed. */
2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393
		if (!dc_link_detect_sink(dc_link, &new_connection_type))
			DRM_ERROR("KMS: Failed to detect connector\n");

		if (aconnector->base.force && new_connection_type == dc_connection_none) {
			emulated_link_detect(dc_link);

			if (aconnector->fake_enable)
				aconnector->fake_enable = false;

			amdgpu_dm_update_connector_after_detect(aconnector);


			drm_modeset_lock_all(dev);
			dm_restore_drm_connector_state(dev, connector);
			drm_modeset_unlock_all(dev);

			drm_kms_helper_hotplug_event(dev);
		} else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
2394 2395 2396 2397

			if (aconnector->fake_enable)
				aconnector->fake_enable = false;

2398 2399 2400 2401 2402 2403 2404 2405 2406 2407
			amdgpu_dm_update_connector_after_detect(aconnector);


			drm_modeset_lock_all(dev);
			dm_restore_drm_connector_state(dev, connector);
			drm_modeset_unlock_all(dev);

			drm_kms_helper_hotplug_event(dev);
		}
	}
2408
#ifdef CONFIG_DRM_AMD_DC_HDCP
2409 2410 2411 2412
	if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
		if (adev->dm.hdcp_workqueue)
			hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
	}
2413
#endif
2414
	if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2415
	    (dc_link->type == dc_connection_mst_branch))
2416 2417
		dm_handle_hpd_rx_irq(aconnector);

2418 2419
	if (dc_link->type != dc_connection_mst_branch) {
		drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
2420
		mutex_unlock(&aconnector->hpd_lock);
2421
	}
2422 2423 2424 2425 2426 2427
}

static void register_hpd_handlers(struct amdgpu_device *adev)
{
	struct drm_device *dev = adev->ddev;
	struct drm_connector *connector;
2428
	struct amdgpu_dm_connector *aconnector;
2429 2430 2431 2432 2433 2434 2435 2436 2437
	const struct dc_link *dc_link;
	struct dc_interrupt_params int_params = {0};

	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

	list_for_each_entry(connector,
			&dev->mode_config.connector_list, head)	{

2438
		aconnector = to_amdgpu_dm_connector(connector);
2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470
		dc_link = aconnector->dc_link;

		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
			int_params.irq_source = dc_link->irq_source_hpd;

			amdgpu_dm_irq_register_interrupt(adev, &int_params,
					handle_hpd_irq,
					(void *) aconnector);
		}

		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {

			/* Also register for DP short pulse (hpd_rx). */
			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
			int_params.irq_source =	dc_link->irq_source_hpd_rx;

			amdgpu_dm_irq_register_interrupt(adev, &int_params,
					handle_hpd_rx_irq,
					(void *) aconnector);
		}
	}
}

/* Register IRQ sources and initialize IRQ callbacks */
static int dce110_register_irq_handlers(struct amdgpu_device *adev)
{
	struct dc *dc = adev->dm.dc;
	struct common_irq_params *c_irq_params;
	struct dc_interrupt_params int_params = {0};
	int r;
	int i;
2471
	unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
2472

2473
	if (adev->asic_type >= CHIP_VEGA10)
2474
		client_id = SOC15_IH_CLIENTID_DCE;
2475 2476 2477 2478

	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

2479 2480
	/*
	 * Actions of amdgpu_irq_add_id():
2481 2482 2483 2484 2485 2486 2487 2488 2489
	 * 1. Register a set() function with base driver.
	 *    Base driver will call set() function to enable/disable an
	 *    interrupt in DC hardware.
	 * 2. Register amdgpu_dm_irq_handler().
	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
	 *    coming from DC hardware.
	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
	 *    for acknowledging and handling. */

2490
	/* Use VBLANK interrupt */
2491
	for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
2492
		r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
2493 2494 2495 2496 2497 2498 2499
		if (r) {
			DRM_ERROR("Failed to add crtc irq id!\n");
			return r;
		}

		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
		int_params.irq_source =
2500
			dc_interrupt_to_irq_source(dc, i, 0);
2501

2502
		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
2503 2504 2505 2506 2507 2508 2509 2510

		c_irq_params->adev = adev;
		c_irq_params->irq_src = int_params.irq_source;

		amdgpu_dm_irq_register_interrupt(adev, &int_params,
				dm_crtc_high_irq, c_irq_params);
	}

2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531
	/* Use VUPDATE interrupt */
	for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
		r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
		if (r) {
			DRM_ERROR("Failed to add vupdate irq id!\n");
			return r;
		}

		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
		int_params.irq_source =
			dc_interrupt_to_irq_source(dc, i, 0);

		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];

		c_irq_params->adev = adev;
		c_irq_params->irq_src = int_params.irq_source;

		amdgpu_dm_irq_register_interrupt(adev, &int_params,
				dm_vupdate_high_irq, c_irq_params);
	}

2532
	/* Use GRPH_PFLIP interrupt */
2533 2534
	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
			i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
2535
		r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555
		if (r) {
			DRM_ERROR("Failed to add page flip irq id!\n");
			return r;
		}

		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
		int_params.irq_source =
			dc_interrupt_to_irq_source(dc, i, 0);

		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];

		c_irq_params->adev = adev;
		c_irq_params->irq_src = int_params.irq_source;

		amdgpu_dm_irq_register_interrupt(adev, &int_params,
				dm_pflip_high_irq, c_irq_params);

	}

	/* HPD */
2556 2557
	r = amdgpu_irq_add_id(adev, client_id,
			VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2558 2559 2560 2561 2562 2563 2564 2565 2566 2567
	if (r) {
		DRM_ERROR("Failed to add hpd irq id!\n");
		return r;
	}

	register_hpd_handlers(adev);

	return 0;
}

2568
#if defined(CONFIG_DRM_AMD_DC_DCN)
2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580
/* Register IRQ sources and initialize IRQ callbacks */
static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
{
	struct dc *dc = adev->dm.dc;
	struct common_irq_params *c_irq_params;
	struct dc_interrupt_params int_params = {0};
	int r;
	int i;

	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

2581 2582
	/*
	 * Actions of amdgpu_irq_add_id():
2583 2584 2585 2586 2587 2588 2589 2590
	 * 1. Register a set() function with base driver.
	 *    Base driver will call set() function to enable/disable an
	 *    interrupt in DC hardware.
	 * 2. Register amdgpu_dm_irq_handler().
	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
	 *    coming from DC hardware.
	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
	 *    for acknowledging and handling.
2591
	 */
2592 2593 2594 2595 2596

	/* Use VSTARTUP interrupt */
	for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
			i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
			i++) {
2597
		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612

		if (r) {
			DRM_ERROR("Failed to add crtc irq id!\n");
			return r;
		}

		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
		int_params.irq_source =
			dc_interrupt_to_irq_source(dc, i, 0);

		c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];

		c_irq_params->adev = adev;
		c_irq_params->irq_src = int_params.irq_source;

2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640
		amdgpu_dm_irq_register_interrupt(
			adev, &int_params, dm_crtc_high_irq, c_irq_params);
	}

	/* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
	 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
	 * to trigger at end of each vblank, regardless of state of the lock,
	 * matching DCE behaviour.
	 */
	for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
	     i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
	     i++) {
		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);

		if (r) {
			DRM_ERROR("Failed to add vupdate irq id!\n");
			return r;
		}

		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
		int_params.irq_source =
			dc_interrupt_to_irq_source(dc, i, 0);

		c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];

		c_irq_params->adev = adev;
		c_irq_params->irq_src = int_params.irq_source;

2641
		amdgpu_dm_irq_register_interrupt(adev, &int_params,
2642
				dm_vupdate_high_irq, c_irq_params);
2643 2644
	}

2645 2646 2647 2648
	/* Use GRPH_PFLIP interrupt */
	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
			i++) {
2649
		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669
		if (r) {
			DRM_ERROR("Failed to add page flip irq id!\n");
			return r;
		}

		int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
		int_params.irq_source =
			dc_interrupt_to_irq_source(dc, i, 0);

		c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];

		c_irq_params->adev = adev;
		c_irq_params->irq_src = int_params.irq_source;

		amdgpu_dm_irq_register_interrupt(adev, &int_params,
				dm_pflip_high_irq, c_irq_params);

	}

	/* HPD */
2670
	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682
			&adev->hpd_irq);
	if (r) {
		DRM_ERROR("Failed to add hpd irq id!\n");
		return r;
	}

	register_hpd_handlers(adev);

	return 0;
}
#endif

2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708
/*
 * Acquires the lock for the atomic state object and returns
 * the new atomic state.
 *
 * This should only be called during atomic check.
 */
static int dm_atomic_get_state(struct drm_atomic_state *state,
			       struct dm_atomic_state **dm_state)
{
	struct drm_device *dev = state->dev;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_display_manager *dm = &adev->dm;
	struct drm_private_state *priv_state;

	if (*dm_state)
		return 0;

	priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
	if (IS_ERR(priv_state))
		return PTR_ERR(priv_state);

	*dm_state = to_dm_atomic_state(priv_state);

	return 0;
}

2709
static struct dm_atomic_state *
2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726
dm_atomic_get_new_state(struct drm_atomic_state *state)
{
	struct drm_device *dev = state->dev;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_display_manager *dm = &adev->dm;
	struct drm_private_obj *obj;
	struct drm_private_state *new_obj_state;
	int i;

	for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
		if (obj->funcs == dm->atomic_obj.funcs)
			return to_dm_atomic_state(new_obj_state);
	}

	return NULL;
}

2727
static struct dm_atomic_state *
2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755
dm_atomic_get_old_state(struct drm_atomic_state *state)
{
	struct drm_device *dev = state->dev;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_display_manager *dm = &adev->dm;
	struct drm_private_obj *obj;
	struct drm_private_state *old_obj_state;
	int i;

	for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
		if (obj->funcs == dm->atomic_obj.funcs)
			return to_dm_atomic_state(old_obj_state);
	}

	return NULL;
}

static struct drm_private_state *
dm_atomic_duplicate_state(struct drm_private_obj *obj)
{
	struct dm_atomic_state *old_state, *new_state;

	new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
	if (!new_state)
		return NULL;

	__drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);

2756 2757 2758 2759 2760
	old_state = to_dm_atomic_state(obj->state);

	if (old_state && old_state->context)
		new_state->context = dc_copy_state(old_state->context);

2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784
	if (!new_state->context) {
		kfree(new_state);
		return NULL;
	}

	return &new_state->base;
}

static void dm_atomic_destroy_state(struct drm_private_obj *obj,
				    struct drm_private_state *state)
{
	struct dm_atomic_state *dm_state = to_dm_atomic_state(state);

	if (dm_state && dm_state->context)
		dc_release_state(dm_state->context);

	kfree(dm_state);
}

static struct drm_private_state_funcs dm_atomic_state_funcs = {
	.atomic_duplicate_state = dm_atomic_duplicate_state,
	.atomic_destroy_state = dm_atomic_destroy_state,
};

2785 2786
static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
{
2787
	struct dm_atomic_state *state;
2788 2789 2790 2791 2792
	int r;

	adev->mode_info.mode_config_initialized = true;

	adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
2793
	adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
2794 2795 2796 2797 2798 2799

	adev->ddev->mode_config.max_width = 16384;
	adev->ddev->mode_config.max_height = 16384;

	adev->ddev->mode_config.preferred_depth = 24;
	adev->ddev->mode_config.prefer_shadow = 1;
2800
	/* indicates support for immediate flip */
2801 2802
	adev->ddev->mode_config.async_page_flip = true;

2803
	adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2804

2805 2806 2807 2808
	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (!state)
		return -ENOMEM;

2809
	state->context = dc_create_state(adev->dm.dc);
2810 2811 2812 2813 2814 2815 2816
	if (!state->context) {
		kfree(state);
		return -ENOMEM;
	}

	dc_resource_state_copy_construct_current(adev->dm.dc, state->context);

2817 2818
	drm_atomic_private_obj_init(adev->ddev,
				    &adev->dm.atomic_obj,
2819 2820 2821
				    &state->base,
				    &dm_atomic_state_funcs);

2822
	r = amdgpu_display_modeset_create_props(adev);
2823 2824 2825
	if (r)
		return r;

2826 2827 2828 2829
	r = amdgpu_dm_audio_init(adev);
	if (r)
		return r;

2830 2831 2832
	return 0;
}

2833 2834
#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2835
#define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
2836

2837 2838 2839
#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

2840 2841 2842 2843 2844 2845 2846 2847 2848 2849
static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
{
#if defined(CONFIG_ACPI)
	struct amdgpu_dm_backlight_caps caps;

	if (dm->backlight_caps.caps_valid)
		return;

	amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
	if (caps.caps_valid) {
2850 2851 2852
		dm->backlight_caps.caps_valid = true;
		if (caps.aux_support)
			return;
2853 2854 2855 2856 2857 2858 2859 2860 2861
		dm->backlight_caps.min_input_signal = caps.min_input_signal;
		dm->backlight_caps.max_input_signal = caps.max_input_signal;
	} else {
		dm->backlight_caps.min_input_signal =
				AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
		dm->backlight_caps.max_input_signal =
				AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
	}
#else
2862 2863 2864
	if (dm->backlight_caps.aux_support)
		return;

2865 2866
	dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
	dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2867 2868 2869
#endif
}

2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929
static int set_backlight_via_aux(struct dc_link *link, uint32_t brightness)
{
	bool rc;

	if (!link)
		return 1;

	rc = dc_link_set_backlight_level_nits(link, true, brightness,
					      AUX_BL_DEFAULT_TRANSITION_TIME_MS);

	return rc ? 0 : 1;
}

static u32 convert_brightness(const struct amdgpu_dm_backlight_caps *caps,
			      const uint32_t user_brightness)
{
	u32 min, max, conversion_pace;
	u32 brightness = user_brightness;

	if (!caps)
		goto out;

	if (!caps->aux_support) {
		max = caps->max_input_signal;
		min = caps->min_input_signal;
		/*
		 * The brightness input is in the range 0-255
		 * It needs to be rescaled to be between the
		 * requested min and max input signal
		 * It also needs to be scaled up by 0x101 to
		 * match the DC interface which has a range of
		 * 0 to 0xffff
		 */
		conversion_pace = 0x101;
		brightness =
			user_brightness
			* conversion_pace
			* (max - min)
			/ AMDGPU_MAX_BL_LEVEL
			+ min * conversion_pace;
	} else {
		/* TODO
		 * We are doing a linear interpolation here, which is OK but
		 * does not provide the optimal result. We probably want
		 * something close to the Perceptual Quantizer (PQ) curve.
		 */
		max = caps->aux_max_input_signal;
		min = caps->aux_min_input_signal;

		brightness = (AMDGPU_MAX_BL_LEVEL - user_brightness) * min
			       + user_brightness * max;
		// Multiple the value by 1000 since we use millinits
		brightness *= 1000;
		brightness = DIV_ROUND_CLOSEST(brightness, AMDGPU_MAX_BL_LEVEL);
	}

out:
	return brightness;
}

2930 2931 2932
static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
{
	struct amdgpu_display_manager *dm = bl_get_data(bd);
2933
	struct amdgpu_dm_backlight_caps caps;
2934 2935 2936
	struct dc_link *link = NULL;
	u32 brightness;
	bool rc;
2937

2938 2939
	amdgpu_dm_update_backlight_caps(dm);
	caps = dm->backlight_caps;
2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950

	link = (struct dc_link *)dm->backlight_link;

	brightness = convert_brightness(&caps, bd->props.brightness);
	// Change brightness based on AUX property
	if (caps.aux_support)
		return set_backlight_via_aux(link, brightness);

	rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0);

	return rc ? 0 : 1;
2951 2952 2953 2954
}

static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
{
2955 2956 2957 2958 2959 2960
	struct amdgpu_display_manager *dm = bl_get_data(bd);
	int ret = dc_link_get_backlight_level(dm->backlight_link);

	if (ret == DC_ERROR_UNEXPECTED)
		return bd->props.brightness;
	return ret;
2961 2962 2963
}

static const struct backlight_ops amdgpu_dm_backlight_ops = {
2964
	.options = BL_CORE_SUSPENDRESUME,
2965 2966 2967 2968
	.get_brightness = amdgpu_dm_backlight_get_brightness,
	.update_status	= amdgpu_dm_backlight_update_status,
};

2969 2970
static void
amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
2971 2972 2973 2974
{
	char bl_name[16];
	struct backlight_properties props = { 0 };

2975 2976
	amdgpu_dm_update_backlight_caps(dm);

2977
	props.max_brightness = AMDGPU_MAX_BL_LEVEL;
2978
	props.brightness = AMDGPU_MAX_BL_LEVEL;
2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989
	props.type = BACKLIGHT_RAW;

	snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
			dm->adev->ddev->primary->index);

	dm->backlight_dev = backlight_device_register(bl_name,
			dm->adev->ddev->dev,
			dm,
			&amdgpu_dm_backlight_ops,
			&props);

2990
	if (IS_ERR(dm->backlight_dev))
2991 2992
		DRM_ERROR("DM: Backlight registration failed!\n");
	else
2993
		DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
2994 2995 2996 2997
}

#endif

2998
static int initialize_plane(struct amdgpu_display_manager *dm,
2999
			    struct amdgpu_mode_info *mode_info, int plane_id,
3000 3001
			    enum drm_plane_type plane_type,
			    const struct dc_plane_cap *plane_cap)
3002
{
H
Harry Wentland 已提交
3003
	struct drm_plane *plane;
3004 3005 3006
	unsigned long possible_crtcs;
	int ret = 0;

H
Harry Wentland 已提交
3007
	plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
3008 3009 3010 3011
	if (!plane) {
		DRM_ERROR("KMS: Failed to allocate plane\n");
		return -ENOMEM;
	}
3012
	plane->type = plane_type;
3013 3014

	/*
3015 3016 3017 3018
	 * HACK: IGT tests expect that the primary plane for a CRTC
	 * can only have one possible CRTC. Only expose support for
	 * any CRTC if they're not going to be used as a primary plane
	 * for a CRTC - like overlay or underlay planes.
3019 3020 3021 3022 3023
	 */
	possible_crtcs = 1 << plane_id;
	if (plane_id >= dm->dc->caps.max_streams)
		possible_crtcs = 0xff;

3024
	ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
3025 3026 3027

	if (ret) {
		DRM_ERROR("KMS: Failed to initialize plane\n");
3028
		kfree(plane);
3029 3030 3031
		return ret;
	}

3032 3033 3034
	if (mode_info)
		mode_info->planes[plane_id] = plane;

3035 3036 3037
	return ret;
}

3038 3039 3040 3041 3042 3043 3044 3045 3046

static void register_backlight_device(struct amdgpu_display_manager *dm,
				      struct dc_link *link)
{
#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

	if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
	    link->type != dc_connection_none) {
3047 3048
		/*
		 * Event if registration failed, we should continue with
3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060
		 * DM initialization because not having a backlight control
		 * is better then a black screen.
		 */
		amdgpu_dm_register_backlight_device(dm);

		if (dm->backlight_dev)
			dm->backlight_link = link;
	}
#endif
}


3061 3062
/*
 * In this architecture, the association
3063 3064 3065 3066 3067 3068
 * connector -> encoder -> crtc
 * id not really requried. The crtc and connector will hold the
 * display_index as an abstraction to use with DAL component
 *
 * Returns 0 on success
 */
3069
static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
3070 3071
{
	struct amdgpu_display_manager *dm = &adev->dm;
3072
	int32_t i;
3073
	struct amdgpu_dm_connector *aconnector = NULL;
3074
	struct amdgpu_encoder *aencoder = NULL;
3075
	struct amdgpu_mode_info *mode_info = &adev->mode_info;
3076
	uint32_t link_cnt;
3077
	int32_t primary_planes;
3078
	enum dc_connection_type new_connection_type = dc_connection_none;
3079
	const struct dc_plane_cap *plane;
3080 3081 3082 3083

	link_cnt = dm->dc->caps.max_links;
	if (amdgpu_dm_mode_config_init(dm->adev)) {
		DRM_ERROR("DM: Failed to initialize mode config\n");
3084
		return -EINVAL;
3085 3086
	}

3087 3088
	/* There is one primary plane per CRTC */
	primary_planes = dm->dc->caps.max_streams;
3089
	ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
3090

3091 3092 3093 3094 3095
	/*
	 * Initialize primary planes, implicit planes for legacy IOCTLS.
	 * Order is reversed to match iteration order in atomic check.
	 */
	for (i = (primary_planes - 1); i >= 0; i--) {
3096 3097
		plane = &dm->dc->caps.planes[i];

3098
		if (initialize_plane(dm, mode_info, i,
3099
				     DRM_PLANE_TYPE_PRIMARY, plane)) {
3100
			DRM_ERROR("KMS: Failed to initialize primary plane\n");
3101
			goto fail;
3102
		}
3103
	}
3104

3105 3106 3107 3108 3109
	/*
	 * Initialize overlay planes, index starting after primary planes.
	 * These planes have a higher DRM index than the primary planes since
	 * they should be considered as having a higher z-order.
	 * Order is reversed to match iteration order in atomic check.
3110 3111 3112
	 *
	 * Only support DCN for now, and only expose one so we don't encourage
	 * userspace to use up all the pipes.
3113
	 */
3114 3115 3116 3117 3118 3119 3120 3121 3122
	for (i = 0; i < dm->dc->caps.max_planes; ++i) {
		struct dc_plane_cap *plane = &dm->dc->caps.planes[i];

		if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
			continue;

		if (!plane->blends_with_above || !plane->blends_with_below)
			continue;

3123
		if (!plane->pixel_format_support.argb8888)
3124 3125
			continue;

3126
		if (initialize_plane(dm, NULL, primary_planes + i,
3127
				     DRM_PLANE_TYPE_OVERLAY, plane)) {
3128
			DRM_ERROR("KMS: Failed to initialize overlay plane\n");
3129
			goto fail;
3130
		}
3131 3132 3133

		/* Only create one overlay plane. */
		break;
3134
	}
3135

3136
	for (i = 0; i < dm->dc->caps.max_streams; i++)
H
Harry Wentland 已提交
3137
		if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
3138
			DRM_ERROR("KMS: Failed to initialize crtc\n");
3139
			goto fail;
3140 3141
		}

3142
	dm->display_indexes_num = dm->dc->caps.max_streams;
3143 3144 3145

	/* loops over all connectors on the board */
	for (i = 0; i < link_cnt; i++) {
3146
		struct dc_link *link = NULL;
3147 3148 3149 3150 3151 3152 3153 3154 3155 3156

		if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
			DRM_ERROR(
				"KMS: Cannot support more than %d display indexes\n",
					AMDGPU_DM_MAX_DISPLAY_INDEX);
			continue;
		}

		aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
		if (!aconnector)
3157
			goto fail;
3158 3159

		aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
3160
		if (!aencoder)
3161
			goto fail;
3162 3163 3164

		if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
			DRM_ERROR("KMS: Failed to initialize encoder\n");
3165
			goto fail;
3166 3167 3168 3169
		}

		if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
			DRM_ERROR("KMS: Failed to initialize connector\n");
3170
			goto fail;
3171 3172
		}

3173 3174
		link = dc_get_link_at_index(dm->dc, i);

3175 3176 3177 3178 3179 3180 3181 3182
		if (!dc_link_detect_sink(link, &new_connection_type))
			DRM_ERROR("KMS: Failed to detect connector\n");

		if (aconnector->base.force && new_connection_type == dc_connection_none) {
			emulated_link_detect(link);
			amdgpu_dm_update_connector_after_detect(aconnector);

		} else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
3183
			amdgpu_dm_update_connector_after_detect(aconnector);
3184
			register_backlight_device(dm, link);
3185 3186
			if (amdgpu_dc_feature_mask & DC_PSR_MASK)
				amdgpu_dm_set_psr_caps(link);
3187 3188 3189
		}


3190 3191 3192 3193 3194 3195
	}

	/* Software is initialized. Now we can register interrupt handlers. */
	switch (adev->asic_type) {
	case CHIP_BONAIRE:
	case CHIP_HAWAII:
3196 3197 3198
	case CHIP_KAVERI:
	case CHIP_KABINI:
	case CHIP_MULLINS:
3199 3200 3201 3202 3203 3204
	case CHIP_TONGA:
	case CHIP_FIJI:
	case CHIP_CARRIZO:
	case CHIP_STONEY:
	case CHIP_POLARIS11:
	case CHIP_POLARIS10:
3205
	case CHIP_POLARIS12:
3206
	case CHIP_VEGAM:
3207
	case CHIP_VEGA10:
3208
	case CHIP_VEGA12:
3209
	case CHIP_VEGA20:
3210 3211
		if (dce110_register_irq_handlers(dm->adev)) {
			DRM_ERROR("DM: Failed to initialize IRQ\n");
3212
			goto fail;
3213 3214
		}
		break;
3215
#if defined(CONFIG_DRM_AMD_DC_DCN)
3216
	case CHIP_RAVEN:
3217
	case CHIP_NAVI12:
3218
	case CHIP_NAVI10:
3219
	case CHIP_NAVI14:
3220
	case CHIP_RENOIR:
3221 3222 3223
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	case CHIP_SIENNA_CICHLID:
#endif
3224 3225
		if (dcn10_register_irq_handlers(dm->adev)) {
			DRM_ERROR("DM: Failed to initialize IRQ\n");
3226
			goto fail;
3227 3228 3229
		}
		break;
#endif
3230
	default:
3231
		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
3232
		goto fail;
3233 3234
	}

3235 3236 3237
	/* No userspace support. */
	dm->dc->debug.disable_tri_buf = true;

3238
	return 0;
3239
fail:
3240 3241
	kfree(aencoder);
	kfree(aconnector);
3242

3243
	return -EINVAL;
3244 3245
}

3246
static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
3247 3248
{
	drm_mode_config_cleanup(dm->ddev);
3249
	drm_atomic_private_obj_fini(&dm->atomic_obj);
3250 3251 3252 3253 3254 3255 3256
	return;
}

/******************************************************************************
 * amdgpu_display_funcs functions
 *****************************************************************************/

3257
/*
3258 3259 3260 3261 3262 3263 3264 3265
 * dm_bandwidth_update - program display watermarks
 *
 * @adev: amdgpu_device pointer
 *
 * Calculate and program the display watermarks and line buffer allocation.
 */
static void dm_bandwidth_update(struct amdgpu_device *adev)
{
3266
	/* TODO: implement later */
3267 3268
}

3269
static const struct amdgpu_display_funcs dm_display_funcs = {
3270 3271
	.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
	.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
3272 3273
	.backlight_set_level = NULL, /* never called for DC */
	.backlight_get_level = NULL, /* never called for DC */
3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284
	.hpd_sense = NULL,/* called unconditionally */
	.hpd_set_polarity = NULL, /* called unconditionally */
	.hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
	.page_flip_get_scanoutpos =
		dm_crtc_get_scanoutpos,/* called unconditionally */
	.add_encoder = NULL, /* VBIOS parsing. DAL does it. */
	.add_connector = NULL, /* VBIOS parsing. DAL does it. */
};

#if defined(CONFIG_DEBUG_KERNEL_DC)

3285 3286 3287 3288
static ssize_t s3_debug_store(struct device *device,
			      struct device_attribute *attr,
			      const char *buf,
			      size_t count)
3289 3290 3291
{
	int ret;
	int s3_state;
3292
	struct drm_device *drm_dev = dev_get_drvdata(device);
3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322
	struct amdgpu_device *adev = drm_dev->dev_private;

	ret = kstrtoint(buf, 0, &s3_state);

	if (ret == 0) {
		if (s3_state) {
			dm_resume(adev);
			drm_kms_helper_hotplug_event(adev->ddev);
		} else
			dm_suspend(adev);
	}

	return ret == 0 ? count : 0;
}

DEVICE_ATTR_WO(s3_debug);

#endif

static int dm_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	switch (adev->asic_type) {
	case CHIP_BONAIRE:
	case CHIP_HAWAII:
		adev->mode_info.num_crtc = 6;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 6;
		break;
3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333
	case CHIP_KAVERI:
		adev->mode_info.num_crtc = 4;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 7;
		break;
	case CHIP_KABINI:
	case CHIP_MULLINS:
		adev->mode_info.num_crtc = 2;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 6;
		break;
3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350
	case CHIP_FIJI:
	case CHIP_TONGA:
		adev->mode_info.num_crtc = 6;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 7;
		break;
	case CHIP_CARRIZO:
		adev->mode_info.num_crtc = 3;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 9;
		break;
	case CHIP_STONEY:
		adev->mode_info.num_crtc = 2;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 9;
		break;
	case CHIP_POLARIS11:
3351
	case CHIP_POLARIS12:
3352 3353 3354 3355 3356
		adev->mode_info.num_crtc = 5;
		adev->mode_info.num_hpd = 5;
		adev->mode_info.num_dig = 5;
		break;
	case CHIP_POLARIS10:
3357
	case CHIP_VEGAM:
3358 3359 3360 3361
		adev->mode_info.num_crtc = 6;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 6;
		break;
3362
	case CHIP_VEGA10:
3363
	case CHIP_VEGA12:
3364
	case CHIP_VEGA20:
3365 3366 3367 3368
		adev->mode_info.num_crtc = 6;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 6;
		break;
3369
#if defined(CONFIG_DRM_AMD_DC_DCN)
3370 3371 3372 3373 3374
	case CHIP_RAVEN:
		adev->mode_info.num_crtc = 4;
		adev->mode_info.num_hpd = 4;
		adev->mode_info.num_dig = 4;
		break;
3375 3376
#endif
	case CHIP_NAVI10:
3377
	case CHIP_NAVI12:
3378 3379 3380
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
	case CHIP_SIENNA_CICHLID:
#endif
3381 3382 3383 3384
		adev->mode_info.num_crtc = 6;
		adev->mode_info.num_hpd = 6;
		adev->mode_info.num_dig = 6;
		break;
3385 3386 3387 3388 3389
	case CHIP_NAVI14:
		adev->mode_info.num_crtc = 5;
		adev->mode_info.num_hpd = 5;
		adev->mode_info.num_dig = 5;
		break;
3390 3391 3392 3393 3394
	case CHIP_RENOIR:
		adev->mode_info.num_crtc = 4;
		adev->mode_info.num_hpd = 4;
		adev->mode_info.num_dig = 4;
		break;
3395
	default:
3396
		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
3397 3398 3399
		return -EINVAL;
	}

3400 3401
	amdgpu_dm_set_irq_funcs(adev);

3402 3403 3404
	if (adev->mode_info.funcs == NULL)
		adev->mode_info.funcs = &dm_display_funcs;

3405 3406
	/*
	 * Note: Do NOT change adev->audio_endpt_rreg and
3407
	 * adev->audio_endpt_wreg because they are initialised in
3408 3409
	 * amdgpu_device_init()
	 */
3410 3411 3412 3413 3414 3415 3416 3417 3418
#if defined(CONFIG_DEBUG_KERNEL_DC)
	device_create_file(
		adev->ddev->dev,
		&dev_attr_s3_debug);
#endif

	return 0;
}

3419
static bool modeset_required(struct drm_crtc_state *crtc_state,
3420 3421
			     struct dc_stream_state *new_stream,
			     struct dc_stream_state *old_stream)
3422
{
3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439
	if (!drm_atomic_crtc_needs_modeset(crtc_state))
		return false;

	if (!crtc_state->enable)
		return false;

	return crtc_state->active;
}

static bool modereset_required(struct drm_crtc_state *crtc_state)
{
	if (!drm_atomic_crtc_needs_modeset(crtc_state))
		return false;

	return !crtc_state->enable || !crtc_state->active;
}

3440
static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
3441 3442 3443 3444 3445 3446 3447 3448 3449 3450
{
	drm_encoder_cleanup(encoder);
	kfree(encoder);
}

static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
	.destroy = amdgpu_dm_encoder_destroy,
};


3451 3452
static int fill_dc_scaling_info(const struct drm_plane_state *state,
				struct dc_scaling_info *scaling_info)
3453
{
3454
	int scale_w, scale_h;
3455

3456
	memset(scaling_info, 0, sizeof(*scaling_info));
3457

3458 3459 3460
	/* Source is fixed 16.16 but we ignore mantissa for now... */
	scaling_info->src_rect.x = state->src_x >> 16;
	scaling_info->src_rect.y = state->src_y >> 16;
3461

3462 3463 3464 3465 3466 3467 3468 3469 3470 3471
	scaling_info->src_rect.width = state->src_w >> 16;
	if (scaling_info->src_rect.width == 0)
		return -EINVAL;

	scaling_info->src_rect.height = state->src_h >> 16;
	if (scaling_info->src_rect.height == 0)
		return -EINVAL;

	scaling_info->dst_rect.x = state->crtc_x;
	scaling_info->dst_rect.y = state->crtc_y;
3472 3473

	if (state->crtc_w == 0)
3474
		return -EINVAL;
3475

3476
	scaling_info->dst_rect.width = state->crtc_w;
3477 3478

	if (state->crtc_h == 0)
3479
		return -EINVAL;
3480

3481
	scaling_info->dst_rect.height = state->crtc_h;
3482

3483 3484
	/* DRM doesn't specify clipping on destination output. */
	scaling_info->clip_rect = scaling_info->dst_rect;
3485

3486 3487 3488
	/* TODO: Validate scaling per-format with DC plane caps */
	scale_w = scaling_info->dst_rect.width * 1000 /
		  scaling_info->src_rect.width;
3489

3490 3491 3492 3493 3494 3495 3496 3497 3498
	if (scale_w < 250 || scale_w > 16000)
		return -EINVAL;

	scale_h = scaling_info->dst_rect.height * 1000 /
		  scaling_info->src_rect.height;

	if (scale_h < 250 || scale_h > 16000)
		return -EINVAL;

3499 3500 3501 3502
	/*
	 * The "scaling_quality" can be ignored for now, quality = 0 has DC
	 * assume reasonable defaults based on the format.
	 */
3503

3504
	return 0;
3505
}
3506

3507
static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
3508
		       uint64_t *tiling_flags, bool *tmz_surface)
3509
{
3510
	struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
3511
	int r = amdgpu_bo_reserve(rbo, false);
3512

3513
	if (unlikely(r)) {
3514
		/* Don't show error message when returning -ERESTARTSYS */
3515 3516
		if (r != -ERESTARTSYS)
			DRM_ERROR("Unable to reserve buffer: %d\n", r);
3517 3518 3519 3520 3521 3522
		return r;
	}

	if (tiling_flags)
		amdgpu_bo_get_tiling_flags(rbo, tiling_flags);

3523 3524 3525
	if (tmz_surface)
		*tmz_surface = amdgpu_bo_encrypted(rbo);

3526 3527 3528 3529 3530
	amdgpu_bo_unreserve(rbo);

	return r;
}

3531 3532 3533 3534 3535 3536 3537
static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
{
	uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);

	return offset ? (address + offset * 256) : 0;
}

3538 3539 3540 3541 3542
static int
fill_plane_dcc_attributes(struct amdgpu_device *adev,
			  const struct amdgpu_framebuffer *afb,
			  const enum surface_pixel_format format,
			  const enum dc_rotation_angle rotation,
3543
			  const struct plane_size *plane_size,
3544 3545 3546
			  const union dc_tiling_info *tiling_info,
			  const uint64_t info,
			  struct dc_plane_dcc_param *dcc,
3547 3548
			  struct dc_plane_address *address,
			  bool force_disable_dcc)
3549 3550
{
	struct dc *dc = adev->dm.dc;
3551 3552
	struct dc_dcc_surface_param input;
	struct dc_surface_dcc_cap output;
3553 3554 3555 3556
	uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
	uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
	uint64_t dcc_address;

3557 3558 3559
	memset(&input, 0, sizeof(input));
	memset(&output, 0, sizeof(output));

3560 3561 3562
	if (force_disable_dcc)
		return 0;

3563
	if (!offset)
3564 3565
		return 0;

3566
	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
3567
		return 0;
3568 3569

	if (!dc->cap_funcs.get_dcc_compression_cap)
3570
		return -EINVAL;
3571

3572
	input.format = format;
3573 3574
	input.surface_size.width = plane_size->surface_size.width;
	input.surface_size.height = plane_size->surface_size.height;
3575
	input.swizzle_mode = tiling_info->gfx9.swizzle;
3576

3577
	if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
3578
		input.scan = SCAN_DIRECTION_HORIZONTAL;
3579
	else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
3580 3581 3582
		input.scan = SCAN_DIRECTION_VERTICAL;

	if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
3583
		return -EINVAL;
3584 3585

	if (!output.capable)
3586
		return -EINVAL;
3587 3588

	if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
3589
		return -EINVAL;
3590

3591
	dcc->enable = 1;
3592
	dcc->meta_pitch =
3593
		AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
3594
	dcc->independent_64b_blks = i64b;
3595 3596

	dcc_address = get_dcc_address(afb->address, info);
3597 3598
	address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
	address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
3599

3600 3601 3602 3603
	return 0;
}

static int
3604
fill_plane_buffer_attributes(struct amdgpu_device *adev,
3605
			     const struct amdgpu_framebuffer *afb,
3606 3607 3608
			     const enum surface_pixel_format format,
			     const enum dc_rotation_angle rotation,
			     const uint64_t tiling_flags,
3609
			     union dc_tiling_info *tiling_info,
3610
			     struct plane_size *plane_size,
3611
			     struct dc_plane_dcc_param *dcc,
3612
			     struct dc_plane_address *address,
3613
			     bool tmz_surface,
3614
			     bool force_disable_dcc)
3615
{
3616
	const struct drm_framebuffer *fb = &afb->base;
3617 3618 3619
	int ret;

	memset(tiling_info, 0, sizeof(*tiling_info));
3620
	memset(plane_size, 0, sizeof(*plane_size));
3621
	memset(dcc, 0, sizeof(*dcc));
3622 3623
	memset(address, 0, sizeof(*address));

3624 3625
	address->tmz_surface = tmz_surface;

3626
	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3627 3628 3629 3630 3631
		plane_size->surface_size.x = 0;
		plane_size->surface_size.y = 0;
		plane_size->surface_size.width = fb->width;
		plane_size->surface_size.height = fb->height;
		plane_size->surface_pitch =
3632 3633
			fb->pitches[0] / fb->format->cpp[0];

3634 3635 3636
		address->type = PLN_ADDR_TYPE_GRAPHICS;
		address->grph.addr.low_part = lower_32_bits(afb->address);
		address->grph.addr.high_part = upper_32_bits(afb->address);
3637
	} else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
3638
		uint64_t chroma_addr = afb->address + fb->offsets[1];
3639

3640 3641 3642 3643 3644
		plane_size->surface_size.x = 0;
		plane_size->surface_size.y = 0;
		plane_size->surface_size.width = fb->width;
		plane_size->surface_size.height = fb->height;
		plane_size->surface_pitch =
3645 3646
			fb->pitches[0] / fb->format->cpp[0];

3647 3648
		plane_size->chroma_size.x = 0;
		plane_size->chroma_size.y = 0;
3649
		/* TODO: set these based on surface format */
3650 3651
		plane_size->chroma_size.width = fb->width / 2;
		plane_size->chroma_size.height = fb->height / 2;
3652

3653
		plane_size->chroma_pitch =
3654 3655
			fb->pitches[1] / fb->format->cpp[1];

3656 3657 3658 3659 3660 3661 3662 3663 3664 3665
		address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
		address->video_progressive.luma_addr.low_part =
			lower_32_bits(afb->address);
		address->video_progressive.luma_addr.high_part =
			upper_32_bits(afb->address);
		address->video_progressive.chroma_addr.low_part =
			lower_32_bits(chroma_addr);
		address->video_progressive.chroma_addr.high_part =
			upper_32_bits(chroma_addr);
	}
3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697

	/* Fill GFX8 params */
	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
		unsigned int bankw, bankh, mtaspect, tile_split, num_banks;

		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);

		/* XXX fix me for VI */
		tiling_info->gfx8.num_banks = num_banks;
		tiling_info->gfx8.array_mode =
				DC_ARRAY_2D_TILED_THIN1;
		tiling_info->gfx8.tile_split = tile_split;
		tiling_info->gfx8.bank_width = bankw;
		tiling_info->gfx8.bank_height = bankh;
		tiling_info->gfx8.tile_aspect = mtaspect;
		tiling_info->gfx8.tile_mode =
				DC_ADDR_SURF_MICRO_TILING_DISPLAY;
	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
			== DC_ARRAY_1D_TILED_THIN1) {
		tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
	}

	tiling_info->gfx8.pipe_config =
			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);

	if (adev->asic_type == CHIP_VEGA10 ||
	    adev->asic_type == CHIP_VEGA12 ||
	    adev->asic_type == CHIP_VEGA20 ||
3698
	    adev->asic_type == CHIP_NAVI10 ||
3699
	    adev->asic_type == CHIP_NAVI14 ||
3700
	    adev->asic_type == CHIP_NAVI12 ||
3701 3702 3703
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
		adev->asic_type == CHIP_SIENNA_CICHLID ||
#endif
3704
	    adev->asic_type == CHIP_RENOIR ||
3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722
	    adev->asic_type == CHIP_RAVEN) {
		/* Fill GFX9 params */
		tiling_info->gfx9.num_pipes =
			adev->gfx.config.gb_addr_config_fields.num_pipes;
		tiling_info->gfx9.num_banks =
			adev->gfx.config.gb_addr_config_fields.num_banks;
		tiling_info->gfx9.pipe_interleave =
			adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
		tiling_info->gfx9.num_shader_engines =
			adev->gfx.config.gb_addr_config_fields.num_se;
		tiling_info->gfx9.max_compressed_frags =
			adev->gfx.config.gb_addr_config_fields.max_compress_frags;
		tiling_info->gfx9.num_rb_per_se =
			adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
		tiling_info->gfx9.swizzle =
			AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
		tiling_info->gfx9.shaderEnable = 1;

3723 3724 3725 3726 3727
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
		if (adev->asic_type == CHIP_SIENNA_CICHLID)
			tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;

#endif
3728 3729
		ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
						plane_size, tiling_info,
3730 3731
						tiling_flags, dcc, address,
						force_disable_dcc);
3732 3733 3734 3735 3736
		if (ret)
			return ret;
	}

	return 0;
3737 3738
}

3739
static void
3740
fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773
			       bool *per_pixel_alpha, bool *global_alpha,
			       int *global_alpha_value)
{
	*per_pixel_alpha = false;
	*global_alpha = false;
	*global_alpha_value = 0xff;

	if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
		return;

	if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
		static const uint32_t alpha_formats[] = {
			DRM_FORMAT_ARGB8888,
			DRM_FORMAT_RGBA8888,
			DRM_FORMAT_ABGR8888,
		};
		uint32_t format = plane_state->fb->format->format;
		unsigned int i;

		for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
			if (format == alpha_formats[i]) {
				*per_pixel_alpha = true;
				break;
			}
		}
	}

	if (plane_state->alpha < 0xffff) {
		*global_alpha = true;
		*global_alpha_value = plane_state->alpha >> 8;
	}
}

3774 3775
static int
fill_plane_color_attributes(const struct drm_plane_state *plane_state,
3776
			    const enum surface_pixel_format format,
3777 3778 3779 3780 3781 3782 3783
			    enum dc_color_space *color_space)
{
	bool full_range;

	*color_space = COLOR_SPACE_SRGB;

	/* DRM color properties only affect non-RGB formats. */
3784
	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817
		return 0;

	full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);

	switch (plane_state->color_encoding) {
	case DRM_COLOR_YCBCR_BT601:
		if (full_range)
			*color_space = COLOR_SPACE_YCBCR601;
		else
			*color_space = COLOR_SPACE_YCBCR601_LIMITED;
		break;

	case DRM_COLOR_YCBCR_BT709:
		if (full_range)
			*color_space = COLOR_SPACE_YCBCR709;
		else
			*color_space = COLOR_SPACE_YCBCR709_LIMITED;
		break;

	case DRM_COLOR_YCBCR_BT2020:
		if (full_range)
			*color_space = COLOR_SPACE_2020_YCBCR;
		else
			return -EINVAL;
		break;

	default:
		return -EINVAL;
	}

	return 0;
}

3818 3819 3820 3821 3822
static int
fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
			    const struct drm_plane_state *plane_state,
			    const uint64_t tiling_flags,
			    struct dc_plane_info *plane_info,
3823
			    struct dc_plane_address *address,
3824
			    bool tmz_surface,
3825
			    bool force_disable_dcc)
3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864
{
	const struct drm_framebuffer *fb = plane_state->fb;
	const struct amdgpu_framebuffer *afb =
		to_amdgpu_framebuffer(plane_state->fb);
	struct drm_format_name_buf format_name;
	int ret;

	memset(plane_info, 0, sizeof(*plane_info));

	switch (fb->format->format) {
	case DRM_FORMAT_C8:
		plane_info->format =
			SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
		break;
	case DRM_FORMAT_RGB565:
		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
		break;
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_ARGB8888:
		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
		break;
	case DRM_FORMAT_XRGB2101010:
	case DRM_FORMAT_ARGB2101010:
		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
		break;
	case DRM_FORMAT_XBGR2101010:
	case DRM_FORMAT_ABGR2101010:
		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
		break;
	case DRM_FORMAT_XBGR8888:
	case DRM_FORMAT_ABGR8888:
		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
		break;
	case DRM_FORMAT_NV21:
		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
		break;
	case DRM_FORMAT_NV12:
		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
		break;
3865 3866 3867
	case DRM_FORMAT_P010:
		plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
		break;
3868 3869 3870 3871
	case DRM_FORMAT_XRGB16161616F:
	case DRM_FORMAT_ARGB16161616F:
		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
		break;
3872 3873 3874 3875
	case DRM_FORMAT_XBGR16161616F:
	case DRM_FORMAT_ABGR16161616F:
		plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
		break;
3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903
	default:
		DRM_ERROR(
			"Unsupported screen format %s\n",
			drm_get_format_name(fb->format->format, &format_name));
		return -EINVAL;
	}

	switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
	case DRM_MODE_ROTATE_0:
		plane_info->rotation = ROTATION_ANGLE_0;
		break;
	case DRM_MODE_ROTATE_90:
		plane_info->rotation = ROTATION_ANGLE_90;
		break;
	case DRM_MODE_ROTATE_180:
		plane_info->rotation = ROTATION_ANGLE_180;
		break;
	case DRM_MODE_ROTATE_270:
		plane_info->rotation = ROTATION_ANGLE_270;
		break;
	default:
		plane_info->rotation = ROTATION_ANGLE_0;
		break;
	}

	plane_info->visible = true;
	plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;

3904 3905
	plane_info->layer_index = 0;

3906 3907 3908 3909 3910 3911 3912 3913 3914
	ret = fill_plane_color_attributes(plane_state, plane_info->format,
					  &plane_info->color_space);
	if (ret)
		return ret;

	ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
					   plane_info->rotation, tiling_flags,
					   &plane_info->tiling_info,
					   &plane_info->plane_size,
3915
					   &plane_info->dcc, address, tmz_surface,
3916
					   force_disable_dcc);
3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930
	if (ret)
		return ret;

	fill_blending_from_plane_state(
		plane_state, &plane_info->per_pixel_alpha,
		&plane_info->global_alpha, &plane_info->global_alpha_value);

	return 0;
}

static int fill_dc_plane_attributes(struct amdgpu_device *adev,
				    struct dc_plane_state *dc_plane_state,
				    struct drm_plane_state *plane_state,
				    struct drm_crtc_state *crtc_state)
3931
{
3932
	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
3933 3934
	const struct amdgpu_framebuffer *amdgpu_fb =
		to_amdgpu_framebuffer(plane_state->fb);
3935 3936 3937 3938
	struct dc_scaling_info scaling_info;
	struct dc_plane_info plane_info;
	uint64_t tiling_flags;
	int ret;
3939
	bool tmz_surface = false;
3940
	bool force_disable_dcc = false;
3941

3942 3943 3944
	ret = fill_dc_scaling_info(plane_state, &scaling_info);
	if (ret)
		return ret;
3945

3946 3947 3948 3949
	dc_plane_state->src_rect = scaling_info.src_rect;
	dc_plane_state->dst_rect = scaling_info.dst_rect;
	dc_plane_state->clip_rect = scaling_info.clip_rect;
	dc_plane_state->scaling_quality = scaling_info.scaling_quality;
3950

3951
	ret = get_fb_info(amdgpu_fb, &tiling_flags, &tmz_surface);
3952 3953 3954
	if (ret)
		return ret;

3955
	force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
3956 3957
	ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
					  &plane_info,
3958
					  &dc_plane_state->address,
3959
					  tmz_surface,
3960
					  force_disable_dcc);
3961 3962 3963
	if (ret)
		return ret;

3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976
	dc_plane_state->format = plane_info.format;
	dc_plane_state->color_space = plane_info.color_space;
	dc_plane_state->format = plane_info.format;
	dc_plane_state->plane_size = plane_info.plane_size;
	dc_plane_state->rotation = plane_info.rotation;
	dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
	dc_plane_state->stereo_format = plane_info.stereo_format;
	dc_plane_state->tiling_info = plane_info.tiling_info;
	dc_plane_state->visible = plane_info.visible;
	dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
	dc_plane_state->global_alpha = plane_info.global_alpha;
	dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
	dc_plane_state->dcc = plane_info.dcc;
3977
	dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
3978

3979 3980 3981 3982
	/*
	 * Always set input transfer function, since plane state is refreshed
	 * every time.
	 */
3983 3984 3985
	ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
	if (ret)
		return ret;
3986

3987
	return 0;
3988 3989
}

3990 3991 3992
static void update_stream_scaling_settings(const struct drm_display_mode *mode,
					   const struct dm_connector_state *dm_state,
					   struct dc_stream_state *stream)
3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008
{
	enum amdgpu_rmx_type rmx_type;

	struct rect src = { 0 }; /* viewport in composition space*/
	struct rect dst = { 0 }; /* stream addressable area */

	/* no mode. nothing to be done */
	if (!mode)
		return;

	/* Full screen scaling by default */
	src.width = mode->hdisplay;
	src.height = mode->vdisplay;
	dst.width = stream->timing.h_addressable;
	dst.height = stream->timing.v_addressable;

4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023
	if (dm_state) {
		rmx_type = dm_state->scaling;
		if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
			if (src.width * dst.height <
					src.height * dst.width) {
				/* height needs less upscaling/more downscaling */
				dst.width = src.width *
						dst.height / src.height;
			} else {
				/* width needs less upscaling/more downscaling */
				dst.height = src.height *
						dst.width / src.width;
			}
		} else if (rmx_type == RMX_CENTER) {
			dst = src;
4024 4025
		}

4026 4027
		dst.x = (stream->timing.h_addressable - dst.width) / 2;
		dst.y = (stream->timing.v_addressable - dst.height) / 2;
4028

4029 4030 4031 4032 4033 4034
		if (dm_state->underscan_enable) {
			dst.x += dm_state->underscan_hborder / 2;
			dst.y += dm_state->underscan_vborder / 2;
			dst.width -= dm_state->underscan_hborder;
			dst.height -= dm_state->underscan_vborder;
		}
4035 4036 4037 4038 4039
	}

	stream->src = src;
	stream->dst = dst;

4040
	DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
4041 4042 4043 4044
			dst.x, dst.y, dst.width, dst.height);

}

4045
static enum dc_color_depth
4046
convert_color_depth_from_display_info(const struct drm_connector *connector,
4047
				      bool is_y420, int requested_bpc)
4048
{
4049
	uint8_t bpc;
4050

4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065
	if (is_y420) {
		bpc = 8;

		/* Cap display bpc based on HDMI 2.0 HF-VSDB */
		if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
			bpc = 16;
		else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
			bpc = 12;
		else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
			bpc = 10;
	} else {
		bpc = (uint8_t)connector->display_info.bpc;
		/* Assume 8 bpc by default if no bpc is specified. */
		bpc = bpc ? bpc : 8;
	}
4066

4067
	if (requested_bpc > 0) {
4068 4069 4070 4071 4072 4073 4074 4075
		/*
		 * Cap display bpc based on the user requested value.
		 *
		 * The value for state->max_bpc may not correctly updated
		 * depending on when the connector gets added to the state
		 * or if this was called outside of atomic check, so it
		 * can't be used directly.
		 */
4076
		bpc = min_t(u8, bpc, requested_bpc);
4077

4078 4079 4080
		/* Round down to the nearest even number. */
		bpc = bpc - (bpc & 1);
	}
4081

4082 4083
	switch (bpc) {
	case 0:
4084 4085
		/*
		 * Temporary Work around, DRM doesn't parse color depth for
4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106
		 * EDID revision before 1.4
		 * TODO: Fix edid parsing
		 */
		return COLOR_DEPTH_888;
	case 6:
		return COLOR_DEPTH_666;
	case 8:
		return COLOR_DEPTH_888;
	case 10:
		return COLOR_DEPTH_101010;
	case 12:
		return COLOR_DEPTH_121212;
	case 14:
		return COLOR_DEPTH_141414;
	case 16:
		return COLOR_DEPTH_161616;
	default:
		return COLOR_DEPTH_UNDEFINED;
	}
}

4107 4108
static enum dc_aspect_ratio
get_aspect_ratio(const struct drm_display_mode *mode_in)
4109
{
4110 4111
	/* 1-1 mapping, since both enums follow the HDMI spec. */
	return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
4112 4113
}

4114 4115
static enum dc_color_space
get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128
{
	enum dc_color_space color_space = COLOR_SPACE_SRGB;

	switch (dc_crtc_timing->pixel_encoding)	{
	case PIXEL_ENCODING_YCBCR422:
	case PIXEL_ENCODING_YCBCR444:
	case PIXEL_ENCODING_YCBCR420:
	{
		/*
		 * 27030khz is the separation point between HDTV and SDTV
		 * according to HDMI spec, we use YCbCr709 and YCbCr601
		 * respectively
		 */
4129
		if (dc_crtc_timing->pix_clk_100hz > 270300) {
4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156
			if (dc_crtc_timing->flags.Y_ONLY)
				color_space =
					COLOR_SPACE_YCBCR709_LIMITED;
			else
				color_space = COLOR_SPACE_YCBCR709;
		} else {
			if (dc_crtc_timing->flags.Y_ONLY)
				color_space =
					COLOR_SPACE_YCBCR601_LIMITED;
			else
				color_space = COLOR_SPACE_YCBCR601;
		}

	}
	break;
	case PIXEL_ENCODING_RGB:
		color_space = COLOR_SPACE_SRGB;
		break;

	default:
		WARN_ON(1);
		break;
	}

	return color_space;
}

4157 4158 4159
static bool adjust_colour_depth_from_display_info(
	struct dc_crtc_timing *timing_out,
	const struct drm_display_info *info)
4160
{
4161
	enum dc_color_depth depth = timing_out->display_color_depth;
4162 4163
	int normalized_clk;
	do {
4164
		normalized_clk = timing_out->pix_clk_100hz / 10;
4165 4166 4167 4168
		/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
		if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
			normalized_clk /= 2;
		/* Adjusting pix clock following on HDMI spec based on colour depth */
4169 4170 4171
		switch (depth) {
		case COLOR_DEPTH_888:
			break;
4172 4173 4174 4175 4176 4177 4178 4179 4180 4181
		case COLOR_DEPTH_101010:
			normalized_clk = (normalized_clk * 30) / 24;
			break;
		case COLOR_DEPTH_121212:
			normalized_clk = (normalized_clk * 36) / 24;
			break;
		case COLOR_DEPTH_161616:
			normalized_clk = (normalized_clk * 48) / 24;
			break;
		default:
4182 4183
			/* The above depths are the only ones valid for HDMI. */
			return false;
4184
		}
4185 4186 4187 4188 4189 4190
		if (normalized_clk <= info->max_tmds_clock) {
			timing_out->display_color_depth = depth;
			return true;
		}
	} while (--depth > COLOR_DEPTH_666);
	return false;
4191
}
4192

4193 4194 4195 4196 4197
static void fill_stream_properties_from_drm_display_mode(
	struct dc_stream_state *stream,
	const struct drm_display_mode *mode_in,
	const struct drm_connector *connector,
	const struct drm_connector_state *connector_state,
4198 4199
	const struct dc_stream_state *old_stream,
	int requested_bpc)
4200 4201
{
	struct dc_crtc_timing *timing_out = &stream->timing;
4202
	const struct drm_display_info *info = &connector->display_info;
4203
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4204 4205
	struct hdmi_vendor_infoframe hv_frame;
	struct hdmi_avi_infoframe avi_frame;
4206

4207 4208 4209
	memset(&hv_frame, 0, sizeof(hv_frame));
	memset(&avi_frame, 0, sizeof(avi_frame));

4210 4211 4212 4213 4214
	timing_out->h_border_left = 0;
	timing_out->h_border_right = 0;
	timing_out->v_border_top = 0;
	timing_out->v_border_bottom = 0;
	/* TODO: un-hardcode */
4215
	if (drm_mode_is_420_only(info, mode_in)
4216
			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
4217
		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
4218 4219 4220
	else if (drm_mode_is_420_also(info, mode_in)
			&& aconnector->force_yuv420_output)
		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
4221
	else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
4222
			&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
4223 4224 4225 4226 4227 4228
		timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
	else
		timing_out->pixel_encoding = PIXEL_ENCODING_RGB;

	timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
	timing_out->display_color_depth = convert_color_depth_from_display_info(
4229 4230 4231
		connector,
		(timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
		requested_bpc);
4232 4233
	timing_out->scan_type = SCANNING_TYPE_NODATA;
	timing_out->hdmi_vic = 0;
4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245

	if(old_stream) {
		timing_out->vic = old_stream->timing.vic;
		timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
		timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
	} else {
		timing_out->vic = drm_match_cea_mode(mode_in);
		if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
			timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
		if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
			timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
	}
4246

4247 4248 4249 4250 4251 4252 4253
	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
		drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
		timing_out->vic = avi_frame.video_code;
		drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
		timing_out->hdmi_vic = hv_frame.vic;
	}

4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265
	timing_out->h_addressable = mode_in->crtc_hdisplay;
	timing_out->h_total = mode_in->crtc_htotal;
	timing_out->h_sync_width =
		mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
	timing_out->h_front_porch =
		mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
	timing_out->v_total = mode_in->crtc_vtotal;
	timing_out->v_addressable = mode_in->crtc_vdisplay;
	timing_out->v_front_porch =
		mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
	timing_out->v_sync_width =
		mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
4266
	timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
4267 4268 4269 4270
	timing_out->aspect_ratio = get_aspect_ratio(mode_in);

	stream->output_color_space = get_output_color_space(timing_out);

4271 4272
	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
4273 4274 4275 4276 4277 4278 4279 4280
	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
		if (!adjust_colour_depth_from_display_info(timing_out, info) &&
		    drm_mode_is_420_also(info, mode_in) &&
		    timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
			timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
			adjust_colour_depth_from_display_info(timing_out, info);
		}
	}
4281 4282
}

4283 4284 4285
static void fill_audio_info(struct audio_info *audio_info,
			    const struct drm_connector *drm_connector,
			    const struct dc_sink *dc_sink)
4286 4287 4288 4289 4290 4291 4292 4293 4294 4295
{
	int i = 0;
	int cea_revision = 0;
	const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;

	audio_info->manufacture_id = edid_caps->manufacturer_id;
	audio_info->product_id = edid_caps->product_id;

	cea_revision = drm_connector->display_info.cea_rev;

4296
	strscpy(audio_info->display_name,
4297
		edid_caps->display_name,
4298
		AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
4299

4300
	if (cea_revision >= 3) {
4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318
		audio_info->mode_count = edid_caps->audio_mode_count;

		for (i = 0; i < audio_info->mode_count; ++i) {
			audio_info->modes[i].format_code =
					(enum audio_format_code)
					(edid_caps->audio_modes[i].format_code);
			audio_info->modes[i].channel_count =
					edid_caps->audio_modes[i].channel_count;
			audio_info->modes[i].sample_rates.all =
					edid_caps->audio_modes[i].sample_rate;
			audio_info->modes[i].sample_size =
					edid_caps->audio_modes[i].sample_size;
		}
	}

	audio_info->flags.all = edid_caps->speaker_flags;

	/* TODO: We only check for the progressive mode, check for interlace mode too */
4319
	if (drm_connector->latency_present[0]) {
4320 4321 4322 4323 4324 4325 4326 4327
		audio_info->video_latency = drm_connector->video_latency[0];
		audio_info->audio_latency = drm_connector->audio_latency[0];
	}

	/* TODO: For DP, video and audio latency should be calculated from DPCD caps */

}

4328 4329 4330
static void
copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
				      struct drm_display_mode *dst_mode)
4331 4332 4333 4334 4335 4336
{
	dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
	dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
	dst_mode->crtc_clock = src_mode->crtc_clock;
	dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
	dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
4337
	dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
4338 4339 4340 4341 4342 4343 4344 4345 4346 4347
	dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
	dst_mode->crtc_htotal = src_mode->crtc_htotal;
	dst_mode->crtc_hskew = src_mode->crtc_hskew;
	dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
	dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
	dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
	dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
	dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
}

4348 4349 4350 4351
static void
decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
					const struct drm_display_mode *native_mode,
					bool scale_enabled)
4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363
{
	if (scale_enabled) {
		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
	} else if (native_mode->clock == drm_mode->clock &&
			native_mode->htotal == drm_mode->htotal &&
			native_mode->vtotal == drm_mode->vtotal) {
		copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
	} else {
		/* no scaling nor amdgpu inserted, no need to patch */
	}
}

4364 4365
static struct dc_sink *
create_fake_sink(struct amdgpu_dm_connector *aconnector)
4366 4367
{
	struct dc_sink_init_data sink_init_data = { 0 };
4368
	struct dc_sink *sink = NULL;
4369 4370 4371 4372
	sink_init_data.link = aconnector->dc_link;
	sink_init_data.sink_signal = aconnector->dc_link->connector_signal;

	sink = dc_sink_create(&sink_init_data);
4373
	if (!sink) {
4374
		DRM_ERROR("Failed to create sink!\n");
4375
		return NULL;
4376
	}
4377
	sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
4378

4379
	return sink;
4380 4381
}

4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399
static void set_multisync_trigger_params(
		struct dc_stream_state *stream)
{
	if (stream->triggered_crtc_reset.enabled) {
		stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
		stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
	}
}

static void set_master_stream(struct dc_stream_state *stream_set[],
			      int stream_count)
{
	int j, highest_rfr = 0, master_stream = 0;

	for (j = 0;  j < stream_count; j++) {
		if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
			int refresh_rate = 0;

4400
			refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
4401 4402 4403 4404 4405 4406 4407 4408
				(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
			if (refresh_rate > highest_rfr) {
				highest_rfr = refresh_rate;
				master_stream = j;
			}
		}
	}
	for (j = 0;  j < stream_count; j++) {
4409
		if (stream_set[j])
4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422
			stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
	}
}

static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
{
	int i = 0;

	if (context->stream_count < 2)
		return;
	for (i = 0; i < context->stream_count ; i++) {
		if (!context->streams[i])
			continue;
4423 4424
		/*
		 * TODO: add a function to read AMD VSDB bits and set
4425
		 * crtc_sync_master.multi_sync_enabled flag
4426
		 * For now it's set to false
4427 4428 4429 4430 4431 4432
		 */
		set_multisync_trigger_params(context->streams[i]);
	}
	set_master_stream(context->streams, context->stream_count);
}

4433 4434 4435
static struct dc_stream_state *
create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
		       const struct drm_display_mode *drm_mode,
4436
		       const struct dm_connector_state *dm_state,
4437 4438
		       const struct dc_stream_state *old_stream,
		       int requested_bpc)
4439 4440
{
	struct drm_display_mode *preferred_mode = NULL;
4441
	struct drm_connector *drm_connector;
4442 4443
	const struct drm_connector_state *con_state =
		dm_state ? &dm_state->base : NULL;
4444
	struct dc_stream_state *stream = NULL;
4445 4446
	struct drm_display_mode mode = *drm_mode;
	bool native_mode_found = false;
4447 4448
	bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
	int mode_refresh;
4449
	int preferred_refresh = 0;
4450
#if defined(CONFIG_DRM_AMD_DC_DCN)
4451 4452 4453
	struct dsc_dec_dpcd_caps dsc_caps;
#endif
	uint32_t link_bandwidth_kbps;
4454

4455
	struct dc_sink *sink = NULL;
4456
	if (aconnector == NULL) {
4457
		DRM_ERROR("aconnector is NULL!\n");
4458
		return stream;
4459 4460 4461
	}

	drm_connector = &aconnector->base;
4462

4463
	if (!aconnector->dc_sink) {
4464 4465 4466
		sink = create_fake_sink(aconnector);
		if (!sink)
			return stream;
4467 4468
	} else {
		sink = aconnector->dc_sink;
4469
		dc_sink_retain(sink);
4470
	}
4471

4472
	stream = dc_create_stream_for_sink(sink);
4473

4474
	if (stream == NULL) {
4475
		DRM_ERROR("Failed to create stream for sink!\n");
4476
		goto finish;
4477 4478
	}

4479 4480
	stream->dm_stream_context = aconnector;

4481 4482 4483
	stream->timing.flags.LTE_340MCSC_SCRAMBLE =
		drm_connector->display_info.hdmi.scdc.scrambling.low_rates;

4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496
	list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
		/* Search for preferred mode */
		if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
			native_mode_found = true;
			break;
		}
	}
	if (!native_mode_found)
		preferred_mode = list_first_entry_or_null(
				&aconnector->base.modes,
				struct drm_display_mode,
				head);

4497 4498
	mode_refresh = drm_mode_vrefresh(&mode);

4499
	if (preferred_mode == NULL) {
4500 4501
		/*
		 * This may not be an error, the use case is when we have no
4502 4503 4504 4505
		 * usermode calls to reset and set mode upon hotplug. In this
		 * case, we call set mode ourselves to restore the previous mode
		 * and the modelist may not be filled in in time.
		 */
4506
		DRM_DEBUG_DRIVER("No preferred mode found\n");
4507 4508 4509
	} else {
		decide_crtc_timing_for_drm_display_mode(
				&mode, preferred_mode,
4510
				dm_state ? (dm_state->scaling != RMX_OFF) : false);
4511
		preferred_refresh = drm_mode_vrefresh(preferred_mode);
4512 4513
	}

4514 4515 4516
	if (!dm_state)
		drm_mode_set_crtcinfo(&mode, 0);

4517 4518 4519 4520 4521 4522
	/*
	* If scaling is enabled and refresh rate didn't change
	* we copy the vic and polarities of the old timings
	*/
	if (!scale || mode_refresh != preferred_refresh)
		fill_stream_properties_from_drm_display_mode(stream,
4523
			&mode, &aconnector->base, con_state, NULL, requested_bpc);
4524 4525
	else
		fill_stream_properties_from_drm_display_mode(stream,
4526
			&mode, &aconnector->base, con_state, old_stream, requested_bpc);
4527

4528 4529 4530
	stream->timing.flags.DSC = 0;

	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4531
#if defined(CONFIG_DRM_AMD_DC_DCN)
4532 4533
		dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
4534 4535
				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
				      &dsc_caps);
4536
#endif
4537 4538 4539
		link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
							     dc_link_get_link_cap(aconnector->dc_link));

4540
#if defined(CONFIG_DRM_AMD_DC_DCN)
4541
		if (dsc_caps.is_dsc_supported)
4542
			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
4543
						  &dsc_caps,
4544
						  aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
4545 4546 4547 4548
						  link_bandwidth_kbps,
						  &stream->timing,
						  &stream->timing.dsc_cfg))
				stream->timing.flags.DSC = 1;
4549
#endif
4550
	}
4551

4552 4553 4554 4555 4556
	update_stream_scaling_settings(&mode, dm_state, stream);

	fill_audio_info(
		&stream->audio_info,
		drm_connector,
4557
		sink);
4558

4559
	update_stream_signal(stream, sink);
4560

4561 4562
	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
		mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, false, false);
4563
	if (stream->link->psr_settings.psr_feature_enabled)	{
R
Roman Li 已提交
4564
		struct dc  *core_dc = stream->link->ctx->dc;
4565

R
Roman Li 已提交
4566
		if (dc_is_dmcu_initialized(core_dc)) {
4567 4568 4569 4570 4571 4572 4573 4574 4575
			//
			// should decide stream support vsc sdp colorimetry capability
			// before building vsc info packet
			//
			stream->use_vsc_sdp_for_colorimetry = false;
			if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
				stream->use_vsc_sdp_for_colorimetry =
					aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
			} else {
4576
				if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
4577 4578 4579
					stream->use_vsc_sdp_for_colorimetry = true;
			}
			mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
R
Roman Li 已提交
4580 4581
		}
	}
4582
finish:
4583
	dc_sink_release(sink);
4584

4585 4586 4587
	return stream;
}

4588
static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
4589 4590 4591 4592 4593 4594
{
	drm_crtc_cleanup(crtc);
	kfree(crtc);
}

static void dm_crtc_destroy_state(struct drm_crtc *crtc,
4595
				  struct drm_crtc_state *state)
4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635
{
	struct dm_crtc_state *cur = to_dm_crtc_state(state);

	/* TODO Destroy dc_stream objects are stream object is flattened */
	if (cur->stream)
		dc_stream_release(cur->stream);


	__drm_atomic_helper_crtc_destroy_state(state);


	kfree(state);
}

static void dm_crtc_reset_state(struct drm_crtc *crtc)
{
	struct dm_crtc_state *state;

	if (crtc->state)
		dm_crtc_destroy_state(crtc, crtc->state);

	state = kzalloc(sizeof(*state), GFP_KERNEL);
	if (WARN_ON(!state))
		return;

	crtc->state = &state->base;
	crtc->state->crtc = crtc;

}

static struct drm_crtc_state *
dm_crtc_duplicate_state(struct drm_crtc *crtc)
{
	struct dm_crtc_state *state, *cur;

	cur = to_dm_crtc_state(crtc->state);

	if (WARN_ON(!crtc->state))
		return NULL;

4636
	state = kzalloc(sizeof(*state), GFP_KERNEL);
4637 4638
	if (!state)
		return NULL;
4639 4640 4641 4642 4643 4644 4645 4646

	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

	if (cur->stream) {
		state->stream = cur->stream;
		dc_stream_retain(state->stream);
	}

4647 4648
	state->active_planes = cur->active_planes;
	state->interrupts_enabled = cur->interrupts_enabled;
4649
	state->vrr_params = cur->vrr_params;
4650
	state->vrr_infopacket = cur->vrr_infopacket;
4651
	state->abm_level = cur->abm_level;
4652 4653
	state->vrr_supported = cur->vrr_supported;
	state->freesync_config = cur->freesync_config;
4654
	state->crc_src = cur->crc_src;
4655 4656
	state->cm_has_degamma = cur->cm_has_degamma;
	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
4657

4658 4659 4660 4661 4662
	/* TODO Duplicate dc_stream after objects are stream object is flattened */

	return &state->base;
}

4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677
static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
{
	enum dc_irq_source irq_source;
	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
	struct amdgpu_device *adev = crtc->dev->dev_private;
	int rc;

	irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;

	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;

	DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
			 acrtc->crtc_id, enable ? "en" : "dis", rc);
	return rc;
}
4678 4679 4680 4681 4682 4683

static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
{
	enum dc_irq_source irq_source;
	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
	struct amdgpu_device *adev = crtc->dev->dev_private;
4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697
	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
	int rc = 0;

	if (enable) {
		/* vblank irq on -> Only need vupdate irq in vrr mode */
		if (amdgpu_dm_vrr_active(acrtc_state))
			rc = dm_set_vupdate_irq(crtc, true);
	} else {
		/* vblank irq off -> vupdate irq off */
		rc = dm_set_vupdate_irq(crtc, false);
	}

	if (rc)
		return rc;
4698 4699

	irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
4700
	return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712
}

static int dm_enable_vblank(struct drm_crtc *crtc)
{
	return dm_set_vblank(crtc, true);
}

static void dm_disable_vblank(struct drm_crtc *crtc)
{
	dm_set_vblank(crtc, false);
}

4713 4714 4715 4716 4717 4718 4719 4720 4721
/* Implemented only the options currently availible for the driver */
static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
	.reset = dm_crtc_reset_state,
	.destroy = amdgpu_dm_crtc_destroy,
	.gamma_set = drm_atomic_helper_legacy_gamma_set,
	.set_config = drm_atomic_helper_set_config,
	.page_flip = drm_atomic_helper_page_flip,
	.atomic_duplicate_state = dm_crtc_duplicate_state,
	.atomic_destroy_state = dm_crtc_destroy_state,
4722
	.set_crc_source = amdgpu_dm_crtc_set_crc_source,
4723
	.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
4724
	.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
4725
	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
4726 4727
	.enable_vblank = dm_enable_vblank,
	.disable_vblank = dm_disable_vblank,
4728
	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
4729 4730 4731 4732 4733 4734
};

static enum drm_connector_status
amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
{
	bool connected;
4735
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4736

4737 4738
	/*
	 * Notes:
4739 4740
	 * 1. This interface is NOT called in context of HPD irq.
	 * 2. This interface *is called* in context of user-mode ioctl. Which
4741 4742
	 * makes it a bad place for *any* MST-related activity.
	 */
4743

4744 4745
	if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
	    !aconnector->fake_enable)
4746 4747 4748 4749 4750 4751 4752 4753
		connected = (aconnector->dc_sink != NULL);
	else
		connected = (aconnector->base.force == DRM_FORCE_ON);

	return (connected ? connector_status_connected :
			connector_status_disconnected);
}

4754 4755 4756 4757
int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
					    struct drm_connector_state *connector_state,
					    struct drm_property *property,
					    uint64_t val)
4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800
{
	struct drm_device *dev = connector->dev;
	struct amdgpu_device *adev = dev->dev_private;
	struct dm_connector_state *dm_old_state =
		to_dm_connector_state(connector->state);
	struct dm_connector_state *dm_new_state =
		to_dm_connector_state(connector_state);

	int ret = -EINVAL;

	if (property == dev->mode_config.scaling_mode_property) {
		enum amdgpu_rmx_type rmx_type;

		switch (val) {
		case DRM_MODE_SCALE_CENTER:
			rmx_type = RMX_CENTER;
			break;
		case DRM_MODE_SCALE_ASPECT:
			rmx_type = RMX_ASPECT;
			break;
		case DRM_MODE_SCALE_FULLSCREEN:
			rmx_type = RMX_FULL;
			break;
		case DRM_MODE_SCALE_NONE:
		default:
			rmx_type = RMX_OFF;
			break;
		}

		if (dm_old_state->scaling == rmx_type)
			return 0;

		dm_new_state->scaling = rmx_type;
		ret = 0;
	} else if (property == adev->mode_info.underscan_hborder_property) {
		dm_new_state->underscan_hborder = val;
		ret = 0;
	} else if (property == adev->mode_info.underscan_vborder_property) {
		dm_new_state->underscan_vborder = val;
		ret = 0;
	} else if (property == adev->mode_info.underscan_property) {
		dm_new_state->underscan_enable = val;
		ret = 0;
4801 4802 4803
	} else if (property == adev->mode_info.abm_level_property) {
		dm_new_state->abm_level = val;
		ret = 0;
4804 4805 4806 4807 4808
	}

	return ret;
}

4809 4810 4811 4812
int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
					    const struct drm_connector_state *state,
					    struct drm_property *property,
					    uint64_t *val)
4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845
{
	struct drm_device *dev = connector->dev;
	struct amdgpu_device *adev = dev->dev_private;
	struct dm_connector_state *dm_state =
		to_dm_connector_state(state);
	int ret = -EINVAL;

	if (property == dev->mode_config.scaling_mode_property) {
		switch (dm_state->scaling) {
		case RMX_CENTER:
			*val = DRM_MODE_SCALE_CENTER;
			break;
		case RMX_ASPECT:
			*val = DRM_MODE_SCALE_ASPECT;
			break;
		case RMX_FULL:
			*val = DRM_MODE_SCALE_FULLSCREEN;
			break;
		case RMX_OFF:
		default:
			*val = DRM_MODE_SCALE_NONE;
			break;
		}
		ret = 0;
	} else if (property == adev->mode_info.underscan_hborder_property) {
		*val = dm_state->underscan_hborder;
		ret = 0;
	} else if (property == adev->mode_info.underscan_vborder_property) {
		*val = dm_state->underscan_vborder;
		ret = 0;
	} else if (property == adev->mode_info.underscan_property) {
		*val = dm_state->underscan_enable;
		ret = 0;
4846 4847 4848
	} else if (property == adev->mode_info.abm_level_property) {
		*val = dm_state->abm_level;
		ret = 0;
4849
	}
4850

4851 4852 4853
	return ret;
}

4854 4855 4856 4857 4858 4859 4860
static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
{
	struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);

	drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
}

4861
static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
4862
{
4863
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4864 4865 4866
	const struct dc_link *link = aconnector->dc_link;
	struct amdgpu_device *adev = connector->dev->dev_private;
	struct amdgpu_display_manager *dm = &adev->dm;
4867

4868 4869 4870
#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
	defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

4871
	if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4872 4873 4874 4875
	    link->type != dc_connection_none &&
	    dm->backlight_dev) {
		backlight_device_unregister(dm->backlight_dev);
		dm->backlight_dev = NULL;
4876 4877
	}
#endif
4878 4879 4880 4881 4882 4883 4884 4885

	if (aconnector->dc_em_sink)
		dc_sink_release(aconnector->dc_em_sink);
	aconnector->dc_em_sink = NULL;
	if (aconnector->dc_sink)
		dc_sink_release(aconnector->dc_sink);
	aconnector->dc_sink = NULL;

4886
	drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
4887 4888
	drm_connector_unregister(connector);
	drm_connector_cleanup(connector);
4889 4890 4891 4892
	if (aconnector->i2c) {
		i2c_del_adapter(&aconnector->i2c->base);
		kfree(aconnector->i2c);
	}
4893
	kfree(aconnector->dm_dp_aux.aux.name);
4894

4895 4896 4897 4898 4899 4900 4901 4902
	kfree(connector);
}

void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
{
	struct dm_connector_state *state =
		to_dm_connector_state(connector->state);

4903 4904 4905
	if (connector->state)
		__drm_atomic_helper_connector_destroy_state(connector->state);

4906 4907 4908 4909 4910 4911 4912 4913 4914
	kfree(state);

	state = kzalloc(sizeof(*state), GFP_KERNEL);

	if (state) {
		state->scaling = RMX_OFF;
		state->underscan_enable = false;
		state->underscan_hborder = 0;
		state->underscan_vborder = 0;
4915
		state->base.max_requested_bpc = 8;
4916 4917
		state->vcpi_slots = 0;
		state->pbn = 0;
4918 4919 4920
		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
			state->abm_level = amdgpu_dm_abm_level;

4921
		__drm_atomic_helper_connector_reset(connector, &state->base);
4922 4923 4924
	}
}

4925 4926
struct drm_connector_state *
amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
4927 4928 4929 4930 4931 4932 4933
{
	struct dm_connector_state *state =
		to_dm_connector_state(connector->state);

	struct dm_connector_state *new_state =
			kmemdup(state, sizeof(*state), GFP_KERNEL);

4934 4935
	if (!new_state)
		return NULL;
4936

4937 4938 4939
	__drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);

	new_state->freesync_capable = state->freesync_capable;
4940
	new_state->abm_level = state->abm_level;
4941 4942 4943 4944
	new_state->scaling = state->scaling;
	new_state->underscan_enable = state->underscan_enable;
	new_state->underscan_hborder = state->underscan_hborder;
	new_state->underscan_vborder = state->underscan_vborder;
4945 4946
	new_state->vcpi_slots = state->vcpi_slots;
	new_state->pbn = state->pbn;
4947
	return &new_state->base;
4948 4949
}

4950 4951 4952
static int
amdgpu_dm_connector_late_register(struct drm_connector *connector)
{
4953
#if defined(CONFIG_DEBUG_FS)
4954 4955
	struct amdgpu_dm_connector *amdgpu_dm_connector =
		to_amdgpu_dm_connector(connector);
4956
	int r;
4957

4958 4959 4960 4961 4962 4963 4964
	if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
	    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
		amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
		r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
		if (r)
			return r;
	}
4965 4966 4967 4968 4969 4970 4971

	connector_debugfs_init(amdgpu_dm_connector);
#endif

	return 0;
}

4972 4973 4974 4975 4976 4977 4978 4979
static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
	.reset = amdgpu_dm_connector_funcs_reset,
	.detect = amdgpu_dm_connector_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.destroy = amdgpu_dm_connector_destroy,
	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
4980
	.atomic_get_property = amdgpu_dm_connector_atomic_get_property,
4981
	.late_register = amdgpu_dm_connector_late_register,
4982
	.early_unregister = amdgpu_dm_connector_unregister
4983 4984 4985 4986 4987 4988 4989
};

static int get_modes(struct drm_connector *connector)
{
	return amdgpu_dm_connector_get_modes(connector);
}

4990
static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
4991 4992 4993 4994 4995
{
	struct dc_sink_init_data init_params = {
			.link = aconnector->dc_link,
			.sink_signal = SIGNAL_TYPE_VIRTUAL
	};
4996
	struct edid *edid;
4997

4998
	if (!aconnector->base.edid_blob_ptr) {
4999 5000 5001 5002 5003 5004 5005 5006
		DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
				aconnector->base.name);

		aconnector->base.force = DRM_FORCE_OFF;
		aconnector->base.override_edid = false;
		return;
	}

5007 5008
	edid = (struct edid *) aconnector->base.edid_blob_ptr->data;

5009 5010 5011 5012 5013 5014 5015 5016
	aconnector->edid = edid;

	aconnector->dc_em_sink = dc_link_add_remote_sink(
		aconnector->dc_link,
		(uint8_t *)edid,
		(edid->extensions + 1) * EDID_LENGTH,
		&init_params);

5017
	if (aconnector->base.force == DRM_FORCE_ON) {
5018 5019 5020
		aconnector->dc_sink = aconnector->dc_link->local_sink ?
		aconnector->dc_link->local_sink :
		aconnector->dc_em_sink;
5021 5022
		dc_sink_retain(aconnector->dc_sink);
	}
5023 5024
}

5025
static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
5026 5027 5028
{
	struct dc_link *link = (struct dc_link *)aconnector->dc_link;

5029 5030
	/*
	 * In case of headless boot with force on for DP managed connector
5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042
	 * Those settings have to be != 0 to get initial modeset
	 */
	if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
		link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
		link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
	}


	aconnector->base.override_edid = true;
	create_eml_sink(aconnector);
}

5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066
static struct dc_stream_state *
create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
				const struct drm_display_mode *drm_mode,
				const struct dm_connector_state *dm_state,
				const struct dc_stream_state *old_stream)
{
	struct drm_connector *connector = &aconnector->base;
	struct amdgpu_device *adev = connector->dev->dev_private;
	struct dc_stream_state *stream;
	int requested_bpc = connector->state ? connector->state->max_requested_bpc : 8;
	enum dc_status dc_result = DC_OK;

	do {
		stream = create_stream_for_sink(aconnector, drm_mode,
						dm_state, old_stream,
						requested_bpc);
		if (stream == NULL) {
			DRM_ERROR("Failed to create stream for sink!\n");
			break;
		}

		dc_result = dc_validate_stream(adev->dm.dc, stream);

		if (dc_result != DC_OK) {
5067
			DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
5068 5069 5070
				      drm_mode->hdisplay,
				      drm_mode->vdisplay,
				      drm_mode->clock,
5071 5072
				      dc_result,
				      dc_status_to_str(dc_result));
5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083

			dc_stream_release(stream);
			stream = NULL;
			requested_bpc -= 2; /* lower bpc to retry validation */
		}

	} while (stream == NULL && requested_bpc >= 6);

	return stream;
}

5084
enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
5085
				   struct drm_display_mode *mode)
5086 5087 5088 5089
{
	int result = MODE_ERROR;
	struct dc_sink *dc_sink;
	/* TODO: Unhardcode stream count */
5090
	struct dc_stream_state *stream;
5091
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5092 5093 5094 5095 5096

	if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
			(mode->flags & DRM_MODE_FLAG_DBLSCAN))
		return result;

5097 5098
	/*
	 * Only run this the first time mode_valid is called to initilialize
5099 5100 5101 5102 5103 5104
	 * EDID mgmt
	 */
	if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
		!aconnector->dc_em_sink)
		handle_edid_mgmt(aconnector);

5105
	dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
5106

5107
	if (dc_sink == NULL) {
5108 5109 5110 5111
		DRM_ERROR("dc_sink is NULL!\n");
		goto fail;
	}

5112 5113 5114
	stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
	if (stream) {
		dc_stream_release(stream);
5115
		result = MODE_OK;
5116
	}
5117 5118 5119 5120 5121 5122

fail:
	/* TODO: error handling*/
	return result;
}

5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202
static int fill_hdr_info_packet(const struct drm_connector_state *state,
				struct dc_info_packet *out)
{
	struct hdmi_drm_infoframe frame;
	unsigned char buf[30]; /* 26 + 4 */
	ssize_t len;
	int ret, i;

	memset(out, 0, sizeof(*out));

	if (!state->hdr_output_metadata)
		return 0;

	ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
	if (ret)
		return ret;

	len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
	if (len < 0)
		return (int)len;

	/* Static metadata is a fixed 26 bytes + 4 byte header. */
	if (len != 30)
		return -EINVAL;

	/* Prepare the infopacket for DC. */
	switch (state->connector->connector_type) {
	case DRM_MODE_CONNECTOR_HDMIA:
		out->hb0 = 0x87; /* type */
		out->hb1 = 0x01; /* version */
		out->hb2 = 0x1A; /* length */
		out->sb[0] = buf[3]; /* checksum */
		i = 1;
		break;

	case DRM_MODE_CONNECTOR_DisplayPort:
	case DRM_MODE_CONNECTOR_eDP:
		out->hb0 = 0x00; /* sdp id, zero */
		out->hb1 = 0x87; /* type */
		out->hb2 = 0x1D; /* payload len - 1 */
		out->hb3 = (0x13 << 2); /* sdp version */
		out->sb[0] = 0x01; /* version */
		out->sb[1] = 0x1A; /* length */
		i = 2;
		break;

	default:
		return -EINVAL;
	}

	memcpy(&out->sb[i], &buf[4], 26);
	out->valid = true;

	print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
		       sizeof(out->sb), false);

	return 0;
}

static bool
is_hdr_metadata_different(const struct drm_connector_state *old_state,
			  const struct drm_connector_state *new_state)
{
	struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
	struct drm_property_blob *new_blob = new_state->hdr_output_metadata;

	if (old_blob != new_blob) {
		if (old_blob && new_blob &&
		    old_blob->length == new_blob->length)
			return memcmp(old_blob->data, new_blob->data,
				      old_blob->length);

		return true;
	}

	return false;
}

static int
amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
5203
				 struct drm_atomic_state *state)
5204
{
5205 5206
	struct drm_connector_state *new_con_state =
		drm_atomic_get_new_connector_state(state, conn);
5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230
	struct drm_connector_state *old_con_state =
		drm_atomic_get_old_connector_state(state, conn);
	struct drm_crtc *crtc = new_con_state->crtc;
	struct drm_crtc_state *new_crtc_state;
	int ret;

	if (!crtc)
		return 0;

	if (is_hdr_metadata_different(old_con_state, new_con_state)) {
		struct dc_info_packet hdr_infopacket;

		ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
		if (ret)
			return ret;

		new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
		if (IS_ERR(new_crtc_state))
			return PTR_ERR(new_crtc_state);

		/*
		 * DC considers the stream backends changed if the
		 * static metadata changes. Forcing the modeset also
		 * gives a simple way for userspace to switch from
5231 5232 5233 5234 5235 5236
		 * 8bpc to 10bpc when setting the metadata to enter
		 * or exit HDR.
		 *
		 * Changing the static metadata after it's been
		 * set is permissible, however. So only force a
		 * modeset if we're entering or exiting HDR.
5237
		 */
5238 5239 5240
		new_crtc_state->mode_changed =
			!old_con_state->hdr_output_metadata ||
			!new_con_state->hdr_output_metadata;
5241 5242 5243 5244 5245
	}

	return 0;
}

5246 5247 5248
static const struct drm_connector_helper_funcs
amdgpu_dm_connector_helper_funcs = {
	/*
5249
	 * If hotplugging a second bigger display in FB Con mode, bigger resolution
5250
	 * modes will be filtered by drm_mode_validate_size(), and those modes
5251
	 * are missing after user start lightdm. So we need to renew modes list.
5252 5253
	 * in get_modes call back, not just return the modes count
	 */
5254 5255
	.get_modes = get_modes,
	.mode_valid = amdgpu_dm_connector_mode_valid,
5256
	.atomic_check = amdgpu_dm_connector_atomic_check,
5257 5258 5259 5260 5261 5262
};

static void dm_crtc_helper_disable(struct drm_crtc *crtc)
{
}

5263 5264 5265 5266 5267 5268 5269 5270 5271 5272 5273 5274 5275
static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
{
	struct drm_device *dev = new_crtc_state->crtc->dev;
	struct drm_plane *plane;

	drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
		if (plane->type == DRM_PLANE_TYPE_CURSOR)
			return true;
	}

	return false;
}

5276
static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
5277 5278 5279 5280 5281 5282 5283 5284 5285 5286 5287 5288 5289 5290 5291 5292 5293 5294 5295 5296 5297 5298 5299 5300 5301 5302 5303 5304
{
	struct drm_atomic_state *state = new_crtc_state->state;
	struct drm_plane *plane;
	int num_active = 0;

	drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
		struct drm_plane_state *new_plane_state;

		/* Cursor planes are "fake". */
		if (plane->type == DRM_PLANE_TYPE_CURSOR)
			continue;

		new_plane_state = drm_atomic_get_new_plane_state(state, plane);

		if (!new_plane_state) {
			/*
			 * The plane is enable on the CRTC and hasn't changed
			 * state. This means that it previously passed
			 * validation and is therefore enabled.
			 */
			num_active += 1;
			continue;
		}

		/* We need a framebuffer to be considered enabled. */
		num_active += (new_plane_state->fb != NULL);
	}

5305 5306 5307 5308 5309 5310 5311 5312 5313 5314 5315 5316 5317 5318 5319 5320 5321 5322 5323 5324 5325 5326 5327 5328 5329 5330
	return num_active;
}

/*
 * Sets whether interrupts should be enabled on a specific CRTC.
 * We require that the stream be enabled and that there exist active
 * DC planes on the stream.
 */
static void
dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
			       struct drm_crtc_state *new_crtc_state)
{
	struct dm_crtc_state *dm_new_crtc_state =
		to_dm_crtc_state(new_crtc_state);

	dm_new_crtc_state->active_planes = 0;
	dm_new_crtc_state->interrupts_enabled = false;

	if (!dm_new_crtc_state->stream)
		return;

	dm_new_crtc_state->active_planes =
		count_crtc_active_planes(new_crtc_state);

	dm_new_crtc_state->interrupts_enabled =
		dm_new_crtc_state->active_planes > 0;
5331 5332
}

5333 5334
static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
				       struct drm_crtc_state *state)
5335 5336 5337 5338 5339 5340
{
	struct amdgpu_device *adev = crtc->dev->dev_private;
	struct dc *dc = adev->dm.dc;
	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
	int ret = -EINVAL;

5341 5342 5343 5344 5345 5346 5347 5348
	/*
	 * Update interrupt state for the CRTC. This needs to happen whenever
	 * the CRTC has changed or whenever any of its planes have changed.
	 * Atomic check satisfies both of these requirements since the CRTC
	 * is added to the state by DRM during drm_atomic_helper_check_planes.
	 */
	dm_update_crtc_interrupt_state(crtc, state);

5349 5350
	if (unlikely(!dm_crtc_state->stream &&
		     modeset_required(state, NULL, dm_crtc_state->stream))) {
5351 5352 5353 5354
		WARN_ON(1);
		return ret;
	}

5355
	/* In some use cases, like reset, no stream is attached */
5356 5357 5358
	if (!dm_crtc_state->stream)
		return 0;

5359 5360 5361 5362
	/*
	 * We want at least one hardware plane enabled to use
	 * the stream with a cursor enabled.
	 */
5363
	if (state->enable && state->active &&
5364
	    does_crtc_have_active_cursor(state) &&
5365
	    dm_crtc_state->active_planes == 0)
5366 5367
		return -EINVAL;

5368
	if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
5369 5370 5371 5372 5373
		return 0;

	return ret;
}

5374 5375 5376
static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
				      const struct drm_display_mode *mode,
				      struct drm_display_mode *adjusted_mode)
5377 5378 5379 5380 5381 5382 5383
{
	return true;
}

static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
	.disable = dm_crtc_helper_disable,
	.atomic_check = dm_crtc_helper_atomic_check,
5384 5385
	.mode_fixup = dm_crtc_helper_mode_fixup,
	.get_scanout_position = amdgpu_crtc_get_scanout_position,
5386 5387 5388 5389 5390 5391 5392
};

static void dm_encoder_helper_disable(struct drm_encoder *encoder)
{

}

5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413
static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
{
	switch (display_color_depth) {
		case COLOR_DEPTH_666:
			return 6;
		case COLOR_DEPTH_888:
			return 8;
		case COLOR_DEPTH_101010:
			return 10;
		case COLOR_DEPTH_121212:
			return 12;
		case COLOR_DEPTH_141414:
			return 14;
		case COLOR_DEPTH_161616:
			return 16;
		default:
			break;
		}
	return 0;
}

5414 5415 5416
static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
					  struct drm_crtc_state *crtc_state,
					  struct drm_connector_state *conn_state)
5417
{
5418 5419 5420 5421 5422 5423 5424 5425 5426
	struct drm_atomic_state *state = crtc_state->state;
	struct drm_connector *connector = conn_state->connector;
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
	struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
	const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
	struct drm_dp_mst_topology_mgr *mst_mgr;
	struct drm_dp_mst_port *mst_port;
	enum dc_color_depth color_depth;
	int clock, bpp = 0;
5427
	bool is_y420 = false;
5428 5429 5430 5431 5432 5433 5434 5435 5436 5437 5438

	if (!aconnector->port || !aconnector->dc_sink)
		return 0;

	mst_port = aconnector->port;
	mst_mgr = &aconnector->mst_port->mst_mgr;

	if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
		return 0;

	if (!state->duplicated) {
5439
		int max_bpc = conn_state->max_requested_bpc;
5440 5441
		is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
				aconnector->force_yuv420_output;
5442 5443 5444
		color_depth = convert_color_depth_from_display_info(connector,
								    is_y420,
								    max_bpc);
5445 5446
		bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
		clock = adjusted_mode->clock;
5447
		dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
5448 5449 5450 5451
	}
	dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
									   mst_mgr,
									   mst_port,
5452
									   dm_new_connector_state->pbn,
5453
									   dm_mst_get_pbn_divider(aconnector->dc_link));
5454 5455 5456 5457
	if (dm_new_connector_state->vcpi_slots < 0) {
		DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
		return dm_new_connector_state->vcpi_slots;
	}
5458 5459 5460 5461 5462 5463 5464 5465
	return 0;
}

const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
	.disable = dm_encoder_helper_disable,
	.atomic_check = dm_encoder_helper_atomic_check
};

5466
#if defined(CONFIG_DRM_AMD_DC_DCN)
5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504 5505 5506 5507 5508 5509 5510 5511 5512 5513 5514 5515 5516 5517 5518 5519 5520 5521 5522 5523 5524 5525 5526 5527 5528
static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
					    struct dc_state *dc_state)
{
	struct dc_stream_state *stream = NULL;
	struct drm_connector *connector;
	struct drm_connector_state *new_con_state, *old_con_state;
	struct amdgpu_dm_connector *aconnector;
	struct dm_connector_state *dm_conn_state;
	int i, j, clock, bpp;
	int vcpi, pbn_div, pbn = 0;

	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {

		aconnector = to_amdgpu_dm_connector(connector);

		if (!aconnector->port)
			continue;

		if (!new_con_state || !new_con_state->crtc)
			continue;

		dm_conn_state = to_dm_connector_state(new_con_state);

		for (j = 0; j < dc_state->stream_count; j++) {
			stream = dc_state->streams[j];
			if (!stream)
				continue;

			if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector)
				break;

			stream = NULL;
		}

		if (!stream)
			continue;

		if (stream->timing.flags.DSC != 1) {
			drm_dp_mst_atomic_enable_dsc(state,
						     aconnector->port,
						     dm_conn_state->pbn,
						     0,
						     false);
			continue;
		}

		pbn_div = dm_mst_get_pbn_divider(stream->link);
		bpp = stream->timing.dsc_cfg.bits_per_pixel;
		clock = stream->timing.pix_clk_100hz / 10;
		pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
		vcpi = drm_dp_mst_atomic_enable_dsc(state,
						    aconnector->port,
						    pbn, pbn_div,
						    true);
		if (vcpi < 0)
			return vcpi;

		dm_conn_state->pbn = pbn;
		dm_conn_state->vcpi_slots = vcpi;
	}
	return 0;
}
5529
#endif
5530

5531 5532 5533 5534 5535 5536 5537 5538
static void dm_drm_plane_reset(struct drm_plane *plane)
{
	struct dm_plane_state *amdgpu_state = NULL;

	if (plane->state)
		plane->funcs->atomic_destroy_state(plane, plane->state);

	amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
5539
	WARN_ON(amdgpu_state == NULL);
5540

5541 5542
	if (amdgpu_state)
		__drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
5543 5544 5545 5546 5547 5548 5549 5550 5551 5552 5553 5554 5555 5556
}

static struct drm_plane_state *
dm_drm_plane_duplicate_state(struct drm_plane *plane)
{
	struct dm_plane_state *dm_plane_state, *old_dm_plane_state;

	old_dm_plane_state = to_dm_plane_state(plane->state);
	dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
	if (!dm_plane_state)
		return NULL;

	__drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);

5557 5558 5559
	if (old_dm_plane_state->dc_state) {
		dm_plane_state->dc_state = old_dm_plane_state->dc_state;
		dc_plane_state_retain(dm_plane_state->dc_state);
5560 5561 5562 5563 5564
	}

	return &dm_plane_state->base;
}

5565
static void dm_drm_plane_destroy_state(struct drm_plane *plane,
5566
				struct drm_plane_state *state)
5567 5568 5569
{
	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);

5570 5571
	if (dm_plane_state->dc_state)
		dc_plane_state_release(dm_plane_state->dc_state);
5572

5573
	drm_atomic_helper_plane_destroy_state(plane, state);
5574 5575 5576 5577 5578
}

static const struct drm_plane_funcs dm_plane_funcs = {
	.update_plane	= drm_atomic_helper_update_plane,
	.disable_plane	= drm_atomic_helper_disable_plane,
5579
	.destroy	= drm_primary_helper_destroy,
5580 5581 5582 5583 5584
	.reset = dm_drm_plane_reset,
	.atomic_duplicate_state = dm_drm_plane_duplicate_state,
	.atomic_destroy_state = dm_drm_plane_destroy_state,
};

5585 5586
static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
				      struct drm_plane_state *new_state)
5587 5588 5589
{
	struct amdgpu_framebuffer *afb;
	struct drm_gem_object *obj;
5590
	struct amdgpu_device *adev;
5591 5592
	struct amdgpu_bo *rbo;
	struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
5593 5594 5595
	struct list_head list;
	struct ttm_validate_buffer tv;
	struct ww_acquire_ctx ticket;
5596
	uint64_t tiling_flags;
5597 5598
	uint32_t domain;
	int r;
5599
	bool tmz_surface = false;
5600
	bool force_disable_dcc = false;
5601 5602 5603 5604 5605

	dm_plane_state_old = to_dm_plane_state(plane->state);
	dm_plane_state_new = to_dm_plane_state(new_state);

	if (!new_state->fb) {
5606
		DRM_DEBUG_DRIVER("No FB bound\n");
5607 5608 5609 5610
		return 0;
	}

	afb = to_amdgpu_framebuffer(new_state->fb);
5611
	obj = new_state->fb->obj[0];
5612
	rbo = gem_to_amdgpu_bo(obj);
5613
	adev = amdgpu_ttm_adev(rbo->tbo.bdev);
5614 5615 5616 5617 5618 5619
	INIT_LIST_HEAD(&list);

	tv.bo = &rbo->tbo;
	tv.num_shared = 1;
	list_add(&tv.head, &list);

5620
	r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL);
5621 5622
	if (r) {
		dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
5623
		return r;
5624
	}
5625

5626
	if (plane->type != DRM_PLANE_TYPE_CURSOR)
5627
		domain = amdgpu_display_supported_domains(adev, rbo->flags);
5628 5629
	else
		domain = AMDGPU_GEM_DOMAIN_VRAM;
5630

5631
	r = amdgpu_bo_pin(rbo, domain);
5632
	if (unlikely(r != 0)) {
5633 5634
		if (r != -ERESTARTSYS)
			DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
5635
		ttm_eu_backoff_reservation(&ticket, &list);
5636 5637 5638
		return r;
	}

5639 5640 5641
	r = amdgpu_ttm_alloc_gart(&rbo->tbo);
	if (unlikely(r != 0)) {
		amdgpu_bo_unpin(rbo);
5642
		ttm_eu_backoff_reservation(&ticket, &list);
5643
		DRM_ERROR("%p bind failed\n", rbo);
5644 5645
		return r;
	}
5646 5647 5648

	amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);

5649 5650
	tmz_surface = amdgpu_bo_encrypted(rbo);

5651
	ttm_eu_backoff_reservation(&ticket, &list);
5652

5653
	afb->address = amdgpu_bo_gpu_offset(rbo);
5654 5655 5656

	amdgpu_bo_ref(rbo);

5657 5658 5659
	if (dm_plane_state_new->dc_state &&
			dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
		struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
5660

5661
		force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5662
		fill_plane_buffer_attributes(
5663 5664
			adev, afb, plane_state->format, plane_state->rotation,
			tiling_flags, &plane_state->tiling_info,
5665
			&plane_state->plane_size, &plane_state->dcc,
5666
			&plane_state->address, tmz_surface,
5667
			force_disable_dcc);
5668 5669 5670 5671 5672
	}

	return 0;
}

5673 5674
static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
				       struct drm_plane_state *old_state)
5675 5676 5677 5678 5679 5680 5681
{
	struct amdgpu_bo *rbo;
	int r;

	if (!old_state->fb)
		return;

5682
	rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
5683 5684 5685 5686
	r = amdgpu_bo_reserve(rbo, false);
	if (unlikely(r)) {
		DRM_ERROR("failed to reserve rbo before unpin\n");
		return;
5687 5688 5689 5690 5691
	}

	amdgpu_bo_unpin(rbo);
	amdgpu_bo_unreserve(rbo);
	amdgpu_bo_unref(&rbo);
5692 5693
}

5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704
static int dm_plane_helper_check_state(struct drm_plane_state *state,
				       struct drm_crtc_state *new_crtc_state)
{
	int max_downscale = 0;
	int max_upscale = INT_MAX;

	/* TODO: These should be checked against DC plane caps */
	return drm_atomic_helper_check_plane_state(
		state, new_crtc_state, max_downscale, max_upscale, true, true);
}

5705 5706
static int dm_plane_atomic_check(struct drm_plane *plane,
				 struct drm_plane_state *state)
5707 5708 5709
{
	struct amdgpu_device *adev = plane->dev->dev_private;
	struct dc *dc = adev->dm.dc;
5710
	struct dm_plane_state *dm_plane_state;
5711
	struct dc_scaling_info scaling_info;
5712
	struct drm_crtc_state *new_crtc_state;
5713
	int ret;
5714 5715

	dm_plane_state = to_dm_plane_state(state);
5716

5717
	if (!dm_plane_state->dc_state)
5718
		return 0;
5719

5720 5721 5722 5723 5724 5725 5726 5727 5728
	new_crtc_state =
		drm_atomic_get_new_crtc_state(state->state, state->crtc);
	if (!new_crtc_state)
		return -EINVAL;

	ret = dm_plane_helper_check_state(state, new_crtc_state);
	if (ret)
		return ret;

5729 5730 5731
	ret = fill_dc_scaling_info(state, &scaling_info);
	if (ret)
		return ret;
5732

5733
	if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
5734 5735 5736 5737 5738
		return 0;

	return -EINVAL;
}

5739 5740 5741 5742 5743 5744 5745 5746 5747 5748 5749 5750 5751 5752 5753 5754
static int dm_plane_atomic_async_check(struct drm_plane *plane,
				       struct drm_plane_state *new_plane_state)
{
	/* Only support async updates on cursor planes. */
	if (plane->type != DRM_PLANE_TYPE_CURSOR)
		return -EINVAL;

	return 0;
}

static void dm_plane_atomic_async_update(struct drm_plane *plane,
					 struct drm_plane_state *new_state)
{
	struct drm_plane_state *old_state =
		drm_atomic_get_old_plane_state(new_state->state, plane);

5755
	swap(plane->state->fb, new_state->fb);
5756 5757 5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768

	plane->state->src_x = new_state->src_x;
	plane->state->src_y = new_state->src_y;
	plane->state->src_w = new_state->src_w;
	plane->state->src_h = new_state->src_h;
	plane->state->crtc_x = new_state->crtc_x;
	plane->state->crtc_y = new_state->crtc_y;
	plane->state->crtc_w = new_state->crtc_w;
	plane->state->crtc_h = new_state->crtc_h;

	handle_cursor_update(plane, old_state);
}

5769 5770 5771
static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
	.prepare_fb = dm_plane_helper_prepare_fb,
	.cleanup_fb = dm_plane_helper_cleanup_fb,
5772
	.atomic_check = dm_plane_atomic_check,
5773 5774
	.atomic_async_check = dm_plane_atomic_async_check,
	.atomic_async_update = dm_plane_atomic_async_update
5775 5776 5777 5778 5779 5780
};

/*
 * TODO: these are currently initialized to rgb formats only.
 * For future use cases we should either initialize them dynamically based on
 * plane capabilities, or initialize this array to all formats, so internal drm
5781
 * check will succeed, and let DC implement proper check
5782
 */
D
Dave Airlie 已提交
5783
static const uint32_t rgb_formats[] = {
5784 5785 5786 5787 5788 5789 5790
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_RGBA8888,
	DRM_FORMAT_XRGB2101010,
	DRM_FORMAT_XBGR2101010,
	DRM_FORMAT_ARGB2101010,
	DRM_FORMAT_ABGR2101010,
5791 5792
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ABGR8888,
5793
	DRM_FORMAT_RGB565,
5794 5795
};

5796 5797 5798 5799 5800 5801
static const uint32_t overlay_formats[] = {
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_RGBA8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ABGR8888,
5802
	DRM_FORMAT_RGB565
5803 5804 5805 5806 5807 5808
};

static const u32 cursor_formats[] = {
	DRM_FORMAT_ARGB8888
};

5809 5810 5811
static int get_plane_formats(const struct drm_plane *plane,
			     const struct dc_plane_cap *plane_cap,
			     uint32_t *formats, int max_formats)
5812
{
5813 5814 5815 5816 5817 5818 5819
	int i, num_formats = 0;

	/*
	 * TODO: Query support for each group of formats directly from
	 * DC plane caps. This will require adding more formats to the
	 * caps list.
	 */
5820

H
Harry Wentland 已提交
5821
	switch (plane->type) {
5822
	case DRM_PLANE_TYPE_PRIMARY:
5823 5824 5825 5826 5827 5828 5829
		for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
			if (num_formats >= max_formats)
				break;

			formats[num_formats++] = rgb_formats[i];
		}

5830
		if (plane_cap && plane_cap->pixel_format_support.nv12)
5831
			formats[num_formats++] = DRM_FORMAT_NV12;
5832 5833
		if (plane_cap && plane_cap->pixel_format_support.p010)
			formats[num_formats++] = DRM_FORMAT_P010;
5834 5835 5836
		if (plane_cap && plane_cap->pixel_format_support.fp16) {
			formats[num_formats++] = DRM_FORMAT_XRGB16161616F;
			formats[num_formats++] = DRM_FORMAT_ARGB16161616F;
5837 5838
			formats[num_formats++] = DRM_FORMAT_XBGR16161616F;
			formats[num_formats++] = DRM_FORMAT_ABGR16161616F;
5839
		}
5840
		break;
5841

5842
	case DRM_PLANE_TYPE_OVERLAY:
5843 5844 5845 5846 5847 5848
		for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
			if (num_formats >= max_formats)
				break;

			formats[num_formats++] = overlay_formats[i];
		}
5849
		break;
5850

5851
	case DRM_PLANE_TYPE_CURSOR:
5852 5853 5854 5855 5856 5857
		for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
			if (num_formats >= max_formats)
				break;

			formats[num_formats++] = cursor_formats[i];
		}
5858 5859 5860
		break;
	}

5861 5862 5863 5864 5865 5866 5867 5868 5869 5870 5871 5872 5873 5874 5875 5876 5877 5878 5879 5880 5881
	return num_formats;
}

static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
				struct drm_plane *plane,
				unsigned long possible_crtcs,
				const struct dc_plane_cap *plane_cap)
{
	uint32_t formats[32];
	int num_formats;
	int res = -EPERM;

	num_formats = get_plane_formats(plane, plane_cap, formats,
					ARRAY_SIZE(formats));

	res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
				       &dm_plane_funcs, formats, num_formats,
				       NULL, plane->type, NULL);
	if (res)
		return res;

5882 5883
	if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
	    plane_cap && plane_cap->per_pixel_alpha) {
5884 5885 5886 5887 5888 5889 5890
		unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
					  BIT(DRM_MODE_BLEND_PREMULTI);

		drm_plane_create_alpha_property(plane);
		drm_plane_create_blend_mode_property(plane, blend_caps);
	}

5891
	if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
5892 5893 5894
	    plane_cap &&
	    (plane_cap->pixel_format_support.nv12 ||
	     plane_cap->pixel_format_support.p010)) {
5895 5896 5897 5898
		/* This only affects YUV formats. */
		drm_plane_create_color_properties(
			plane,
			BIT(DRM_COLOR_YCBCR_BT601) |
5899 5900
			BIT(DRM_COLOR_YCBCR_BT709) |
			BIT(DRM_COLOR_YCBCR_BT2020),
5901 5902 5903 5904 5905
			BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
			BIT(DRM_COLOR_YCBCR_FULL_RANGE),
			DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
	}

H
Harry Wentland 已提交
5906
	drm_plane_helper_add(plane, &dm_plane_helper_funcs);
5907

5908
	/* Create (reset) the plane state */
H
Harry Wentland 已提交
5909 5910
	if (plane->funcs->reset)
		plane->funcs->reset(plane);
5911

5912
	return 0;
5913 5914
}

5915 5916 5917
static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
			       struct drm_plane *plane,
			       uint32_t crtc_index)
5918 5919
{
	struct amdgpu_crtc *acrtc = NULL;
H
Harry Wentland 已提交
5920
	struct drm_plane *cursor_plane;
5921 5922 5923 5924 5925 5926 5927

	int res = -ENOMEM;

	cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
	if (!cursor_plane)
		goto fail;

H
Harry Wentland 已提交
5928
	cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
5929
	res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
5930 5931 5932 5933 5934 5935 5936 5937 5938

	acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
	if (!acrtc)
		goto fail;

	res = drm_crtc_init_with_planes(
			dm->ddev,
			&acrtc->base,
			plane,
H
Harry Wentland 已提交
5939
			cursor_plane,
5940 5941 5942 5943 5944 5945 5946
			&amdgpu_dm_crtc_funcs, NULL);

	if (res)
		goto fail;

	drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);

5947 5948 5949 5950
	/* Create (reset) the plane state */
	if (acrtc->base.funcs->reset)
		acrtc->base.funcs->reset(&acrtc->base);

5951 5952 5953 5954 5955
	acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
	acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;

	acrtc->crtc_id = crtc_index;
	acrtc->base.enabled = false;
5956
	acrtc->otg_inst = -1;
5957 5958

	dm->adev->mode_info.crtcs[crtc_index] = acrtc;
5959 5960
	drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
				   true, MAX_COLOR_LUT_ENTRIES);
5961
	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
5962 5963 5964 5965

	return 0;

fail:
5966 5967
	kfree(acrtc);
	kfree(cursor_plane);
5968 5969 5970 5971 5972 5973 5974 5975 5976 5977 5978
	return res;
}


static int to_drm_connector_type(enum signal_type st)
{
	switch (st) {
	case SIGNAL_TYPE_HDMI_TYPE_A:
		return DRM_MODE_CONNECTOR_HDMIA;
	case SIGNAL_TYPE_EDP:
		return DRM_MODE_CONNECTOR_eDP;
5979 5980
	case SIGNAL_TYPE_LVDS:
		return DRM_MODE_CONNECTOR_LVDS;
5981 5982 5983 5984 5985 5986 5987 5988 5989 5990 5991 5992 5993 5994 5995 5996
	case SIGNAL_TYPE_RGB:
		return DRM_MODE_CONNECTOR_VGA;
	case SIGNAL_TYPE_DISPLAY_PORT:
	case SIGNAL_TYPE_DISPLAY_PORT_MST:
		return DRM_MODE_CONNECTOR_DisplayPort;
	case SIGNAL_TYPE_DVI_DUAL_LINK:
	case SIGNAL_TYPE_DVI_SINGLE_LINK:
		return DRM_MODE_CONNECTOR_DVID;
	case SIGNAL_TYPE_VIRTUAL:
		return DRM_MODE_CONNECTOR_VIRTUAL;

	default:
		return DRM_MODE_CONNECTOR_Unknown;
	}
}

5997 5998
static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
{
5999 6000 6001 6002 6003 6004 6005
	struct drm_encoder *encoder;

	/* There is only one encoder per connector */
	drm_connector_for_each_possible_encoder(connector, encoder)
		return encoder;

	return NULL;
6006 6007
}

6008 6009 6010 6011 6012
static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
{
	struct drm_encoder *encoder;
	struct amdgpu_encoder *amdgpu_encoder;

6013
	encoder = amdgpu_dm_connector_to_encoder(connector);
6014 6015 6016 6017 6018 6019 6020 6021 6022 6023

	if (encoder == NULL)
		return;

	amdgpu_encoder = to_amdgpu_encoder(encoder);

	amdgpu_encoder->native_mode.clock = 0;

	if (!list_empty(&connector->probed_modes)) {
		struct drm_display_mode *preferred_mode = NULL;
6024

6025
		list_for_each_entry(preferred_mode,
6026 6027 6028 6029 6030
				    &connector->probed_modes,
				    head) {
			if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
				amdgpu_encoder->native_mode = *preferred_mode;

6031 6032 6033 6034 6035 6036
			break;
		}

	}
}

6037 6038 6039 6040
static struct drm_display_mode *
amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
			     char *name,
			     int hdisplay, int vdisplay)
6041 6042 6043 6044 6045 6046 6047 6048
{
	struct drm_device *dev = encoder->dev;
	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
	struct drm_display_mode *mode = NULL;
	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;

	mode = drm_mode_duplicate(dev, native_mode);

6049
	if (mode == NULL)
6050 6051 6052 6053 6054
		return NULL;

	mode->hdisplay = hdisplay;
	mode->vdisplay = vdisplay;
	mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6055
	strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6056 6057 6058 6059 6060 6061

	return mode;

}

static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6062
						 struct drm_connector *connector)
6063 6064 6065 6066
{
	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
	struct drm_display_mode *mode = NULL;
	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6067 6068
	struct amdgpu_dm_connector *amdgpu_dm_connector =
				to_amdgpu_dm_connector(connector);
6069 6070 6071 6072 6073 6074
	int i;
	int n;
	struct mode_size {
		char name[DRM_DISPLAY_MODE_LEN];
		int w;
		int h;
6075
	} common_modes[] = {
6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087 6088
		{  "640x480",  640,  480},
		{  "800x600",  800,  600},
		{ "1024x768", 1024,  768},
		{ "1280x720", 1280,  720},
		{ "1280x800", 1280,  800},
		{"1280x1024", 1280, 1024},
		{ "1440x900", 1440,  900},
		{"1680x1050", 1680, 1050},
		{"1600x1200", 1600, 1200},
		{"1920x1080", 1920, 1080},
		{"1920x1200", 1920, 1200}
	};

6089
	n = ARRAY_SIZE(common_modes);
6090 6091 6092 6093 6094 6095

	for (i = 0; i < n; i++) {
		struct drm_display_mode *curmode = NULL;
		bool mode_existed = false;

		if (common_modes[i].w > native_mode->hdisplay ||
6096 6097 6098 6099
		    common_modes[i].h > native_mode->vdisplay ||
		   (common_modes[i].w == native_mode->hdisplay &&
		    common_modes[i].h == native_mode->vdisplay))
			continue;
6100 6101 6102

		list_for_each_entry(curmode, &connector->probed_modes, head) {
			if (common_modes[i].w == curmode->hdisplay &&
6103
			    common_modes[i].h == curmode->vdisplay) {
6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115
				mode_existed = true;
				break;
			}
		}

		if (mode_existed)
			continue;

		mode = amdgpu_dm_create_common_mode(encoder,
				common_modes[i].name, common_modes[i].w,
				common_modes[i].h);
		drm_mode_probed_add(connector, mode);
6116
		amdgpu_dm_connector->num_modes++;
6117 6118 6119
	}
}

6120 6121
static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
					      struct edid *edid)
6122
{
6123 6124
	struct amdgpu_dm_connector *amdgpu_dm_connector =
			to_amdgpu_dm_connector(connector);
6125 6126 6127 6128

	if (edid) {
		/* empty probed_modes */
		INIT_LIST_HEAD(&connector->probed_modes);
6129
		amdgpu_dm_connector->num_modes =
6130 6131
				drm_add_edid_modes(connector, edid);

6132 6133 6134 6135 6136 6137 6138 6139 6140
		/* sorting the probed modes before calling function
		 * amdgpu_dm_get_native_mode() since EDID can have
		 * more than one preferred mode. The modes that are
		 * later in the probed mode list could be of higher
		 * and preferred resolution. For example, 3840x2160
		 * resolution in base EDID preferred timing and 4096x2160
		 * preferred resolution in DID extension block later.
		 */
		drm_mode_sort(&connector->probed_modes);
6141
		amdgpu_dm_get_native_mode(connector);
6142
	} else {
6143
		amdgpu_dm_connector->num_modes = 0;
6144
	}
6145 6146
}

6147
static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
6148
{
6149 6150
	struct amdgpu_dm_connector *amdgpu_dm_connector =
			to_amdgpu_dm_connector(connector);
6151
	struct drm_encoder *encoder;
6152
	struct edid *edid = amdgpu_dm_connector->edid;
6153

6154
	encoder = amdgpu_dm_connector_to_encoder(connector);
6155

6156
	if (!edid || !drm_edid_is_valid(edid)) {
6157 6158
		amdgpu_dm_connector->num_modes =
				drm_add_modes_noedid(connector, 640, 480);
6159 6160 6161 6162
	} else {
		amdgpu_dm_connector_ddc_get_modes(connector, edid);
		amdgpu_dm_connector_add_common_modes(encoder, connector);
	}
6163
	amdgpu_dm_fbc_init(connector);
6164

6165
	return amdgpu_dm_connector->num_modes;
6166 6167
}

6168 6169 6170 6171 6172
void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
				     struct amdgpu_dm_connector *aconnector,
				     int connector_type,
				     struct dc_link *link,
				     int link_index)
6173 6174 6175
{
	struct amdgpu_device *adev = dm->ddev->dev_private;

6176 6177 6178 6179 6180 6181 6182
	/*
	 * Some of the properties below require access to state, like bpc.
	 * Allocate some default initial connector state with our reset helper.
	 */
	if (aconnector->base.funcs->reset)
		aconnector->base.funcs->reset(&aconnector->base);

6183 6184 6185 6186 6187 6188 6189
	aconnector->connector_id = link_index;
	aconnector->dc_link = link;
	aconnector->base.interlace_allowed = false;
	aconnector->base.doublescan_allowed = false;
	aconnector->base.stereo_allowed = false;
	aconnector->base.dpms = DRM_MODE_DPMS_OFF;
	aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
6190
	aconnector->audio_inst = -1;
6191 6192
	mutex_init(&aconnector->hpd_lock);

6193 6194
	/*
	 * configure support HPD hot plug connector_>polled default value is 0
6195 6196
	 * which means HPD hot plug not supported
	 */
6197 6198 6199
	switch (connector_type) {
	case DRM_MODE_CONNECTOR_HDMIA:
		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6200
		aconnector->base.ycbcr_420_allowed =
6201
			link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
6202 6203 6204
		break;
	case DRM_MODE_CONNECTOR_DisplayPort:
		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6205
		aconnector->base.ycbcr_420_allowed =
6206
			link->link_enc->features.dp_ycbcr420_supported ? true : false;
6207 6208 6209 6210 6211 6212 6213 6214 6215 6216 6217 6218 6219 6220 6221 6222 6223 6224 6225 6226 6227
		break;
	case DRM_MODE_CONNECTOR_DVID:
		aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
		break;
	default:
		break;
	}

	drm_object_attach_property(&aconnector->base.base,
				dm->ddev->mode_config.scaling_mode_property,
				DRM_MODE_SCALE_NONE);

	drm_object_attach_property(&aconnector->base.base,
				adev->mode_info.underscan_property,
				UNDERSCAN_OFF);
	drm_object_attach_property(&aconnector->base.base,
				adev->mode_info.underscan_hborder_property,
				0);
	drm_object_attach_property(&aconnector->base.base,
				adev->mode_info.underscan_vborder_property,
				0);
6228

6229 6230
	if (!aconnector->mst_port)
		drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
6231

6232 6233 6234
	/* This defaults to the max in the range, but we want 8bpc for non-edp. */
	aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
	aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
6235

6236 6237 6238 6239 6240
	if (connector_type == DRM_MODE_CONNECTOR_eDP &&
	    dc_is_dmcu_initialized(adev->dm.dc)) {
		drm_object_attach_property(&aconnector->base.base,
				adev->mode_info.abm_level_property, 0);
	}
6241 6242

	if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
6243 6244
	    connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
	    connector_type == DRM_MODE_CONNECTOR_eDP) {
6245 6246 6247 6248
		drm_object_attach_property(
			&aconnector->base.base,
			dm->ddev->mode_config.hdr_output_metadata_property, 0);

6249 6250 6251
		if (!aconnector->mst_port)
			drm_connector_attach_vrr_capable_property(&aconnector->base);

6252
#ifdef CONFIG_DRM_AMD_DC_HDCP
6253
		if (adev->dm.hdcp_workqueue)
6254
			drm_connector_attach_content_protection_property(&aconnector->base, true);
6255
#endif
6256
	}
6257 6258
}

6259 6260
static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
			      struct i2c_msg *msgs, int num)
6261 6262 6263 6264 6265 6266 6267
{
	struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
	struct ddc_service *ddc_service = i2c->ddc_service;
	struct i2c_command cmd;
	int i;
	int result = -EIO;

6268
	cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
6269 6270 6271 6272 6273 6274 6275 6276 6277 6278 6279 6280 6281 6282 6283

	if (!cmd.payloads)
		return result;

	cmd.number_of_payloads = num;
	cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
	cmd.speed = 100;

	for (i = 0; i < num; i++) {
		cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
		cmd.payloads[i].address = msgs[i].addr;
		cmd.payloads[i].length = msgs[i].len;
		cmd.payloads[i].data = msgs[i].buf;
	}

6284 6285 6286
	if (dc_submit_i2c(
			ddc_service->ctx->dc,
			ddc_service->ddc_pin->hw_info.ddc_channel,
6287 6288 6289 6290 6291 6292 6293
			&cmd))
		result = num;

	kfree(cmd.payloads);
	return result;
}

6294
static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
6295 6296 6297 6298 6299 6300 6301 6302 6303
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
	.master_xfer = amdgpu_dm_i2c_xfer,
	.functionality = amdgpu_dm_i2c_func,
};

6304 6305 6306 6307
static struct amdgpu_i2c_adapter *
create_i2c(struct ddc_service *ddc_service,
	   int link_index,
	   int *res)
6308 6309 6310 6311
{
	struct amdgpu_device *adev = ddc_service->ctx->driver_context;
	struct amdgpu_i2c_adapter *i2c;

6312
	i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
6313 6314
	if (!i2c)
		return NULL;
6315 6316 6317 6318
	i2c->base.owner = THIS_MODULE;
	i2c->base.class = I2C_CLASS_DDC;
	i2c->base.dev.parent = &adev->pdev->dev;
	i2c->base.algo = &amdgpu_dm_i2c_algo;
6319
	snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
6320 6321
	i2c_set_adapdata(&i2c->base, i2c);
	i2c->ddc_service = ddc_service;
6322
	i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
6323 6324 6325 6326

	return i2c;
}

6327

6328 6329
/*
 * Note: this function assumes that dc_link_detect() was called for the
6330 6331
 * dc_link which will be represented by this aconnector.
 */
6332 6333 6334 6335
static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
				    struct amdgpu_dm_connector *aconnector,
				    uint32_t link_index,
				    struct amdgpu_encoder *aencoder)
6336 6337 6338 6339 6340 6341
{
	int res = 0;
	int connector_type;
	struct dc *dc = dm->dc;
	struct dc_link *link = dc_get_link_at_index(dc, link_index);
	struct amdgpu_i2c_adapter *i2c;
6342 6343

	link->priv = aconnector;
6344

6345
	DRM_DEBUG_DRIVER("%s()\n", __func__);
6346 6347

	i2c = create_i2c(link->ddc, link->link_index, &res);
6348 6349 6350 6351 6352
	if (!i2c) {
		DRM_ERROR("Failed to create i2c adapter data\n");
		return -ENOMEM;
	}

6353 6354 6355 6356 6357 6358 6359 6360 6361 6362
	aconnector->i2c = i2c;
	res = i2c_add_adapter(&i2c->base);

	if (res) {
		DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
		goto out_free;
	}

	connector_type = to_drm_connector_type(link->connector_signal);

6363
	res = drm_connector_init_with_ddc(
6364 6365 6366
			dm->ddev,
			&aconnector->base,
			&amdgpu_dm_connector_funcs,
6367 6368
			connector_type,
			&i2c->base);
6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382 6383 6384 6385 6386

	if (res) {
		DRM_ERROR("connector_init failed\n");
		aconnector->connector_id = -1;
		goto out_free;
	}

	drm_connector_helper_add(
			&aconnector->base,
			&amdgpu_dm_connector_helper_funcs);

	amdgpu_dm_connector_init_helper(
		dm,
		aconnector,
		connector_type,
		link,
		link_index);

6387
	drm_connector_attach_encoder(
6388 6389 6390 6391
		&aconnector->base, &aencoder->base);

	if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
		|| connector_type == DRM_MODE_CONNECTOR_eDP)
6392
		amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406 6407 6408 6409 6410 6411 6412 6413 6414 6415 6416 6417 6418 6419 6420

out_free:
	if (res) {
		kfree(i2c);
		aconnector->i2c = NULL;
	}
	return res;
}

int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
{
	switch (adev->mode_info.num_crtc) {
	case 1:
		return 0x1;
	case 2:
		return 0x3;
	case 3:
		return 0x7;
	case 4:
		return 0xf;
	case 5:
		return 0x1f;
	case 6:
	default:
		return 0x3f;
	}
}

6421 6422 6423
static int amdgpu_dm_encoder_init(struct drm_device *dev,
				  struct amdgpu_encoder *aencoder,
				  uint32_t link_index)
6424 6425 6426 6427 6428 6429 6430 6431 6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444
{
	struct amdgpu_device *adev = dev->dev_private;

	int res = drm_encoder_init(dev,
				   &aencoder->base,
				   &amdgpu_dm_encoder_funcs,
				   DRM_MODE_ENCODER_TMDS,
				   NULL);

	aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);

	if (!res)
		aencoder->encoder_id = link_index;
	else
		aencoder->encoder_id = -1;

	drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);

	return res;
}

6445 6446 6447
static void manage_dm_interrupts(struct amdgpu_device *adev,
				 struct amdgpu_crtc *acrtc,
				 bool enable)
6448 6449 6450 6451 6452 6453
{
	/*
	 * this is not correct translation but will work as soon as VBLANK
	 * constant is the same as PFLIP
	 */
	int irq_type =
6454
		amdgpu_display_crtc_idx_to_irq_type(
6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465 6466 6467 6468 6469 6470 6471 6472 6473
			adev,
			acrtc->crtc_id);

	if (enable) {
		drm_crtc_vblank_on(&acrtc->base);
		amdgpu_irq_get(
			adev,
			&adev->pageflip_irq,
			irq_type);
	} else {

		amdgpu_irq_put(
			adev,
			&adev->pageflip_irq,
			irq_type);
		drm_crtc_vblank_off(&acrtc->base);
	}
}

6474 6475 6476
static bool
is_scaling_state_different(const struct dm_connector_state *dm_state,
			   const struct dm_connector_state *old_dm_state)
6477 6478 6479 6480 6481 6482 6483 6484 6485
{
	if (dm_state->scaling != old_dm_state->scaling)
		return true;
	if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
		if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
			return true;
	} else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
		if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
			return true;
6486 6487 6488
	} else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
		   dm_state->underscan_vborder != old_dm_state->underscan_vborder)
		return true;
6489 6490 6491
	return false;
}

6492 6493 6494 6495 6496 6497 6498
#ifdef CONFIG_DRM_AMD_DC_HDCP
static bool is_content_protection_different(struct drm_connector_state *state,
					    const struct drm_connector_state *old_state,
					    const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
{
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);

6499 6500 6501 6502 6503 6504
	if (old_state->hdcp_content_type != state->hdcp_content_type &&
	    state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
		state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
		return true;
	}

6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524 6525 6526 6527 6528 6529 6530 6531 6532 6533
	/* CP is being re enabled, ignore this */
	if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
	    state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
		state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
		return false;
	}

	/* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */
	if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
	    state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
		state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;

	/* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
	 * hot-plug, headless s3, dpms
	 */
	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED && connector->dpms == DRM_MODE_DPMS_ON &&
	    aconnector->dc_sink != NULL)
		return true;

	if (old_state->content_protection == state->content_protection)
		return false;

	if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
		return true;

	return false;
}

#endif
6534 6535 6536
static void remove_stream(struct amdgpu_device *adev,
			  struct amdgpu_crtc *acrtc,
			  struct dc_stream_state *stream)
6537 6538 6539 6540 6541 6542 6543
{
	/* this is the update mode case */

	acrtc->otg_inst = -1;
	acrtc->enabled = false;
}

6544 6545
static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
			       struct dc_cursor_position *position)
6546
{
6547
	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
6548 6549 6550
	int x, y;
	int xorigin = 0, yorigin = 0;

6551 6552 6553 6554 6555
	position->enable = false;
	position->x = 0;
	position->y = 0;

	if (!crtc || !plane->state->fb)
6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567 6568
		return 0;

	if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
	    (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
		DRM_ERROR("%s: bad cursor width or height %d x %d\n",
			  __func__,
			  plane->state->crtc_w,
			  plane->state->crtc_h);
		return -EINVAL;
	}

	x = plane->state->crtc_x;
	y = plane->state->crtc_y;
6569

6570 6571 6572 6573
	if (x <= -amdgpu_crtc->max_cursor_width ||
	    y <= -amdgpu_crtc->max_cursor_height)
		return 0;

6574 6575 6576 6577 6578 6579 6580 6581 6582
	if (x < 0) {
		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
		x = 0;
	}
	if (y < 0) {
		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
		y = 0;
	}
	position->enable = true;
6583
	position->translate_by_source = true;
6584 6585 6586 6587 6588 6589 6590 6591
	position->x = x;
	position->y = y;
	position->x_hotspot = xorigin;
	position->y_hotspot = yorigin;

	return 0;
}

6592 6593
static void handle_cursor_update(struct drm_plane *plane,
				 struct drm_plane_state *old_plane_state)
6594
{
6595
	struct amdgpu_device *adev = plane->dev->dev_private;
6596 6597 6598 6599 6600 6601 6602 6603 6604
	struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
	struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
	struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
	uint64_t address = afb ? afb->address : 0;
	struct dc_cursor_position position;
	struct dc_cursor_attributes attributes;
	int ret;

6605 6606 6607
	if (!plane->state->fb && !old_plane_state->fb)
		return;

6608
	DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
6609 6610 6611 6612
			 __func__,
			 amdgpu_crtc->crtc_id,
			 plane->state->crtc_w,
			 plane->state->crtc_h);
6613 6614 6615 6616 6617 6618 6619

	ret = get_cursor_position(plane, crtc, &position);
	if (ret)
		return;

	if (!position.enable) {
		/* turn off cursor */
6620 6621
		if (crtc_state && crtc_state->stream) {
			mutex_lock(&adev->dm.dc_lock);
6622 6623
			dc_stream_set_cursor_position(crtc_state->stream,
						      &position);
6624 6625
			mutex_unlock(&adev->dm.dc_lock);
		}
6626
		return;
6627 6628
	}

6629 6630 6631
	amdgpu_crtc->cursor_width = plane->state->crtc_w;
	amdgpu_crtc->cursor_height = plane->state->crtc_h;

6632
	memset(&attributes, 0, sizeof(attributes));
6633 6634 6635 6636 6637 6638 6639 6640 6641 6642
	attributes.address.high_part = upper_32_bits(address);
	attributes.address.low_part  = lower_32_bits(address);
	attributes.width             = plane->state->crtc_w;
	attributes.height            = plane->state->crtc_h;
	attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
	attributes.rotation_angle    = 0;
	attributes.attribute_flags.value = 0;

	attributes.pitch = attributes.width;

6643
	if (crtc_state->stream) {
6644
		mutex_lock(&adev->dm.dc_lock);
6645 6646 6647
		if (!dc_stream_set_cursor_attributes(crtc_state->stream,
							 &attributes))
			DRM_ERROR("DC failed to set cursor attributes\n");
6648 6649 6650 6651

		if (!dc_stream_set_cursor_position(crtc_state->stream,
						   &position))
			DRM_ERROR("DC failed to set cursor position\n");
6652
		mutex_unlock(&adev->dm.dc_lock);
6653
	}
6654
}
6655 6656 6657 6658 6659 6660 6661 6662 6663 6664 6665 6666 6667 6668 6669 6670 6671 6672 6673

static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
{

	assert_spin_locked(&acrtc->base.dev->event_lock);
	WARN_ON(acrtc->event);

	acrtc->event = acrtc->base.state->event;

	/* Set the flip status */
	acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;

	/* Mark this event as consumed */
	acrtc->base.state->event = NULL;

	DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
						 acrtc->crtc_id);
}

6674 6675 6676
static void update_freesync_state_on_stream(
	struct amdgpu_display_manager *dm,
	struct dm_crtc_state *new_crtc_state,
6677 6678 6679
	struct dc_stream_state *new_stream,
	struct dc_plane_state *surface,
	u32 flip_timestamp_in_us)
6680
{
6681
	struct mod_vrr_params vrr_params;
6682
	struct dc_info_packet vrr_infopacket = {0};
6683 6684
	struct amdgpu_device *adev = dm->adev;
	unsigned long flags;
6685 6686 6687 6688 6689 6690 6691 6692 6693 6694 6695 6696

	if (!new_stream)
		return;

	/*
	 * TODO: Determine why min/max totals and vrefresh can be 0 here.
	 * For now it's sufficient to just guard against these conditions.
	 */

	if (!new_stream->timing.h_total || !new_stream->timing.v_total)
		return;

6697 6698 6699
	spin_lock_irqsave(&adev->ddev->event_lock, flags);
	vrr_params = new_crtc_state->vrr_params;

6700 6701 6702 6703 6704 6705 6706
	if (surface) {
		mod_freesync_handle_preflip(
			dm->freesync_module,
			surface,
			new_stream,
			flip_timestamp_in_us,
			&vrr_params);
6707 6708 6709 6710 6711

		if (adev->family < AMDGPU_FAMILY_AI &&
		    amdgpu_dm_vrr_active(new_crtc_state)) {
			mod_freesync_handle_v_update(dm->freesync_module,
						     new_stream, &vrr_params);
6712 6713 6714 6715 6716

			/* Need to call this before the frame ends. */
			dc_stream_adjust_vmin_vmax(dm->dc,
						   new_crtc_state->stream,
						   &vrr_params.adjust);
6717
		}
6718
	}
6719 6720 6721 6722

	mod_freesync_build_vrr_infopacket(
		dm->freesync_module,
		new_stream,
6723
		&vrr_params,
6724 6725
		PACKET_TYPE_VRR,
		TRANSFER_FUNC_UNKNOWN,
6726 6727
		&vrr_infopacket);

6728
	new_crtc_state->freesync_timing_changed |=
6729 6730 6731
		(memcmp(&new_crtc_state->vrr_params.adjust,
			&vrr_params.adjust,
			sizeof(vrr_params.adjust)) != 0);
6732

6733
	new_crtc_state->freesync_vrr_info_changed |=
6734 6735 6736 6737
		(memcmp(&new_crtc_state->vrr_infopacket,
			&vrr_infopacket,
			sizeof(vrr_infopacket)) != 0);

6738
	new_crtc_state->vrr_params = vrr_params;
6739 6740
	new_crtc_state->vrr_infopacket = vrr_infopacket;

6741
	new_stream->adjust = new_crtc_state->vrr_params.adjust;
6742 6743 6744 6745 6746 6747
	new_stream->vrr_infopacket = vrr_infopacket;

	if (new_crtc_state->freesync_vrr_info_changed)
		DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
			      new_crtc_state->base.crtc->base.id,
			      (int)new_crtc_state->base.vrr_enabled,
6748
			      (int)vrr_params.state);
6749 6750

	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6751 6752
}

6753 6754 6755 6756 6757
static void pre_update_freesync_state_on_stream(
	struct amdgpu_display_manager *dm,
	struct dm_crtc_state *new_crtc_state)
{
	struct dc_stream_state *new_stream = new_crtc_state->stream;
6758
	struct mod_vrr_params vrr_params;
6759
	struct mod_freesync_config config = new_crtc_state->freesync_config;
6760 6761
	struct amdgpu_device *adev = dm->adev;
	unsigned long flags;
6762 6763 6764 6765 6766 6767 6768 6769 6770 6771 6772

	if (!new_stream)
		return;

	/*
	 * TODO: Determine why min/max totals and vrefresh can be 0 here.
	 * For now it's sufficient to just guard against these conditions.
	 */
	if (!new_stream->timing.h_total || !new_stream->timing.v_total)
		return;

6773 6774 6775
	spin_lock_irqsave(&adev->ddev->event_lock, flags);
	vrr_params = new_crtc_state->vrr_params;

6776 6777 6778 6779 6780 6781 6782 6783 6784 6785 6786 6787 6788 6789 6790 6791 6792 6793 6794 6795
	if (new_crtc_state->vrr_supported &&
	    config.min_refresh_in_uhz &&
	    config.max_refresh_in_uhz) {
		config.state = new_crtc_state->base.vrr_enabled ?
			VRR_STATE_ACTIVE_VARIABLE :
			VRR_STATE_INACTIVE;
	} else {
		config.state = VRR_STATE_UNSUPPORTED;
	}

	mod_freesync_build_vrr_params(dm->freesync_module,
				      new_stream,
				      &config, &vrr_params);

	new_crtc_state->freesync_timing_changed |=
		(memcmp(&new_crtc_state->vrr_params.adjust,
			&vrr_params.adjust,
			sizeof(vrr_params.adjust)) != 0);

	new_crtc_state->vrr_params = vrr_params;
6796
	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
6797 6798
}

6799 6800 6801 6802 6803 6804 6805 6806 6807 6808 6809
static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
					    struct dm_crtc_state *new_state)
{
	bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
	bool new_vrr_active = amdgpu_dm_vrr_active(new_state);

	if (!old_vrr_active && new_vrr_active) {
		/* Transition VRR inactive -> active:
		 * While VRR is active, we must not disable vblank irq, as a
		 * reenable after disable would compute bogus vblank/pflip
		 * timestamps if it likely happened inside display front-porch.
6810 6811 6812
		 *
		 * We also need vupdate irq for the actual core vblank handling
		 * at end of vblank.
6813
		 */
6814
		dm_set_vupdate_irq(new_state->base.crtc, true);
6815 6816 6817 6818 6819 6820 6821
		drm_crtc_vblank_get(new_state->base.crtc);
		DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
				 __func__, new_state->base.crtc->base.id);
	} else if (old_vrr_active && !new_vrr_active) {
		/* Transition VRR active -> inactive:
		 * Allow vblank irq disable again for fixed refresh rate.
		 */
6822
		dm_set_vupdate_irq(new_state->base.crtc, false);
6823 6824 6825 6826 6827 6828
		drm_crtc_vblank_put(new_state->base.crtc);
		DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
				 __func__, new_state->base.crtc->base.id);
	}
}

6829 6830 6831 6832 6833 6834 6835 6836 6837 6838 6839 6840 6841 6842 6843 6844
static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
{
	struct drm_plane *plane;
	struct drm_plane_state *old_plane_state, *new_plane_state;
	int i;

	/*
	 * TODO: Make this per-stream so we don't issue redundant updates for
	 * commits with multiple streams.
	 */
	for_each_oldnew_plane_in_state(state, plane, old_plane_state,
				       new_plane_state, i)
		if (plane->type == DRM_PLANE_TYPE_CURSOR)
			handle_cursor_update(plane, old_plane_state);
}

6845
static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
6846
				    struct dc_state *dc_state,
6847 6848 6849
				    struct drm_device *dev,
				    struct amdgpu_display_manager *dm,
				    struct drm_crtc *pcrtc,
6850
				    bool wait_for_vblank)
6851
{
6852
	uint32_t i;
6853
	uint64_t timestamp_ns;
6854
	struct drm_plane *plane;
6855
	struct drm_plane_state *old_plane_state, *new_plane_state;
6856
	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
6857 6858 6859
	struct drm_crtc_state *new_pcrtc_state =
			drm_atomic_get_new_crtc_state(state, pcrtc);
	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
6860 6861
	struct dm_crtc_state *dm_old_crtc_state =
			to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
6862
	int planes_count = 0, vpos, hpos;
6863
	long r;
6864
	unsigned long flags;
6865
	struct amdgpu_bo *abo;
6866
	uint64_t tiling_flags;
6867
	bool tmz_surface = false;
6868 6869
	uint32_t target_vblank, last_flip_vblank;
	bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
6870
	bool pflip_present = false;
6871 6872 6873 6874
	struct {
		struct dc_surface_update surface_updates[MAX_SURFACES];
		struct dc_plane_info plane_infos[MAX_SURFACES];
		struct dc_scaling_info scaling_infos[MAX_SURFACES];
6875
		struct dc_flip_addrs flip_addrs[MAX_SURFACES];
6876
		struct dc_stream_update stream_update;
6877
	} *bundle;
6878

6879
	bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
6880

6881 6882
	if (!bundle) {
		dm_error("Failed to allocate update bundle\n");
6883 6884
		goto cleanup;
	}
6885

6886 6887 6888 6889 6890 6891 6892 6893
	/*
	 * Disable the cursor first if we're disabling all the planes.
	 * It'll remain on the screen after the planes are re-enabled
	 * if we don't.
	 */
	if (acrtc_state->active_planes == 0)
		amdgpu_dm_commit_cursors(state);

6894
	/* update planes when needed */
6895 6896
	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
		struct drm_crtc *crtc = new_plane_state->crtc;
6897
		struct drm_crtc_state *new_crtc_state;
6898
		struct drm_framebuffer *fb = new_plane_state->fb;
6899
		bool plane_needs_flip;
6900
		struct dc_plane_state *dc_plane;
6901
		struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
6902

6903 6904
		/* Cursor plane is handled after stream updates */
		if (plane->type == DRM_PLANE_TYPE_CURSOR)
6905 6906
			continue;

6907 6908 6909 6910 6911
		if (!fb || !crtc || pcrtc != crtc)
			continue;

		new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
		if (!new_crtc_state->active)
6912 6913
			continue;

6914
		dc_plane = dm_new_plane_state->dc_state;
6915

6916
		bundle->surface_updates[planes_count].surface = dc_plane;
6917
		if (new_pcrtc_state->color_mgmt_changed) {
6918 6919
			bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
			bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
6920
			bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
6921
		}
6922

6923 6924
		fill_dc_scaling_info(new_plane_state,
				     &bundle->scaling_infos[planes_count]);
6925

6926 6927
		bundle->surface_updates[planes_count].scaling_info =
			&bundle->scaling_infos[planes_count];
6928

6929
		plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
6930

6931
		pflip_present = pflip_present || plane_needs_flip;
6932

6933 6934 6935 6936
		if (!plane_needs_flip) {
			planes_count += 1;
			continue;
		}
6937

6938 6939
		abo = gem_to_amdgpu_bo(fb->obj[0]);

6940 6941 6942 6943 6944
		/*
		 * Wait for all fences on this FB. Do limited wait to avoid
		 * deadlock during GPU reset when this fence will not signal
		 * but we hold reservation lock for the BO.
		 */
6945
		r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true,
6946
							false,
6947 6948
							msecs_to_jiffies(5000));
		if (unlikely(r <= 0))
6949
			DRM_ERROR("Waiting for fences timed out!");
6950

6951 6952 6953 6954 6955 6956 6957
		/*
		 * TODO This might fail and hence better not used, wait
		 * explicitly on fences instead
		 * and in general should be called for
		 * blocking commit to as per framework helpers
		 */
		r = amdgpu_bo_reserve(abo, true);
6958
		if (unlikely(r != 0))
6959
			DRM_ERROR("failed to reserve buffer before flip\n");
6960

6961
		amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
6962

6963 6964
		tmz_surface = amdgpu_bo_encrypted(abo);

6965
		amdgpu_bo_unreserve(abo);
6966

6967 6968 6969
		fill_dc_plane_info_and_addr(
			dm->adev, new_plane_state, tiling_flags,
			&bundle->plane_infos[planes_count],
6970
			&bundle->flip_addrs[planes_count].address,
6971
			tmz_surface,
6972 6973 6974 6975 6976
			false);

		DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",
				 new_plane_state->plane->index,
				 bundle->plane_infos[planes_count].dcc.enable);
6977 6978 6979

		bundle->surface_updates[planes_count].plane_info =
			&bundle->plane_infos[planes_count];
6980

6981 6982 6983 6984
		/*
		 * Only allow immediate flips for fast updates that don't
		 * change FB pitch, DCC state, rotation or mirroing.
		 */
6985
		bundle->flip_addrs[planes_count].flip_immediate =
6986
			crtc->state->async_flip &&
6987
			acrtc_state->update_type == UPDATE_TYPE_FAST;
6988

6989 6990 6991 6992
		timestamp_ns = ktime_get_ns();
		bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
		bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
		bundle->surface_updates[planes_count].surface = dc_plane;
6993

6994 6995 6996 6997
		if (!bundle->surface_updates[planes_count].surface) {
			DRM_ERROR("No surface for CRTC: id=%d\n",
					acrtc_attach->crtc_id);
			continue;
6998 6999
		}

7000 7001 7002 7003 7004 7005 7006
		if (plane == pcrtc->primary)
			update_freesync_state_on_stream(
				dm,
				acrtc_state,
				acrtc_state->stream,
				dc_plane,
				bundle->flip_addrs[planes_count].flip_timestamp_in_us);
7007

7008 7009 7010 7011
		DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
				 __func__,
				 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
				 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
7012 7013 7014

		planes_count += 1;

7015 7016
	}

7017
	if (pflip_present) {
7018 7019 7020 7021 7022 7023 7024
		if (!vrr_active) {
			/* Use old throttling in non-vrr fixed refresh rate mode
			 * to keep flip scheduling based on target vblank counts
			 * working in a backwards compatible way, e.g., for
			 * clients using the GLX_OML_sync_control extension or
			 * DRI3/Present extension with defined target_msc.
			 */
7025
			last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
7026 7027 7028 7029 7030 7031 7032 7033 7034 7035 7036 7037 7038 7039 7040
		}
		else {
			/* For variable refresh rate mode only:
			 * Get vblank of last completed flip to avoid > 1 vrr
			 * flips per video frame by use of throttling, but allow
			 * flip programming anywhere in the possibly large
			 * variable vrr vblank interval for fine-grained flip
			 * timing control and more opportunity to avoid stutter
			 * on late submission of flips.
			 */
			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
			last_flip_vblank = acrtc_attach->last_flip_vblank;
			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
		}

7041
		target_vblank = last_flip_vblank + wait_for_vblank;
7042 7043 7044 7045 7046 7047 7048 7049 7050 7051 7052 7053

		/*
		 * Wait until we're out of the vertical blank period before the one
		 * targeted by the flip
		 */
		while ((acrtc_attach->enabled &&
			(amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
							    0, &vpos, &hpos, NULL,
							    NULL, &pcrtc->hwmode)
			 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
			(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
			(int)(target_vblank -
7054
			  amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
7055 7056 7057 7058 7059 7060 7061 7062 7063 7064 7065 7066 7067 7068 7069 7070
			usleep_range(1000, 1100);
		}

		if (acrtc_attach->base.state->event) {
			drm_crtc_vblank_get(pcrtc);

			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);

			WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
			prepare_flip_isr(acrtc_attach);

			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
		}

		if (acrtc_state->stream) {
			if (acrtc_state->freesync_vrr_info_changed)
7071
				bundle->stream_update.vrr_infopacket =
7072
					&acrtc_state->stream->vrr_infopacket;
7073 7074 7075
		}
	}

7076
	/* Update the planes if changed or disable if we don't have any. */
7077 7078
	if ((planes_count || acrtc_state->active_planes == 0) &&
		acrtc_state->stream) {
7079
		bundle->stream_update.stream = acrtc_state->stream;
7080
		if (new_pcrtc_state->mode_changed) {
7081 7082
			bundle->stream_update.src = acrtc_state->stream->src;
			bundle->stream_update.dst = acrtc_state->stream->dst;
7083 7084
		}

7085 7086 7087 7088 7089 7090 7091 7092 7093 7094 7095 7096
		if (new_pcrtc_state->color_mgmt_changed) {
			/*
			 * TODO: This isn't fully correct since we've actually
			 * already modified the stream in place.
			 */
			bundle->stream_update.gamut_remap =
				&acrtc_state->stream->gamut_remap_matrix;
			bundle->stream_update.output_csc_transform =
				&acrtc_state->stream->csc_color_matrix;
			bundle->stream_update.out_transfer_func =
				acrtc_state->stream->out_transfer_func;
		}
7097

7098
		acrtc_state->stream->abm_level = acrtc_state->abm_level;
7099
		if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
7100
			bundle->stream_update.abm_level = &acrtc_state->abm_level;
7101

7102 7103 7104 7105 7106 7107 7108 7109 7110 7111 7112 7113 7114
		/*
		 * If FreeSync state on the stream has changed then we need to
		 * re-adjust the min/max bounds now that DC doesn't handle this
		 * as part of commit.
		 */
		if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
		    amdgpu_dm_vrr_active(acrtc_state)) {
			spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
			dc_stream_adjust_vmin_vmax(
				dm->dc, acrtc_state->stream,
				&acrtc_state->vrr_params.adjust);
			spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
		}
7115
		mutex_lock(&dm->dc_lock);
R
Roman Li 已提交
7116
		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7117
				acrtc_state->stream->link->psr_settings.psr_allow_active)
R
Roman Li 已提交
7118 7119
			amdgpu_dm_psr_disable(acrtc_state->stream);

7120
		dc_commit_updates_for_stream(dm->dc,
7121
						     bundle->surface_updates,
7122 7123
						     planes_count,
						     acrtc_state->stream,
7124
						     &bundle->stream_update,
7125
						     dc_state);
R
Roman Li 已提交
7126 7127

		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7128
				acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
7129
				!acrtc_state->stream->link->psr_settings.psr_feature_enabled)
R
Roman Li 已提交
7130 7131
			amdgpu_dm_link_setup_psr(acrtc_state->stream);
		else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
7132 7133
				acrtc_state->stream->link->psr_settings.psr_feature_enabled &&
				!acrtc_state->stream->link->psr_settings.psr_allow_active) {
R
Roman Li 已提交
7134 7135 7136
			amdgpu_dm_psr_enable(acrtc_state->stream);
		}

7137
		mutex_unlock(&dm->dc_lock);
7138
	}
7139

7140 7141 7142 7143 7144 7145 7146
	/*
	 * Update cursor state *after* programming all the planes.
	 * This avoids redundant programming in the case where we're going
	 * to be disabling a single plane - those pipes are being disabled.
	 */
	if (acrtc_state->active_planes)
		amdgpu_dm_commit_cursors(state);
7147

7148
cleanup:
7149
	kfree(bundle);
7150 7151
}

7152 7153 7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170 7171 7172 7173 7174 7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187 7188 7189 7190 7191 7192 7193 7194 7195 7196 7197 7198 7199 7200 7201 7202 7203 7204 7205 7206 7207 7208 7209 7210 7211 7212 7213 7214 7215 7216 7217 7218 7219 7220 7221 7222 7223 7224 7225 7226
static void amdgpu_dm_commit_audio(struct drm_device *dev,
				   struct drm_atomic_state *state)
{
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_dm_connector *aconnector;
	struct drm_connector *connector;
	struct drm_connector_state *old_con_state, *new_con_state;
	struct drm_crtc_state *new_crtc_state;
	struct dm_crtc_state *new_dm_crtc_state;
	const struct dc_stream_status *status;
	int i, inst;

	/* Notify device removals. */
	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
		if (old_con_state->crtc != new_con_state->crtc) {
			/* CRTC changes require notification. */
			goto notify;
		}

		if (!new_con_state->crtc)
			continue;

		new_crtc_state = drm_atomic_get_new_crtc_state(
			state, new_con_state->crtc);

		if (!new_crtc_state)
			continue;

		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
			continue;

	notify:
		aconnector = to_amdgpu_dm_connector(connector);

		mutex_lock(&adev->dm.audio_lock);
		inst = aconnector->audio_inst;
		aconnector->audio_inst = -1;
		mutex_unlock(&adev->dm.audio_lock);

		amdgpu_dm_audio_eld_notify(adev, inst);
	}

	/* Notify audio device additions. */
	for_each_new_connector_in_state(state, connector, new_con_state, i) {
		if (!new_con_state->crtc)
			continue;

		new_crtc_state = drm_atomic_get_new_crtc_state(
			state, new_con_state->crtc);

		if (!new_crtc_state)
			continue;

		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
			continue;

		new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
		if (!new_dm_crtc_state->stream)
			continue;

		status = dc_stream_get_status(new_dm_crtc_state->stream);
		if (!status)
			continue;

		aconnector = to_amdgpu_dm_connector(connector);

		mutex_lock(&adev->dm.audio_lock);
		inst = status->audio_inst;
		aconnector->audio_inst = inst;
		mutex_unlock(&adev->dm.audio_lock);

		amdgpu_dm_audio_eld_notify(adev, inst);
	}
}

7227 7228 7229 7230 7231 7232 7233 7234 7235 7236 7237 7238 7239 7240 7241 7242 7243 7244 7245 7246
/*
 * Enable interrupts on CRTCs that are newly active, undergone
 * a modeset, or have active planes again.
 *
 * Done in two passes, based on the for_modeset flag:
 * Pass 1: For CRTCs going through modeset
 * Pass 2: For CRTCs going from 0 to n active planes
 *
 * Interrupts can only be enabled after the planes are programmed,
 * so this requires a two-pass approach since we don't want to
 * just defer the interrupts until after commit planes every time.
 */
static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
					     struct drm_atomic_state *state,
					     bool for_modeset)
{
	struct amdgpu_device *adev = dev->dev_private;
	struct drm_crtc *crtc;
	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
	int i;
7247
#ifdef CONFIG_DEBUG_FS
7248
	enum amdgpu_dm_pipe_crc_source source;
7249
#endif
7250 7251 7252 7253 7254 7255 7256 7257 7258 7259 7260 7261 7262 7263 7264 7265 7266 7267 7268 7269 7270 7271 7272 7273 7274

	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
				      new_crtc_state, i) {
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
		struct dm_crtc_state *dm_new_crtc_state =
			to_dm_crtc_state(new_crtc_state);
		struct dm_crtc_state *dm_old_crtc_state =
			to_dm_crtc_state(old_crtc_state);
		bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
		bool run_pass;

		run_pass = (for_modeset && modeset) ||
			   (!for_modeset && !modeset &&
			    !dm_old_crtc_state->interrupts_enabled);

		if (!run_pass)
			continue;

		if (!dm_new_crtc_state->interrupts_enabled)
			continue;

		manage_dm_interrupts(adev, acrtc, true);

#ifdef CONFIG_DEBUG_FS
		/* The stream has changed so CRC capture needs to re-enabled. */
7275 7276
		source = dm_new_crtc_state->crc_src;
		if (amdgpu_dm_is_valid_crc_source(source)) {
7277 7278 7279
			amdgpu_dm_crtc_configure_crc_source(
				crtc, dm_new_crtc_state,
				dm_new_crtc_state->crc_src);
7280 7281 7282 7283 7284
		}
#endif
	}
}

7285
/*
7286 7287 7288 7289 7290 7291 7292 7293 7294 7295
 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
 * @crtc_state: the DRM CRTC state
 * @stream_state: the DC stream state.
 *
 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
 */
static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
						struct dc_stream_state *stream_state)
{
7296
	stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
7297
}
7298

7299 7300 7301
static int amdgpu_dm_atomic_commit(struct drm_device *dev,
				   struct drm_atomic_state *state,
				   bool nonblock)
7302 7303
{
	struct drm_crtc *crtc;
7304
	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7305 7306 7307 7308
	struct amdgpu_device *adev = dev->dev_private;
	int i;

	/*
7309 7310 7311 7312 7313 7314 7315 7316 7317 7318 7319 7320 7321
	 * We evade vblank and pflip interrupts on CRTCs that are undergoing
	 * a modeset, being disabled, or have no active planes.
	 *
	 * It's done in atomic commit rather than commit tail for now since
	 * some of these interrupt handlers access the current CRTC state and
	 * potentially the stream pointer itself.
	 *
	 * Since the atomic state is swapped within atomic commit and not within
	 * commit tail this would leave to new state (that hasn't been committed yet)
	 * being accesssed from within the handlers.
	 *
	 * TODO: Fix this so we can do this in commit tail and not have to block
	 * in atomic check.
7322
	 */
7323
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7324
		struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7325
		struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7326 7327
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

7328 7329
		if (dm_old_crtc_state->interrupts_enabled &&
		    (!dm_new_crtc_state->interrupts_enabled ||
7330
		     drm_atomic_crtc_needs_modeset(new_crtc_state)))
7331 7332
			manage_dm_interrupts(adev, acrtc, false);
	}
7333 7334 7335 7336
	/*
	 * Add check here for SoC's that support hardware cursor plane, to
	 * unset legacy_cursor_update
	 */
7337 7338 7339 7340 7341 7342

	return drm_atomic_helper_commit(dev, state, nonblock);

	/*TODO Handle EINTR, reenable IRQ*/
}

7343 7344 7345 7346 7347 7348 7349 7350
/**
 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
 * @state: The atomic state to commit
 *
 * This will tell DC to commit the constructed DC state from atomic_check,
 * programming the hardware. Any failures here implies a hardware failure, since
 * atomic check should have filtered anything non-kosher.
 */
7351
static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
7352 7353 7354 7355 7356
{
	struct drm_device *dev = state->dev;
	struct amdgpu_device *adev = dev->dev_private;
	struct amdgpu_display_manager *dm = &adev->dm;
	struct dm_atomic_state *dm_state;
7357
	struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
7358
	uint32_t i, j;
7359
	struct drm_crtc *crtc;
7360
	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7361 7362 7363
	unsigned long flags;
	bool wait_for_vblank = true;
	struct drm_connector *connector;
7364
	struct drm_connector_state *old_con_state, *new_con_state;
7365
	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
7366
	int crtc_disable_count = 0;
7367 7368 7369

	drm_atomic_helper_update_legacy_modeset_state(dev, state);

7370 7371 7372 7373 7374
	dm_state = dm_atomic_get_new_state(state);
	if (dm_state && dm_state->context) {
		dc_state = dm_state->context;
	} else {
		/* No state changes, retain current state. */
7375
		dc_state_temp = dc_create_state(dm->dc);
7376 7377 7378 7379
		ASSERT(dc_state_temp);
		dc_state = dc_state_temp;
		dc_resource_state_copy_construct_current(dm->dc, dc_state);
	}
7380 7381

	/* update changed items */
7382
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7383
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
7384

7385 7386
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7387

7388
		DRM_DEBUG_DRIVER(
7389 7390 7391 7392
			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
			"planes_changed:%d, mode_changed:%d,active_changed:%d,"
			"connectors_changed:%d\n",
			acrtc->crtc_id,
7393 7394 7395 7396 7397 7398
			new_crtc_state->enable,
			new_crtc_state->active,
			new_crtc_state->planes_changed,
			new_crtc_state->mode_changed,
			new_crtc_state->active_changed,
			new_crtc_state->connectors_changed);
7399

7400 7401 7402 7403 7404 7405
		/* Copy all transient state flags into dc state */
		if (dm_new_crtc_state->stream) {
			amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
							    dm_new_crtc_state->stream);
		}

7406 7407 7408 7409
		/* handles headless hotplug case, updating new_state and
		 * aconnector as needed
		 */

7410
		if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
7411

7412
			DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
7413

7414
			if (!dm_new_crtc_state->stream) {
7415
				/*
7416 7417 7418
				 * this could happen because of issues with
				 * userspace notifications delivery.
				 * In this case userspace tries to set mode on
7419 7420
				 * display which is disconnected in fact.
				 * dc_sink is NULL in this case on aconnector.
7421 7422 7423 7424 7425 7426 7427 7428 7429
				 * We expect reset mode will come soon.
				 *
				 * This can also happen when unplug is done
				 * during resume sequence ended
				 *
				 * In this case, we want to pretend we still
				 * have a sink to keep the pipe running so that
				 * hw state is consistent with the sw state
				 */
7430
				DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
7431 7432 7433 7434
						__func__, acrtc->base.base.id);
				continue;
			}

7435 7436
			if (dm_old_crtc_state->stream)
				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
7437

7438 7439
			pm_runtime_get_noresume(dev->dev);

7440
			acrtc->enabled = true;
7441 7442 7443
			acrtc->hw_mode = new_crtc_state->mode;
			crtc->hwmode = new_crtc_state->mode;
		} else if (modereset_required(new_crtc_state)) {
7444
			DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
7445
			/* i.e. reset mode */
R
Roman Li 已提交
7446
			if (dm_old_crtc_state->stream) {
7447
				if (dm_old_crtc_state->stream->link->psr_settings.psr_allow_active)
R
Roman Li 已提交
7448 7449
					amdgpu_dm_psr_disable(dm_old_crtc_state->stream);

7450
				remove_stream(adev, acrtc, dm_old_crtc_state->stream);
R
Roman Li 已提交
7451
			}
7452 7453 7454
		}
	} /* for_each_crtc_in_state() */

7455 7456
	if (dc_state) {
		dm_enable_per_frame_crtc_master_sync(dc_state);
7457
		mutex_lock(&dm->dc_lock);
7458
		WARN_ON(!dc_commit_state(dm->dc, dc_state));
7459
		mutex_unlock(&dm->dc_lock);
7460
	}
7461

7462
	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
7463
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
7464

7465
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7466

7467
		if (dm_new_crtc_state->stream != NULL) {
7468
			const struct dc_stream_status *status =
7469
					dc_stream_get_status(dm_new_crtc_state->stream);
7470

7471
			if (!status)
7472 7473
				status = dc_stream_get_status_from_state(dc_state,
									 dm_new_crtc_state->stream);
7474

7475
			if (!status)
7476
				DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
7477 7478 7479 7480
			else
				acrtc->otg_inst = status->primary_otg_inst;
		}
	}
7481 7482 7483 7484 7485 7486 7487 7488 7489 7490 7491 7492 7493 7494 7495 7496 7497 7498 7499 7500 7501
#ifdef CONFIG_DRM_AMD_DC_HDCP
	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);

		new_crtc_state = NULL;

		if (acrtc)
			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);

		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);

		if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
		    connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
			hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
			new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
			continue;
		}

		if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
7502 7503
			hdcp_update_display(
				adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
7504
				new_con_state->hdcp_content_type,
7505 7506
				new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED ? true
													 : false);
7507 7508
	}
#endif
7509

7510
	/* Handle connector state changes */
7511
	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
7512 7513 7514
		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
7515 7516
		struct dc_surface_update dummy_updates[MAX_SURFACES];
		struct dc_stream_update stream_update;
7517
		struct dc_info_packet hdr_packet;
7518
		struct dc_stream_status *status = NULL;
7519
		bool abm_changed, hdr_changed, scaling_changed;
7520

7521 7522 7523
		memset(&dummy_updates, 0, sizeof(dummy_updates));
		memset(&stream_update, 0, sizeof(stream_update));

7524
		if (acrtc) {
7525
			new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
7526 7527
			old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
		}
7528

7529
		/* Skip any modesets/resets */
7530
		if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
7531 7532
			continue;

7533
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7534 7535
		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);

7536 7537 7538 7539 7540 7541 7542 7543 7544 7545
		scaling_changed = is_scaling_state_different(dm_new_con_state,
							     dm_old_con_state);

		abm_changed = dm_new_crtc_state->abm_level !=
			      dm_old_crtc_state->abm_level;

		hdr_changed =
			is_hdr_metadata_different(old_con_state, new_con_state);

		if (!scaling_changed && !abm_changed && !hdr_changed)
7546
			continue;
7547

7548
		stream_update.stream = dm_new_crtc_state->stream;
7549
		if (scaling_changed) {
7550
			update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
7551
					dm_new_con_state, dm_new_crtc_state->stream);
7552

7553 7554 7555 7556
			stream_update.src = dm_new_crtc_state->stream->src;
			stream_update.dst = dm_new_crtc_state->stream->dst;
		}

7557
		if (abm_changed) {
7558 7559 7560 7561
			dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;

			stream_update.abm_level = &dm_new_crtc_state->abm_level;
		}
7562

7563 7564 7565 7566 7567
		if (hdr_changed) {
			fill_hdr_info_packet(new_con_state, &hdr_packet);
			stream_update.hdr_static_metadata = &hdr_packet;
		}

7568
		status = dc_stream_get_status(dm_new_crtc_state->stream);
7569
		WARN_ON(!status);
7570
		WARN_ON(!status->plane_count);
7571

7572 7573 7574 7575 7576 7577 7578 7579 7580 7581 7582 7583 7584 7585 7586 7587 7588
		/*
		 * TODO: DC refuses to perform stream updates without a dc_surface_update.
		 * Here we create an empty update on each plane.
		 * To fix this, DC should permit updating only stream properties.
		 */
		for (j = 0; j < status->plane_count; j++)
			dummy_updates[j].surface = status->plane_states[0];


		mutex_lock(&dm->dc_lock);
		dc_commit_updates_for_stream(dm->dc,
						     dummy_updates,
						     status->plane_count,
						     dm_new_crtc_state->stream,
						     &stream_update,
						     dc_state);
		mutex_unlock(&dm->dc_lock);
7589 7590
	}

7591
	/* Count number of newly disabled CRTCs for dropping PM refs later. */
7592
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
7593
				      new_crtc_state, i) {
7594 7595 7596
		if (old_crtc_state->active && !new_crtc_state->active)
			crtc_disable_count++;

7597
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7598
		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7599

7600 7601 7602
		/* Update freesync active state. */
		pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);

7603 7604 7605
		/* Handle vrr on->off / off->on transitions */
		amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
						dm_new_crtc_state);
7606 7607
	}

7608 7609
	/* Enable interrupts for CRTCs going through a modeset. */
	amdgpu_dm_enable_crtc_interrupts(dev, state, true);
7610

7611
	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
7612
		if (new_crtc_state->async_flip)
7613 7614
			wait_for_vblank = false;

7615
	/* update planes when needed per crtc*/
7616
	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
7617
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
7618

7619
		if (dm_new_crtc_state->stream)
7620
			amdgpu_dm_commit_planes(state, dc_state, dev,
7621
						dm, crtc, wait_for_vblank);
7622 7623
	}

7624 7625
	/* Enable interrupts for CRTCs going from 0 to n active planes. */
	amdgpu_dm_enable_crtc_interrupts(dev, state, false);
7626

7627 7628 7629
	/* Update audio instances for each connector. */
	amdgpu_dm_commit_audio(dev, state);

7630 7631 7632 7633 7634
	/*
	 * send vblank event on all events not handled in flip and
	 * mark consumed event for drm_atomic_helper_commit_hw_done
	 */
	spin_lock_irqsave(&adev->ddev->event_lock, flags);
7635
	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
7636

7637 7638
		if (new_crtc_state->event)
			drm_send_event_locked(dev, &new_crtc_state->event->base);
7639

7640
		new_crtc_state->event = NULL;
7641 7642 7643
	}
	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);

7644 7645
	/* Signal HW programming completion */
	drm_atomic_helper_commit_hw_done(state);
7646 7647

	if (wait_for_vblank)
7648
		drm_atomic_helper_wait_for_flip_done(dev, state);
7649 7650

	drm_atomic_helper_cleanup_planes(dev, state);
7651

7652 7653
	/*
	 * Finally, drop a runtime PM reference for each newly disabled CRTC,
7654 7655 7656
	 * so we can put the GPU into runtime suspend if we're not driving any
	 * displays anymore
	 */
7657 7658
	for (i = 0; i < crtc_disable_count; i++)
		pm_runtime_put_autosuspend(dev->dev);
7659
	pm_runtime_mark_last_busy(dev->dev);
7660 7661 7662

	if (dc_state_temp)
		dc_release_state(dc_state_temp);
7663 7664 7665 7666 7667 7668 7669 7670 7671 7672 7673 7674 7675 7676 7677 7678 7679 7680 7681 7682 7683 7684 7685 7686 7687 7688 7689 7690 7691 7692 7693 7694 7695 7696 7697 7698 7699 7700 7701 7702 7703 7704 7705 7706 7707 7708 7709 7710 7711 7712 7713 7714 7715 7716 7717 7718 7719 7720 7721 7722 7723
}


static int dm_force_atomic_commit(struct drm_connector *connector)
{
	int ret = 0;
	struct drm_device *ddev = connector->dev;
	struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
	struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
	struct drm_plane *plane = disconnected_acrtc->base.primary;
	struct drm_connector_state *conn_state;
	struct drm_crtc_state *crtc_state;
	struct drm_plane_state *plane_state;

	if (!state)
		return -ENOMEM;

	state->acquire_ctx = ddev->mode_config.acquire_ctx;

	/* Construct an atomic state to restore previous display setting */

	/*
	 * Attach connectors to drm_atomic_state
	 */
	conn_state = drm_atomic_get_connector_state(state, connector);

	ret = PTR_ERR_OR_ZERO(conn_state);
	if (ret)
		goto err;

	/* Attach crtc to drm_atomic_state*/
	crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);

	ret = PTR_ERR_OR_ZERO(crtc_state);
	if (ret)
		goto err;

	/* force a restore */
	crtc_state->mode_changed = true;

	/* Attach plane to drm_atomic_state */
	plane_state = drm_atomic_get_plane_state(state, plane);

	ret = PTR_ERR_OR_ZERO(plane_state);
	if (ret)
		goto err;


	/* Call commit internally with the state we just constructed */
	ret = drm_atomic_commit(state);
	if (!ret)
		return 0;

err:
	DRM_ERROR("Restoring old state failed with %i\n", ret);
	drm_atomic_state_put(state);

	return ret;
}

/*
7724 7725 7726
 * This function handles all cases when set mode does not come upon hotplug.
 * This includes when a display is unplugged then plugged back into the
 * same port and when running without usermode desktop manager supprot
7727
 */
7728 7729
void dm_restore_drm_connector_state(struct drm_device *dev,
				    struct drm_connector *connector)
7730
{
7731
	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7732 7733 7734 7735 7736 7737 7738
	struct amdgpu_crtc *disconnected_acrtc;
	struct dm_crtc_state *acrtc_state;

	if (!aconnector->dc_sink || !connector->state || !connector->encoder)
		return;

	disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
7739 7740
	if (!disconnected_acrtc)
		return;
7741

7742 7743
	acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
	if (!acrtc_state->stream)
7744 7745 7746 7747 7748 7749 7750 7751 7752 7753 7754
		return;

	/*
	 * If the previous sink is not released and different from the current,
	 * we deduce we are in a state where we can not rely on usermode call
	 * to turn on the display, so we do it here
	 */
	if (acrtc_state->stream->sink != aconnector->dc_sink)
		dm_force_atomic_commit(&aconnector->base);
}

7755
/*
7756 7757 7758
 * Grabs all modesetting locks to serialize against any blocking commits,
 * Waits for completion of all non blocking commits.
 */
7759 7760
static int do_aquire_global_lock(struct drm_device *dev,
				 struct drm_atomic_state *state)
7761 7762 7763 7764 7765
{
	struct drm_crtc *crtc;
	struct drm_crtc_commit *commit;
	long ret;

7766 7767
	/*
	 * Adding all modeset locks to aquire_ctx will
7768 7769 7770 7771 7772 7773 7774 7775 7776 7777 7778 7779 7780 7781 7782 7783 7784 7785
	 * ensure that when the framework release it the
	 * extra locks we are locking here will get released to
	 */
	ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
	if (ret)
		return ret;

	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		spin_lock(&crtc->commit_lock);
		commit = list_first_entry_or_null(&crtc->commit_list,
				struct drm_crtc_commit, commit_entry);
		if (commit)
			drm_crtc_commit_get(commit);
		spin_unlock(&crtc->commit_lock);

		if (!commit)
			continue;

7786 7787
		/*
		 * Make sure all pending HW programming completed and
7788 7789 7790 7791 7792 7793 7794 7795 7796 7797
		 * page flips done
		 */
		ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);

		if (ret > 0)
			ret = wait_for_completion_interruptible_timeout(
					&commit->flip_done, 10*HZ);

		if (ret == 0)
			DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
7798
				  "timed out\n", crtc->base.id, crtc->name);
7799 7800 7801 7802 7803 7804 7805

		drm_crtc_commit_put(commit);
	}

	return ret < 0 ? ret : 0;
}

7806 7807 7808
static void get_freesync_config_for_crtc(
	struct dm_crtc_state *new_crtc_state,
	struct dm_connector_state *new_con_state)
7809 7810 7811 7812
{
	struct mod_freesync_config config = {0};
	struct amdgpu_dm_connector *aconnector =
			to_amdgpu_dm_connector(new_con_state->base.connector);
7813
	struct drm_display_mode *mode = &new_crtc_state->base.mode;
7814
	int vrefresh = drm_mode_vrefresh(mode);
7815

7816
	new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
7817 7818
					vrefresh >= aconnector->min_vfreq &&
					vrefresh <= aconnector->max_vfreq;
7819

7820 7821
	if (new_crtc_state->vrr_supported) {
		new_crtc_state->stream->ignore_msa_timing_param = true;
7822
		config.state = new_crtc_state->base.vrr_enabled ?
7823 7824 7825 7826 7827 7828
				VRR_STATE_ACTIVE_VARIABLE :
				VRR_STATE_INACTIVE;
		config.min_refresh_in_uhz =
				aconnector->min_vfreq * 1000000;
		config.max_refresh_in_uhz =
				aconnector->max_vfreq * 1000000;
7829
		config.vsif_supported = true;
7830
		config.btr = true;
7831 7832
	}

7833 7834
	new_crtc_state->freesync_config = config;
}
7835

7836 7837 7838 7839
static void reset_freesync_config_for_crtc(
	struct dm_crtc_state *new_crtc_state)
{
	new_crtc_state->vrr_supported = false;
7840

7841 7842
	memset(&new_crtc_state->vrr_params, 0,
	       sizeof(new_crtc_state->vrr_params));
7843 7844
	memset(&new_crtc_state->vrr_infopacket, 0,
	       sizeof(new_crtc_state->vrr_infopacket));
7845 7846
}

7847 7848 7849 7850 7851 7852 7853
static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
				struct drm_atomic_state *state,
				struct drm_crtc *crtc,
				struct drm_crtc_state *old_crtc_state,
				struct drm_crtc_state *new_crtc_state,
				bool enable,
				bool *lock_and_validation_needed)
7854
{
7855
	struct dm_atomic_state *dm_state = NULL;
7856
	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
7857
	struct dc_stream_state *new_stream;
7858
	int ret = 0;
7859

7860 7861 7862 7863
	/*
	 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
	 * update changed items
	 */
7864 7865 7866 7867
	struct amdgpu_crtc *acrtc = NULL;
	struct amdgpu_dm_connector *aconnector = NULL;
	struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
	struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
7868

7869
	new_stream = NULL;
7870

7871 7872 7873 7874
	dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
	acrtc = to_amdgpu_crtc(crtc);
	aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
7875

7876 7877 7878 7879 7880 7881 7882
	/* TODO This hack should go away */
	if (aconnector && enable) {
		/* Make sure fake sink is created in plug-in scenario */
		drm_new_conn_state = drm_atomic_get_new_connector_state(state,
							    &aconnector->base);
		drm_old_conn_state = drm_atomic_get_old_connector_state(state,
							    &aconnector->base);
7883

7884 7885 7886 7887
		if (IS_ERR(drm_new_conn_state)) {
			ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
			goto fail;
		}
7888

7889 7890
		dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
		dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
7891

7892 7893 7894
		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
			goto skip_modeset;

7895 7896 7897 7898
		new_stream = create_validate_stream_for_sink(aconnector,
							     &new_crtc_state->mode,
							     dm_new_conn_state,
							     dm_old_crtc_state->stream);
7899

7900 7901 7902 7903 7904 7905
		/*
		 * we can have no stream on ACTION_SET if a display
		 * was disconnected during S3, in this case it is not an
		 * error, the OS will be updated after detection, and
		 * will do the right thing on next atomic commit
		 */
7906

7907 7908 7909 7910 7911 7912
		if (!new_stream) {
			DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
					__func__, acrtc->base.base.id);
			ret = -ENOMEM;
			goto fail;
		}
7913

7914
		dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
7915

7916 7917 7918 7919 7920
		ret = fill_hdr_info_packet(drm_new_conn_state,
					   &new_stream->hdr_static_metadata);
		if (ret)
			goto fail;

7921 7922 7923 7924 7925 7926 7927 7928 7929 7930 7931
		/*
		 * If we already removed the old stream from the context
		 * (and set the new stream to NULL) then we can't reuse
		 * the old stream even if the stream and scaling are unchanged.
		 * We'll hit the BUG_ON and black screen.
		 *
		 * TODO: Refactor this function to allow this check to work
		 * in all conditions.
		 */
		if (dm_new_crtc_state->stream &&
		    dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
7932 7933 7934 7935
		    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
			new_crtc_state->mode_changed = false;
			DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
					 new_crtc_state->mode_changed);
7936
		}
7937
	}
7938

7939
	/* mode_changed flag may get updated above, need to check again */
7940 7941
	if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
		goto skip_modeset;
7942

7943 7944 7945 7946 7947 7948 7949 7950 7951 7952 7953
	DRM_DEBUG_DRIVER(
		"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
		"planes_changed:%d, mode_changed:%d,active_changed:%d,"
		"connectors_changed:%d\n",
		acrtc->crtc_id,
		new_crtc_state->enable,
		new_crtc_state->active,
		new_crtc_state->planes_changed,
		new_crtc_state->mode_changed,
		new_crtc_state->active_changed,
		new_crtc_state->connectors_changed);
7954

7955 7956
	/* Remove stream for any changed/disabled CRTC */
	if (!enable) {
7957

7958 7959
		if (!dm_old_crtc_state->stream)
			goto skip_modeset;
7960

7961 7962 7963
		ret = dm_atomic_get_state(state, &dm_state);
		if (ret)
			goto fail;
7964

7965 7966
		DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
				crtc->base.id);
7967

7968 7969 7970 7971 7972 7973 7974 7975
		/* i.e. reset mode */
		if (dc_remove_stream_from_ctx(
				dm->dc,
				dm_state->context,
				dm_old_crtc_state->stream) != DC_OK) {
			ret = -EINVAL;
			goto fail;
		}
7976

7977 7978
		dc_stream_release(dm_old_crtc_state->stream);
		dm_new_crtc_state->stream = NULL;
7979

7980
		reset_freesync_config_for_crtc(dm_new_crtc_state);
7981

7982
		*lock_and_validation_needed = true;
7983

7984 7985 7986 7987 7988 7989 7990 7991
	} else {/* Add stream for any updated/enabled CRTC */
		/*
		 * Quick fix to prevent NULL pointer on new_stream when
		 * added MST connectors not found in existing crtc_state in the chained mode
		 * TODO: need to dig out the root cause of that
		 */
		if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
			goto skip_modeset;
7992

7993 7994
		if (modereset_required(new_crtc_state))
			goto skip_modeset;
7995

7996 7997
		if (modeset_required(new_crtc_state, new_stream,
				     dm_old_crtc_state->stream)) {
7998

7999
			WARN_ON(dm_new_crtc_state->stream);
8000

8001 8002 8003
			ret = dm_atomic_get_state(state, &dm_state);
			if (ret)
				goto fail;
8004

8005
			dm_new_crtc_state->stream = new_stream;
8006

8007
			dc_stream_retain(new_stream);
8008

8009 8010
			DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
						crtc->base.id);
8011

8012 8013 8014 8015 8016 8017
			if (dc_add_stream_to_ctx(
					dm->dc,
					dm_state->context,
					dm_new_crtc_state->stream) != DC_OK) {
				ret = -EINVAL;
				goto fail;
8018 8019
			}

8020 8021 8022
			*lock_and_validation_needed = true;
		}
	}
8023

8024 8025 8026 8027
skip_modeset:
	/* Release extra reference */
	if (new_stream)
		 dc_stream_release(new_stream);
8028

8029 8030 8031 8032 8033 8034 8035 8036 8037 8038 8039 8040 8041 8042 8043 8044
	/*
	 * We want to do dc stream updates that do not require a
	 * full modeset below.
	 */
	if (!(enable && aconnector && new_crtc_state->enable &&
	      new_crtc_state->active))
		return 0;
	/*
	 * Given above conditions, the dc state cannot be NULL because:
	 * 1. We're in the process of enabling CRTCs (just been added
	 *    to the dc context, or already is on the context)
	 * 2. Has a valid connector attached, and
	 * 3. Is currently active and enabled.
	 * => The dc stream state currently exists.
	 */
	BUG_ON(dm_new_crtc_state->stream == NULL);
8045

8046 8047 8048 8049
	/* Scaling or underscan settings */
	if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
		update_stream_scaling_settings(
			&new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
8050

8051 8052 8053
	/* ABM settings */
	dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;

8054 8055 8056 8057 8058 8059
	/*
	 * Color management settings. We also update color properties
	 * when a modeset is needed, to ensure it gets reprogrammed.
	 */
	if (dm_new_crtc_state->base.color_mgmt_changed ||
	    drm_atomic_crtc_needs_modeset(new_crtc_state)) {
8060
		ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
8061 8062
		if (ret)
			goto fail;
8063
	}
8064

8065 8066 8067 8068
	/* Update Freesync settings. */
	get_freesync_config_for_crtc(dm_new_crtc_state,
				     dm_new_conn_state);

8069
	return ret;
8070 8071 8072 8073 8074

fail:
	if (new_stream)
		dc_stream_release(new_stream);
	return ret;
8075
}
8076

8077 8078 8079 8080 8081 8082 8083 8084 8085 8086
static bool should_reset_plane(struct drm_atomic_state *state,
			       struct drm_plane *plane,
			       struct drm_plane_state *old_plane_state,
			       struct drm_plane_state *new_plane_state)
{
	struct drm_plane *other;
	struct drm_plane_state *old_other_state, *new_other_state;
	struct drm_crtc_state *new_crtc_state;
	int i;

8087 8088 8089 8090 8091 8092 8093 8094
	/*
	 * TODO: Remove this hack once the checks below are sufficient
	 * enough to determine when we need to reset all the planes on
	 * the stream.
	 */
	if (state->allow_modeset)
		return true;

8095 8096 8097 8098 8099 8100 8101 8102 8103 8104 8105 8106 8107 8108
	/* Exit early if we know that we're adding or removing the plane. */
	if (old_plane_state->crtc != new_plane_state->crtc)
		return true;

	/* old crtc == new_crtc == NULL, plane not in context. */
	if (!new_plane_state->crtc)
		return false;

	new_crtc_state =
		drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);

	if (!new_crtc_state)
		return true;

8109 8110 8111 8112
	/* CRTC Degamma changes currently require us to recreate planes. */
	if (new_crtc_state->color_mgmt_changed)
		return true;

8113 8114 8115 8116 8117 8118 8119 8120 8121 8122 8123 8124 8125 8126 8127 8128 8129 8130 8131 8132 8133 8134 8135 8136 8137 8138 8139 8140 8141 8142 8143
	if (drm_atomic_crtc_needs_modeset(new_crtc_state))
		return true;

	/*
	 * If there are any new primary or overlay planes being added or
	 * removed then the z-order can potentially change. To ensure
	 * correct z-order and pipe acquisition the current DC architecture
	 * requires us to remove and recreate all existing planes.
	 *
	 * TODO: Come up with a more elegant solution for this.
	 */
	for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
		if (other->type == DRM_PLANE_TYPE_CURSOR)
			continue;

		if (old_other_state->crtc != new_plane_state->crtc &&
		    new_other_state->crtc != new_plane_state->crtc)
			continue;

		if (old_other_state->crtc != new_other_state->crtc)
			return true;

		/* TODO: Remove this once we can handle fast format changes. */
		if (old_other_state->fb && new_other_state->fb &&
		    old_other_state->fb->format != new_other_state->fb->format)
			return true;
	}

	return false;
}

8144 8145 8146 8147 8148 8149 8150
static int dm_update_plane_state(struct dc *dc,
				 struct drm_atomic_state *state,
				 struct drm_plane *plane,
				 struct drm_plane_state *old_plane_state,
				 struct drm_plane_state *new_plane_state,
				 bool enable,
				 bool *lock_and_validation_needed)
8151
{
8152 8153

	struct dm_atomic_state *dm_state = NULL;
8154
	struct drm_crtc *new_plane_crtc, *old_plane_crtc;
8155
	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8156 8157
	struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
	struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
8158
	struct amdgpu_crtc *new_acrtc;
8159
	bool needs_reset;
8160
	int ret = 0;
8161

8162

8163 8164 8165 8166
	new_plane_crtc = new_plane_state->crtc;
	old_plane_crtc = old_plane_state->crtc;
	dm_new_plane_state = to_dm_plane_state(new_plane_state);
	dm_old_plane_state = to_dm_plane_state(old_plane_state);
8167

8168 8169 8170 8171 8172 8173 8174 8175 8176 8177 8178 8179 8180 8181 8182
	/*TODO Implement better atomic check for cursor plane */
	if (plane->type == DRM_PLANE_TYPE_CURSOR) {
		if (!enable || !new_plane_crtc ||
			drm_atomic_plane_disabling(plane->state, new_plane_state))
			return 0;

		new_acrtc = to_amdgpu_crtc(new_plane_crtc);

		if ((new_plane_state->crtc_w > new_acrtc->max_cursor_width) ||
			(new_plane_state->crtc_h > new_acrtc->max_cursor_height)) {
			DRM_DEBUG_ATOMIC("Bad cursor size %d x %d\n",
							 new_plane_state->crtc_w, new_plane_state->crtc_h);
			return -EINVAL;
		}

8183
		return 0;
8184
	}
8185

8186 8187 8188
	needs_reset = should_reset_plane(state, plane, old_plane_state,
					 new_plane_state);

8189 8190
	/* Remove any changed/removed planes */
	if (!enable) {
8191
		if (!needs_reset)
8192
			return 0;
8193

8194 8195
		if (!old_plane_crtc)
			return 0;
8196

8197 8198 8199
		old_crtc_state = drm_atomic_get_old_crtc_state(
				state, old_plane_crtc);
		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8200

8201 8202
		if (!dm_old_crtc_state->stream)
			return 0;
8203

8204 8205
		DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
				plane->base.id, old_plane_crtc->base.id);
8206

8207 8208 8209
		ret = dm_atomic_get_state(state, &dm_state);
		if (ret)
			return ret;
8210

8211 8212 8213 8214 8215
		if (!dc_remove_plane_from_context(
				dc,
				dm_old_crtc_state->stream,
				dm_old_plane_state->dc_state,
				dm_state->context)) {
8216

8217 8218 8219
			ret = EINVAL;
			return ret;
		}
8220

8221

8222 8223
		dc_plane_state_release(dm_old_plane_state->dc_state);
		dm_new_plane_state->dc_state = NULL;
8224

8225
		*lock_and_validation_needed = true;
8226

8227 8228
	} else { /* Add new planes */
		struct dc_plane_state *dc_new_plane_state;
8229

8230 8231
		if (drm_atomic_plane_disabling(plane->state, new_plane_state))
			return 0;
8232

8233 8234
		if (!new_plane_crtc)
			return 0;
8235

8236 8237
		new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8238

8239 8240
		if (!dm_new_crtc_state->stream)
			return 0;
8241

8242
		if (!needs_reset)
8243
			return 0;
8244

8245 8246 8247 8248
		ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
		if (ret)
			return ret;

8249
		WARN_ON(dm_new_plane_state->dc_state);
8250

8251 8252 8253
		dc_new_plane_state = dc_create_plane_state(dc);
		if (!dc_new_plane_state)
			return -ENOMEM;
8254

8255 8256
		DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
				plane->base.id, new_plane_crtc->base.id);
8257

8258
		ret = fill_dc_plane_attributes(
8259 8260 8261 8262 8263 8264 8265 8266
			new_plane_crtc->dev->dev_private,
			dc_new_plane_state,
			new_plane_state,
			new_crtc_state);
		if (ret) {
			dc_plane_state_release(dc_new_plane_state);
			return ret;
		}
8267

8268 8269 8270 8271 8272
		ret = dm_atomic_get_state(state, &dm_state);
		if (ret) {
			dc_plane_state_release(dc_new_plane_state);
			return ret;
		}
8273

8274 8275 8276 8277 8278 8279 8280 8281 8282 8283 8284 8285
		/*
		 * Any atomic check errors that occur after this will
		 * not need a release. The plane state will be attached
		 * to the stream, and therefore part of the atomic
		 * state. It'll be released when the atomic state is
		 * cleaned.
		 */
		if (!dc_add_plane_to_context(
				dc,
				dm_new_crtc_state->stream,
				dc_new_plane_state,
				dm_state->context)) {
8286

8287 8288 8289
			dc_plane_state_release(dc_new_plane_state);
			return -EINVAL;
		}
8290

8291
		dm_new_plane_state->dc_state = dc_new_plane_state;
8292

8293 8294 8295 8296 8297 8298
		/* Tell DC to do a full surface update every time there
		 * is a plane change. Inefficient, but works for now.
		 */
		dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;

		*lock_and_validation_needed = true;
8299
	}
8300 8301


8302 8303
	return ret;
}
8304

8305
static int
8306
dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
8307 8308 8309
				    struct drm_atomic_state *state,
				    enum surface_update_type *out_type)
{
8310
	struct dc *dc = dm->dc;
8311 8312
	struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
	int i, j, num_plane, ret = 0;
8313 8314
	struct drm_plane_state *old_plane_state, *new_plane_state;
	struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
8315
	struct drm_crtc *new_plane_crtc;
8316 8317 8318 8319 8320 8321 8322
	struct drm_plane *plane;

	struct drm_crtc *crtc;
	struct drm_crtc_state *new_crtc_state, *old_crtc_state;
	struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
	struct dc_stream_status *status = NULL;
	enum surface_update_type update_type = UPDATE_TYPE_FAST;
8323 8324 8325 8326 8327 8328 8329
	struct surface_info_bundle {
		struct dc_surface_update surface_updates[MAX_SURFACES];
		struct dc_plane_info plane_infos[MAX_SURFACES];
		struct dc_scaling_info scaling_infos[MAX_SURFACES];
		struct dc_flip_addrs flip_addrs[MAX_SURFACES];
		struct dc_stream_update stream_update;
	} *bundle;
8330

8331
	bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8332

8333 8334
	if (!bundle) {
		DRM_ERROR("Failed to allocate update bundle\n");
8335 8336
		/* Set type to FULL to avoid crashing in DC*/
		update_type = UPDATE_TYPE_FULL;
8337
		goto cleanup;
8338
	}
8339 8340

	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8341

8342
		memset(bundle, 0, sizeof(struct surface_info_bundle));
8343

8344 8345 8346 8347
		new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
		old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
		num_plane = 0;

8348 8349 8350 8351
		if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
			update_type = UPDATE_TYPE_FULL;
			goto cleanup;
		}
8352

8353
		if (!new_dm_crtc_state->stream)
8354
			continue;
8355

8356
		for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
8357 8358
			const struct amdgpu_framebuffer *amdgpu_fb =
				to_amdgpu_framebuffer(new_plane_state->fb);
8359 8360 8361
			struct dc_plane_info *plane_info = &bundle->plane_infos[num_plane];
			struct dc_flip_addrs *flip_addr = &bundle->flip_addrs[num_plane];
			struct dc_scaling_info *scaling_info = &bundle->scaling_infos[num_plane];
8362
			uint64_t tiling_flags;
8363
			bool tmz_surface = false;
8364

8365 8366 8367
			new_plane_crtc = new_plane_state->crtc;
			new_dm_plane_state = to_dm_plane_state(new_plane_state);
			old_dm_plane_state = to_dm_plane_state(old_plane_state);
8368

8369 8370
			if (plane->type == DRM_PLANE_TYPE_CURSOR)
				continue;
8371

8372 8373 8374 8375 8376
			if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
				update_type = UPDATE_TYPE_FULL;
				goto cleanup;
			}

8377 8378 8379
			if (crtc != new_plane_crtc)
				continue;

8380 8381
			bundle->surface_updates[num_plane].surface =
					new_dm_plane_state->dc_state;
8382 8383

			if (new_crtc_state->mode_changed) {
8384 8385
				bundle->stream_update.dst = new_dm_crtc_state->stream->dst;
				bundle->stream_update.src = new_dm_crtc_state->stream->src;
8386 8387 8388
			}

			if (new_crtc_state->color_mgmt_changed) {
8389
				bundle->surface_updates[num_plane].gamma =
8390
						new_dm_plane_state->dc_state->gamma_correction;
8391
				bundle->surface_updates[num_plane].in_transfer_func =
8392
						new_dm_plane_state->dc_state->in_transfer_func;
8393 8394
				bundle->surface_updates[num_plane].gamut_remap_matrix =
						&new_dm_plane_state->dc_state->gamut_remap_matrix;
8395
				bundle->stream_update.gamut_remap =
8396
						&new_dm_crtc_state->stream->gamut_remap_matrix;
8397
				bundle->stream_update.output_csc_transform =
8398
						&new_dm_crtc_state->stream->csc_color_matrix;
8399
				bundle->stream_update.out_transfer_func =
8400
						new_dm_crtc_state->stream->out_transfer_func;
8401 8402
			}

8403
			ret = fill_dc_scaling_info(new_plane_state,
8404
						   scaling_info);
8405 8406 8407
			if (ret)
				goto cleanup;

8408
			bundle->surface_updates[num_plane].scaling_info = scaling_info;
8409

8410
			if (amdgpu_fb) {
8411
				ret = get_fb_info(amdgpu_fb, &tiling_flags, &tmz_surface);
8412 8413 8414 8415 8416
				if (ret)
					goto cleanup;

				ret = fill_dc_plane_info_and_addr(
					dm->adev, new_plane_state, tiling_flags,
8417
					plane_info,
8418
					&flip_addr->address, tmz_surface,
8419
					false);
8420 8421 8422
				if (ret)
					goto cleanup;

8423 8424
				bundle->surface_updates[num_plane].plane_info = plane_info;
				bundle->surface_updates[num_plane].flip_addr = flip_addr;
8425 8426
			}

8427 8428 8429 8430 8431 8432 8433 8434 8435 8436 8437 8438 8439 8440 8441 8442 8443 8444
			num_plane++;
		}

		if (num_plane == 0)
			continue;

		ret = dm_atomic_get_state(state, &dm_state);
		if (ret)
			goto cleanup;

		old_dm_state = dm_atomic_get_old_state(state);
		if (!old_dm_state) {
			ret = -EINVAL;
			goto cleanup;
		}

		status = dc_stream_get_status_from_state(old_dm_state->context,
							 new_dm_crtc_state->stream);
8445
		bundle->stream_update.stream = new_dm_crtc_state->stream;
8446 8447 8448 8449 8450
		/*
		 * TODO: DC modifies the surface during this call so we need
		 * to lock here - find a way to do this without locking.
		 */
		mutex_lock(&dm->dc_lock);
8451 8452 8453
		update_type = dc_check_update_surfaces_for_stream(
				dc,	bundle->surface_updates, num_plane,
				&bundle->stream_update, status);
8454
		mutex_unlock(&dm->dc_lock);
8455 8456

		if (update_type > UPDATE_TYPE_MED) {
8457
			update_type = UPDATE_TYPE_FULL;
8458
			goto cleanup;
8459 8460 8461
		}
	}

8462
cleanup:
8463
	kfree(bundle);
8464

8465 8466
	*out_type = update_type;
	return ret;
8467
}
8468

8469 8470 8471 8472 8473 8474 8475 8476 8477 8478 8479 8480 8481 8482 8483 8484 8485 8486 8487 8488 8489 8490 8491
static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
{
	struct drm_connector *connector;
	struct drm_connector_state *conn_state;
	struct amdgpu_dm_connector *aconnector = NULL;
	int i;
	for_each_new_connector_in_state(state, connector, conn_state, i) {
		if (conn_state->crtc != crtc)
			continue;

		aconnector = to_amdgpu_dm_connector(connector);
		if (!aconnector->port || !aconnector->mst_port)
			aconnector = NULL;
		else
			break;
	}

	if (!aconnector)
		return 0;

	return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
}

8492 8493 8494 8495 8496 8497 8498 8499 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 8510 8511 8512 8513 8514 8515 8516
/**
 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
 * @dev: The DRM device
 * @state: The atomic state to commit
 *
 * Validate that the given atomic state is programmable by DC into hardware.
 * This involves constructing a &struct dc_state reflecting the new hardware
 * state we wish to commit, then querying DC to see if it is programmable. It's
 * important not to modify the existing DC state. Otherwise, atomic_check
 * may unexpectedly commit hardware changes.
 *
 * When validating the DC state, it's important that the right locks are
 * acquired. For full updates case which removes/adds/updates streams on one
 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
 * that any such full update commit will wait for completion of any outstanding
 * flip using DRMs synchronization events. See
 * dm_determine_update_type_for_commit()
 *
 * Note that DM adds the affected connectors for all CRTCs in state, when that
 * might not seem necessary. This is because DC stream creation requires the
 * DC sink, which is tied to the DRM connector state. Cleaning this up should
 * be possible but non-trivial - a possible TODO item.
 *
 * Return: -Error code if validation failed.
 */
8517 8518
static int amdgpu_dm_atomic_check(struct drm_device *dev,
				  struct drm_atomic_state *state)
8519 8520
{
	struct amdgpu_device *adev = dev->dev_private;
8521
	struct dm_atomic_state *dm_state = NULL;
8522 8523
	struct dc *dc = adev->dm.dc;
	struct drm_connector *connector;
8524
	struct drm_connector_state *old_con_state, *new_con_state;
8525
	struct drm_crtc *crtc;
8526
	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8527 8528
	struct drm_plane *plane;
	struct drm_plane_state *old_plane_state, *new_plane_state;
8529 8530
	enum surface_update_type update_type = UPDATE_TYPE_FAST;
	enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
8531
	enum dc_status status;
8532
	int ret, i;
8533

8534 8535 8536 8537 8538 8539 8540
	/*
	 * This bool will be set for true for any modeset/reset
	 * or plane update which implies non fast surface update.
	 */
	bool lock_and_validation_needed = false;

	ret = drm_atomic_helper_check_modeset(dev, state);
8541 8542
	if (ret)
		goto fail;
8543

8544 8545 8546 8547 8548 8549 8550 8551 8552 8553
	if (adev->asic_type >= CHIP_NAVI10) {
		for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
			if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
				ret = add_affected_mst_dsc_crtcs(state, crtc);
				if (ret)
					goto fail;
			}
		}
	}

8554 8555
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
		if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
8556
		    !new_crtc_state->color_mgmt_changed &&
8557
		    old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
8558
			continue;
8559

8560 8561
		if (!new_crtc_state->enable)
			continue;
8562

8563 8564 8565
		ret = drm_atomic_add_affected_connectors(state, crtc);
		if (ret)
			return ret;
8566

8567 8568 8569
		ret = drm_atomic_add_affected_planes(state, crtc);
		if (ret)
			goto fail;
8570 8571
	}

8572 8573 8574 8575 8576 8577 8578 8579 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 8590 8591 8592 8593 8594 8595 8596 8597 8598 8599 8600 8601 8602 8603 8604 8605 8606 8607
	/*
	 * Add all primary and overlay planes on the CRTC to the state
	 * whenever a plane is enabled to maintain correct z-ordering
	 * and to enable fast surface updates.
	 */
	drm_for_each_crtc(crtc, dev) {
		bool modified = false;

		for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
			if (plane->type == DRM_PLANE_TYPE_CURSOR)
				continue;

			if (new_plane_state->crtc == crtc ||
			    old_plane_state->crtc == crtc) {
				modified = true;
				break;
			}
		}

		if (!modified)
			continue;

		drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
			if (plane->type == DRM_PLANE_TYPE_CURSOR)
				continue;

			new_plane_state =
				drm_atomic_get_plane_state(state, plane);

			if (IS_ERR(new_plane_state)) {
				ret = PTR_ERR(new_plane_state);
				goto fail;
			}
		}
	}

8608
	/* Remove exiting planes if they are modified */
8609 8610 8611 8612 8613 8614 8615 8616
	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
		ret = dm_update_plane_state(dc, state, plane,
					    old_plane_state,
					    new_plane_state,
					    false,
					    &lock_and_validation_needed);
		if (ret)
			goto fail;
8617 8618 8619
	}

	/* Disable all crtcs which require disable */
8620 8621 8622 8623 8624 8625 8626 8627
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
		ret = dm_update_crtc_state(&adev->dm, state, crtc,
					   old_crtc_state,
					   new_crtc_state,
					   false,
					   &lock_and_validation_needed);
		if (ret)
			goto fail;
8628 8629 8630
	}

	/* Enable all crtcs which require enable */
8631 8632 8633 8634 8635 8636 8637 8638
	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
		ret = dm_update_crtc_state(&adev->dm, state, crtc,
					   old_crtc_state,
					   new_crtc_state,
					   true,
					   &lock_and_validation_needed);
		if (ret)
			goto fail;
8639 8640 8641
	}

	/* Add new/modified planes */
8642 8643 8644 8645 8646 8647 8648 8649
	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
		ret = dm_update_plane_state(dc, state, plane,
					    old_plane_state,
					    new_plane_state,
					    true,
					    &lock_and_validation_needed);
		if (ret)
			goto fail;
8650 8651
	}

8652 8653 8654 8655
	/* Run this here since we want to validate the streams we created */
	ret = drm_atomic_helper_check_planes(dev, state);
	if (ret)
		goto fail;
8656

8657 8658 8659 8660 8661 8662 8663 8664 8665 8666 8667 8668 8669 8670 8671 8672 8673 8674 8675 8676
	if (state->legacy_cursor_update) {
		/*
		 * This is a fast cursor update coming from the plane update
		 * helper, check if it can be done asynchronously for better
		 * performance.
		 */
		state->async_update =
			!drm_atomic_helper_async_check(dev, state);

		/*
		 * Skip the remaining global validation if this is an async
		 * update. Cursor updates can be done without affecting
		 * state or bandwidth calcs and this avoids the performance
		 * penalty of locking the private state object and
		 * allocating a new dc_state.
		 */
		if (state->async_update)
			return 0;
	}

L
Leo (Sunpeng) Li 已提交
8677
	/* Check scaling and underscan changes*/
8678
	/* TODO Removed scaling changes validation due to inability to commit
8679 8680 8681
	 * new stream into context w\o causing full reset. Need to
	 * decide how to handle.
	 */
8682
	for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8683 8684 8685
		struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
		struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8686 8687

		/* Skip any modesets/resets */
8688 8689
		if (!acrtc || drm_atomic_crtc_needs_modeset(
				drm_atomic_get_new_crtc_state(state, &acrtc->base)))
8690 8691
			continue;

8692
		/* Skip any thing not scale or underscan changes */
8693
		if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
8694 8695
			continue;

8696
		overall_update_type = UPDATE_TYPE_FULL;
8697 8698 8699
		lock_and_validation_needed = true;
	}

8700
	ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
8701 8702
	if (ret)
		goto fail;
8703 8704 8705 8706 8707 8708 8709 8710 8711 8712 8713 8714

	if (overall_update_type < update_type)
		overall_update_type = update_type;

	/*
	 * lock_and_validation_needed was an old way to determine if we need to set
	 * the global lock. Leaving it in to check if we broke any corner cases
	 * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
	 * lock_and_validation_needed false = UPDATE_TYPE_FAST
	 */
	if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
		WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
8715

8716
	if (overall_update_type > UPDATE_TYPE_FAST) {
8717 8718 8719
		ret = dm_atomic_get_state(state, &dm_state);
		if (ret)
			goto fail;
8720 8721 8722 8723

		ret = do_aquire_global_lock(dev, state);
		if (ret)
			goto fail;
8724

8725
#if defined(CONFIG_DRM_AMD_DC_DCN)
8726 8727 8728
		if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
			goto fail;

8729 8730 8731
		ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);
		if (ret)
			goto fail;
8732
#endif
8733

8734 8735 8736 8737 8738 8739 8740 8741 8742
		/*
		 * Perform validation of MST topology in the state:
		 * We need to perform MST atomic check before calling
		 * dc_validate_global_state(), or there is a chance
		 * to get stuck in an infinite loop and hang eventually.
		 */
		ret = drm_dp_mst_atomic_check(state);
		if (ret)
			goto fail;
8743 8744 8745 8746
		status = dc_validate_global_state(dc, dm_state->context, false);
		if (status != DC_OK) {
			DC_LOG_WARNING("DC global validation failure: %s (%d)",
				       dc_status_to_str(status), status);
8747 8748 8749
			ret = -EINVAL;
			goto fail;
		}
8750
	} else {
8751
		/*
8752 8753 8754 8755 8756 8757
		 * The commit is a fast update. Fast updates shouldn't change
		 * the DC context, affect global validation, and can have their
		 * commit work done in parallel with other commits not touching
		 * the same resource. If we have a new DC context as part of
		 * the DM atomic state from validation we need to free it and
		 * retain the existing one instead.
8758
		 */
8759 8760 8761 8762 8763 8764 8765 8766 8767 8768 8769 8770 8771 8772
		struct dm_atomic_state *new_dm_state, *old_dm_state;

		new_dm_state = dm_atomic_get_new_state(state);
		old_dm_state = dm_atomic_get_old_state(state);

		if (new_dm_state && old_dm_state) {
			if (new_dm_state->context)
				dc_release_state(new_dm_state->context);

			new_dm_state->context = old_dm_state->context;

			if (old_dm_state->context)
				dc_retain_state(old_dm_state->context);
		}
8773 8774
	}

8775 8776 8777 8778 8779 8780
	/* Store the overall update type for use later in atomic check. */
	for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
		struct dm_crtc_state *dm_new_crtc_state =
			to_dm_crtc_state(new_crtc_state);

		dm_new_crtc_state->update_type = (int)overall_update_type;
8781 8782 8783 8784 8785 8786 8787 8788
	}

	/* Must be success */
	WARN_ON(ret);
	return ret;

fail:
	if (ret == -EDEADLK)
8789
		DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
8790
	else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
8791
		DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
8792
	else
8793
		DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
8794 8795 8796 8797

	return ret;
}

8798 8799
static bool is_dp_capable_without_timing_msa(struct dc *dc,
					     struct amdgpu_dm_connector *amdgpu_dm_connector)
8800 8801 8802 8803
{
	uint8_t dpcd_data;
	bool capable = false;

8804
	if (amdgpu_dm_connector->dc_link &&
8805 8806
		dm_helpers_dp_read_dpcd(
				NULL,
8807
				amdgpu_dm_connector->dc_link,
8808 8809 8810 8811 8812 8813 8814 8815
				DP_DOWN_STREAM_PORT_COUNT,
				&dpcd_data,
				sizeof(dpcd_data))) {
		capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
	}

	return capable;
}
8816 8817
void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
					struct edid *edid)
8818 8819 8820 8821 8822 8823
{
	int i;
	bool edid_check_required;
	struct detailed_timing *timing;
	struct detailed_non_pixel *data;
	struct detailed_data_monitor_range *range;
8824 8825
	struct amdgpu_dm_connector *amdgpu_dm_connector =
			to_amdgpu_dm_connector(connector);
8826
	struct dm_connector_state *dm_con_state = NULL;
8827 8828 8829

	struct drm_device *dev = connector->dev;
	struct amdgpu_device *adev = dev->dev_private;
8830
	bool freesync_capable = false;
8831

8832 8833
	if (!connector->state) {
		DRM_ERROR("%s - Connector has no state", __func__);
8834
		goto update;
8835 8836
	}

8837 8838 8839 8840 8841 8842 8843
	if (!edid) {
		dm_con_state = to_dm_connector_state(connector->state);

		amdgpu_dm_connector->min_vfreq = 0;
		amdgpu_dm_connector->max_vfreq = 0;
		amdgpu_dm_connector->pixel_clock_mhz = 0;

8844
		goto update;
8845 8846
	}

8847 8848
	dm_con_state = to_dm_connector_state(connector->state);

8849
	edid_check_required = false;
8850
	if (!amdgpu_dm_connector->dc_sink) {
8851
		DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
8852
		goto update;
8853 8854
	}
	if (!adev->dm.freesync_module)
8855
		goto update;
8856 8857 8858 8859
	/*
	 * if edid non zero restrict freesync only for dp and edp
	 */
	if (edid) {
8860 8861
		if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
			|| amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
8862 8863
			edid_check_required = is_dp_capable_without_timing_msa(
						adev->dm.dc,
8864
						amdgpu_dm_connector);
8865 8866 8867 8868 8869 8870 8871 8872 8873 8874 8875 8876 8877 8878 8879 8880 8881 8882 8883 8884 8885 8886 8887
		}
	}
	if (edid_check_required == true && (edid->version > 1 ||
	   (edid->version == 1 && edid->revision > 1))) {
		for (i = 0; i < 4; i++) {

			timing	= &edid->detailed_timings[i];
			data	= &timing->data.other_data;
			range	= &data->data.range;
			/*
			 * Check if monitor has continuous frequency mode
			 */
			if (data->type != EDID_DETAIL_MONITOR_RANGE)
				continue;
			/*
			 * Check for flag range limits only. If flag == 1 then
			 * no additional timing information provided.
			 * Default GTF, GTF Secondary curve and CVT are not
			 * supported
			 */
			if (range->flags != 1)
				continue;

8888 8889 8890
			amdgpu_dm_connector->min_vfreq = range->min_vfreq;
			amdgpu_dm_connector->max_vfreq = range->max_vfreq;
			amdgpu_dm_connector->pixel_clock_mhz =
8891 8892 8893 8894
				range->pixel_clock_mhz * 10;
			break;
		}

8895
		if (amdgpu_dm_connector->max_vfreq -
8896 8897
		    amdgpu_dm_connector->min_vfreq > 10) {

8898
			freesync_capable = true;
8899 8900
		}
	}
8901 8902 8903 8904 8905 8906 8907 8908

update:
	if (dm_con_state)
		dm_con_state->freesync_capable = freesync_capable;

	if (connector->vrr_capable_property)
		drm_connector_set_vrr_capable_property(connector,
						       freesync_capable);
8909 8910
}

R
Roman Li 已提交
8911 8912 8913 8914 8915 8916 8917 8918 8919 8920
static void amdgpu_dm_set_psr_caps(struct dc_link *link)
{
	uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];

	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
		return;
	if (link->type == dc_connection_none)
		return;
	if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
					dpcd_data, sizeof(dpcd_data))) {
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		link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];

		if (dpcd_data[0] == 0) {
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			link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
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			link->psr_settings.psr_feature_enabled = false;
		} else {
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			link->psr_settings.psr_version = DC_PSR_VERSION_1;
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			link->psr_settings.psr_feature_enabled = true;
		}

		DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
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	}
}

/*
 * amdgpu_dm_link_setup_psr() - configure psr link
 * @stream: stream state
 *
 * Return: true if success
 */
static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
{
	struct dc_link *link = NULL;
	struct psr_config psr_config = {0};
	struct psr_context psr_context = {0};
	bool ret = false;

	if (stream == NULL)
		return false;

	link = stream->link;

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	psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
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	if (psr_config.psr_version > 0) {
		psr_config.psr_exit_link_training_required = 0x1;
		psr_config.psr_frame_capture_indication_req = 0;
		psr_config.psr_rfb_setup_time = 0x37;
		psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
		psr_config.allow_smu_optimizations = 0x0;

		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);

	}
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	DRM_DEBUG_DRIVER("PSR link: %d\n",	link->psr_settings.psr_feature_enabled);
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	return ret;
}

/*
 * amdgpu_dm_psr_enable() - enable psr f/w
 * @stream: stream state
 *
 * Return: true if success
 */
bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
{
	struct dc_link *link = stream->link;
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	unsigned int vsync_rate_hz = 0;
	struct dc_static_screen_params params = {0};
	/* Calculate number of static frames before generating interrupt to
	 * enter PSR.
	 */
	// Init fail safe of 2 frames static
	unsigned int num_frames_static = 2;
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	DRM_DEBUG_DRIVER("Enabling psr...\n");

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	vsync_rate_hz = div64_u64(div64_u64((
			stream->timing.pix_clk_100hz * 100),
			stream->timing.v_total),
			stream->timing.h_total);

	/* Round up
	 * Calculate number of frames such that at least 30 ms of time has
	 * passed.
	 */
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	if (vsync_rate_hz != 0) {
		unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
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		num_frames_static = (30000 / frame_time_microsec) + 1;
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	}
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	params.triggers.cursor_update = true;
	params.triggers.overlay_update = true;
	params.triggers.surface_update = true;
	params.num_frames = num_frames_static;
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	dc_stream_set_static_screen_params(link->ctx->dc,
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					   &stream, 1,
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					   &params);
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	return dc_link_set_psr_allow_active(link, true, false);
}

/*
 * amdgpu_dm_psr_disable() - disable psr f/w
 * @stream:  stream state
 *
 * Return: true if success
 */
static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
{

	DRM_DEBUG_DRIVER("Disabling psr...\n");

	return dc_link_set_psr_allow_active(stream->link, false, true);
}