i915_gpu_error.c 43.2 KB
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/*
 * Copyright (c) 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *    Mika Kuoppala <mika.kuoppala@intel.com>
 *
 */

#include <generated/utsrelease.h>
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#include <linux/stop_machine.h>
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#include <linux/zlib.h>
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#include "i915_drv.h"

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static const char *engine_str(int engine)
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{
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	switch (engine) {
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	case RCS: return "render";
	case VCS: return "bsd";
	case BCS: return "blt";
	case VECS: return "vebox";
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	case VCS2: return "bsd2";
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	default: return "";
	}
}

static const char *tiling_flag(int tiling)
{
	switch (tiling) {
	default:
	case I915_TILING_NONE: return "";
	case I915_TILING_X: return " X";
	case I915_TILING_Y: return " Y";
	}
}

static const char *dirty_flag(int dirty)
{
	return dirty ? " dirty" : "";
}

static const char *purgeable_flag(int purgeable)
{
	return purgeable ? " purgeable" : "";
}

static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
{

	if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
		e->err = -ENOSPC;
		return false;
	}

	if (e->bytes == e->size - 1 || e->err)
		return false;

	return true;
}

static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
			      unsigned len)
{
	if (e->pos + len <= e->start) {
		e->pos += len;
		return false;
	}

	/* First vsnprintf needs to fit in its entirety for memmove */
	if (len >= e->size) {
		e->err = -EIO;
		return false;
	}

	return true;
}

static void __i915_error_advance(struct drm_i915_error_state_buf *e,
				 unsigned len)
{
	/* If this is first printf in this window, adjust it so that
	 * start position matches start of the buffer
	 */

	if (e->pos < e->start) {
		const size_t off = e->start - e->pos;

		/* Should not happen but be paranoid */
		if (off > len || e->bytes) {
			e->err = -EIO;
			return;
		}

		memmove(e->buf, e->buf + off, len - off);
		e->bytes = len - off;
		e->pos = e->start;
		return;
	}

	e->bytes += len;
	e->pos += len;
}

static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
			       const char *f, va_list args)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
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		va_list tmp;

		va_copy(tmp, args);
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		len = vsnprintf(NULL, 0, f, tmp);
		va_end(tmp);

		if (!__i915_error_seek(e, len))
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			return;
	}

	len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;

	__i915_error_advance(e, len);
}

static void i915_error_puts(struct drm_i915_error_state_buf *e,
			    const char *str)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	len = strlen(str);

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
		if (!__i915_error_seek(e, len))
			return;
	}

	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;
	memcpy(e->buf + e->bytes, str, len);

	__i915_error_advance(e, len);
}

#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
#define err_puts(e, s) i915_error_puts(e, s)

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#ifdef CONFIG_DRM_I915_COMPRESS_ERROR

static bool compress_init(struct z_stream_s *zstream)
{
	memset(zstream, 0, sizeof(*zstream));

	zstream->workspace =
		kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
			GFP_ATOMIC | __GFP_NOWARN);
	if (!zstream->workspace)
		return false;

	if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
		kfree(zstream->workspace);
		return false;
	}

	return true;
}

static int compress_page(struct z_stream_s *zstream,
			 void *src,
			 struct drm_i915_error_object *dst)
{
	zstream->next_in = src;
	zstream->avail_in = PAGE_SIZE;

	do {
		if (zstream->avail_out == 0) {
			unsigned long page;

			page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
			if (!page)
				return -ENOMEM;

			dst->pages[dst->page_count++] = (void *)page;

			zstream->next_out = (void *)page;
			zstream->avail_out = PAGE_SIZE;
		}

		if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
			return -EIO;
	} while (zstream->avail_in);

	/* Fallback to uncompressed if we increase size? */
	if (0 && zstream->total_out > zstream->total_in)
		return -E2BIG;

	return 0;
}

static void compress_fini(struct z_stream_s *zstream,
			  struct drm_i915_error_object *dst)
{
	if (dst) {
		zlib_deflate(zstream, Z_FINISH);
		dst->unused = zstream->avail_out;
	}

	zlib_deflateEnd(zstream);
	kfree(zstream->workspace);
}

static void err_compression_marker(struct drm_i915_error_state_buf *m)
{
	err_puts(m, ":");
}

#else

static bool compress_init(struct z_stream_s *zstream)
{
	return true;
}

static int compress_page(struct z_stream_s *zstream,
			 void *src,
			 struct drm_i915_error_object *dst)
{
	unsigned long page;

	page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
	if (!page)
		return -ENOMEM;

	dst->pages[dst->page_count++] =
		memcpy((void *)page, src, PAGE_SIZE);

	return 0;
}

static void compress_fini(struct z_stream_s *zstream,
			  struct drm_i915_error_object *dst)
{
}

static void err_compression_marker(struct drm_i915_error_state_buf *m)
{
	err_puts(m, "~");
}

#endif

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static void print_error_buffers(struct drm_i915_error_state_buf *m,
				const char *name,
				struct drm_i915_error_buffer *err,
				int count)
{
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	int i;

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	err_printf(m, "%s [%d]:\n", name, count);
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	while (count--) {
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		err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
			   upper_32_bits(err->gtt_offset),
			   lower_32_bits(err->gtt_offset),
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			   err->size,
			   err->read_domains,
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			   err->write_domain);
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		for (i = 0; i < I915_NUM_ENGINES; i++)
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			err_printf(m, "%02x ", err->rseqno[i]);

		err_printf(m, "] %02x", err->wseqno);
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		err_puts(m, tiling_flag(err->tiling));
		err_puts(m, dirty_flag(err->dirty));
		err_puts(m, purgeable_flag(err->purgeable));
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		err_puts(m, err->userptr ? " userptr" : "");
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		err_puts(m, err->engine != -1 ? " " : "");
		err_puts(m, engine_str(err->engine));
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		err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
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		if (err->name)
			err_printf(m, " (name: %d)", err->name);
		if (err->fence_reg != I915_FENCE_REG_NONE)
			err_printf(m, " (fence: %d)", err->fence_reg);

		err_puts(m, "\n");
		err++;
	}
}

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static void error_print_instdone(struct drm_i915_error_state_buf *m,
				 struct drm_i915_error_engine *ee)
{
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	int slice;
	int subslice;

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	err_printf(m, "  INSTDONE: 0x%08x\n",
		   ee->instdone.instdone);

	if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
		return;

	err_printf(m, "  SC_INSTDONE: 0x%08x\n",
		   ee->instdone.slice_common);

	if (INTEL_GEN(m->i915) <= 6)
		return;

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	for_each_instdone_slice_subslice(m->i915, slice, subslice)
		err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
			   slice, subslice,
			   ee->instdone.sampler[slice][subslice]);

	for_each_instdone_slice_subslice(m->i915, slice, subslice)
		err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
			   slice, subslice,
			   ee->instdone.row[slice][subslice]);
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}

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static void error_print_request(struct drm_i915_error_state_buf *m,
				const char *prefix,
				struct drm_i915_error_request *erq)
{
	if (!erq->seqno)
		return;

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	err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, emitted %dms ago, head %08x, tail %08x\n",
		   prefix, erq->pid, erq->ban_score,
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		   erq->context, erq->seqno,
		   jiffies_to_msecs(jiffies - erq->jiffies),
		   erq->head, erq->tail);
}

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static void error_print_engine(struct drm_i915_error_state_buf *m,
			       struct drm_i915_error_engine *ee)
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{
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	err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
	err_printf(m, "  START: 0x%08x\n", ee->start);
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	err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
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	err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
		   ee->tail, ee->rq_post, ee->rq_tail);
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	err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
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	err_printf(m, "  MODE:  0x%08x\n", ee->mode);
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	err_printf(m, "  HWS:   0x%08x\n", ee->hws);
	err_printf(m, "  ACTHD: 0x%08x %08x\n",
		   (u32)(ee->acthd>>32), (u32)ee->acthd);
	err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
	err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
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	error_print_instdone(m, ee);

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	if (ee->batchbuffer) {
		u64 start = ee->batchbuffer->gtt_offset;
		u64 end = start + ee->batchbuffer->gtt_size;

		err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
			   upper_32_bits(start), lower_32_bits(start),
			   upper_32_bits(end), lower_32_bits(end));
	}
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	if (INTEL_GEN(m->i915) >= 4) {
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		err_printf(m, "  BBADDR: 0x%08x_%08x\n",
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			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
		err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
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	}
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	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
		   lower_32_bits(ee->faddr));
	if (INTEL_GEN(m->i915) >= 6) {
		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
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		err_printf(m, "  SYNC_0: 0x%08x\n",
			   ee->semaphore_mboxes[0]);
		err_printf(m, "  SYNC_1: 0x%08x\n",
			   ee->semaphore_mboxes[1]);
		if (HAS_VEBOX(m->i915))
			err_printf(m, "  SYNC_2: 0x%08x\n",
				   ee->semaphore_mboxes[2]);
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	}
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	if (USES_PPGTT(m->i915)) {
		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
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		if (INTEL_GEN(m->i915) >= 8) {
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			int i;
			for (i = 0; i < 4; i++)
				err_printf(m, "  PDP%d: 0x%016llx\n",
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					   i, ee->vm_info.pdp[i]);
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		} else {
			err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
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				   ee->vm_info.pp_dir_base);
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		}
	}
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	err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
	err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
	err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
	err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
	err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
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	err_printf(m, "  hangcheck stall: %s\n", yesno(ee->hangcheck_stalled));
	err_printf(m, "  hangcheck action: %s\n",
		   hangcheck_action_to_str(ee->hangcheck_action));
	err_printf(m, "  hangcheck action timestamp: %lu, %u ms ago\n",
		   ee->hangcheck_timestamp,
		   jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));

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	error_print_request(m, "  ELSP[0]: ", &ee->execlist[0]);
	error_print_request(m, "  ELSP[1]: ", &ee->execlist[1]);
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}

void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
{
	va_list args;

	va_start(args, f);
	i915_error_vprintf(e, f, args);
	va_end(args);
}

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static int
ascii85_encode_len(int len)
{
	return DIV_ROUND_UP(len, 4);
}

static bool
ascii85_encode(u32 in, char *out)
{
	int i;

	if (in == 0)
		return false;

	out[5] = '\0';
	for (i = 5; i--; ) {
		out[i] = '!' + in % 85;
		in /= 85;
	}

	return true;
}

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static void print_error_obj(struct drm_i915_error_state_buf *m,
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			    struct intel_engine_cs *engine,
			    const char *name,
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			    struct drm_i915_error_object *obj)
{
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	char out[6];
	int page;
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	if (!obj)
		return;

	if (name) {
		err_printf(m, "%s --- %s = 0x%08x %08x\n",
			   engine ? engine->name : "global", name,
			   upper_32_bits(obj->gtt_offset),
			   lower_32_bits(obj->gtt_offset));
	}

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	err_compression_marker(m);
	for (page = 0; page < obj->page_count; page++) {
		int i, len;

		len = PAGE_SIZE;
		if (page == obj->page_count - 1)
			len -= obj->unused;
		len = ascii85_encode_len(len);

		for (i = 0; i < len; i++) {
			if (ascii85_encode(obj->pages[page][i], out))
				err_puts(m, out);
			else
				err_puts(m, "z");
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		}
	}
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	err_puts(m, "\n");
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}

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static void err_print_capabilities(struct drm_i915_error_state_buf *m,
				   const struct intel_device_info *info)
{
#define PRINT_FLAG(x)  err_printf(m, #x ": %s\n", yesno(info->x))
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	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
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#undef PRINT_FLAG
}

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int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
			    const struct i915_error_state_file_priv *error_priv)
{
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	struct drm_i915_private *dev_priv = to_i915(error_priv->dev);
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David Weinehall 已提交
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	struct pci_dev *pdev = dev_priv->drm.pdev;
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	struct drm_i915_error_state *error = error_priv->error;
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	struct drm_i915_error_object *obj;
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	int i, j;
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	if (!error) {
		err_printf(m, "no error state collected\n");
		goto out;
	}

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	err_printf(m, "%s\n", error->error_msg);
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	err_printf(m, "Kernel: " UTS_RELEASE "\n");
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	err_printf(m, "Time: %ld s %ld us\n",
		   error->time.tv_sec, error->time.tv_usec);
	err_printf(m, "Boottime: %ld s %ld us\n",
		   error->boottime.tv_sec, error->boottime.tv_usec);
	err_printf(m, "Uptime: %ld s %ld us\n",
		   error->uptime.tv_sec, error->uptime.tv_usec);
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	err_print_capabilities(m, &error->device_info);
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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
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		if (error->engine[i].hangcheck_stalled &&
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		    error->engine[i].pid != -1) {
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			err_printf(m, "Active process (on ring %s): %s [%d], context bans %d\n",
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				   engine_str(i),
				   error->engine[i].comm,
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				   error->engine[i].pid,
				   error->engine[i].context_bans);
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		}
	}
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	err_printf(m, "Reset count: %u\n", error->reset_count);
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	err_printf(m, "Suspend count: %u\n", error->suspend_count);
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David Weinehall 已提交
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	err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
	err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
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	err_printf(m, "PCI Subsystem: %04x:%04x\n",
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David Weinehall 已提交
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		   pdev->subsystem_vendor,
		   pdev->subsystem_device);
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	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
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	if (HAS_CSR(dev_priv)) {
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		struct intel_csr *csr = &dev_priv->csr;

		err_printf(m, "DMC loaded: %s\n",
			   yesno(csr->dmc_payload != NULL));
		err_printf(m, "DMC fw version: %d.%d\n",
			   CSR_VERSION_MAJOR(csr->version),
			   CSR_VERSION_MINOR(csr->version));
	}

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	err_printf(m, "EIR: 0x%08x\n", error->eir);
	err_printf(m, "IER: 0x%08x\n", error->ier);
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	if (INTEL_GEN(dev_priv) >= 8) {
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		for (i = 0; i < 4; i++)
			err_printf(m, "GTIER gt %d: 0x%08x\n", i,
				   error->gtier[i]);
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	} else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv))
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		err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
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	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
	err_printf(m, "CCID: 0x%08x\n", error->ccid);
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	err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
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	for (i = 0; i < dev_priv->num_fence_regs; i++)
		err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);

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	if (INTEL_GEN(dev_priv) >= 6) {
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		err_printf(m, "ERROR: 0x%08x\n", error->error);
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		if (INTEL_GEN(dev_priv) >= 8)
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			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
				   error->fault_data1, error->fault_data0);

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		err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
	}

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	if (IS_GEN7(dev_priv))
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		err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);

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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].engine_id != -1)
			error_print_engine(m, &error->engine[i]);
	}
601

602 603 604
	for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
		char buf[128];
		int len, first = 1;
605

606 607 608 609 610 611 612 613 614 615
		if (!error->active_vm[i])
			break;

		len = scnprintf(buf, sizeof(buf), "Active (");
		for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
			if (error->engine[j].vm != error->active_vm[i])
				continue;

			len += scnprintf(buf + len, sizeof(buf), "%s%s",
					 first ? "" : ", ",
616
					 dev_priv->engine[j]->name);
617 618 619 620
			first = 0;
		}
		scnprintf(buf + len, sizeof(buf), ")");
		print_error_buffers(m, buf,
621 622 623
				    error->active_bo[i],
				    error->active_bo_count[i]);
	}
624

625 626 627 628
	print_error_buffers(m, "Pinned (global)",
			    error->pinned_bo,
			    error->pinned_bo_count);

629 630 631 632
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];

		obj = ee->batchbuffer;
633
		if (obj) {
634
			err_puts(m, dev_priv->engine[i]->name);
635
			if (ee->pid != -1)
636
				err_printf(m, " (submitted by %s [%d], bans %d)",
637
					   ee->comm,
638 639
					   ee->pid,
					   ee->context_bans);
640 641 642
			err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
				   upper_32_bits(obj->gtt_offset),
				   lower_32_bits(obj->gtt_offset));
643
			print_error_obj(m, dev_priv->engine[i], NULL, obj);
644 645
		}

646
		if (ee->num_requests) {
647
			err_printf(m, "%s --- %d requests\n",
648
				   dev_priv->engine[i]->name,
649
				   ee->num_requests);
650 651
			for (j = 0; j < ee->num_requests; j++)
				error_print_request(m, " ", &ee->requests[j]);
652 653
		}

654 655
		if (IS_ERR(ee->waiters)) {
			err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
656
				   dev_priv->engine[i]->name);
657
		} else if (ee->num_waiters) {
658
			err_printf(m, "%s --- %d waiters\n",
659
				   dev_priv->engine[i]->name,
660 661
				   ee->num_waiters);
			for (j = 0; j < ee->num_waiters; j++) {
662
				err_printf(m, " seqno 0x%08x for %s [%d]\n",
663 664 665
					   ee->waiters[j].seqno,
					   ee->waiters[j].comm,
					   ee->waiters[j].pid);
666 667 668
			}
		}

669
		print_error_obj(m, dev_priv->engine[i],
670
				"ringbuffer", ee->ringbuffer);
671

672
		print_error_obj(m, dev_priv->engine[i],
673
				"HW Status", ee->hws_page);
674

675
		print_error_obj(m, dev_priv->engine[i],
676
				"HW context", ee->ctx);
677

678
		print_error_obj(m, dev_priv->engine[i],
679
				"WA context", ee->wa_ctx);
680

681
		print_error_obj(m, dev_priv->engine[i],
682
				"WA batchbuffer", ee->wa_batchbuffer);
683 684
	}

685
	print_error_obj(m, NULL, "Semaphores", error->semaphore);
686

687 688
	print_error_obj(m, NULL, "GuC log buffer", error->guc_log);

689 690 691 692
	if (error->overlay)
		intel_overlay_print_error_state(m, error->overlay);

	if (error->display)
693
		intel_display_print_error_state(m, dev_priv, error->display);
694 695 696 697 698 699 700 701 702

out:
	if (m->bytes == 0 && m->err)
		return m->err;

	return 0;
}

int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
703
			      struct drm_i915_private *i915,
704 705 706
			      size_t count, loff_t pos)
{
	memset(ebuf, 0, sizeof(*ebuf));
707
	ebuf->i915 = i915;
708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741

	/* We need to have enough room to store any i915_error_state printf
	 * so that we can move it to start position.
	 */
	ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
	ebuf->buf = kmalloc(ebuf->size,
				GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);

	if (ebuf->buf == NULL) {
		ebuf->size = PAGE_SIZE;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL) {
		ebuf->size = 128;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL)
		return -ENOMEM;

	ebuf->start = pos;

	return 0;
}

static void i915_error_object_free(struct drm_i915_error_object *obj)
{
	int page;

	if (obj == NULL)
		return;

	for (page = 0; page < obj->page_count; page++)
742
		free_page((unsigned long)obj->pages[page]);
743 744 745 746 747 748 749 750 751 752

	kfree(obj);
}

static void i915_error_state_free(struct kref *error_ref)
{
	struct drm_i915_error_state *error = container_of(error_ref,
							  typeof(*error), ref);
	int i;

753 754 755 756 757 758 759 760 761 762 763
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];

		i915_error_object_free(ee->batchbuffer);
		i915_error_object_free(ee->wa_batchbuffer);
		i915_error_object_free(ee->ringbuffer);
		i915_error_object_free(ee->hws_page);
		i915_error_object_free(ee->ctx);
		i915_error_object_free(ee->wa_ctx);

		kfree(ee->requests);
764 765
		if (!IS_ERR_OR_NULL(ee->waiters))
			kfree(ee->waiters);
766 767
	}

768
	i915_error_object_free(error->semaphore);
769
	i915_error_object_free(error->guc_log);
770

771
	for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
772 773
		kfree(error->active_bo[i]);
	kfree(error->pinned_bo);
774

775 776 777 778 779 780
	kfree(error->overlay);
	kfree(error->display);
	kfree(error);
}

static struct drm_i915_error_object *
781
i915_error_object_create(struct drm_i915_private *i915,
C
Chris Wilson 已提交
782
			 struct i915_vma *vma)
783
{
784 785
	struct i915_ggtt *ggtt = &i915->ggtt;
	const u64 slot = ggtt->error_capture.start;
786
	struct drm_i915_error_object *dst;
787
	struct z_stream_s zstream;
788 789 790
	unsigned long num_pages;
	struct sgt_iter iter;
	dma_addr_t dma;
791

C
Chris Wilson 已提交
792 793 794
	if (!vma)
		return NULL;

795
	num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
796
	num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
797 798
	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
		      GFP_ATOMIC | __GFP_NOWARN);
C
Chris Wilson 已提交
799
	if (!dst)
800 801
		return NULL;

802 803
	dst->gtt_offset = vma->node.start;
	dst->gtt_size = vma->node.size;
804
	dst->page_count = 0;
805 806 807 808 809 810
	dst->unused = 0;

	if (!compress_init(&zstream)) {
		kfree(dst);
		return NULL;
	}
811

812 813 814
	for_each_sgt_dma(dma, iter, vma->pages) {
		void __iomem *s;
		int ret;
815

816 817
		ggtt->base.insert_page(&ggtt->base, dma, slot,
				       I915_CACHE_NONE, 0);
818

819
		s = io_mapping_map_atomic_wc(&ggtt->mappable, slot);
820
		ret = compress_page(&zstream, (void  __force *)s, dst);
821
		io_mapping_unmap_atomic(s);
822

823
		if (ret)
824 825
			goto unwind;
	}
826
	goto out;
827 828

unwind:
829 830
	while (dst->page_count--)
		free_page((unsigned long)dst->pages[dst->page_count]);
831
	kfree(dst);
832 833 834
	dst = NULL;

out:
835
	compress_fini(&zstream, dst);
836
	ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE);
837
	return dst;
838 839
}

840 841 842 843 844 845
/* The error capture is special as tries to run underneath the normal
 * locking rules - so we use the raw version of the i915_gem_active lookup.
 */
static inline uint32_t
__active_get_seqno(struct i915_gem_active *active)
{
846 847 848 849
	struct drm_i915_gem_request *request;

	request = __i915_gem_active_peek(active);
	return request ? request->global_seqno : 0;
850 851 852 853 854
}

static inline int
__active_get_engine_id(struct i915_gem_active *active)
{
855
	struct drm_i915_gem_request *request;
856

857 858
	request = __i915_gem_active_peek(active);
	return request ? request->engine->id : -1;
859 860
}

861
static void capture_bo(struct drm_i915_error_buffer *err,
862
		       struct i915_vma *vma)
863
{
864
	struct drm_i915_gem_object *obj = vma->obj;
865
	int i;
866

867 868
	err->size = obj->base.size;
	err->name = obj->base.name;
869

870
	for (i = 0; i < I915_NUM_ENGINES; i++)
871
		err->rseqno[i] = __active_get_seqno(&vma->last_read[i]);
872 873
	err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
	err->engine = __active_get_engine_id(&obj->frontbuffer_write);
874

875
	err->gtt_offset = vma->node.start;
876 877
	err->read_domains = obj->base.read_domains;
	err->write_domain = obj->base.write_domain;
878
	err->fence_reg = vma->fence ? vma->fence->id : -1;
879
	err->tiling = i915_gem_object_get_tiling(obj);
C
Chris Wilson 已提交
880 881
	err->dirty = obj->mm.dirty;
	err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
882
	err->userptr = obj->userptr.mm != NULL;
883 884 885
	err->cache_level = obj->cache_level;
}

886 887 888
static u32 capture_error_bo(struct drm_i915_error_buffer *err,
			    int count, struct list_head *head,
			    bool pinned_only)
889
{
B
Ben Widawsky 已提交
890
	struct i915_vma *vma;
891 892
	int i = 0;

893
	list_for_each_entry(vma, head, vm_link) {
894 895 896
		if (pinned_only && !i915_vma_is_pinned(vma))
			continue;

897
		capture_bo(err++, vma);
898 899 900 901 902 903 904
		if (++i == count)
			break;
	}

	return i;
}

905 906 907 908 909 910 911 912 913 914
/* Generate a semi-unique error code. The code is not meant to have meaning, The
 * code's only purpose is to try to prevent false duplicated bug reports by
 * grossly estimating a GPU error state.
 *
 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
 * the hang if we could strip the GTT offset information from it.
 *
 * It's only a small step better than a random number in its current form.
 */
static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
915
					 struct drm_i915_error_state *error,
916
					 int *engine_id)
917 918 919 920 921 922 923 924 925
{
	uint32_t error_code = 0;
	int i;

	/* IPEHR would be an ideal way to detect errors, as it's the gross
	 * measure of "the command that hung." However, has some very common
	 * synchronization commands which almost always appear in the case
	 * strictly a client bug. Use instdone to differentiate those some.
	 */
926
	for (i = 0; i < I915_NUM_ENGINES; i++) {
927
		if (error->engine[i].hangcheck_stalled) {
928 929
			if (engine_id)
				*engine_id = i;
930

931 932
			return error->engine[i].ipehr ^
			       error->engine[i].instdone.instdone;
933 934
		}
	}
935 936 937 938

	return error_code;
}

939
static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
940 941 942 943
				   struct drm_i915_error_state *error)
{
	int i;

944
	if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
945
		for (i = 0; i < dev_priv->num_fence_regs; i++)
946
			error->fence[i] = I915_READ(FENCE_REG(i));
947
	} else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
948 949
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
950
	} else if (INTEL_GEN(dev_priv) >= 6) {
951 952 953
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
	}
954 955
}

956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975
static inline u32
gen8_engine_sync_index(struct intel_engine_cs *engine,
		       struct intel_engine_cs *other)
{
	int idx;

	/*
	 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
	 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
	 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
	 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
	 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
	 */

	idx = (other - engine) - 1;
	if (idx < 0)
		idx += I915_NUM_ENGINES;

	return idx;
}
976

977
static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
978
					struct intel_engine_cs *engine,
979
					struct drm_i915_error_engine *ee)
980
{
981
	struct drm_i915_private *dev_priv = engine->i915;
982
	struct intel_engine_cs *to;
983
	enum intel_engine_id id;
984

985
	if (!error->semaphore)
986
		return;
987

988
	for_each_engine(to, dev_priv, id) {
989 990 991
		int idx;
		u16 signal_offset;
		u32 *tmp;
992

993
		if (engine == to)
994 995
			continue;

996 997
		signal_offset =
			(GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
998
		tmp = error->semaphore->pages[0];
999
		idx = gen8_engine_sync_index(engine, to);
1000

1001
		ee->semaphore_mboxes[idx] = tmp[signal_offset];
1002 1003 1004
	}
}

1005 1006
static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
					struct drm_i915_error_engine *ee)
1007
{
1008 1009 1010 1011
	struct drm_i915_private *dev_priv = engine->i915;

	ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
	ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1012
	if (HAS_VEBOX(dev_priv))
1013
		ee->semaphore_mboxes[2] =
1014
			I915_READ(RING_SYNC_2(engine->mmio_base));
1015 1016
}

1017 1018
static void error_record_engine_waiters(struct intel_engine_cs *engine,
					struct drm_i915_error_engine *ee)
1019 1020 1021 1022 1023 1024
{
	struct intel_breadcrumbs *b = &engine->breadcrumbs;
	struct drm_i915_error_waiter *waiter;
	struct rb_node *rb;
	int count;

1025 1026
	ee->num_waiters = 0;
	ee->waiters = NULL;
1027

1028 1029 1030
	if (RB_EMPTY_ROOT(&b->waiters))
		return;

1031
	if (!spin_trylock_irq(&b->lock)) {
1032 1033 1034 1035
		ee->waiters = ERR_PTR(-EDEADLK);
		return;
	}

1036 1037 1038
	count = 0;
	for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
		count++;
1039
	spin_unlock_irq(&b->lock);
1040 1041 1042 1043 1044 1045 1046 1047 1048

	waiter = NULL;
	if (count)
		waiter = kmalloc_array(count,
				       sizeof(struct drm_i915_error_waiter),
				       GFP_ATOMIC);
	if (!waiter)
		return;

1049
	if (!spin_trylock_irq(&b->lock)) {
1050 1051 1052 1053
		kfree(waiter);
		ee->waiters = ERR_PTR(-EDEADLK);
		return;
	}
1054

1055
	ee->waiters = waiter;
1056 1057 1058 1059 1060 1061 1062 1063
	for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
		struct intel_wait *w = container_of(rb, typeof(*w), node);

		strcpy(waiter->comm, w->tsk->comm);
		waiter->pid = w->tsk->pid;
		waiter->seqno = w->seqno;
		waiter++;

1064
		if (++ee->num_waiters == count)
1065 1066
			break;
	}
1067
	spin_unlock_irq(&b->lock);
1068 1069
}

1070 1071 1072
static void error_record_engine_registers(struct drm_i915_error_state *error,
					  struct intel_engine_cs *engine,
					  struct drm_i915_error_engine *ee)
1073
{
1074 1075
	struct drm_i915_private *dev_priv = engine->i915;

1076
	if (INTEL_GEN(dev_priv) >= 6) {
1077 1078
		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
		ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1079
		if (INTEL_GEN(dev_priv) >= 8)
1080
			gen8_record_semaphore_state(error, engine, ee);
1081
		else
1082
			gen6_record_semaphore_state(engine, ee);
1083 1084
	}

1085
	if (INTEL_GEN(dev_priv) >= 4) {
1086 1087 1088 1089 1090
		ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
		ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
		ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
		ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
		ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1091
		if (INTEL_GEN(dev_priv) >= 8) {
1092 1093
			ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
			ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1094
		}
1095
		ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1096
	} else {
1097 1098 1099
		ee->faddr = I915_READ(DMA_FADD_I8XX);
		ee->ipeir = I915_READ(IPEIR);
		ee->ipehr = I915_READ(IPEHR);
1100 1101
	}

1102
	intel_engine_get_instdone(engine, &ee->instdone);
1103

1104 1105
	ee->waiting = intel_engine_has_waiter(engine);
	ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1106
	ee->acthd = intel_engine_get_active_head(engine);
1107
	ee->seqno = intel_engine_get_seqno(engine);
1108
	ee->last_seqno = intel_engine_last_submit(engine);
1109 1110 1111 1112
	ee->start = I915_READ_START(engine);
	ee->head = I915_READ_HEAD(engine);
	ee->tail = I915_READ_TAIL(engine);
	ee->ctl = I915_READ_CTL(engine);
1113 1114
	if (INTEL_GEN(dev_priv) > 2)
		ee->mode = I915_READ_MODE(engine);
1115

1116
	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1117
		i915_reg_t mmio;
1118

1119
		if (IS_GEN7(dev_priv)) {
1120
			switch (engine->id) {
1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134
			default:
			case RCS:
				mmio = RENDER_HWS_PGA_GEN7;
				break;
			case BCS:
				mmio = BLT_HWS_PGA_GEN7;
				break;
			case VCS:
				mmio = BSD_HWS_PGA_GEN7;
				break;
			case VECS:
				mmio = VEBOX_HWS_PGA_GEN7;
				break;
			}
1135
		} else if (IS_GEN6(engine->i915)) {
1136
			mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1137 1138
		} else {
			/* XXX: gen8 returns to sanity */
1139
			mmio = RING_HWS_PGA(engine->mmio_base);
1140 1141
		}

1142
		ee->hws = I915_READ(mmio);
1143 1144
	}

1145
	ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1146
	ee->hangcheck_action = engine->hangcheck.action;
1147
	ee->hangcheck_stalled = engine->hangcheck.stalled;
1148

1149
	if (USES_PPGTT(dev_priv)) {
1150 1151
		int i;

1152
		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1153

1154
		if (IS_GEN6(dev_priv))
1155
			ee->vm_info.pp_dir_base =
1156
				I915_READ(RING_PP_DIR_BASE_READ(engine));
1157
		else if (IS_GEN7(dev_priv))
1158
			ee->vm_info.pp_dir_base =
1159
				I915_READ(RING_PP_DIR_BASE(engine));
1160
		else if (INTEL_GEN(dev_priv) >= 8)
1161
			for (i = 0; i < 4; i++) {
1162
				ee->vm_info.pdp[i] =
1163
					I915_READ(GEN8_RING_PDP_UDW(engine, i));
1164 1165
				ee->vm_info.pdp[i] <<= 32;
				ee->vm_info.pdp[i] |=
1166
					I915_READ(GEN8_RING_PDP_LDW(engine, i));
1167 1168
			}
	}
1169 1170
}

1171 1172 1173 1174
static void record_request(struct drm_i915_gem_request *request,
			   struct drm_i915_error_request *erq)
{
	erq->context = request->ctx->hw_id;
1175
	erq->ban_score = request->ctx->ban_score;
1176
	erq->seqno = request->global_seqno;
1177 1178 1179 1180 1181 1182 1183 1184 1185
	erq->jiffies = request->emitted_jiffies;
	erq->head = request->head;
	erq->tail = request->tail;

	rcu_read_lock();
	erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
	rcu_read_unlock();
}

1186 1187 1188 1189 1190 1191 1192 1193 1194
static void engine_record_requests(struct intel_engine_cs *engine,
				   struct drm_i915_gem_request *first,
				   struct drm_i915_error_engine *ee)
{
	struct drm_i915_gem_request *request;
	int count;

	count = 0;
	request = first;
1195
	list_for_each_entry_from(request, &engine->timeline->requests, link)
1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207
		count++;
	if (!count)
		return;

	ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
	if (!ee->requests)
		return;

	ee->num_requests = count;

	count = 0;
	request = first;
1208
	list_for_each_entry_from(request, &engine->timeline->requests, link) {
1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227
		if (count >= ee->num_requests) {
			/*
			 * If the ring request list was changed in
			 * between the point where the error request
			 * list was created and dimensioned and this
			 * point then just exit early to avoid crashes.
			 *
			 * We don't need to communicate that the
			 * request list changed state during error
			 * state capture and that the error state is
			 * slightly incorrect as a consequence since we
			 * are typically only interested in the request
			 * list state at the point of error state
			 * capture, not in any changes happening during
			 * the capture.
			 */
			break;
		}

1228
		record_request(request, &ee->requests[count++]);
1229 1230 1231 1232
	}
	ee->num_requests = count;
}

1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243
static void error_record_engine_execlists(struct intel_engine_cs *engine,
					  struct drm_i915_error_engine *ee)
{
	unsigned int n;

	for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
		if (engine->execlist_port[n].request)
			record_request(engine->execlist_port[n].request,
				       &ee->execlist[n]);
}

1244
static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
1245 1246
				  struct drm_i915_error_state *error)
{
1247
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
1248
	int i;
1249

1250
	error->semaphore =
C
Chris Wilson 已提交
1251
		i915_error_object_create(dev_priv, dev_priv->semaphore);
1252

1253
	for (i = 0; i < I915_NUM_ENGINES; i++) {
1254
		struct intel_engine_cs *engine = dev_priv->engine[i];
1255
		struct drm_i915_error_engine *ee = &error->engine[i];
1256
		struct drm_i915_gem_request *request;
1257

1258 1259
		ee->pid = -1;
		ee->engine_id = -1;
1260

1261
		if (!engine)
1262 1263
			continue;

1264
		ee->engine_id = i;
1265

1266 1267
		error_record_engine_registers(error, engine, ee);
		error_record_engine_waiters(engine, ee);
1268
		error_record_engine_execlists(engine, ee);
1269

1270
		request = i915_gem_find_active_request(engine);
1271
		if (request) {
1272
			struct intel_ring *ring;
1273
			struct pid *pid;
1274

1275
			ee->vm = request->ctx->ppgtt ?
1276
				&request->ctx->ppgtt->base : &ggtt->base;
1277

1278 1279 1280 1281
			/* We need to copy these to an anonymous buffer
			 * as the simplest method to avoid being overwritten
			 * by userspace.
			 */
1282
			ee->batchbuffer =
1283
				i915_error_object_create(dev_priv,
C
Chris Wilson 已提交
1284
							 request->batch);
1285

1286
			if (HAS_BROKEN_CS_TLB(dev_priv))
1287
				ee->wa_batchbuffer =
C
Chris Wilson 已提交
1288 1289
					i915_error_object_create(dev_priv,
								 engine->scratch);
1290

C
Chris Wilson 已提交
1291 1292 1293
			ee->ctx =
				i915_error_object_create(dev_priv,
							 request->ctx->engine[i].state);
1294

1295 1296
			pid = request->ctx->pid;
			if (pid) {
1297 1298 1299
				struct task_struct *task;

				rcu_read_lock();
1300
				task = pid_task(pid, PIDTYPE_PID);
1301
				if (task) {
1302 1303
					strcpy(ee->comm, task->comm);
					ee->pid = task->pid;
1304 1305 1306
				}
				rcu_read_unlock();
			}
1307

1308 1309 1310
			error->simulated |=
				request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;

1311 1312 1313 1314
			ee->rq_head = request->head;
			ee->rq_post = request->postfix;
			ee->rq_tail = request->tail;

1315 1316 1317
			ring = request->ring;
			ee->cpu_ring_head = ring->head;
			ee->cpu_ring_tail = ring->tail;
1318
			ee->ringbuffer =
C
Chris Wilson 已提交
1319
				i915_error_object_create(dev_priv, ring->vma);
1320 1321

			engine_record_requests(engine, request, ee);
1322
		}
1323

1324
		ee->hws_page =
C
Chris Wilson 已提交
1325 1326
			i915_error_object_create(dev_priv,
						 engine->status_page.vma);
1327

C
Chris Wilson 已提交
1328 1329
		ee->wa_ctx =
			i915_error_object_create(dev_priv, engine->wa_ctx.vma);
1330 1331 1332
	}
}

1333 1334 1335
static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
				struct drm_i915_error_state *error,
				struct i915_address_space *vm,
1336
				int idx)
1337
{
1338
	struct drm_i915_error_buffer *active_bo;
1339
	struct i915_vma *vma;
1340
	int count;
1341

1342
	count = 0;
1343
	list_for_each_entry(vma, &vm->active_list, vm_link)
1344
		count++;
1345

1346 1347 1348
	active_bo = NULL;
	if (count)
		active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1349
	if (active_bo)
1350 1351 1352 1353 1354 1355 1356
		count = capture_error_bo(active_bo, count, &vm->active_list, false);
	else
		count = 0;

	error->active_vm[idx] = vm;
	error->active_bo[idx] = active_bo;
	error->active_bo_count[idx] = count;
1357 1358
}

1359 1360
static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
					struct drm_i915_error_state *error)
1361
{
1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374
	int cnt = 0, i, j;

	BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
	BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
	BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));

	/* Scan each engine looking for unique active contexts/vm */
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];
		bool found;

		if (!ee->vm)
			continue;
1375

1376 1377 1378 1379 1380
		found = false;
		for (j = 0; j < i && !found; j++)
			found = error->engine[j].vm == ee->vm;
		if (!found)
			i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
1381
	}
1382 1383
}

1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414
static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
					struct drm_i915_error_state *error)
{
	struct i915_address_space *vm = &dev_priv->ggtt.base;
	struct drm_i915_error_buffer *bo;
	struct i915_vma *vma;
	int count_inactive, count_active;

	count_inactive = 0;
	list_for_each_entry(vma, &vm->active_list, vm_link)
		count_inactive++;

	count_active = 0;
	list_for_each_entry(vma, &vm->inactive_list, vm_link)
		count_active++;

	bo = NULL;
	if (count_inactive + count_active)
		bo = kcalloc(count_inactive + count_active,
			     sizeof(*bo), GFP_ATOMIC);
	if (!bo)
		return;

	count_inactive = capture_error_bo(bo, count_inactive,
					  &vm->active_list, true);
	count_active = capture_error_bo(bo + count_inactive, count_active,
					&vm->inactive_list, true);
	error->pinned_bo_count = count_inactive + count_active;
	error->pinned_bo = bo;
}

1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425
static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv,
					    struct drm_i915_error_state *error)
{
	/* Capturing log buf contents won't be useful if logging was disabled */
	if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0))
		return;

	error->guc_log = i915_error_object_create(dev_priv,
						  dev_priv->guc.log.vma);
}

1426 1427 1428
/* Capture all registers which don't fit into another category. */
static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
1429
{
1430
	int i;
1431

1432 1433 1434 1435 1436 1437 1438
	/* General organization
	 * 1. Registers specific to a single generation
	 * 2. Registers which belong to multiple generations
	 * 3. Feature specific registers.
	 * 4. Everything else
	 * Please try to follow the order.
	 */
1439

1440
	/* 1: Registers specific to a single generation */
1441
	if (IS_VALLEYVIEW(dev_priv)) {
1442
		error->gtier[0] = I915_READ(GTIER);
1443
		error->ier = I915_READ(VLV_IER);
1444
		error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1445
	}
1446

1447
	if (IS_GEN7(dev_priv))
1448
		error->err_int = I915_READ(GEN7_ERR_INT);
1449

1450
	if (INTEL_GEN(dev_priv) >= 8) {
1451 1452 1453 1454
		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
	}

1455
	if (IS_GEN6(dev_priv)) {
1456
		error->forcewake = I915_READ_FW(FORCEWAKE);
1457 1458 1459
		error->gab_ctl = I915_READ(GAB_CTL);
		error->gfx_mode = I915_READ(GFX_MODE);
	}
1460

1461
	/* 2: Registers which belong to multiple generations */
1462
	if (INTEL_GEN(dev_priv) >= 7)
1463
		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1464

1465
	if (INTEL_GEN(dev_priv) >= 6) {
1466
		error->derrmr = I915_READ(DERRMR);
1467 1468 1469 1470
		error->error = I915_READ(ERROR_GEN6);
		error->done_reg = I915_READ(DONE_REG);
	}

1471
	/* 3: Feature specific registers */
1472
	if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1473 1474 1475 1476 1477
		error->gam_ecochk = I915_READ(GAM_ECOCHK);
		error->gac_eco = I915_READ(GAC_ECO_BITS);
	}

	/* 4: Everything else */
1478
	if (HAS_HW_CONTEXTS(dev_priv))
1479 1480
		error->ccid = I915_READ(CCID);

1481
	if (INTEL_GEN(dev_priv) >= 8) {
1482 1483 1484
		error->ier = I915_READ(GEN8_DE_MISC_IER);
		for (i = 0; i < 4; i++)
			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1485
	} else if (HAS_PCH_SPLIT(dev_priv)) {
1486
		error->ier = I915_READ(DEIER);
1487
		error->gtier[0] = I915_READ(GTIER);
1488
	} else if (IS_GEN2(dev_priv)) {
1489
		error->ier = I915_READ16(IER);
1490
	} else if (!IS_VALLEYVIEW(dev_priv)) {
1491
		error->ier = I915_READ(IER);
1492 1493 1494
	}
	error->eir = I915_READ(EIR);
	error->pgtbl_er = I915_READ(PGTBL_ER);
1495 1496
}

1497
static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1498
				   struct drm_i915_error_state *error,
1499
				   u32 engine_mask,
1500
				   const char *error_msg)
1501 1502
{
	u32 ecode;
1503
	int engine_id = -1, len;
1504

1505
	ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1506

1507
	len = scnprintf(error->error_msg, sizeof(error->error_msg),
1508
			"GPU HANG: ecode %d:%d:0x%08x",
1509
			INTEL_GEN(dev_priv), engine_id, ecode);
1510

1511
	if (engine_id != -1 && error->engine[engine_id].pid != -1)
1512 1513 1514
		len += scnprintf(error->error_msg + len,
				 sizeof(error->error_msg) - len,
				 ", in %s [%d]",
1515 1516
				 error->engine[engine_id].comm,
				 error->engine[engine_id].pid);
1517 1518 1519 1520

	scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
		  ", reason: %s, action: %s",
		  error_msg,
1521
		  engine_mask ? "reset" : "continue");
1522 1523
}

1524 1525 1526
static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
{
1527 1528 1529 1530
	error->iommu = -1;
#ifdef CONFIG_INTEL_IOMMU
	error->iommu = intel_iommu_gfx_mapped;
#endif
1531
	error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1532
	error->suspend_count = dev_priv->suspend_count;
1533 1534 1535 1536

	memcpy(&error->device_info,
	       INTEL_INFO(dev_priv),
	       sizeof(error->device_info));
1537 1538
}

1539 1540 1541 1542 1543 1544 1545 1546 1547 1548
static int capture(void *data)
{
	struct drm_i915_error_state *error = data;

	i915_capture_gen_state(error->i915, error);
	i915_capture_reg_state(error->i915, error);
	i915_gem_record_fences(error->i915, error);
	i915_gem_record_rings(error->i915, error);
	i915_capture_active_buffers(error->i915, error);
	i915_capture_pinned_buffers(error->i915, error);
1549
	i915_gem_capture_guc_log_buffer(error->i915, error);
1550 1551

	do_gettimeofday(&error->time);
1552 1553 1554 1555
	error->boottime = ktime_to_timeval(ktime_get_boottime());
	error->uptime =
		ktime_to_timeval(ktime_sub(ktime_get(),
					   error->i915->gt.last_init_time));
1556 1557 1558 1559 1560 1561 1562

	error->overlay = intel_overlay_capture_error_state(error->i915);
	error->display = intel_display_capture_error_state(error->i915);

	return 0;
}

1563 1564
#define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))

1565 1566 1567 1568 1569 1570 1571 1572 1573
/**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
 *
 * Should be called when an error is detected (either a hang or an error
 * interrupt) to capture error state from the time of the error.  Fills
 * out a structure which becomes available in debugfs for user level tools
 * to pick up.
 */
1574 1575
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
1576
			      const char *error_msg)
1577
{
1578
	static bool warned;
1579 1580 1581
	struct drm_i915_error_state *error;
	unsigned long flags;

1582 1583 1584
	if (!i915.error_capture)
		return;

1585 1586 1587
	if (READ_ONCE(dev_priv->gpu_error.first_error))
		return;

1588 1589 1590 1591 1592 1593 1594
	/* Account for pipe specific data like PIPE*STAT */
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
	if (!error) {
		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		return;
	}

1595
	kref_init(&error->ref);
1596
	error->i915 = dev_priv;
1597

1598
	stop_machine(capture, error, NULL);
1599

1600
	i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
1601 1602
	DRM_INFO("%s\n", error->error_msg);

1603 1604 1605 1606 1607 1608 1609
	if (!error->simulated) {
		spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
		if (!dev_priv->gpu_error.first_error) {
			dev_priv->gpu_error.first_error = error;
			error = NULL;
		}
		spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1610 1611
	}

1612
	if (error) {
1613
		i915_error_state_free(&error->ref);
1614 1615 1616
		return;
	}

1617 1618
	if (!warned &&
	    ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1619 1620 1621 1622
		DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
		DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
		DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
		DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1623 1624
		DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
			 dev_priv->drm.primary->index);
1625 1626
		warned = true;
	}
1627 1628 1629 1630 1631
}

void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv)
{
1632
	struct drm_i915_private *dev_priv = to_i915(dev);
1633

1634
	spin_lock_irq(&dev_priv->gpu_error.lock);
1635 1636 1637
	error_priv->error = dev_priv->gpu_error.first_error;
	if (error_priv->error)
		kref_get(&error_priv->error->ref);
1638
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1639 1640 1641 1642 1643 1644 1645 1646 1647 1648
}

void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
{
	if (error_priv->error)
		kref_put(&error_priv->error->ref, i915_error_state_free);
}

void i915_destroy_error_state(struct drm_device *dev)
{
1649
	struct drm_i915_private *dev_priv = to_i915(dev);
1650 1651
	struct drm_i915_error_state *error;

1652
	spin_lock_irq(&dev_priv->gpu_error.lock);
1653 1654
	error = dev_priv->gpu_error.first_error;
	dev_priv->gpu_error.first_error = NULL;
1655
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1656 1657 1658 1659

	if (error)
		kref_put(&error->ref, i915_error_state_free);
}