i915_gpu_error.c 42.2 KB
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/*
 * Copyright (c) 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Keith Packard <keithp@keithp.com>
 *    Mika Kuoppala <mika.kuoppala@intel.com>
 *
 */

#include <generated/utsrelease.h>
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#include <linux/stop_machine.h>
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#include <linux/zlib.h>
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#include "i915_drv.h"

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static const char *engine_str(int engine)
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{
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	switch (engine) {
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	case RCS: return "render";
	case VCS: return "bsd";
	case BCS: return "blt";
	case VECS: return "vebox";
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	case VCS2: return "bsd2";
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	default: return "";
	}
}

static const char *tiling_flag(int tiling)
{
	switch (tiling) {
	default:
	case I915_TILING_NONE: return "";
	case I915_TILING_X: return " X";
	case I915_TILING_Y: return " Y";
	}
}

static const char *dirty_flag(int dirty)
{
	return dirty ? " dirty" : "";
}

static const char *purgeable_flag(int purgeable)
{
	return purgeable ? " purgeable" : "";
}

static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
{

	if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
		e->err = -ENOSPC;
		return false;
	}

	if (e->bytes == e->size - 1 || e->err)
		return false;

	return true;
}

static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
			      unsigned len)
{
	if (e->pos + len <= e->start) {
		e->pos += len;
		return false;
	}

	/* First vsnprintf needs to fit in its entirety for memmove */
	if (len >= e->size) {
		e->err = -EIO;
		return false;
	}

	return true;
}

static void __i915_error_advance(struct drm_i915_error_state_buf *e,
				 unsigned len)
{
	/* If this is first printf in this window, adjust it so that
	 * start position matches start of the buffer
	 */

	if (e->pos < e->start) {
		const size_t off = e->start - e->pos;

		/* Should not happen but be paranoid */
		if (off > len || e->bytes) {
			e->err = -EIO;
			return;
		}

		memmove(e->buf, e->buf + off, len - off);
		e->bytes = len - off;
		e->pos = e->start;
		return;
	}

	e->bytes += len;
	e->pos += len;
}

static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
			       const char *f, va_list args)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
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		va_list tmp;

		va_copy(tmp, args);
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		len = vsnprintf(NULL, 0, f, tmp);
		va_end(tmp);

		if (!__i915_error_seek(e, len))
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			return;
	}

	len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;

	__i915_error_advance(e, len);
}

static void i915_error_puts(struct drm_i915_error_state_buf *e,
			    const char *str)
{
	unsigned len;

	if (!__i915_error_ok(e))
		return;

	len = strlen(str);

	/* Seek the first printf which is hits start position */
	if (e->pos < e->start) {
		if (!__i915_error_seek(e, len))
			return;
	}

	if (len >= e->size - e->bytes)
		len = e->size - e->bytes - 1;
	memcpy(e->buf + e->bytes, str, len);

	__i915_error_advance(e, len);
}

#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
#define err_puts(e, s) i915_error_puts(e, s)

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#ifdef CONFIG_DRM_I915_COMPRESS_ERROR

static bool compress_init(struct z_stream_s *zstream)
{
	memset(zstream, 0, sizeof(*zstream));

	zstream->workspace =
		kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
			GFP_ATOMIC | __GFP_NOWARN);
	if (!zstream->workspace)
		return false;

	if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
		kfree(zstream->workspace);
		return false;
	}

	return true;
}

static int compress_page(struct z_stream_s *zstream,
			 void *src,
			 struct drm_i915_error_object *dst)
{
	zstream->next_in = src;
	zstream->avail_in = PAGE_SIZE;

	do {
		if (zstream->avail_out == 0) {
			unsigned long page;

			page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
			if (!page)
				return -ENOMEM;

			dst->pages[dst->page_count++] = (void *)page;

			zstream->next_out = (void *)page;
			zstream->avail_out = PAGE_SIZE;
		}

		if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
			return -EIO;
	} while (zstream->avail_in);

	/* Fallback to uncompressed if we increase size? */
	if (0 && zstream->total_out > zstream->total_in)
		return -E2BIG;

	return 0;
}

static void compress_fini(struct z_stream_s *zstream,
			  struct drm_i915_error_object *dst)
{
	if (dst) {
		zlib_deflate(zstream, Z_FINISH);
		dst->unused = zstream->avail_out;
	}

	zlib_deflateEnd(zstream);
	kfree(zstream->workspace);
}

static void err_compression_marker(struct drm_i915_error_state_buf *m)
{
	err_puts(m, ":");
}

#else

static bool compress_init(struct z_stream_s *zstream)
{
	return true;
}

static int compress_page(struct z_stream_s *zstream,
			 void *src,
			 struct drm_i915_error_object *dst)
{
	unsigned long page;

	page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
	if (!page)
		return -ENOMEM;

	dst->pages[dst->page_count++] =
		memcpy((void *)page, src, PAGE_SIZE);

	return 0;
}

static void compress_fini(struct z_stream_s *zstream,
			  struct drm_i915_error_object *dst)
{
}

static void err_compression_marker(struct drm_i915_error_state_buf *m)
{
	err_puts(m, "~");
}

#endif

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static void print_error_buffers(struct drm_i915_error_state_buf *m,
				const char *name,
				struct drm_i915_error_buffer *err,
				int count)
{
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	int i;

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	err_printf(m, "%s [%d]:\n", name, count);
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	while (count--) {
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		err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
			   upper_32_bits(err->gtt_offset),
			   lower_32_bits(err->gtt_offset),
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			   err->size,
			   err->read_domains,
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			   err->write_domain);
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		for (i = 0; i < I915_NUM_ENGINES; i++)
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			err_printf(m, "%02x ", err->rseqno[i]);

		err_printf(m, "] %02x", err->wseqno);
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		err_puts(m, tiling_flag(err->tiling));
		err_puts(m, dirty_flag(err->dirty));
		err_puts(m, purgeable_flag(err->purgeable));
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		err_puts(m, err->userptr ? " userptr" : "");
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		err_puts(m, err->engine != -1 ? " " : "");
		err_puts(m, engine_str(err->engine));
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		err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
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		if (err->name)
			err_printf(m, " (name: %d)", err->name);
		if (err->fence_reg != I915_FENCE_REG_NONE)
			err_printf(m, " (fence: %d)", err->fence_reg);

		err_puts(m, "\n");
		err++;
	}
}

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static const char *hangcheck_action_to_str(enum intel_engine_hangcheck_action a)
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{
	switch (a) {
	case HANGCHECK_IDLE:
		return "idle";
	case HANGCHECK_WAIT:
		return "wait";
	case HANGCHECK_ACTIVE:
		return "active";
	case HANGCHECK_KICK:
		return "kick";
	case HANGCHECK_HUNG:
		return "hung";
	}

	return "unknown";
}

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static void error_print_instdone(struct drm_i915_error_state_buf *m,
				 struct drm_i915_error_engine *ee)
{
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	int slice;
	int subslice;

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	err_printf(m, "  INSTDONE: 0x%08x\n",
		   ee->instdone.instdone);

	if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
		return;

	err_printf(m, "  SC_INSTDONE: 0x%08x\n",
		   ee->instdone.slice_common);

	if (INTEL_GEN(m->i915) <= 6)
		return;

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	for_each_instdone_slice_subslice(m->i915, slice, subslice)
		err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
			   slice, subslice,
			   ee->instdone.sampler[slice][subslice]);

	for_each_instdone_slice_subslice(m->i915, slice, subslice)
		err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
			   slice, subslice,
			   ee->instdone.row[slice][subslice]);
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}

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static void error_print_request(struct drm_i915_error_state_buf *m,
				const char *prefix,
				struct drm_i915_error_request *erq)
{
	if (!erq->seqno)
		return;

	err_printf(m, "%s pid %d, seqno %8x:%08x, emitted %dms ago, head %08x, tail %08x\n",
		   prefix, erq->pid,
		   erq->context, erq->seqno,
		   jiffies_to_msecs(jiffies - erq->jiffies),
		   erq->head, erq->tail);
}

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static void error_print_engine(struct drm_i915_error_state_buf *m,
			       struct drm_i915_error_engine *ee)
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{
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	err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
	err_printf(m, "  START: 0x%08x\n", ee->start);
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	err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
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	err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
		   ee->tail, ee->rq_post, ee->rq_tail);
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	err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
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	err_printf(m, "  MODE:  0x%08x\n", ee->mode);
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	err_printf(m, "  HWS:   0x%08x\n", ee->hws);
	err_printf(m, "  ACTHD: 0x%08x %08x\n",
		   (u32)(ee->acthd>>32), (u32)ee->acthd);
	err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
	err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
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	error_print_instdone(m, ee);

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	if (ee->batchbuffer) {
		u64 start = ee->batchbuffer->gtt_offset;
		u64 end = start + ee->batchbuffer->gtt_size;

		err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
			   upper_32_bits(start), lower_32_bits(start),
			   upper_32_bits(end), lower_32_bits(end));
	}
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	if (INTEL_GEN(m->i915) >= 4) {
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		err_printf(m, "  BBADDR: 0x%08x_%08x\n",
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			   (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
		err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
		err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
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	}
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	err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
		   lower_32_bits(ee->faddr));
	if (INTEL_GEN(m->i915) >= 6) {
		err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
		err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
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		err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
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			   ee->semaphore_mboxes[0],
			   ee->semaphore_seqno[0]);
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		err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
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			   ee->semaphore_mboxes[1],
			   ee->semaphore_seqno[1]);
		if (HAS_VEBOX(m->i915)) {
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			err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
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				   ee->semaphore_mboxes[2],
				   ee->semaphore_seqno[2]);
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		}
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	}
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	if (USES_PPGTT(m->i915)) {
		err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
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		if (INTEL_GEN(m->i915) >= 8) {
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			int i;
			for (i = 0; i < 4; i++)
				err_printf(m, "  PDP%d: 0x%016llx\n",
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					   i, ee->vm_info.pdp[i]);
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		} else {
			err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
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				   ee->vm_info.pp_dir_base);
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		}
	}
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	err_printf(m, "  seqno: 0x%08x\n", ee->seqno);
	err_printf(m, "  last_seqno: 0x%08x\n", ee->last_seqno);
	err_printf(m, "  waiting: %s\n", yesno(ee->waiting));
	err_printf(m, "  ring->head: 0x%08x\n", ee->cpu_ring_head);
	err_printf(m, "  ring->tail: 0x%08x\n", ee->cpu_ring_tail);
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	err_printf(m, "  hangcheck: %s [%d]\n",
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		   hangcheck_action_to_str(ee->hangcheck_action),
		   ee->hangcheck_score);
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	error_print_request(m, "  ELSP[0]: ", &ee->execlist[0]);
	error_print_request(m, "  ELSP[1]: ", &ee->execlist[1]);
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}

void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
{
	va_list args;

	va_start(args, f);
	i915_error_vprintf(e, f, args);
	va_end(args);
}

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static int
ascii85_encode_len(int len)
{
	return DIV_ROUND_UP(len, 4);
}

static bool
ascii85_encode(u32 in, char *out)
{
	int i;

	if (in == 0)
		return false;

	out[5] = '\0';
	for (i = 5; i--; ) {
		out[i] = '!' + in % 85;
		in /= 85;
	}

	return true;
}

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static void print_error_obj(struct drm_i915_error_state_buf *m,
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			    struct intel_engine_cs *engine,
			    const char *name,
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			    struct drm_i915_error_object *obj)
{
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	char out[6];
	int page;
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	if (!obj)
		return;

	if (name) {
		err_printf(m, "%s --- %s = 0x%08x %08x\n",
			   engine ? engine->name : "global", name,
			   upper_32_bits(obj->gtt_offset),
			   lower_32_bits(obj->gtt_offset));
	}

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	err_compression_marker(m);
	for (page = 0; page < obj->page_count; page++) {
		int i, len;

		len = PAGE_SIZE;
		if (page == obj->page_count - 1)
			len -= obj->unused;
		len = ascii85_encode_len(len);

		for (i = 0; i < len; i++) {
			if (ascii85_encode(obj->pages[page][i], out))
				err_puts(m, out);
			else
				err_puts(m, "z");
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		}
	}
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	err_puts(m, "\n");
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}

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static void err_print_capabilities(struct drm_i915_error_state_buf *m,
				   const struct intel_device_info *info)
{
#define PRINT_FLAG(x)  err_printf(m, #x ": %s\n", yesno(info->x))
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	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
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#undef PRINT_FLAG
}

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int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
			    const struct i915_error_state_file_priv *error_priv)
{
	struct drm_device *dev = error_priv->dev;
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	struct drm_i915_private *dev_priv = to_i915(dev);
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David Weinehall 已提交
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	struct pci_dev *pdev = dev_priv->drm.pdev;
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	struct drm_i915_error_state *error = error_priv->error;
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	struct drm_i915_error_object *obj;
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	int max_hangcheck_score;
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	int i, j;
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	if (!error) {
		err_printf(m, "no error state collected\n");
		goto out;
	}

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	err_printf(m, "%s\n", error->error_msg);
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	err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
		   error->time.tv_usec);
	err_printf(m, "Kernel: " UTS_RELEASE "\n");
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	err_print_capabilities(m, &error->device_info);
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	max_hangcheck_score = 0;
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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].hangcheck_score > max_hangcheck_score)
			max_hangcheck_score = error->engine[i].hangcheck_score;
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	}
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	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].hangcheck_score == max_hangcheck_score &&
		    error->engine[i].pid != -1) {
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			err_printf(m, "Active process (on ring %s): %s [%d]\n",
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				   engine_str(i),
				   error->engine[i].comm,
				   error->engine[i].pid);
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		}
	}
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	err_printf(m, "Reset count: %u\n", error->reset_count);
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	err_printf(m, "Suspend count: %u\n", error->suspend_count);
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	err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
	err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
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	err_printf(m, "PCI Subsystem: %04x:%04x\n",
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David Weinehall 已提交
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		   pdev->subsystem_vendor,
		   pdev->subsystem_device);
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	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
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	if (HAS_CSR(dev)) {
		struct intel_csr *csr = &dev_priv->csr;

		err_printf(m, "DMC loaded: %s\n",
			   yesno(csr->dmc_payload != NULL));
		err_printf(m, "DMC fw version: %d.%d\n",
			   CSR_VERSION_MAJOR(csr->version),
			   CSR_VERSION_MINOR(csr->version));
	}

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	err_printf(m, "EIR: 0x%08x\n", error->eir);
	err_printf(m, "IER: 0x%08x\n", error->ier);
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	if (INTEL_INFO(dev)->gen >= 8) {
		for (i = 0; i < 4; i++)
			err_printf(m, "GTIER gt %d: 0x%08x\n", i,
				   error->gtier[i]);
	} else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
		err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
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	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
	err_printf(m, "CCID: 0x%08x\n", error->ccid);
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	err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
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	for (i = 0; i < dev_priv->num_fence_regs; i++)
		err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);

	if (INTEL_INFO(dev)->gen >= 6) {
		err_printf(m, "ERROR: 0x%08x\n", error->error);
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		if (INTEL_INFO(dev)->gen >= 8)
			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
				   error->fault_data1, error->fault_data0);

610 611 612
		err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
	}

613
	if (IS_GEN7(dev))
614 615
		err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);

616 617 618 619
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		if (error->engine[i].engine_id != -1)
			error_print_engine(m, &error->engine[i]);
	}
620

621 622 623
	for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
		char buf[128];
		int len, first = 1;
624

625 626 627 628 629 630 631 632 633 634
		if (!error->active_vm[i])
			break;

		len = scnprintf(buf, sizeof(buf), "Active (");
		for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
			if (error->engine[j].vm != error->active_vm[i])
				continue;

			len += scnprintf(buf + len, sizeof(buf), "%s%s",
					 first ? "" : ", ",
635
					 dev_priv->engine[j]->name);
636 637 638 639
			first = 0;
		}
		scnprintf(buf + len, sizeof(buf), ")");
		print_error_buffers(m, buf,
640 641 642
				    error->active_bo[i],
				    error->active_bo_count[i]);
	}
643

644 645 646 647
	print_error_buffers(m, "Pinned (global)",
			    error->pinned_bo,
			    error->pinned_bo_count);

648 649 650 651
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];

		obj = ee->batchbuffer;
652
		if (obj) {
653
			err_puts(m, dev_priv->engine[i]->name);
654
			if (ee->pid != -1)
655
				err_printf(m, " (submitted by %s [%d])",
656 657
					   ee->comm,
					   ee->pid);
658 659 660
			err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
				   upper_32_bits(obj->gtt_offset),
				   lower_32_bits(obj->gtt_offset));
661
			print_error_obj(m, dev_priv->engine[i], NULL, obj);
662 663
		}

664
		if (ee->num_requests) {
665
			err_printf(m, "%s --- %d requests\n",
666
				   dev_priv->engine[i]->name,
667
				   ee->num_requests);
668 669
			for (j = 0; j < ee->num_requests; j++)
				error_print_request(m, " ", &ee->requests[j]);
670 671
		}

672 673
		if (IS_ERR(ee->waiters)) {
			err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
674
				   dev_priv->engine[i]->name);
675
		} else if (ee->num_waiters) {
676
			err_printf(m, "%s --- %d waiters\n",
677
				   dev_priv->engine[i]->name,
678 679
				   ee->num_waiters);
			for (j = 0; j < ee->num_waiters; j++) {
680
				err_printf(m, " seqno 0x%08x for %s [%d]\n",
681 682 683
					   ee->waiters[j].seqno,
					   ee->waiters[j].comm,
					   ee->waiters[j].pid);
684 685 686
			}
		}

687
		print_error_obj(m, dev_priv->engine[i],
688
				"ringbuffer", ee->ringbuffer);
689

690
		print_error_obj(m, dev_priv->engine[i],
691
				"HW Status", ee->hws_page);
692

693
		print_error_obj(m, dev_priv->engine[i],
694
				"HW context", ee->ctx);
695

696
		print_error_obj(m, dev_priv->engine[i],
697
				"WA context", ee->wa_ctx);
698

699
		print_error_obj(m, dev_priv->engine[i],
700
				"WA batchbuffer", ee->wa_batchbuffer);
701 702
	}

703
	print_error_obj(m, NULL, "Semaphores", error->semaphore);
704

705 706 707 708 709 710 711 712 713 714 715 716 717 718
	if (error->overlay)
		intel_overlay_print_error_state(m, error->overlay);

	if (error->display)
		intel_display_print_error_state(m, dev, error->display);

out:
	if (m->bytes == 0 && m->err)
		return m->err;

	return 0;
}

int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
719
			      struct drm_i915_private *i915,
720 721 722
			      size_t count, loff_t pos)
{
	memset(ebuf, 0, sizeof(*ebuf));
723
	ebuf->i915 = i915;
724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757

	/* We need to have enough room to store any i915_error_state printf
	 * so that we can move it to start position.
	 */
	ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
	ebuf->buf = kmalloc(ebuf->size,
				GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);

	if (ebuf->buf == NULL) {
		ebuf->size = PAGE_SIZE;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL) {
		ebuf->size = 128;
		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
	}

	if (ebuf->buf == NULL)
		return -ENOMEM;

	ebuf->start = pos;

	return 0;
}

static void i915_error_object_free(struct drm_i915_error_object *obj)
{
	int page;

	if (obj == NULL)
		return;

	for (page = 0; page < obj->page_count; page++)
758
		free_page((unsigned long)obj->pages[page]);
759 760 761 762 763 764 765 766 767 768

	kfree(obj);
}

static void i915_error_state_free(struct kref *error_ref)
{
	struct drm_i915_error_state *error = container_of(error_ref,
							  typeof(*error), ref);
	int i;

769 770 771 772 773 774 775 776 777 778 779
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];

		i915_error_object_free(ee->batchbuffer);
		i915_error_object_free(ee->wa_batchbuffer);
		i915_error_object_free(ee->ringbuffer);
		i915_error_object_free(ee->hws_page);
		i915_error_object_free(ee->ctx);
		i915_error_object_free(ee->wa_ctx);

		kfree(ee->requests);
780 781
		if (!IS_ERR_OR_NULL(ee->waiters))
			kfree(ee->waiters);
782 783
	}

784
	i915_error_object_free(error->semaphore);
785

786
	for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
787 788
		kfree(error->active_bo[i]);
	kfree(error->pinned_bo);
789

790 791 792 793 794 795
	kfree(error->overlay);
	kfree(error->display);
	kfree(error);
}

static struct drm_i915_error_object *
796
i915_error_object_create(struct drm_i915_private *i915,
C
Chris Wilson 已提交
797
			 struct i915_vma *vma)
798
{
799 800
	struct i915_ggtt *ggtt = &i915->ggtt;
	const u64 slot = ggtt->error_capture.start;
801
	struct drm_i915_error_object *dst;
802
	struct z_stream_s zstream;
803 804 805
	unsigned long num_pages;
	struct sgt_iter iter;
	dma_addr_t dma;
806

C
Chris Wilson 已提交
807 808 809
	if (!vma)
		return NULL;

810
	num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
811
	num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
812 813
	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
		      GFP_ATOMIC | __GFP_NOWARN);
C
Chris Wilson 已提交
814
	if (!dst)
815 816
		return NULL;

817 818
	dst->gtt_offset = vma->node.start;
	dst->gtt_size = vma->node.size;
819
	dst->page_count = 0;
820 821 822 823 824 825
	dst->unused = 0;

	if (!compress_init(&zstream)) {
		kfree(dst);
		return NULL;
	}
826

827 828 829
	for_each_sgt_dma(dma, iter, vma->pages) {
		void __iomem *s;
		int ret;
830

831 832
		ggtt->base.insert_page(&ggtt->base, dma, slot,
				       I915_CACHE_NONE, 0);
833

834
		s = io_mapping_map_atomic_wc(&ggtt->mappable, slot);
835
		ret = compress_page(&zstream, (void  __force *)s, dst);
836
		io_mapping_unmap_atomic(s);
837

838
		if (ret)
839 840
			goto unwind;
	}
841
	goto out;
842 843

unwind:
844 845
	while (dst->page_count--)
		free_page((unsigned long)dst->pages[dst->page_count]);
846
	kfree(dst);
847 848 849
	dst = NULL;

out:
850
	compress_fini(&zstream, dst);
851 852
	ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE, true);
	return dst;
853 854
}

855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872
/* The error capture is special as tries to run underneath the normal
 * locking rules - so we use the raw version of the i915_gem_active lookup.
 */
static inline uint32_t
__active_get_seqno(struct i915_gem_active *active)
{
	return i915_gem_request_get_seqno(__i915_gem_active_peek(active));
}

static inline int
__active_get_engine_id(struct i915_gem_active *active)
{
	struct intel_engine_cs *engine;

	engine = i915_gem_request_get_engine(__i915_gem_active_peek(active));
	return engine ? engine->id : -1;
}

873
static void capture_bo(struct drm_i915_error_buffer *err,
874
		       struct i915_vma *vma)
875
{
876
	struct drm_i915_gem_object *obj = vma->obj;
877
	int i;
878

879 880
	err->size = obj->base.size;
	err->name = obj->base.name;
881

882
	for (i = 0; i < I915_NUM_ENGINES; i++)
883 884 885 886
		err->rseqno[i] = __active_get_seqno(&obj->last_read[i]);
	err->wseqno = __active_get_seqno(&obj->last_write);
	err->engine = __active_get_engine_id(&obj->last_write);

887
	err->gtt_offset = vma->node.start;
888 889
	err->read_domains = obj->base.read_domains;
	err->write_domain = obj->base.write_domain;
890
	err->fence_reg = vma->fence ? vma->fence->id : -1;
891
	err->tiling = i915_gem_object_get_tiling(obj);
892 893
	err->dirty = obj->dirty;
	err->purgeable = obj->madv != I915_MADV_WILLNEED;
894
	err->userptr = obj->userptr.mm != NULL;
895 896 897
	err->cache_level = obj->cache_level;
}

898 899 900
static u32 capture_error_bo(struct drm_i915_error_buffer *err,
			    int count, struct list_head *head,
			    bool pinned_only)
901
{
B
Ben Widawsky 已提交
902
	struct i915_vma *vma;
903 904
	int i = 0;

905
	list_for_each_entry(vma, head, vm_link) {
906 907 908
		if (pinned_only && !i915_vma_is_pinned(vma))
			continue;

909
		capture_bo(err++, vma);
910 911 912 913 914 915 916
		if (++i == count)
			break;
	}

	return i;
}

917 918 919 920 921 922 923 924 925 926
/* Generate a semi-unique error code. The code is not meant to have meaning, The
 * code's only purpose is to try to prevent false duplicated bug reports by
 * grossly estimating a GPU error state.
 *
 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
 * the hang if we could strip the GTT offset information from it.
 *
 * It's only a small step better than a random number in its current form.
 */
static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
927
					 struct drm_i915_error_state *error,
928
					 int *engine_id)
929 930 931 932 933 934 935 936 937
{
	uint32_t error_code = 0;
	int i;

	/* IPEHR would be an ideal way to detect errors, as it's the gross
	 * measure of "the command that hung." However, has some very common
	 * synchronization commands which almost always appear in the case
	 * strictly a client bug. Use instdone to differentiate those some.
	 */
938
	for (i = 0; i < I915_NUM_ENGINES; i++) {
939 940 941
		if (error->engine[i].hangcheck_action == HANGCHECK_HUNG) {
			if (engine_id)
				*engine_id = i;
942

943 944
			return error->engine[i].ipehr ^
			       error->engine[i].instdone.instdone;
945 946
		}
	}
947 948 949 950

	return error_code;
}

951
static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
952 953 954 955
				   struct drm_i915_error_state *error)
{
	int i;

956
	if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
957
		for (i = 0; i < dev_priv->num_fence_regs; i++)
958
			error->fence[i] = I915_READ(FENCE_REG(i));
959
	} else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
960 961
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
962
	} else if (INTEL_GEN(dev_priv) >= 6) {
963 964 965
		for (i = 0; i < dev_priv->num_fence_regs; i++)
			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
	}
966 967
}

968

969
static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
970
					struct intel_engine_cs *engine,
971
					struct drm_i915_error_engine *ee)
972
{
973
	struct drm_i915_private *dev_priv = engine->i915;
974
	struct intel_engine_cs *to;
975
	enum intel_engine_id id;
976

977
	if (!error->semaphore)
978
		return;
979

980
	for_each_engine(to, dev_priv, id) {
981 982 983
		int idx;
		u16 signal_offset;
		u32 *tmp;
984

985
		if (engine == to)
986 987
			continue;

988 989
		signal_offset =
			(GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
990
		tmp = error->semaphore->pages[0];
991
		idx = intel_engine_sync_index(engine, to);
992

993 994
		ee->semaphore_mboxes[idx] = tmp[signal_offset];
		ee->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
995 996 997
	}
}

998 999
static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
					struct drm_i915_error_engine *ee)
1000
{
1001 1002 1003 1004 1005 1006
	struct drm_i915_private *dev_priv = engine->i915;

	ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
	ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
	ee->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
	ee->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
1007

1008
	if (HAS_VEBOX(dev_priv)) {
1009
		ee->semaphore_mboxes[2] =
1010
			I915_READ(RING_SYNC_2(engine->mmio_base));
1011
		ee->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
1012 1013 1014
	}
}

1015 1016
static void error_record_engine_waiters(struct intel_engine_cs *engine,
					struct drm_i915_error_engine *ee)
1017 1018 1019 1020 1021 1022
{
	struct intel_breadcrumbs *b = &engine->breadcrumbs;
	struct drm_i915_error_waiter *waiter;
	struct rb_node *rb;
	int count;

1023 1024
	ee->num_waiters = 0;
	ee->waiters = NULL;
1025

1026 1027 1028 1029 1030 1031 1032 1033
	if (RB_EMPTY_ROOT(&b->waiters))
		return;

	if (!spin_trylock(&b->lock)) {
		ee->waiters = ERR_PTR(-EDEADLK);
		return;
	}

1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046
	count = 0;
	for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
		count++;
	spin_unlock(&b->lock);

	waiter = NULL;
	if (count)
		waiter = kmalloc_array(count,
				       sizeof(struct drm_i915_error_waiter),
				       GFP_ATOMIC);
	if (!waiter)
		return;

1047 1048 1049 1050 1051
	if (!spin_trylock(&b->lock)) {
		kfree(waiter);
		ee->waiters = ERR_PTR(-EDEADLK);
		return;
	}
1052

1053
	ee->waiters = waiter;
1054 1055 1056 1057 1058 1059 1060 1061
	for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
		struct intel_wait *w = container_of(rb, typeof(*w), node);

		strcpy(waiter->comm, w->tsk->comm);
		waiter->pid = w->tsk->pid;
		waiter->seqno = w->seqno;
		waiter++;

1062
		if (++ee->num_waiters == count)
1063 1064 1065 1066 1067
			break;
	}
	spin_unlock(&b->lock);
}

1068 1069 1070
static void error_record_engine_registers(struct drm_i915_error_state *error,
					  struct intel_engine_cs *engine,
					  struct drm_i915_error_engine *ee)
1071
{
1072 1073
	struct drm_i915_private *dev_priv = engine->i915;

1074
	if (INTEL_GEN(dev_priv) >= 6) {
1075 1076
		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
		ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1077
		if (INTEL_GEN(dev_priv) >= 8)
1078
			gen8_record_semaphore_state(error, engine, ee);
1079
		else
1080
			gen6_record_semaphore_state(engine, ee);
1081 1082
	}

1083
	if (INTEL_GEN(dev_priv) >= 4) {
1084 1085 1086 1087 1088
		ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
		ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
		ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
		ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
		ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1089
		if (INTEL_GEN(dev_priv) >= 8) {
1090 1091
			ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
			ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1092
		}
1093
		ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1094
	} else {
1095 1096 1097
		ee->faddr = I915_READ(DMA_FADD_I8XX);
		ee->ipeir = I915_READ(IPEIR);
		ee->ipehr = I915_READ(IPEHR);
1098 1099
	}

1100
	intel_engine_get_instdone(engine, &ee->instdone);
1101

1102 1103
	ee->waiting = intel_engine_has_waiter(engine);
	ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1104
	ee->acthd = intel_engine_get_active_head(engine);
1105 1106 1107 1108 1109 1110
	ee->seqno = intel_engine_get_seqno(engine);
	ee->last_seqno = engine->last_submitted_seqno;
	ee->start = I915_READ_START(engine);
	ee->head = I915_READ_HEAD(engine);
	ee->tail = I915_READ_TAIL(engine);
	ee->ctl = I915_READ_CTL(engine);
1111 1112
	if (INTEL_GEN(dev_priv) > 2)
		ee->mode = I915_READ_MODE(engine);
1113

1114
	if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1115
		i915_reg_t mmio;
1116

1117
		if (IS_GEN7(dev_priv)) {
1118
			switch (engine->id) {
1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132
			default:
			case RCS:
				mmio = RENDER_HWS_PGA_GEN7;
				break;
			case BCS:
				mmio = BLT_HWS_PGA_GEN7;
				break;
			case VCS:
				mmio = BSD_HWS_PGA_GEN7;
				break;
			case VECS:
				mmio = VEBOX_HWS_PGA_GEN7;
				break;
			}
1133
		} else if (IS_GEN6(engine->i915)) {
1134
			mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1135 1136
		} else {
			/* XXX: gen8 returns to sanity */
1137
			mmio = RING_HWS_PGA(engine->mmio_base);
1138 1139
		}

1140
		ee->hws = I915_READ(mmio);
1141 1142
	}

1143 1144
	ee->hangcheck_score = engine->hangcheck.score;
	ee->hangcheck_action = engine->hangcheck.action;
1145

1146
	if (USES_PPGTT(dev_priv)) {
1147 1148
		int i;

1149
		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1150

1151
		if (IS_GEN6(dev_priv))
1152
			ee->vm_info.pp_dir_base =
1153
				I915_READ(RING_PP_DIR_BASE_READ(engine));
1154
		else if (IS_GEN7(dev_priv))
1155
			ee->vm_info.pp_dir_base =
1156
				I915_READ(RING_PP_DIR_BASE(engine));
1157
		else if (INTEL_GEN(dev_priv) >= 8)
1158
			for (i = 0; i < 4; i++) {
1159
				ee->vm_info.pdp[i] =
1160
					I915_READ(GEN8_RING_PDP_UDW(engine, i));
1161 1162
				ee->vm_info.pdp[i] <<= 32;
				ee->vm_info.pdp[i] |=
1163
					I915_READ(GEN8_RING_PDP_LDW(engine, i));
1164 1165
			}
	}
1166 1167
}

1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181
static void record_request(struct drm_i915_gem_request *request,
			   struct drm_i915_error_request *erq)
{
	erq->context = request->ctx->hw_id;
	erq->seqno = request->fence.seqno;
	erq->jiffies = request->emitted_jiffies;
	erq->head = request->head;
	erq->tail = request->tail;

	rcu_read_lock();
	erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
	rcu_read_unlock();
}

1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223
static void engine_record_requests(struct intel_engine_cs *engine,
				   struct drm_i915_gem_request *first,
				   struct drm_i915_error_engine *ee)
{
	struct drm_i915_gem_request *request;
	int count;

	count = 0;
	request = first;
	list_for_each_entry_from(request, &engine->request_list, link)
		count++;
	if (!count)
		return;

	ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
	if (!ee->requests)
		return;

	ee->num_requests = count;

	count = 0;
	request = first;
	list_for_each_entry_from(request, &engine->request_list, link) {
		if (count >= ee->num_requests) {
			/*
			 * If the ring request list was changed in
			 * between the point where the error request
			 * list was created and dimensioned and this
			 * point then just exit early to avoid crashes.
			 *
			 * We don't need to communicate that the
			 * request list changed state during error
			 * state capture and that the error state is
			 * slightly incorrect as a consequence since we
			 * are typically only interested in the request
			 * list state at the point of error state
			 * capture, not in any changes happening during
			 * the capture.
			 */
			break;
		}

1224
		record_request(request, &ee->requests[count++]);
1225 1226 1227 1228
	}
	ee->num_requests = count;
}

1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239
static void error_record_engine_execlists(struct intel_engine_cs *engine,
					  struct drm_i915_error_engine *ee)
{
	unsigned int n;

	for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
		if (engine->execlist_port[n].request)
			record_request(engine->execlist_port[n].request,
				       &ee->execlist[n]);
}

1240
static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
1241 1242
				  struct drm_i915_error_state *error)
{
1243
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
1244
	int i;
1245

1246
	error->semaphore =
C
Chris Wilson 已提交
1247
		i915_error_object_create(dev_priv, dev_priv->semaphore);
1248

1249
	for (i = 0; i < I915_NUM_ENGINES; i++) {
1250
		struct intel_engine_cs *engine = dev_priv->engine[i];
1251
		struct drm_i915_error_engine *ee = &error->engine[i];
1252
		struct drm_i915_gem_request *request;
1253

1254 1255
		ee->pid = -1;
		ee->engine_id = -1;
1256

1257
		if (!engine)
1258 1259
			continue;

1260
		ee->engine_id = i;
1261

1262 1263
		error_record_engine_registers(error, engine, ee);
		error_record_engine_waiters(engine, ee);
1264
		error_record_engine_execlists(engine, ee);
1265

1266
		request = i915_gem_find_active_request(engine);
1267
		if (request) {
1268
			struct intel_ring *ring;
1269
			struct pid *pid;
1270

1271
			ee->vm = request->ctx->ppgtt ?
1272
				&request->ctx->ppgtt->base : &ggtt->base;
1273

1274 1275 1276 1277
			/* We need to copy these to an anonymous buffer
			 * as the simplest method to avoid being overwritten
			 * by userspace.
			 */
1278
			ee->batchbuffer =
1279
				i915_error_object_create(dev_priv,
C
Chris Wilson 已提交
1280
							 request->batch);
1281

1282
			if (HAS_BROKEN_CS_TLB(dev_priv))
1283
				ee->wa_batchbuffer =
C
Chris Wilson 已提交
1284 1285
					i915_error_object_create(dev_priv,
								 engine->scratch);
1286

C
Chris Wilson 已提交
1287 1288 1289
			ee->ctx =
				i915_error_object_create(dev_priv,
							 request->ctx->engine[i].state);
1290

1291 1292
			pid = request->ctx->pid;
			if (pid) {
1293 1294 1295
				struct task_struct *task;

				rcu_read_lock();
1296
				task = pid_task(pid, PIDTYPE_PID);
1297
				if (task) {
1298 1299
					strcpy(ee->comm, task->comm);
					ee->pid = task->pid;
1300 1301 1302
				}
				rcu_read_unlock();
			}
1303

1304 1305 1306
			error->simulated |=
				request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE;

1307 1308 1309 1310
			ee->rq_head = request->head;
			ee->rq_post = request->postfix;
			ee->rq_tail = request->tail;

1311 1312 1313
			ring = request->ring;
			ee->cpu_ring_head = ring->head;
			ee->cpu_ring_tail = ring->tail;
1314
			ee->ringbuffer =
C
Chris Wilson 已提交
1315
				i915_error_object_create(dev_priv, ring->vma);
1316 1317

			engine_record_requests(engine, request, ee);
1318
		}
1319

1320
		ee->hws_page =
C
Chris Wilson 已提交
1321 1322
			i915_error_object_create(dev_priv,
						 engine->status_page.vma);
1323

C
Chris Wilson 已提交
1324 1325
		ee->wa_ctx =
			i915_error_object_create(dev_priv, engine->wa_ctx.vma);
1326 1327 1328
	}
}

1329 1330 1331
static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
				struct drm_i915_error_state *error,
				struct i915_address_space *vm,
1332
				int idx)
1333
{
1334
	struct drm_i915_error_buffer *active_bo;
1335
	struct i915_vma *vma;
1336
	int count;
1337

1338
	count = 0;
1339
	list_for_each_entry(vma, &vm->active_list, vm_link)
1340
		count++;
1341

1342 1343 1344
	active_bo = NULL;
	if (count)
		active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1345
	if (active_bo)
1346 1347 1348 1349 1350 1351 1352
		count = capture_error_bo(active_bo, count, &vm->active_list, false);
	else
		count = 0;

	error->active_vm[idx] = vm;
	error->active_bo[idx] = active_bo;
	error->active_bo_count[idx] = count;
1353 1354
}

1355 1356
static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
					struct drm_i915_error_state *error)
1357
{
1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370
	int cnt = 0, i, j;

	BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
	BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
	BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));

	/* Scan each engine looking for unique active contexts/vm */
	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
		struct drm_i915_error_engine *ee = &error->engine[i];
		bool found;

		if (!ee->vm)
			continue;
1371

1372 1373 1374 1375 1376
		found = false;
		for (j = 0; j < i && !found; j++)
			found = error->engine[j].vm == ee->vm;
		if (!found)
			i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
1377
	}
1378 1379
}

1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410
static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
					struct drm_i915_error_state *error)
{
	struct i915_address_space *vm = &dev_priv->ggtt.base;
	struct drm_i915_error_buffer *bo;
	struct i915_vma *vma;
	int count_inactive, count_active;

	count_inactive = 0;
	list_for_each_entry(vma, &vm->active_list, vm_link)
		count_inactive++;

	count_active = 0;
	list_for_each_entry(vma, &vm->inactive_list, vm_link)
		count_active++;

	bo = NULL;
	if (count_inactive + count_active)
		bo = kcalloc(count_inactive + count_active,
			     sizeof(*bo), GFP_ATOMIC);
	if (!bo)
		return;

	count_inactive = capture_error_bo(bo, count_inactive,
					  &vm->active_list, true);
	count_active = capture_error_bo(bo + count_inactive, count_active,
					&vm->inactive_list, true);
	error->pinned_bo_count = count_inactive + count_active;
	error->pinned_bo = bo;
}

1411 1412 1413
/* Capture all registers which don't fit into another category. */
static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
1414
{
1415
	struct drm_device *dev = &dev_priv->drm;
1416
	int i;
1417

1418 1419 1420 1421 1422 1423 1424
	/* General organization
	 * 1. Registers specific to a single generation
	 * 2. Registers which belong to multiple generations
	 * 3. Feature specific registers.
	 * 4. Everything else
	 * Please try to follow the order.
	 */
1425

1426 1427
	/* 1: Registers specific to a single generation */
	if (IS_VALLEYVIEW(dev)) {
1428
		error->gtier[0] = I915_READ(GTIER);
1429
		error->ier = I915_READ(VLV_IER);
1430
		error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1431
	}
1432

1433 1434
	if (IS_GEN7(dev))
		error->err_int = I915_READ(GEN7_ERR_INT);
1435

1436 1437 1438 1439 1440
	if (INTEL_INFO(dev)->gen >= 8) {
		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
	}

1441
	if (IS_GEN6(dev)) {
1442
		error->forcewake = I915_READ_FW(FORCEWAKE);
1443 1444 1445
		error->gab_ctl = I915_READ(GAB_CTL);
		error->gfx_mode = I915_READ(GFX_MODE);
	}
1446

1447 1448
	/* 2: Registers which belong to multiple generations */
	if (INTEL_INFO(dev)->gen >= 7)
1449
		error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1450 1451

	if (INTEL_INFO(dev)->gen >= 6) {
1452
		error->derrmr = I915_READ(DERRMR);
1453 1454 1455 1456
		error->error = I915_READ(ERROR_GEN6);
		error->done_reg = I915_READ(DONE_REG);
	}

1457
	/* 3: Feature specific registers */
1458 1459 1460 1461 1462 1463
	if (IS_GEN6(dev) || IS_GEN7(dev)) {
		error->gam_ecochk = I915_READ(GAM_ECOCHK);
		error->gac_eco = I915_READ(GAC_ECO_BITS);
	}

	/* 4: Everything else */
1464 1465 1466
	if (HAS_HW_CONTEXTS(dev))
		error->ccid = I915_READ(CCID);

1467 1468 1469 1470 1471
	if (INTEL_INFO(dev)->gen >= 8) {
		error->ier = I915_READ(GEN8_DE_MISC_IER);
		for (i = 0; i < 4; i++)
			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
	} else if (HAS_PCH_SPLIT(dev)) {
1472
		error->ier = I915_READ(DEIER);
1473
		error->gtier[0] = I915_READ(GTIER);
1474 1475 1476 1477
	} else if (IS_GEN2(dev)) {
		error->ier = I915_READ16(IER);
	} else if (!IS_VALLEYVIEW(dev)) {
		error->ier = I915_READ(IER);
1478 1479 1480
	}
	error->eir = I915_READ(EIR);
	error->pgtbl_er = I915_READ(PGTBL_ER);
1481 1482
}

1483
static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1484
				   struct drm_i915_error_state *error,
1485
				   u32 engine_mask,
1486
				   const char *error_msg)
1487 1488
{
	u32 ecode;
1489
	int engine_id = -1, len;
1490

1491
	ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1492

1493
	len = scnprintf(error->error_msg, sizeof(error->error_msg),
1494
			"GPU HANG: ecode %d:%d:0x%08x",
1495
			INTEL_GEN(dev_priv), engine_id, ecode);
1496

1497
	if (engine_id != -1 && error->engine[engine_id].pid != -1)
1498 1499 1500
		len += scnprintf(error->error_msg + len,
				 sizeof(error->error_msg) - len,
				 ", in %s [%d]",
1501 1502
				 error->engine[engine_id].comm,
				 error->engine[engine_id].pid);
1503 1504 1505 1506

	scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
		  ", reason: %s, action: %s",
		  error_msg,
1507
		  engine_mask ? "reset" : "continue");
1508 1509
}

1510 1511 1512
static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
				   struct drm_i915_error_state *error)
{
1513 1514 1515 1516
	error->iommu = -1;
#ifdef CONFIG_INTEL_IOMMU
	error->iommu = intel_iommu_gfx_mapped;
#endif
1517
	error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1518
	error->suspend_count = dev_priv->suspend_count;
1519 1520 1521 1522

	memcpy(&error->device_info,
	       INTEL_INFO(dev_priv),
	       sizeof(error->device_info));
1523 1524
}

1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543
static int capture(void *data)
{
	struct drm_i915_error_state *error = data;

	i915_capture_gen_state(error->i915, error);
	i915_capture_reg_state(error->i915, error);
	i915_gem_record_fences(error->i915, error);
	i915_gem_record_rings(error->i915, error);
	i915_capture_active_buffers(error->i915, error);
	i915_capture_pinned_buffers(error->i915, error);

	do_gettimeofday(&error->time);

	error->overlay = intel_overlay_capture_error_state(error->i915);
	error->display = intel_display_capture_error_state(error->i915);

	return 0;
}

1544 1545 1546 1547 1548 1549 1550 1551 1552
/**
 * i915_capture_error_state - capture an error record for later analysis
 * @dev: drm device
 *
 * Should be called when an error is detected (either a hang or an error
 * interrupt) to capture error state from the time of the error.  Fills
 * out a structure which becomes available in debugfs for user level tools
 * to pick up.
 */
1553 1554
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
1555
			      const char *error_msg)
1556
{
1557
	static bool warned;
1558 1559 1560
	struct drm_i915_error_state *error;
	unsigned long flags;

1561 1562 1563
	if (!i915.error_capture)
		return;

1564 1565 1566
	if (READ_ONCE(dev_priv->gpu_error.first_error))
		return;

1567 1568 1569 1570 1571 1572 1573
	/* Account for pipe specific data like PIPE*STAT */
	error = kzalloc(sizeof(*error), GFP_ATOMIC);
	if (!error) {
		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
		return;
	}

1574
	kref_init(&error->ref);
1575
	error->i915 = dev_priv;
1576

1577
	stop_machine(capture, error, NULL);
1578

1579
	i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
1580 1581
	DRM_INFO("%s\n", error->error_msg);

1582 1583 1584 1585 1586 1587 1588
	if (!error->simulated) {
		spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
		if (!dev_priv->gpu_error.first_error) {
			dev_priv->gpu_error.first_error = error;
			error = NULL;
		}
		spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1589 1590
	}

1591
	if (error) {
1592
		i915_error_state_free(&error->ref);
1593 1594 1595 1596 1597 1598 1599 1600
		return;
	}

	if (!warned) {
		DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
		DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
		DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
		DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1601 1602
		DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
			 dev_priv->drm.primary->index);
1603 1604
		warned = true;
	}
1605 1606 1607 1608 1609
}

void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv)
{
1610
	struct drm_i915_private *dev_priv = to_i915(dev);
1611

1612
	spin_lock_irq(&dev_priv->gpu_error.lock);
1613 1614 1615
	error_priv->error = dev_priv->gpu_error.first_error;
	if (error_priv->error)
		kref_get(&error_priv->error->ref);
1616
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
}

void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
{
	if (error_priv->error)
		kref_put(&error_priv->error->ref, i915_error_state_free);
}

void i915_destroy_error_state(struct drm_device *dev)
{
1627
	struct drm_i915_private *dev_priv = to_i915(dev);
1628 1629
	struct drm_i915_error_state *error;

1630
	spin_lock_irq(&dev_priv->gpu_error.lock);
1631 1632
	error = dev_priv->gpu_error.first_error;
	dev_priv->gpu_error.first_error = NULL;
1633
	spin_unlock_irq(&dev_priv->gpu_error.lock);
1634 1635 1636 1637

	if (error)
		kref_put(&error->ref, i915_error_state_free);
}