Add a pin control driver for the TZ1090's low power pins via the
powerdown controller SOC_GPIO_CONTROL registers.

These pins have individually controlled pull-up, and group controlled
schmitt, slew-rate, drive-strength, and power-on-start (pos).

The pdc_gpio0 and pdc_gpio1 pins can also be muxed onto the
ir_mod_stable_out and ir_mod_power_out functions respectively. If no
function is set they remain in GPIO mode. These muxes can be overridden
by requesting them as GPIOs.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a pin control driver for the main pins on the TZ1090 SoC. This
doesn't include the low-power pins as they're controlled separately via
the Powerdown Controller (PDC) registers.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add support for gpio on Intel BayTrail platforms. BayTrail supports 3 banks
of gpios called SCORE, NCORE ans SUS with 102, 28 and 44 gpio pins.
Supports gpio interrupts and ACPI gpio events

Pins may be muxed to alternate function instead of gpio by firmware.
This driver does not touch the pin muxing and expect firmare
to set pin muxing and pullup/down properties properly.
Signed-off-by: NMathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This driver adds support the Cortex-A9 based SoCs from Rockchip,
so at least the RK2928, RK3066 (a and b) and RK3188.
Earlier Rockchip SoCs seem to use similar mechanics for gpio
handling so should be supportable with relative small changes.
Pull handling on the rk3188 is currently a stub, due to it being
a bit different to the earlier SoCs.

Pinmuxing as well as gpio (and interrupt-) handling tested on
a rk3066a based machine.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Adds Freescale Vybrid VF610 pin controller
driver to IMX common pinctrl driver framework.
Signed-off-by: NJingchang Lu <b35083@freescale.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

atlas6 is a SoC very similar with primaII, the register layput of
pinctrl is same, but the pads, groups and functions of atlas6 have
different layout with prima2, this patch
1. pull the definition of pads, groups and functions out of the
pinctrl-sirf driver,and put them into soc-specific files
2. add pads, groups and functions tables for atlas6
3. let pads, groups and functions tables become the config data of
   the related dt compatible node, so the pinctrl-sirf can support
   all SiRF SoCs with the config data as private data.

In this patch,we create a sirf dir, and let
the old drivers/pinctrl/pinctrl-sirf.c =
        drivers/pinctrl/sirf/pinctrl-prima2.c +
        drivers/pinctrl/sirf/pinctrl-sirf.c

drivers/pinctrl/sirf/pinctrl-atlas6.c is a newly created file for the
pin layout of atlas6.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The pinctrl-imx6sl is in place.  Enable the build of it.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The imx6dl is a derivative of imx6q with very limited difference.  These
two SoCs are so compatible that they can be handled as one platform in
software.  That said, we will not have target SOC_IMX6DL but just
reusing SOC_IMX6Q.   That's why the pinctrl-imx6dl driver is added here
with symbol PINCTRL_IMX6Q controlling the build of it.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds pinctrl-s3c64xx driver which implements pin control
interface for Samsung S3C64xx SoCs.
Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds support for the GPIO/pinmux controller found on the VIA
VT8500 and Wondermedia WM8xxx-series SoCs.

Each pin within the controller is capable of operating as a GPIO or as
an alternate function. The pins are numbered according to their control
bank/bit so that if new pins are added, the existing numbering is maintained.

All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and
WM8850.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

pinctrl-pxa driver doesn't support well on DT mode. Now pinctrl-single
could support DT mode & pin configuration. Use pinctrl-single driver to
support MMP/PXA silicons instead.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since pinctrl-exynos can support exynos4 and exynos5 so changed
the option name to PINCTRL_EXYNOS for more clarity.

Cc: Thomas Abraham <Thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add AB8540 sub driver to the ABx500 family, pins, pin groups and
gpio range.

As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add AB9540 sub driver to the ABx500 family, pins, pin groups and
gpio range.

As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add AB8505 sub driver to the ABx5x family.

As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds a subdriver for the AB8500 pinctrl portions.
As the pin controller (also the ABx500 controllers) is an
inherent part of the SoC and will prevent boot if not
available, select this from the Ux500 SoC Kconfig.
Acked-by: NOlof Johansson <olof@lixom.net>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds the AB8500 core driver, which will be utilized by
the follow-on drivers for different ABx500 variants.
Sselect the driver from the DBX500_SOC, as this chip is
powering and clocking that SoC.

Cc: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NPaul Mundt <lethal@linux-sh.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The Allwinner SoCs have an IP module that handle both the muxing and the
GPIOs.

This IP has 8 banks of 32 bits, with a number of pins actually useful
for each of these banks varying from one to another, and depending on
the SoC used on the board.

This driver only implements the pinctrl part, the gpio part will come
eventually.
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since pinctrl-exynos can support exynos4 and exynos5 so changed
the option name to PINCTRL_EXYNOS for more clarity.

Cc: Thomas Abraham <Thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds a driver for the Tegra114 pinmux, and required
parameterization data for Tegra114.

The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.

This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra114-pinmux".

Originally written by Pritesh.
ldewangan:
	- cleanup the patches,
	- remove non-require tables.
	- Use module_platform_driver() for driver registartion.
Signed-off-by: NPritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a new pinctrl driver for Samsung EXYNOS5440 SoC. The pin controller
module in EXYNOS5440 is different from the pin controller found on other
Samsung SoC. Hence, the pin controller driver for EXYNOS5440 SoC is
independent of the Samsung pinctrl framework.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Like the spear platform, the mvebu platform has multiple files: one
core file, and then one file per SoC family. More files will be added
later, as support for mach-orion5x and mach-mv78xx0 SoCs is added to
pinctrl-mvebu. For those reasons, having a separate subdirectory,
drivers/pinctrl/mvebu/ makes sense, and it had already been suggested
by Linus Wallej when the driver was originally submitted.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This is also include the gpio controller as the IP share both.
Each soc will have to describe the SoC limitation and pin configuration via
DT.

This will allow to do not need to touch the C code when adding new SoC if the
IP version is supported.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
controller, and pinmux/control device.

Original driver by Simon Arlott.
Rewrite including GPIO chip device by Chris Boot.

Upstreaming changes by Stephen Warren:
* Wrote DT binding documentation.
* Changed brcm,function to an integer to more directly match the
  datasheet, and to match brcm,pins being an integer.
* Implemented pull-up/down pin config.
* Removed read-only DT property and related code. The restriction this
  implemented are driven by the board, not the GPIO HW block, so don't
  really make sense of a HW block binding, were in general incomplete
  (since they could only know about the few pins hard-coded into the
  Raspberry Pi B board design and not the uncommitted GPIOS), and are
  better represented simply by not writing incorrect data into pin
  configuration nodes.
* Don't set GPIO_IN function select in gpio_request_enable() to avoid
  glitches; defer this to gpio_set_direction(). Consequently, removed
  empty bcm2835_pmx_gpio_request_enable().
* Simplified enabled_irq_map[]; make it explicitly 1 entry per bank.
* Lifted use of enabled_irq_map[] outside the per-interrupt loop in
  IRQ handler, thus fixing an issue where the code was indexing into
  enabled_irq_map[] by intra-bank GPIO ID, not global GPIO ID.
* Removed locking in IRQ handler, since all other code uses
  spin_lock_irqsave() and so guarantees it doesn't run concurrently
  with the handler.
* Moved duplicated BUILD_BUG_ON()s into probe(). Also check size of
  bcm2835_gpio_pins[].
* Remove range-checking from bcm2835_pctl_get_groups_count() since we've
  decided to trust the pinctrl core.
* Made bcm2835_pmx_gpio_disable_free() call bcm2835_pinctrl_fsel_set()
  directly for simplicity.
* Fixed body of dt_free_map() to match latest dt_node_to_map().
* Removed GPIO ownership check from bcm2835_pmx_enable() since the pinctrl
  core owns doing this.
* Made irq_chip and pinctrl_gpio_range .name == MODULE_NAME so it's more
  descriptive.
* Simplified remove(); removed call to non-existent
  pinctrl_remove_gpio_range(), remove early return on error.
* Don't force gpiochip's base to 0. Set gpio_range.base to gpiochip's
  base GPIO number.
* Error-handling cleanups in probe().
* Switched to module_platform_driver() rather than open-coding.
* Made pin, group, and function names lower-case.
* s/broadcom/brcm/ in DT property names.
* s/2708/2835/.
* Fixed a couple minor checkpatch warnings, and other minor cleanup.
Signed-off-by: NSimon Arlott <simon@fire.lp0.eu>
Signed-off-by: NChris Boot <bootc@bootc.net>
Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all
Marvell EBU SoCs.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Conflicts:

	arch/arm/Kconfig

Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
of up to 32 pins.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Signed-off-by: NThomas Langer <thomas.langer@lantiq.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org

Implement support for pinctrl on lantiq/xway socs. The IO core found on these
socs has the registers for pinctrl, pinconf and gpio mixed up in the same
register range. As the gpio_chip handling is only a few lines, the driver also
implements the gpio functionality. This obseletes the old gpio driver that was
located in the arch/ folder.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org

Add information about the Exynos4210 pin banks and driver data which is
used by the Samsung pinctrl driver. In addition to this, the support for
external gpio and wakeup interrupt support is included and hooked up with
the Samsung pinctrl driver.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add a new device tree enabled pinctrl and gpiolib driver for Samsung
SoC's. This driver provides a common and extensible framework for all
Samsung SoC's to interface with the pinctrl and gpiolib subsystems. This
driver supports only device tree based instantiation and hence can be
used only on those Samsung platforms that have device tree enabled.

This driver is split into two parts: the pinctrl interface and the gpiolib
interface. The pinctrl interface registers pinctrl devices with the pinctrl
subsystem and gpiolib interface registers gpio chips with the gpiolib
subsystem. The information about the pins, pin groups, pin functions and
gpio chips, which are SoC specific, are parsed from device tree node.
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This is mostly cut'n'paste from the imx51 pinctrl driver.
The data was generated using sed and awk on
arch/arm/plat-mxc/include/mach/iomux-mx35.h.

Changes since (implicit) v1
 - remove references to file names in binding documentation
 - remove sed commands from comments in driver
 - add explicit numbers for pins and functions
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Acked-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds support for the STN8815 ASIC for the Nomadik pin
controller.
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This implements a subdriver for the DB8540 ASIC for the
Nomadik pin controller.
Signed-off-by: NPatrice Chotard <patrice.chotard@stericsson.com>
Reviewed-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add one-register-per-pin type device tree based pinctrl driver.

This driver has been tested on omap2+ series of processors,
where there is either an 8 or 16-bit padconf register for each pin.
Support for other similar pinmux controllers can be added.
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

ChangeLog v1->v2:
* change PIN_FUNC_ID base in binding doc to 0 from 1.
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

ChangeLog v1->v2:
* change PIN_FUNC_ID base in binding doc to 0 from 1.
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NDong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>