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  1. 22 9月, 2015 1 次提交
  3. 27 7月, 2015 1 次提交
    • B
      pinctrl: driver for Conexant Digicolor CX92755 pin mapping · 38b0e507
      由 Baruch Siach 提交于 
      This adds pinctrl and gpio driver to the CX92755 SoC "General
Purpose Pin Mapping" hardware block. The CX92755 is one SoC
from the Conexant Digicolor series. Pin mapping hardware supports
configuring pins as either GPIO, or up to 3 other "client select"
functions. This driver adds support for pin muxing using the
generic device tree binding, and a basic gpiolib driver for
the GPIO functionality.

This driver does not currently support GPIO interrupts, and
pad configuration.

v2:
* Address review comments for Linus Walleij:
  - Add a pointer to pinctrl_desc in struct dc_pinmap
  - Drop the now redundant pinctrl_pin_desc field
  - Adapt dc_get_group_{name,pins} to these changes, and
    add a comment explaining the 1-to-1 pin-groups relation
* Staticise dc_pmxops
* Protect the GP_CLIENTSEL clct parameter with parenthesis
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      38b0e507
  5. 16 7月, 2015 1 次提交
  7. 19 5月, 2015 1 次提交
    • W
      pinctrl: sirf: add sirf atlas7 pinctrl and gpio support · f9367793
      由 Wei Chen 提交于 
      The Pinctrl module (ioc) controls the Pad's function select
(each pad can have 8 functions), Pad's Drive Strength, Pad's
Pull Select and Pad's Input Disable status.

The ioc has two modules, ioc_top & ioc_rtc. Both of these two
modules have function select/clear, Pull select and Drive
Strength registers. But only ioc_rtc has input-disable
registers. The Pads on ioc_top have to access ioc_rtc to set
their input-disable status and intpu-disable-value.

So have to use one ioc driver instance to drive these two
ioc modules at the same time, and each ioc module will be
treat as one bank on the "IOC Device".

The GPIO Controller controls the GPIO status if the Pad has
been config as GPIO by Pinctrl already. Includes the GPIO
Input/output, Interrupt type, Interrupt Status, and Set/Get
Values.
The GPIO pull up/down are controlled by Pinctrl.

There are 7 GPIO Groups and splited into 3 MACROs in atlas7.
The GPIO Groups in one MACRO share one GPIO controllers, each
GPIO Group are treated as one GPIO bank.

For example:
In VDIFM macro, there is one GPIO Controller, it has 3 banks
to control 3 gpio groups. Its gpio name space is from 0 to 95.

The Device Tree can be written as following:

gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 32 0 0>,
<&pinctrl 64 0 0>;

gpio-ranges-group-names = "gnss_gpio_grp",
"lcd_vip_gpio_grp",
"sdio_i2s_gpio_grp";

bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp".
bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp".
bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp".
Signed-off-by: NWei Chen <Wei.Chen@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      f9367793
  9. 12 5月, 2015 1 次提交
  11. 06 5月, 2015 1 次提交
  13. 15 4月, 2015 1 次提交
  15. 18 3月, 2015 3 次提交
  17. 10 3月, 2015 1 次提交
  19. 26 1月, 2015 1 次提交
  21. 14 1月, 2015 1 次提交
  23. 12 1月, 2015 1 次提交
    • S
      pinctrl: Add driver for Zynq · add958ce
      由 Soren Brinkmann 提交于 
      This adds a pin-control driver for Zynq.

Changes since v2:
- driver-specific DT properties are passed to the core in two arrays,
  one for the actual DT parsing one for the debugfs representation.
  Issue a compiler warning when the number of entries is not the same
  for both arrays.

Changes since v1:
 - fix EMIO_SD1_CD pin name
 - add USB to pinmux options

changes since RFCv2:
 - let Zynq select PINCTRL_ZYNQ. Boot hangs when pinctrl information is
   present in DT but no driver available.
 - add #defines to get rid of magical constants
 - add commas at end of initializers
 - separate changes in mach-zynq in separate patch
 - add driver specific io-standard DT property
 - refactored pinconf set function to not require arguments for
   argument-less properties
 - squash other patches in
   - support for IO-standard property
   - support for low-power mode property
   - migration to pinconf_generic_dt_node_to_map_all()
 - use newly created infrastructure to add pass driver-specific DT
   params to pinconf-generic

changes since RFC:
 - use syscon/regmap to access registers in SLCR space
 - rebase to 3.18: rename enable -> set_mux
 - add kernel-doc
 - support pinconf
   - supported attributes
     - pin-bias: pull up, tristate, disable
     - slew-rate: 0 == slow, 1 == fast; generic pinconf does not display
       argument
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      add958ce
  25. 29 10月, 2014 1 次提交
  27. 25 9月, 2014 1 次提交
  29. 04 9月, 2014 1 次提交
  31. 28 8月, 2014 1 次提交
  33. 28 7月, 2014 1 次提交
  35. 11 7月, 2014 7 次提交
  37. 27 5月, 2014 1 次提交
  39. 23 5月, 2014 2 次提交
  41. 09 5月, 2014 1 次提交
  43. 04 5月, 2014 1 次提交
  45. 24 4月, 2014 1 次提交
  47. 23 4月, 2014 2 次提交
  49. 22 4月, 2014 3 次提交
  51. 14 4月, 2014 1 次提交
  53. 26 3月, 2014 2 次提交