Add a pinctrl/gpio driver for Atmel PIO4 controller available on SAMA5D2
chip family.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.

Remove the argument.

Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Jiang Liu <jiang.liu@linux.intel.com>

Use irq_set_handler_locked() as it avoids a redundant lookup of the
irq descriptor. Search and replacement was done with coccinelle:
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <julia.lawall@lip6.fr>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org

__irq_set_chip_handler_name_locked() is about to be replaced. Use
irq_set_chip_handler_name_locked() instead.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org

?SYNTAX ERROR

irq_desc_get_irq_chip() does not exist. It should
be irq_desc_get_chip(). Tested by compiling
s3c2410_defconfig.

Cc: Thomas Gleixner <tglx@linutronix.de>
Reported-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

If the gpio driver is confused about the numbers for gpio-ranges,
pinctrl_ready_for_gpio_range() may get called with invalid GPIO
causing a NULL pointer exception. Let's instead provide a warning
that allows fixing the problem and return with error.
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There is no reason to break a line shorter than 80 columns.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since commit 323de9ef ("pinctrl: make pinctrl_register() return proper
error code"), pinctrl_register returns an error code rather than NULL on
failure.  Update a driver that was introduced more recently.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@@
expression e,e1,e2;
@@

e = pinctrl_register(...)
... when != e = e1
if (
-   e == NULL
+   IS_ERR(e)
   ) {
     ...
     return
-      e2
+      PTR_ERR(e)
     ;
     }
// </smpl>
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Acked-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since commit 323de9ef ("pinctrl: make pinctrl_register() return proper
error code"), pinctrl_register returns an error code rather than NULL on
failure.  Update some drivers that were introduced more recently.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@@
expression e,e1,e2;
@@

e = pinctrl_register(...)
... when != e = e1
if (
-   e == NULL
+   IS_ERR(e)
   ) {
     ...
     return
-      e2
+      PTR_ERR(e)
     ;
     }
// </smpl>
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Not all gpio banks are necessarily enabled, in the current code this can
lead to null pointer dereferences.

[   51.130000] Unable to handle kernel NULL pointer dereference at virtual address 00000058
[   51.130000] pgd = dee04000
[   51.130000] [00000058] *pgd=3f66d831, *pte=00000000, *ppte=00000000
[   51.140000] Internal error: Oops: 17 [#1] ARM
[   51.140000] Modules linked in:
[   51.140000] CPU: 0 PID: 1664 Comm: cat Not tainted 4.1.1+ #6
[   51.140000] Hardware name: Atmel SAMA5
[   51.140000] task: df6dd880 ti: dec60000 task.ti: dec60000
[   51.140000] PC is at at91_pinconf_get+0xb4/0x200
[   51.140000] LR is at at91_pinconf_get+0xb4/0x200
[   51.140000] pc : [<c01e71a0>]    lr : [<c01e71a0>]    psr: 600f0013
sp : dec61e48  ip : 600f0013  fp : df522538
[   51.140000] r10: df52250c  r9 : 00000058  r8 : 00000068
[   51.140000] r7 : 00000000  r6 : df53c910  r5 : 00000000  r4 : dec61e7c
[   51.140000] r3 : 00000000  r2 : c06746d4  r1 : 00000000  r0 : 00000003
[   51.140000] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[   51.140000] Control: 10c53c7d  Table: 3ee04059  DAC: 00000015
[   51.140000] Process cat (pid: 1664, stack limit = 0xdec60208)
[   51.140000] Stack: (0xdec61e48 to 0xdec62000)
[   51.140000] 1e40:                   00000358 00000000 df522500 ded15f80 c05a9d08 ded15f80
[   51.140000] 1e60: 0000048c 00000061 df522500 ded15f80 c05a9d08 c01e7304 ded15f80 00000000
[   51.140000] 1e80: c01e6008 00000060 0000048c c01e6034 c01e5f6c ded15f80 dec61ec0 00000000
[   51.140000] 1ea0: 00020000 ded6f280 dec61f80 00000001 00000001 c00ae0b8 b6e80000 ded15fb0
[   51.140000] 1ec0: 00000000 00000000 df4bc974 00000055 00000800 ded6f280 b6e80000 ded6f280
[   51.140000] 1ee0: ded6f280 00020000 b6e80000 00000000 00020000 c0090dec c0671e1c dec61fb0
[   51.140000] 1f00: b6f8b510 00000001 00004201 c000924c 00000000 00000003 00000003 00000000
[   51.140000] 1f20: df4bc940 00022000 00000022 c066e188 b6e7f000 c00836f4 000b6e7f ded6f280
[   51.140000] 1f40: ded6f280 b6e80000 dec61f80 ded6f280 00020000 c0091508 00000000 00000003
[   51.140000] 1f60: 00022000 00000000 00000000 ded6f280 ded6f280 00020000 b6e80000 c0091d9c
[   51.140000] 1f80: 00000000 00000000 ffffffff 00020000 00020000 b6e80000 00000003 c000f124
[   51.140000] 1fa0: dec60000 c000efa0 00020000 00020000 00000003 b6e80000 00020000 000271c4
[   51.140000] 1fc0: 00020000 00020000 b6e80000 00000003 7fffe000 00000000 00000000 00020000
[   51.140000] 1fe0: 00000000 bef50b64 00013835 b6f29c76 400f0030 00000003 00000000 00000000
[   51.140000] [<c01e71a0>] (at91_pinconf_get) from [<c01e7304>] (at91_pinconf_dbg_show+0x18/0x2c0)
[   51.140000] [<c01e7304>] (at91_pinconf_dbg_show) from [<c01e6034>] (pinconf_pins_show+0xc8/0xf8)
[   51.140000] [<c01e6034>] (pinconf_pins_show) from [<c00ae0b8>] (seq_read+0x1a0/0x464)
[   51.140000] [<c00ae0b8>] (seq_read) from [<c0090dec>] (__vfs_read+0x20/0xd0)
[   51.140000] [<c0090dec>] (__vfs_read) from [<c0091508>] (vfs_read+0x7c/0x108)
[   51.140000] [<c0091508>] (vfs_read) from [<c0091d9c>] (SyS_read+0x40/0x94)
[   51.140000] [<c0091d9c>] (SyS_read) from [<c000efa0>] (ret_fast_syscall+0x0/0x3c)
[   51.140000] Code: eb010ec2 e30a0d08 e34c005a eb0ae5a7 (e5993000)
[   51.150000] ---[ end trace fb3c370da3ea4794 ]---

Fixes: a0b957f3 ("pinctrl: at91: allow to have disabled gpio bank")
Cc: stable@vger.kernel.org # 3.18
Signed-off-by: NDavid Dueck <davidcdueck@googlemail.com>
Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch implement irq_set_wake to get who is wakeup source and
setup on suspend resume.
Signed-off-by: NMaoguang Meng <maoguang.meng@mediatek.com>
Reviewed-by: NDaniel Kurtz <djkurtz@chromium.org>
Acked-by: NYingjoe Chen <yingjoe.chen@mediatek.com>
Acked-by: NHongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Since our common driver need support main chip and PMU
at the same time, that means it will register two
pinctrl device, and the pinctrl_desc structure should
be used two times.

But pinctrl_desc use global static definition, then
the latest registered pinctrl device will overwrite
the old one's, all members in pinctrl_desc will set to
the new one's, such as name, pins and pins numbers, etc.
This is a bug.

Move pinctrl_desc into mtk_pinctrl, assign new value for
each pinctrl device to fix it.

Cc: stable@vger.kernel.org # v4.1+
Signed-off-by: NHongzhou Yang <hongzhou.yang@mediatek.com>
Reviewed-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add USB0/1 pin groups to R8A7794 PFC driver.
Signed-off-by: NShinobu Uehara <shinobu.uehara.xc@renesas.com>
[Sergei: rebased, renamed, added changelog.]
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The at91-specific irq_{request,release}_resources() callbacks are
identical to the generic ones, modulo the bug fix in 5b76e79c
("gpiolib: irqchip: prevent driver unloading if gpio is used as irq
only").

Until commit 8b67a1f0 ("gpio: don't override irq_*_resources()
callbacks"), the buggy at91-specific callbacks were never used, though.

Hence drop the at91-specific ones in favor of the generic ones.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When running -rt kernel and an interrupt happens on a GPIO line controlled by
Intel Cherryview/Braswell pinctrl driver we get:

 BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
 in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
 Preemption disabled at:[<ffffffff81092e9f>] cpu_startup_entry+0x17f/0x480

 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #16
  ...
 Call Trace:
  <IRQ>  [<ffffffff816283c6>] dump_stack+0x4a/0x61
  [<ffffffff81077e17>] ___might_sleep+0xe7/0x170
  [<ffffffff8162d6cf>] rt_spin_lock+0x1f/0x50
  [<ffffffff812e52ed>] chv_gpio_irq_ack+0x3d/0xa0
  [<ffffffff810a72f5>] handle_edge_irq+0x75/0x180
  [<ffffffff810a3457>] generic_handle_irq+0x27/0x40
  [<ffffffff812e57de>] chv_gpio_irq_handler+0x7e/0x110
  [<ffffffff810050aa>] handle_irq+0xaa/0x190
  ...

This is because desc->lock is raw_spinlock and is held when chv_gpio_irq_ack()
is called by the genirq core. chv_gpio_irq_ack() in turn takes pctrl->lock
which in -rt is an rt-mutex causing might_sleep() rightfully to complain about
sleeping function called from invalid context.

In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.
Suggested-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Intel Baytrail pinctrl driver implements irqchip callbacks which are
called with desc->lock raw_spinlock held. In mainline this is fine because
spinlock resolves to raw_spinlock. However, running the same code in -rt we
get:

 BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
 in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
 Preemption disabled at:[<ffffffff81092e9f>] cpu_startup_entry+0x17f/0x480

 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #13
  ...
 Call Trace:
  <IRQ>  [<ffffffff816283c6>] dump_stack+0x4a/0x61
  [<ffffffff81077e17>] ___might_sleep+0xe7/0x170
  [<ffffffff8162d6cf>] rt_spin_lock+0x1f/0x50
  [<ffffffff812e3b88>] byt_gpio_clear_triggering+0x38/0x60
  [<ffffffff812e3bc1>] byt_irq_mask+0x11/0x20
  [<ffffffff810a7013>] handle_level_irq+0x83/0x150
  [<ffffffff810a3457>] generic_handle_irq+0x27/0x40
  [<ffffffff812e3a5f>] byt_gpio_irq_handler+0x7f/0xc0
  [<ffffffff810050aa>] handle_irq+0xaa/0x190
  ...

This is because in -rt spinlocks are preemptible so taking the driver
private spinlock in irqchip callbacks causes might_sleep() to trigger.

In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.

Also shorten the critical section a bit in few places.
Suggested-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

platform_driver does not need to set an owner as it will be
populated by the driver core.

The semantic patch that makes this change is available
in scripts/coccinelle/api/platform_no_drv_owner.cocci.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Group names should be smc0_nand_grp and smc0_nor_grp, otherwise you'll
get errors like this if you try to pinmux them via the devicetree:
zynq-pinctrl 700.pinctrl: invalid group "smc0_nand_grp" for function "smc0_nand"

Probably a typo while creating these tables.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Acked-by: NSören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NMoritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The pfc in the R8A7790 (and probably others in the R-Car gen 2 family)
supports switching SDHI signals between 3.3V and 1.8V nominal voltage,
and the SD driver should do that when switching to and from UHS modes.

Add a flag for pins that have configurable I/O voltage and SoC
operations to get and set the nominal voltage.  Implement the pinconf
power-source parameter using these operations.
Signed-off-by: NBen Hutchings <ben.hutchings@codethink.co.uk>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

If the gpio DT node has the gpio-ranges property, the range will be
added by the gpio core and doesn't need to be added by the pinctrl
driver.

By having the gpio-ranges property, we have an explicit dependency from
the gpio node to the pinctrl node and we can stop using the deprecated
pinctrl_add_gpio_range() function.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Signed-off-by: NMarcus Cooper <codekipper@gmail.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

To set/get atlas7 pull & drive strength, we use lots of if/else
to check pad type. But except mask value or immediate value, all
actions in these conditional branches are the same.
So we use predefined pull info table and drive strength table
to reduce these redundancy code.
Signed-off-by: NWei Chen <Wei.Chen@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There is a hardware issue in Intel Baytrail where concurrent GPIO register
access might result reads of 0xffffffff and writes might get dropped
completely.

Prevent this from happening by taking the serializing lock in all places
where it is possible that more than one thread might be accessing the
hardware concurrently.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The FSF address is already mentioned in the COPYING file. No need to
duplicate that information to individual files.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: NLin Huang <hl@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Tested-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Trivial change, fix spelling mistake 'invaild' -> 'invalid' in
dev_err message.
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Acked-by: NHongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There is a hardware issue in Intel Braswell/Cherryview where concurrent
GPIO register access might results reads of 0xffffffff and writes might get
dropped.

Prevent this from happening by taking the serializing lock for all places
where it is possible that more than one thread might be accessing the
hardware concurrently.
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The initial version of this driver missed to add I2C ch6 pin-muxing.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Let us see the current value on the input line in debugfs.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

These are user-visible strings, so can exceed 80 columns.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We had not implemented the pm interface of atlas7 pinctrl
and gpio drivers. So when system resumes from sleep, all
pin configuration and gpio status will be lost.

Now, we implement these interfaces to support pm.

At the same time, this patch also drops a lot of if-else
by look-up table for getting and setting pull.
Signed-off-by: NWei Chen <Wei.Chen@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Split the UART pin groups so we can activate RX/TX, CTS/RTS and
the modem pins (DCD, DSR, RI, DTR) as three different groups
with function u0.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:

IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOEN

For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Lee Jones <lee@kernel.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: linux-gpio@vger.kernel.org
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We no longer have to do GPIO initialization before the
pinctrl initialization, instead we can initialize the pinctrl
portions of the driver first and then the GPIO. Thus we can
move GPIO initialization to a subsystem_initcall(), but
not yet to a device_initcall().
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This gets the GPIO ranges out of the driver and into the device
tree where they belong. Standard DT bindings already exist for
this. Since no systems with this are deployed we can just augment
all device trees and the drivers at the same time and simplify
the world.

This also defines the array of GPIO chips related to the pin
controller.

Cc: arm@kernel.org
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The current interrupt parsing code was working by accident, because the
default was actually parsing the first node of interrupts.

While that was mostly working (and the flags were actually ignored), this
binding has never been documented, and doesn't work with SoCs that have
multiple interrupt banks anyway.

Add a proper interrupt xlate function, that uses the same description than
the GPIOs (<bank> <pin> <flags>), that will make things less confusing.

The EINT number will still be used as the hwirq number, but won't be
exposed through the DT.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use dev_err() rather than pr_err() to display the error message.

pinctrl_dev_get_name(pctldev) is no longer necessary because
dev_err() shows which device the message is related to.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use dev_err() rather than pr_err() to display the error message.
(Besides, dev_err() is already used 7 lines below in this function.)

Also, drop the redundant information "on %s" because dev_err() shows
which device the message is related to.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

In order to ease the debugging, add a name to the irq_chips.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The current code uses some custom variable affectations, while we have
common functions to do exactly that. Move to the common functions.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>