- 20 5月, 2015 1 次提交
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由 Zhou Wang 提交于
Add support for x8 links. Signed-off-by: NZhou Wang <wangzhou1@hisilicon.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jingoohan1@gmail.com> Acked-by: NPratyush Anand <pratyush.anand@gmail.com>
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- 07 3月, 2015 1 次提交
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由 Matwey V. Kornilov 提交于
Struct spear13xx_pcie_driver was in initdata, but we passed a pointer to it to platform_driver_register(), which can use the pointer at arbitrary times in the future, even after the initdata is freed. That leads to crashes. Move spear13xx_pcie_driver and things referenced by it (spear13xx_pcie_probe() and dw_pcie_host_init()) out of initdata. [bhelgaas: changelog] Fixes: 6675ef21 ("PCI: spear: Fix Section mismatch compilation warning for probe()") Signed-off-by: NMatwey V. Kornilov <matwey@sai.msu.ru> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> CC: stable@vger.kernel.org # v3.17+
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- 28 1月, 2015 1 次提交
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由 Lucas Stach 提交于
The DesignWare PCIe MSI hardware does not support MSI-X IRQs. Setting those up failed as a side effect of a bug which was fixed by 91f8ae82 ("PCI: designware: Setup and clear exactly one MSI at a time"). Now that this bug is fixed, MSI-X IRQs need to be rejected explicitly; otherwise devices trying to use them may end up with incorrectly working interrupts. Fixes: 91f8ae82 ("PCI: designware: Setup and clear exactly one MSI at a time") Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com> CC: stable@vger.kernel.org # v3.18+
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- 28 12月, 2014 1 次提交
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由 Lorenzo Pieralisi 提交于
Most if not all ARM PCI host controller device drivers either ignore the domain field in the pci_sys_data structure or just increment it every time a host controller is probed, using it as a domain counter. Therefore, instead of relying on pci_sys_data to stash the domain number in a standard location, ARM pcibios code can be moved to the newly introduced generic PCI domains code, implemented in commits: 41e5c0f8 ("of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()") 670ba0c8 ("PCI: Add generic domain handling") ARM code is made to select PCI_DOMAINS_GENERIC by default, which builds core PCI code that assigns the domain number through the generic function: void pci_bus_assign_domain_nr(...) that relies on a DT property to define the domain number or falls back to a counter according to a predefined logic; its usage replaces the current domain assignment code in PCI host controllers present in the kernel. Tested-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NYijing Wang <wangyijing@huawei.com> Reviewed-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> # mvebu Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk> Acked-by: NLucas Stach <l.stach@pengutronix.de> Acked-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NPhil Edworthy <phil.edworthy@renesas.com> Acked-by: NArnd Bergmann <arnd@arndb.de> CC: Mohit Kumar <mohit.kumar@st.com>
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- 23 11月, 2014 2 次提交
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由 Thomas Gleixner 提交于
The PCI/MSI irq chip callbacks mask/unmask_msi_irq have been renamed to pci_msi_mask/unmask_irq to mark them PCI specific. Rename all usage sites. The conversion helper functions are kept around to avoid conflicts in next and will be removed after merging into mainline. Coccinelle assisted conversion. No functional change. Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: x86@kernel.org Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Mohit Kumar <mohit.kumar@st.com> Cc: Simon Horman <horms@verge.net.au> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Yijing Wang <wangyijing@huawei.com>
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由 Jiang Liu 提交于
Rename write_msi_msg() to pci_write_msi_msg() to mark it as PCI specific. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Yijing Wang <wangyijing@huawei.com> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 22 11月, 2014 1 次提交
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由 Yijing Wang 提交于
Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). [bhelgaas: use dw_pcie_msi_chip, not dw_pcie_msi_controller] Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 14 11月, 2014 1 次提交
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由 Jingoo Han 提交于
This patch fixes the following checkpatch warning: WARNING: Missing a blank line after declarations Signed-off-by: NJingoo Han <jg1.han@samsung.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 12 11月, 2014 1 次提交
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由 Yijing Wang 提交于
"msi_chip" isn't very descriptive, so rename it to "msi_controller". That tells a little more about what it does and is already used in device tree bindings. No functional change. [bhelgaas: changelog, change *only* the struct name so it's reviewable] Suggested-by: NBjorn Helgaas <bhelgaas@google.com> Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 02 10月, 2014 2 次提交
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由 Lucas Stach 提交于
Replace them by using the standard kernel bitmap ops. No functional change, but makes the code a lot cleaner. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NJingoo Han <jg1.han@samsung.com>
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由 Yijing Wang 提交于
"msi_attrib.pos" is only used for MSI (not MSI-X), and we already cache the MSI capability offset in "dev->msi_cap". Remove "pos" from the struct msi_attrib and use "dev->msi_cap" directly. [bhelgaas: changelog, fix whitespace] Signed-off-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 01 10月, 2014 1 次提交
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由 Lucas Stach 提交于
The setup_irq function is supposed to set up exactly one MSI IRQ. Multiple IRQ setup is handled differently, to respect the choices made by the upper layers. Also only clear one MSI IRQ at a time; the PCI core will call into this function multiple times if it has to tear down more than one MSI IRQ. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NJingoo Han <jg1.han@samsung.com>
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- 24 9月, 2014 4 次提交
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由 Minghuan Lian 提交于
Add a struct pcie_host_ops .get_msi_data() method for platforms to return their special MSI message data. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMohit KUMAR <mohit.kumar@st.com>
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由 Minghuan Lian 提交于
The struct pcie_host_ops .get_msi_data() method returns the MSI message address. To accurately express its purpose, rename it to .get_msi_addr(). Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMohit KUMAR <mohit.kumar@st.com>
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由 Minghuan Lian 提交于
End address should be equal to start_addr + size - 1. Fix PCI IO resource end address calculation. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMohit KUMAR <mohit.kumar@st.com>
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由 Minghuan Lian 提交于
The code has calculated cfg0_base and cfg1_base when parsing 'reg' or 'ranges' property of PCI DTS node, so remove duplicate calculation. When using 'reg', resource cfg is not used, so this code computed an incorrect configuration base. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMohit KUMAR <mohit.kumar@st.com>
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- 23 9月, 2014 1 次提交
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由 Fabio Estevam 提交于
of_get_address() expects pointers in the third and fourth parameters. Pass NULL in order to fix the following sparse warnings: drivers/pci/host/pcie-designware.c:433:51: warning: Using plain integer as NULL pointer drivers/pci/host/pcie-designware.c:433:58: warning: Using plain integer as NULL pointer Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NLucas Stach <l.stach@pengutronix.de> Acked-by: NJingoo Han <jg1.han@samsung.com>
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- 06 9月, 2014 1 次提交
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由 Pratyush Anand 提交于
The struct pcie_port_info doesn't contain any exclusive information compared to other elements of struct pcie_port. So, keeping a separate structure does not seem very logical. Therefore remove this struct and embed its elements directly into struct pcie_port. Signed-off-by: NPratyush Anand <pratyush.anand@st.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMohit Kumar <mohit.kumar@st.com>
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- 05 9月, 2014 4 次提交
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由 Lucas Stach 提交于
The driver had checks for this sprinkled all over. As we call sys_to_pcie() before every instance of this check, we can move the check to this single location to make things clear. Removing the statements after BUG[_ON]() is safe as the kernel is halted at this point anyway. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NMohit Kumar <mohit.kumar@st.com>
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由 Lucas Stach 提交于
The pci_common_init_dev() call right before will already handle the device resource allocation, so this call was a no-op. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMohit Kumar <mohit.kumar@st.com>
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由 Lucas Stach 提交于
Use pci_create_root_bus() similar to other PCI host controller drivers. The main problem with pci_scan_root_bus() is that it not only creates the root bus, but also activates all devices on the bus. This triggers PCI device driver probe routines, which fail because resources haven't been allocated. To work around this we made sure that the host controller driver is probed early and finishes resource allocation before any other device drivers are registered. Switching to pci_create_root_bus() allows us to get rid of this special handling. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NMohit Kumar <mohit.kumar@st.com>
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由 Lucas Stach 提交于
This allows to explicitly specify the covered bus numbers in the devicetree, which will come in handy once we see a SoC with more than one PCIe host controller instance. Previously the driver relied on the behavior of pci_scan_root_bus() to fill in a range of 0x00-0xff if no valid range was found. We fall back to the same range if no valid DT entry was found to keep backwards compatibility, but now do it explicitly. [bhelgaas: use %pR in error message to avoid duplication] Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NMohit Kumar <mohit.kumar@st.com>
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- 03 9月, 2014 1 次提交
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由 Murali Karicheri 提交于
The Keystone PCI controller is based on v3.65 DesignWare hardware. This version differs from newer versions of the hardware in functional areas discussed below that make it necessary to change dw_pcie_host_init() to support v3.65 based PCI controller. 1. No support for ATU port. Any ATU-specific resource handling code is to be bypassed for v3.65 h/w. 2. MSI controller uses application space to implement MSI and 32 MSI interrupts are multiplexed over 8 IRQs to the host. Hence the code to process MSI IRQ needs to be different. This patch allows platform driver to provide its own irq_domain_ops ptr to irq_domain_add_linear() through an API callback from the DesignWare core driver. 3. MSI interrupt generation requires EP to write to the RC's application register. So enhance the driver to allow setup of inbound access to MSI IRQ register as a post scan bus API callback. Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NMohit KUMAR <mohit.kumar@st.com> Acked-by: NJingoo Han <jg1.han@samsung.com> CC: Santosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Jingoo Han <jg1.han@samsung.com> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org>
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- 23 7月, 2014 4 次提交
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由 Murali Karicheri 提交于
DesignWare v3.65 hardware implements MSI controller registers in application space. This requires updates to the DesignWare core to support controllers based on this older hardware. Add msi_irq_set()/clear() interfaces to allow Set/Clear MSI IRQ enable bit in the application register. Also, v3.65 hardware uses the MSI_IRQ register in application register space to raise MSI IRQ to the RC from EP. Current code uses the standard mechanism as per PCI spec. So add get_msi_data() to get the address of this register so common code can work on both v3.65 and newer hardware. [bhelgaas: changelog] Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NMohit Kumar <mohit.kumar@st.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org>
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由 Murali Karicheri 提交于
DesignWare v3.65 hardware requires application space registers to be configured to access the remote EP config space. To support this, add rd_other_conf() and wr_other_conf() to pcie_host_ops. [bhelgaas: changelog] Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NPratyush Anand <pratyush.anand@st.com> Acked-by: NMohit Kumar <mohit.kumar@st.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> CC: Russell King <linux@arm.linux.org.uk> CC: Grant Likely <grant.likely@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Richard Zhu <r65037@freescale.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Marek Vasut <marex@denx.de> CC: Arnd Bergmann <arnd@arndb.de> CC: Pawel Moll <pawel.moll@arm.com> CC: Mark Rutland <mark.rutland@arm.com> CC: Ian Campbell <ijc+devicetree@hellion.org.uk> CC: Kumar Gala <galak@codeaurora.org> CC: Randy Dunlap <rdunlap@infradead.org> CC: Grant Likely <grant.likely@linaro.org>
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由 Kishon Vijay Abraham I 提交于
In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see only 28-bit addresses. So whenever the CPU issues a read/write request, the 4 most significant bits are used by L3 to determine the target controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff] for the PCIe controller but the PCIe controller will see only [0x00000000-0x0fffffff]. For programming the outbound translation window the *base* should be programmed as 0x00000000. Whenever we try to write to, e.g., 0x20000000, it will be translated to whatever we have programmed in the translation window with base as 0x00000000. This is needed when the dt node is modelled something like this: axi { compatible = "simple-bus"; #size-cells = <1>; #address-cells = <1>; ranges = <0x0 0x20000000 0x10000000 // 28-bit bus 0x51000000 0x51000000 0x3000>; pcie@51000000 { reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>; reg-names = "config", "ti_conf", "rc_dbics"; #address-cells = <3>; #size-cells = <2>; ranges = <0x81000000 0 0 0x03000 0 0x00010000 0x82000000 0 0x20013000 0x13000 0 0xffed000>; }; }; Here the CPU address for configuration space is 0x20013000 and the controller address for configuration space is 0x13000. The controller address should be used while programming the ATU (in order for translation to happen properly in DRA7xx). Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NMohit Kumar <mohit.kumar@st.com> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de>
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由 Kishon Vijay Abraham I 提交于
The configuration address space has so far been specified in *ranges*, however it should be specified in *reg* making it a platform MEM resource. Hence used 'platform_get_resource_*' API to get configuration address space in the designware driver. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NMohit Kumar <mohit.kumar@st.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de>
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- 31 5月, 2014 1 次提交
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由 Lucas Stach 提交于
On i.MX6 the host controller MSI IRQ is shared with PCI legacy INTD. Make sure we don't bail too early from the IRQ handler. The issue is fairly theoretical as it would require a system setup with a PCIe switch where one connected device is using legacy INTD and another one using MSI, but better fix it now. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NRichard Zhu <r65037@freescale.com>
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- 17 4月, 2014 7 次提交
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由 Lucas Stach 提交于
Use new OF interrupt mapping (of_irq_parse_and_map_pci()) when possible. This is the recommended method of doing the IRQ mapping. For old devicetrees we fall back to the previous practice. This makes INTB, INTC, and INTD work on i.MX. Tested-by: NTim Harvey <tharvey@gateworks.com> Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NMarek Vasut <marex@denx.de> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NJingoo Han <jg1.han@samsung.com>
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由 Mohit Kumar 提交于
This patch corrects iATU programming for cfg1, io and mem viewport. Enable ATU only after configuring it. Signed-off-by: NMohit Kumar <mohit.kumar@st.com> Signed-off-by: NAjay Khandelwal <ajay.khandelwal@st.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Cc: stable@vger.kernel.org
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由 Mohit Kumar 提交于
Corrects comment for setting number of lanes. Signed-off-by: NMohit Kumar <mohit.kumar@st.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com>
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由 Andrew Murray 提交于
Serialization of configuration accesses is provided by 'pci_lock' in drivers/pci/access.c thus making the driver's 'conf_lock' superfluous. Signed-off-by: NAndrew Murray <amurray@embedded-bits.co.uk> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Acked-by: NRichard Zhu <r65037@freescale.com>
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由 Lucas Stach 提交于
Use new OF interrupt mapping (of_irq_parse_and_map_pci()) when possible. This is the recommended method of doing the IRQ mapping. For old devicetrees we fall back to the previous practice. This makes INTB, INTC, and INTD work on i.MX. Tested-by: NTim Harvey <tharvey@gateworks.com> Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NMarek Vasut <marex@denx.de> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NJingoo Han <jg1.han@samsung.com>
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由 Mohit Kumar 提交于
This patch corrects iATU programming for cfg1, io and mem viewport. Enable ATU only after configuring it. Signed-off-by: NMohit Kumar <mohit.kumar@st.com> Signed-off-by: NAjay Khandelwal <ajay.khandelwal@st.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Cc: stable@vger.kernel.org
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由 Mohit Kumar 提交于
Corrects comment for setting number of lanes. Signed-off-by: NMohit Kumar <mohit.kumar@st.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com>
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- 05 3月, 2014 1 次提交
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由 Thomas Gleixner 提交于
There is no reason to care about irq_desc in that context, escpecially as irq_data for that interrupt is retrieved as well. Use the proper accessor for the msi descriptor Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Acked-by: NBjorn Helgaas <bhelgaas@google.com> Acked-by: NJingoo Han <jg1.han@samsung.com> Cc: Mohit Kumar <mohit.kumar@st.com> Cc: pci <linux-pci@vger.kernel.org> Link: http://lkml.kernel.org/r/20140223212736.987803648@linutronix.deSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 20 2月, 2014 1 次提交
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由 Mohit Kumar 提交于
The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR 1). The BARs can be configured as follows: - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs This patch corrects 64-bit, non-prefetchable memory BAR configuration implemented in dw driver. Signed-off-by: NMohit Kumar <mohit.kumar@st.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: stable@vger.kernel.org # v3.12+
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- 03 1月, 2014 1 次提交
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由 Jingoo Han 提交于
Fix indent code style and replace 'MSI interrupt controller' of comment with 'MSI controller' to fix the following checkpatch issues: ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line WARNING: line over 80 characters Signed-off-by: NJingoo Han <jg1.han@samsung.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 21 12月, 2013 2 次提交
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由 Pratyush Anand 提交于
pp->io_base, which is the input of the outbound IO address translation unit, should be the CPU address. It was incorrectly programmed to the realio address. We should pass global_io_offset rather than sys->io_offset to pci_ioremap_io(), so we map the new window into the first available spot in the Linux view of the I/O space. We must also pass CPU address instead of realio address to pci_ioremap_io(). This patch fixes above issue. It has been tested with Lecroy PTC in AIC mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise. Tested-by: NMohit Kumar <mohit.kumar@st.com> Tested-by: NTim Harvey <tharvey@gateworks.com> Signed-off-by: NPratyush Anand <pratyush.anand@st.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marek Vasut <marex@denx.de Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NJingoo Han <jg1.han@samsung.com> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
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由 Pratyush Anand 提交于
The cfg_read/write functions are DesignWare-specific. Add dw_pcie prefix to avoid collision in global name space. Tested-by: NJingoo Han <jg1.han@samsung.com> Signed-off-by: NPratyush Anand <pratyush.anand@st.com> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com> Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: NJingoo Han <jg1.han@samsung.com>
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