提交 c23fdc7d 编写于 作者: M Mohit Kumar 提交者: Bjorn Helgaas

PCI: designware: Fix comment for setting number of lanes

Corrects comment for setting number of lanes.
Signed-off-by: NMohit Kumar <mohit.kumar@st.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>
上级 140ab645
......@@ -764,7 +764,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 membase;
u32 memlimit;
/* set the number of lines as 4 */
/* set the number of lanes */
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
val &= ~PORT_LINK_MODE_MASK;
switch (pp->lanes) {
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册