• M
    PCI: designware: Add MSI-related pcie_host_ops for v3.65 hardware · 2f37c5a8
    Murali Karicheri 提交于
    DesignWare v3.65 hardware implements MSI controller registers in
    application space.  This requires updates to the DesignWare core to
    support controllers based on this older hardware.
    
    Add msi_irq_set()/clear() interfaces to allow Set/Clear MSI IRQ enable bit
    in the application register.  Also, v3.65 hardware uses the MSI_IRQ
    register in application register space to raise MSI IRQ to the RC from EP.
    Current code uses the standard mechanism as per PCI spec.  So add
    get_msi_data() to get the address of this register so common code can
    work on both v3.65 and newer hardware.
    
    [bhelgaas: changelog]
    Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
    Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
    Reviewed-by: NPratyush Anand <pratyush.anand@st.com>
    Acked-by: NMohit Kumar <mohit.kumar@st.com>
    Acked-by: NJingoo Han <jg1.han@samsung.com>
    Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
    CC: Russell King <linux@arm.linux.org.uk>
    CC: Grant Likely <grant.likely@linaro.org>
    CC: Rob Herring <robh+dt@kernel.org>
    CC: Richard Zhu <r65037@freescale.com>
    CC: Kishon Vijay Abraham I <kishon@ti.com>
    CC: Marek Vasut <marex@denx.de>
    CC: Arnd Bergmann <arnd@arndb.de>
    CC: Pawel Moll <pawel.moll@arm.com>
    CC: Mark Rutland <mark.rutland@arm.com>
    CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
    CC: Kumar Gala <galak@codeaurora.org>
    CC: Randy Dunlap <rdunlap@infradead.org>
    CC: Grant Likely <grant.likely@linaro.org>
    2f37c5a8
pcie-designware.c 23.5 KB