提交 d3f8c0ab 编写于 作者: R Rex Zhu 提交者: Alex Deucher

drm/amd/powerplay: refine interface in struct pp_smumgr_func

unify to use struct hwmgr as function parameter in
smumgr.
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 e9c7577c
master alk-4.19.24 alk-4.19.30 alk-4.19.34 alk-4.19.36 alk-4.19.43 alk-4.19.48 alk-4.19.57 ck-4.19.67 ck-4.19.81 ck-4.19.91 github/fork/deepanshu1422/fix-typo-in-comment github/fork/haosdent/fix-typo linux-next v4.19.91 v4.19.90 v4.19.89 v4.19.88 v4.19.87 v4.19.86 v4.19.85 v4.19.84 v4.19.83 v4.19.82 v4.19.81 v4.19.80 v4.19.79 v4.19.78 v4.19.77 v4.19.76 v4.19.75 v4.19.74 v4.19.73 v4.19.72 v4.19.71 v4.19.70 v4.19.69 v4.19.68 v4.19.67 v4.19.66 v4.19.65 v4.19.64 v4.19.63 v4.19.62 v4.19.61 v4.19.60 v4.19.59 v4.19.58 v4.19.57 v4.19.56 v4.19.55 v4.19.54 v4.19.53 v4.19.52 v4.19.51 v4.19.50 v4.19.49 v4.19.48 v4.19.47 v4.19.46 v4.19.45 v4.19.44 v4.19.43 v4.19.42 v4.19.41 v4.19.40 v4.19.39 v4.19.38 v4.19.37 v4.19.36 v4.19.35 v4.19.34 v4.19.33 v4.19.32 v4.19.31 v4.19.30 v4.19.29 v4.19.28 v4.19.27 v4.19.26 v4.19.25 v4.19.24 v4.19.23 v4.19.22 v4.19.21 v4.19.20 v4.19.19 v4.19.18 v4.19.17 v4.19.16 v4.19.15 v4.19.14 v4.19.13 v4.19.12 v4.19.11 v4.19.10 v4.19.9 v4.19.8 v4.19.7 v4.19.6 v4.19.5 v4.19.4 v4.19.3 v4.19.2 v4.19.1 v4.19 v4.19-rc8 v4.19-rc7 v4.19-rc6 v4.19-rc5 v4.19-rc4 v4.19-rc3 v4.19-rc2 v4.19-rc1 ck-release-21 ck-release-20 ck-release-19.2 ck-release-19.1 ck-release-19 ck-release-18 ck-release-17.2 ck-release-17.1 ck-release-17 ck-release-16 ck-release-15.1 ck-release-15 ck-release-14 ck-release-13.2 ck-release-13 ck-release-12 ck-release-11 ck-release-10 ck-release-9 ck-release-7 alk-release-15 alk-release-14 alk-release-13.2 alk-release-13 alk-release-12 alk-release-11 alk-release-10 alk-release-9 alk-release-7
无相关合并请求
......@@ -83,7 +83,7 @@ static int pp_sw_init(void *handle)
if (smumgr->smumgr_funcs->smu_init == NULL)
return -EINVAL;
ret = smumgr->smumgr_funcs->smu_init(smumgr);
ret = smumgr->smumgr_funcs->smu_init(pp_handle->hwmgr);
pr_info("amdgpu: powerplay sw initialized\n");
}
......@@ -103,7 +103,7 @@ static int pp_sw_fini(void *handle)
if (smumgr->smumgr_funcs->smu_fini == NULL)
return -EINVAL;
ret = smumgr->smumgr_funcs->smu_fini(smumgr);
ret = smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
}
return ret;
}
......@@ -122,9 +122,9 @@ static int pp_hw_init(void *handle)
if (smumgr->smumgr_funcs->start_smu == NULL)
return -EINVAL;
if(smumgr->smumgr_funcs->start_smu(smumgr)) {
if(smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr)) {
pr_err("smc start failed\n");
smumgr->smumgr_funcs->smu_fini(smumgr);
smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
return -EINVAL;;
}
if (ret == PP_DPM_DISABLED)
......@@ -246,10 +246,10 @@ static int pp_resume(void *handle)
if (smumgr->smumgr_funcs->start_smu == NULL)
return -EINVAL;
ret = smumgr->smumgr_funcs->start_smu(smumgr);
ret = smumgr->smumgr_funcs->start_smu(pp_handle->hwmgr);
if (ret) {
pr_err("smc start failed\n");
smumgr->smumgr_funcs->smu_fini(smumgr);
smumgr->smumgr_funcs->smu_fini(pp_handle->hwmgr);
return ret;
}
......
......@@ -113,12 +113,12 @@ int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
PHM_PlatformCaps_UVDDPM)) {
cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled;
dpm_features |= UVD_DPM_MASK;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
} else {
dpm_features |= UVD_DPM_MASK;
cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
}
return 0;
......@@ -134,12 +134,12 @@ int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
PHM_PlatformCaps_VCEDPM)) {
cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled;
dpm_features |= VCE_DPM_MASK;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
} else {
dpm_features |= VCE_DPM_MASK;
cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
}
......
......@@ -162,8 +162,8 @@ static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
if (cz_hwmgr->max_sclk_level == 0) {
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel);
cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr) + 1;
}
return cz_hwmgr->max_sclk_level;
......@@ -462,7 +462,7 @@ static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
if (!hwmgr->need_pp_table_upload)
return 0;
ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
ret = smum_download_powerplay_table(hwmgr, &table);
PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
"Fail to get clock table from SMU!", return -EINVAL;);
......@@ -554,7 +554,7 @@ static int cz_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
(uint8_t)dividers.pll_post_divider;
}
ret = smum_upload_powerplay_table(hwmgr->smumgr);
ret = smum_upload_powerplay_table(hwmgr);
return ret;
}
......@@ -598,8 +598,8 @@ static int cz_init_uvd_limit(struct pp_hwmgr *hwmgr)
cz_hwmgr->uvd_dpm.soft_min_clk = 0;
cz_hwmgr->uvd_dpm.hard_min_clk = 0;
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
level = smum_get_argument(hwmgr->smumgr);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel);
level = smum_get_argument(hwmgr);
if (level < table->count)
clock = table->entries[level].vclk;
......@@ -625,8 +625,8 @@ static int cz_init_vce_limit(struct pp_hwmgr *hwmgr)
cz_hwmgr->vce_dpm.soft_min_clk = 0;
cz_hwmgr->vce_dpm.hard_min_clk = 0;
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
level = smum_get_argument(hwmgr->smumgr);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel);
level = smum_get_argument(hwmgr);
if (level < table->count)
clock = table->entries[level].ecclk;
......@@ -652,8 +652,8 @@ static int cz_init_acp_limit(struct pp_hwmgr *hwmgr)
cz_hwmgr->acp_dpm.soft_min_clk = 0;
cz_hwmgr->acp_dpm.hard_min_clk = 0;
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
level = smum_get_argument(hwmgr->smumgr);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel);
level = smum_get_argument(hwmgr);
if (level < table->count)
clock = table->entries[level].acpclk;
......@@ -709,7 +709,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
cz_hwmgr->sclk_dpm.hard_min_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkHardMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.hard_min_clk,
......@@ -735,7 +735,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
cz_hwmgr->sclk_dpm.soft_min_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk,
......@@ -746,7 +746,7 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_StablePState) &&
cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
cz_hwmgr->sclk_dpm.soft_max_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk,
......@@ -766,7 +766,7 @@ static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepSclk,
clks);
}
......@@ -779,7 +779,7 @@ static int cz_set_watermark_threshold(struct pp_hwmgr *hwmgr)
struct cz_hwmgr *cz_hwmgr =
(struct cz_hwmgr *)(hwmgr->backend);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetWatermarkFrequency,
cz_hwmgr->sclk_dpm.soft_max_clk);
......@@ -794,13 +794,13 @@ static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, b
if (enable) {
PP_DBG_LOG("enable Low Memory PState.\n");
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableLowMemoryPstate,
(lock ? 1 : 0));
} else {
PP_DBG_LOG("disable Low Memory PState.\n");
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableLowMemoryPstate,
(lock ? 1 : 0));
}
......@@ -820,7 +820,7 @@ static int cz_disable_nb_dpm(struct pp_hwmgr *hwmgr)
cz_nbdpm_pstate_enable_disable(hwmgr, true, true);
dpm_features |= NB_DPM_MASK;
ret = smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr,
hwmgr,
PPSMC_MSG_DisableAllSmuFeatures,
dpm_features);
if (ret == 0)
......@@ -841,7 +841,7 @@ static int cz_enable_nb_dpm(struct pp_hwmgr *hwmgr)
PP_DBG_LOG("enabling ALL SMU features.\n");
dpm_features |= NB_DPM_MASK;
ret = smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr,
hwmgr,
PPSMC_MSG_EnableAllSmuFeatures,
dpm_features);
if (ret == 0)
......@@ -968,7 +968,7 @@ static int cz_start_dpm(struct pp_hwmgr *hwmgr)
cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
dpm_features |= SCLK_DPM_MASK;
ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
ret = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_EnableAllSmuFeatures,
dpm_features);
......@@ -984,7 +984,7 @@ static int cz_stop_dpm(struct pp_hwmgr *hwmgr)
if (cz_hwmgr->dpm_flags & DPMFlags_SCLK_Enabled) {
dpm_features |= SCLK_DPM_MASK;
cz_hwmgr->dpm_flags &= ~DPMFlags_SCLK_Enabled;
ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
ret = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_DisableAllSmuFeatures,
dpm_features);
}
......@@ -998,13 +998,13 @@ static int cz_program_bootup_state(struct pp_hwmgr *hwmgr)
cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMin));
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk,
......@@ -1026,9 +1026,9 @@ static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
int result;
unsigned long features;
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0);
if (result == 0) {
features = smum_get_argument(hwmgr->smumgr);
features = smum_get_argument(hwmgr);
if (features & check_feature)
return true;
}
......@@ -1178,13 +1178,13 @@ static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk,
PPSMC_MSG_SetSclkSoftMin));
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk,
......@@ -1216,13 +1216,13 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
cz_hwmgr->sclk_dpm.soft_max_clk = clock;
cz_hwmgr->sclk_dpm.hard_max_clk = clock;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMin));
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_max_clk,
......@@ -1235,13 +1235,13 @@ static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
{
struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk,
PPSMC_MSG_SetSclkSoftMax));
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
cz_get_sclk_level(hwmgr,
cz_hwmgr->sclk_dpm.soft_min_clk,
......@@ -1281,7 +1281,7 @@ int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating))
return smum_send_msg_to_smc(hwmgr->smumgr,
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_UVDPowerOFF);
return 0;
}
......@@ -1293,11 +1293,11 @@ int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDDynamicPowerGating)) {
return smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr,
hwmgr,
PPSMC_MSG_UVDPowerON, 1);
} else {
return smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr,
hwmgr,
PPSMC_MSG_UVDPowerON, 0);
}
}
......@@ -1319,7 +1319,7 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
cz_hwmgr->uvd_dpm.hard_min_clk =
ptable->entries[ptable->count - 1].vclk;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetUvdHardMin,
cz_get_uvd_level(hwmgr,
cz_hwmgr->uvd_dpm.hard_min_clk,
......@@ -1349,7 +1349,7 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
cz_hwmgr->vce_dpm.hard_min_clk =
ptable->entries[ptable->count - 1].ecclk;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkHardMin,
cz_get_eclk_level(hwmgr,
cz_hwmgr->vce_dpm.hard_min_clk,
......@@ -1357,15 +1357,15 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
} else {
/*Program HardMin based on the vce_arbiter.ecclk */
if (hwmgr->vce_arbiter.ecclk == 0) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkHardMin, 0);
/* disable ECLK DPM 0. Otherwise VCE could hang if
* switching SCLK from DPM 0 to 6/7 */
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkSoftMin, 1);
} else {
cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetEclkHardMin,
cz_get_eclk_level(hwmgr,
cz_hwmgr->vce_dpm.hard_min_clk,
......@@ -1379,7 +1379,7 @@ int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating))
return smum_send_msg_to_smc(hwmgr->smumgr,
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerOFF);
return 0;
}
......@@ -1388,7 +1388,7 @@ int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_VCEPowerGating))
return smum_send_msg_to_smc(hwmgr->smumgr,
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerON);
return 0;
}
......@@ -1538,7 +1538,7 @@ static void cz_hw_print_display_cfg(
PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
data);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDisplaySizePowerParams,
data);
}
......@@ -1603,10 +1603,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
switch (type) {
case PP_SCLK:
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMin,
mask);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSclkSoftMax,
mask);
break;
......@@ -1848,7 +1848,7 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
*((uint32_t *)value) = 0;
return 0;
case AMDGPU_PP_SENSOR_GPU_LOAD:
result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity);
if (0 == result) {
activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
activity_percent = activity_percent > 100 ? 100 : activity_percent;
......
......@@ -818,7 +818,7 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
for (i = 0; i < vddc_table->count; i++) {
if (req_vddc <= vddc_table->entries[i].vddc) {
req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_VddC_Request, req_volt);
return;
}
......
......@@ -174,33 +174,33 @@ static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) {
rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100;
rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMinVcn,
(rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min);
}
if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinSocclkByFreq,
hwmgr->gfx_arbiter.sclk_hard_min / 100);
rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq);
rv_read_arg_from_smc(hwmgr, &rv_data->soc_actual_hard_min_freq);
}
if ((hwmgr->gfx_arbiter.gfxclk != 0) &&
(rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinVideoGfxclkFreq,
hwmgr->gfx_arbiter.gfxclk / 100);
rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->gfx_actual_soft_min_freq);
rv_read_arg_from_smc(hwmgr, &rv_data->gfx_actual_soft_min_freq);
}
if ((hwmgr->gfx_arbiter.fclk != 0) &&
(rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) {
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinVideoFclkFreq,
hwmgr->gfx_arbiter.fclk / 100);
rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->fabric_actual_soft_min_freq);
rv_read_arg_from_smc(hwmgr, &rv_data->fabric_actual_soft_min_freq);
}
return 0;
......@@ -212,7 +212,7 @@ static int rv_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
if (rv_data->need_min_deep_sleep_dcefclk && rv_data->deep_sleep_dcefclk != clock/100) {
rv_data->deep_sleep_dcefclk = clock/100;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetMinDeepSleepDcefclk,
rv_data->deep_sleep_dcefclk);
}
......@@ -225,7 +225,7 @@ static int rv_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
if (rv_data->num_active_display != count) {
rv_data->num_active_display = count;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetDisplayCount,
rv_data->num_active_display);
}
......@@ -277,7 +277,7 @@ static int rv_disable_gfx_off(struct pp_hwmgr *hwmgr)
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
if (rv_data->gfx_off_controled_by_driver)
smum_send_msg_to_smc(hwmgr->smumgr,
smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_DisableGfxOff);
return 0;
......@@ -293,7 +293,7 @@ static int rv_enable_gfx_off(struct pp_hwmgr *hwmgr)
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
if (rv_data->gfx_off_controled_by_driver)
smum_send_msg_to_smc(hwmgr->smumgr,
smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_EnableGfxOff);
return 0;
......@@ -383,7 +383,7 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
DpmClocks_t *table = &(rv_data->clock_table);
struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
result = rv_copy_table_from_smc(hwmgr->smumgr, (uint8_t *)table, CLOCKTABLE);
result = rv_copy_table_from_smc(hwmgr, (uint8_t *)table, CLOCKTABLE);
PP_ASSERT_WITH_CODE((0 == result),
"Attempt to copy clock table from smc failed",
......@@ -799,7 +799,7 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
return -EINVAL;
}
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg,
result = smum_send_msg_to_smc_with_parameter(hwmgr, msg,
clk_freq);
return result;
......
......@@ -27,21 +27,21 @@
static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
return smum_send_msg_to_smc(hwmgr, enable ?
PPSMC_MSG_UVDDPM_Enable :
PPSMC_MSG_UVDDPM_Disable);
}
static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
return smum_send_msg_to_smc(hwmgr, enable ?
PPSMC_MSG_VCEDPM_Enable :
PPSMC_MSG_VCEDPM_Disable);
}
static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
return smum_send_msg_to_smc(hwmgr, enable ?
PPSMC_MSG_SAMUDPM_Enable :
PPSMC_MSG_SAMUDPM_Disable);
}
......@@ -70,7 +70,7 @@ static int smu7_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_uvd_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr,
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_UVDPowerOFF);
return 0;
}
......@@ -80,10 +80,10 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
if (phm_cf_want_uvd_power_gating(hwmgr)) {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDDynamicPowerGating)) {
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDPowerON, 1);
} else {
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDPowerON, 0);
}
}
......@@ -94,7 +94,7 @@ static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_vce_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr,
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerOFF);
return 0;
}
......@@ -102,7 +102,7 @@ static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
{
if (phm_cf_want_vce_power_gating(hwmgr))
return smum_send_msg_to_smc(hwmgr->smumgr,
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_VCEPowerON);
return 0;
}
......@@ -111,7 +111,7 @@ static int smu7_powerdown_samu(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating))
return smum_send_msg_to_smc(hwmgr->smumgr,
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SAMPowerOFF);
return 0;
}
......@@ -120,7 +120,7 @@ static int smu7_powerup_samu(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SamuPowerGating))
return smum_send_msg_to_smc(hwmgr->smumgr,
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_SAMPowerON);
return 0;
}
......@@ -235,7 +235,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_CGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
if (PP_STATE_SUPPORT_LS & *msg_id) {
......@@ -245,7 +245,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_CGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -258,7 +258,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_3DCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
......@@ -269,7 +269,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_3DLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -282,7 +282,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_RLC_LS_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -295,7 +295,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_GFX_CP_LS_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -309,7 +309,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
CG_GFX_OTHERS_MGCG_MASK);
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -329,7 +329,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_BIF_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
if (PP_STATE_SUPPORT_LS & *msg_id) {
......@@ -339,7 +339,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_BIF_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -352,7 +352,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_MC_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
......@@ -363,7 +363,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_MC_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -376,7 +376,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_DRM_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
if (PP_STATE_SUPPORT_LS & *msg_id) {
......@@ -386,7 +386,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_DRM_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -399,7 +399,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_HDP_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
......@@ -410,7 +410,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_HDP_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -423,7 +423,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_SDMA_MGCG_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
......@@ -434,7 +434,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_SDMA_MGLS_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -447,7 +447,7 @@ int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
value = CG_SYS_ROM_MASK;
if (smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr, msg, value))
hwmgr, msg, value))
return -EINVAL;
}
break;
......@@ -487,9 +487,9 @@ int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
active_cus = sys_info.value;
if (enable)
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_GFX_CU_PG_ENABLE, active_cus);
else
return smum_send_msg_to_smc(hwmgr->smumgr,
return smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GFX_CU_PG_DISABLE);
}
......@@ -660,7 +660,7 @@ static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
didt_block |= block_en << TCP_Enable_SHIFT;
if (enable)
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, didt_block);
result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Didt_Block_Function, didt_block);
return result;
}
......@@ -781,7 +781,7 @@ int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result);
if (hwmgr->chip_id == CHIP_POLARIS11) {
result = smum_send_msg_to_smc(hwmgr->smumgr,
result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_EnableDpmDidt));
PP_ASSERT_WITH_CODE((0 == result),
"Failed to enable DPM DIDT.", return result);
......@@ -809,7 +809,7 @@ int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
"Post DIDT enable clock gating failed.",
return result);
if (hwmgr->chip_id == CHIP_POLARIS11) {
result = smum_send_msg_to_smc(hwmgr->smumgr,
result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_DisableDpmDidt));
PP_ASSERT_WITH_CODE((0 == result),
"Failed to disable DPM DIDT.", return result);
......@@ -827,7 +827,7 @@ int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_CAC)) {
int smc_result;
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_EnableCac));
PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable CAC in SMC.", result = -1);
......@@ -843,7 +843,7 @@ int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr)
int result = 0;
if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) {
int smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
int smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_DisableCac));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable CAC in SMC.", result = -1);
......@@ -859,7 +859,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_PkgPwrLimit)
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PkgPwrSetLimit, n);
return 0;
}
......@@ -867,7 +867,7 @@ int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr,
uint32_t target_tdp)
{
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
}
......@@ -888,7 +888,7 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->enable_tdc_limit_feature) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_TDCLimitEnable));
PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable TDCLimit in SMC.", result = -1;);
......@@ -898,7 +898,7 @@ int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
}
if (data->enable_pkg_pwr_tracking_feature) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
PP_ASSERT_WITH_CODE((0 == smc_result),
"Failed to enable PkgPwrTracking in SMC.", result = -1;);
......@@ -927,7 +927,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_TDCLimit) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_TDCLimitDisable));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable TDCLimit in SMC.",
......@@ -936,7 +936,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_DTE) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_DisableDTE));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable DTE in SMC.",
......@@ -945,7 +945,7 @@ int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
smc_result = smum_send_msg_to_smc(hwmgr,
(uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable PkgPwrTracking in SMC.",
......
......@@ -152,7 +152,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM))
hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
......@@ -165,12 +165,12 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
} else {
cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
}
if (!result && hwmgr->thermal_controller.
advanceFanControlParameters.ucTargetTemperature)
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanTemperatureTarget,
hwmgr->thermal_controller.
advanceFanControlParameters.ucTargetTemperature);
......@@ -183,7 +183,7 @@ int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
{
hwmgr->fan_ctrl_enabled = false;
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl);
return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl);
}
/**
......@@ -371,7 +371,7 @@ static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
CG_THERMAL_INT, THERM_INT_MASK, alert);
/* send message to SMU to enable internal thermal interrupts */
smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable);
}
/**
......@@ -389,7 +389,7 @@ int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr)
CG_THERMAL_INT, THERM_INT_MASK, alert);
/* send message to SMU to disable internal thermal interrupts */
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable);
return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable);
}
/**
......
......@@ -926,7 +926,7 @@ static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
if (enable) {
/* For Vega10, SMC does not support any mask yet. */
result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!");
}
}
......@@ -1243,7 +1243,7 @@ int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
}
if (0 == result) {
PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
PP_ASSERT_WITH_CODE((!vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
"[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
data->smu_features[GNLD_DIDT].enabled = true;
}
......@@ -1290,7 +1290,7 @@ int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
}
if (0 == result) {
PP_ASSERT_WITH_CODE((0 != vega10_enable_smc_features(hwmgr->smumgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
PP_ASSERT_WITH_CODE((0 != vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap)),
"[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
data->smu_features[GNLD_DIDT].enabled = false;
}
......@@ -1344,7 +1344,7 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
(struct vega10_hwmgr *)(hwmgr->backend);
if (data->registry_data.enable_pkg_pwr_tracking_feature)
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetPptLimit, n);
return 0;
......@@ -1363,13 +1363,13 @@ int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->smu_features[GNLD_PPT].supported)
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
"Attempt to enable PPT feature Failed!",
data->smu_features[GNLD_PPT].supported = false);
if (data->smu_features[GNLD_TDC].supported)
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
"Attempt to enable PPT feature Failed!",
data->smu_features[GNLD_TDC].supported = false);
......@@ -1390,13 +1390,13 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
if (data->smu_features[GNLD_PPT].supported)
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
"Attempt to disable PPT feature Failed!",
data->smu_features[GNLD_PPT].supported = false);
if (data->smu_features[GNLD_TDC].supported)
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
"Attempt to disable PPT feature Failed!",
data->smu_features[GNLD_TDC].supported = false);
......@@ -1408,7 +1408,7 @@ int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
static int vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
uint32_t adjust_percent)
{
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
return smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
}
......
......@@ -31,11 +31,11 @@
static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
{
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetCurrentRpm),
"Attempt to get current RPM from SMC Failed!",
return -1);
PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr->smumgr,
PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(hwmgr,
current_rpm),
"Attempt to read current RPM from SMC Failed!",
return -1);
......@@ -199,7 +199,7 @@ static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
hwmgr->smumgr, true,
hwmgr, true,
data->smu_features[GNLD_FAN_CONTROL].
smu_feature_bitmap),
"Attempt to Enable FAN CONTROL feature Failed!",
......@@ -216,7 +216,7 @@ static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
if (data->smu_features[GNLD_FAN_CONTROL].supported) {
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
hwmgr->smumgr, false,
hwmgr, false,
data->smu_features[GNLD_FAN_CONTROL].
smu_feature_bitmap),
"Attempt to Enable FAN CONTROL feature Failed!",
......@@ -458,7 +458,7 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
if (data->smu_features[GNLD_FW_CTF].enabled)
printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
true,
data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
"Attempt to Enable FW CTF feature Failed!",
......@@ -490,7 +490,7 @@ int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
false,
data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
"Attempt to disable FW CTF feature Failed!",
......@@ -546,7 +546,7 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
table->FanTargetTemperature = hwmgr->thermal_controller.
advanceFanControlParameters.usTMax;
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanTemperatureTarget,
(uint32_t)table->FanTargetTemperature);
......@@ -575,7 +575,7 @@ int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
table->FanStartTemp = hwmgr->thermal_controller.
advanceFanControlParameters.usZeroRPMStartTemperature;
ret = vega10_copy_table_to_smc(hwmgr->smumgr,
ret = vega10_copy_table_to_smc(hwmgr,
(uint8_t *)(&(data->smc_state_table.pp_table)), PPTABLE);
if (ret)
pr_info("Failed to update Fan Control Table in PPTable!");
......
......@@ -103,21 +103,21 @@ enum SMU_MAC_DEFINITION {
struct pp_smumgr_func {
int (*smu_init)(struct pp_smumgr *smumgr);
int (*smu_fini)(struct pp_smumgr *smumgr);
int (*start_smu)(struct pp_smumgr *smumgr);
int (*check_fw_load_finish)(struct pp_smumgr *smumgr,
int (*smu_init)(struct pp_hwmgr *hwmgr);
int (*smu_fini)(struct pp_hwmgr *hwmgr);
int (*start_smu)(struct pp_hwmgr *hwmgr);
int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
uint32_t firmware);
int (*request_smu_load_fw)(struct pp_smumgr *smumgr);
int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr,
int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
uint32_t firmware);
int (*get_argument)(struct pp_smumgr *smumgr);
int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg);
int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr,
int (*get_argument)(struct pp_hwmgr *hwmgr);
int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter);
int (*download_pptable_settings)(struct pp_smumgr *smumgr,
int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
void **table);
int (*upload_pptable_settings)(struct pp_smumgr *smumgr);
int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
......@@ -132,7 +132,7 @@ struct pp_smumgr_func {
bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
struct amd_pp_profile *request);
bool (*is_hw_avfs_present)(struct pp_smumgr *smumgr);
bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
};
struct pp_smumgr {
......@@ -148,30 +148,30 @@ struct pp_smumgr {
extern int smum_early_init(struct pp_instance *handle);
extern int smum_get_argument(struct pp_smumgr *smumgr);
extern int smum_get_argument(struct pp_hwmgr *hwmgr);
extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table);
extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr);
extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr);
extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter);
extern int smum_wait_on_register(struct pp_smumgr *smumgr,
extern int smum_wait_on_register(struct pp_hwmgr *hwmgr,
uint32_t index, uint32_t value, uint32_t mask);
extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
extern int smum_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
uint32_t index, uint32_t value, uint32_t mask);
extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
extern int smum_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
uint32_t indirect_port, uint32_t index,
uint32_t value, uint32_t mask);
extern void smum_wait_for_indirect_register_unequal(
struct pp_smumgr *smumgr,
struct pp_hwmgr *hwmgr,
uint32_t indirect_port, uint32_t index,
uint32_t value, uint32_t mask);
......@@ -181,7 +181,7 @@ extern int smu_allocate_memory(void *device, uint32_t size,
void **kptr, void *handle);
extern int smu_free_memory(void *device, void *handle);
extern int vega10_smum_init(struct pp_smumgr *smumgr);
extern int vega10_smum_init(struct pp_hwmgr *hwmgr);
extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
......@@ -193,44 +193,44 @@ extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
extern uint32_t smum_get_offsetof(struct pp_smumgr *smumgr,
extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr,
uint32_t type, uint32_t member);
extern uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value);
extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value);
extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
struct amd_pp_profile *request);
extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr);
extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
#define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
port, index, value, mask) \
smum_wait_on_indirect_register(smumgr, \
smum_wait_on_indirect_register(hwmgr, \
mm##port##_INDEX, index, value, mask)
#define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
#define SMUM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
#define SMUM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
SMUM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field) )
#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
#define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
index, value, mask) \
smum_wait_for_register_unequal(smumgr, \
smum_wait_for_register_unequal(hwmgr, \
index, value, mask)
#define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask) \
SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
#define SMUM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask) \
SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
mm##reg, value, mask)
#define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval) \
SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, \
#define SMUM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval) \
SMUM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, \
(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field))
......@@ -250,22 +250,22 @@ extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr);
SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
reg, field)
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, \
port, index, value, mask) \
smum_wait_on_indirect_register(smumgr, \
smum_wait_on_indirect_register(hwmgr, \
mm##port##_INDEX_0, index, value, mask)
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, \
port, index, value, mask) \
smum_wait_for_indirect_register_unequal(smumgr, \
smum_wait_for_indirect_register_unequal(hwmgr, \
mm##port##_INDEX_0, index, value, mask)
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
#define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
/*Operations on named fields.*/
......@@ -290,25 +290,25 @@ extern bool smum_is_hw_avfs_present(struct pp_smumgr *smumgr);
reg, field, fieldval))
#define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \
#define SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, \
(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field))
#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \
#define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
(fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field))
#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask) \
smum_wait_for_indirect_register_unequal(smumgr, \
#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
smum_wait_for_indirect_register_unequal(hwmgr, \
mm##port##_INDEX, index, value, mask)
#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
#define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask) \
SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
#define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
SMUM_FIELD_MASK(reg, field) )
#endif
......@@ -94,7 +94,7 @@ static const struct ci_pt_defaults defaults_saturn_xt = {
};
static int ci_set_smc_sram_address(struct pp_smumgr *smumgr,
static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr,
uint32_t smc_addr, uint32_t limit)
{
if ((0 != (3 & smc_addr))
......@@ -103,12 +103,12 @@ static int ci_set_smc_sram_address(struct pp_smumgr *smumgr,
return -EINVAL;
}
cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, smc_addr);
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr);
SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
return 0;
}
static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit)
{
int result;
......@@ -129,12 +129,12 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
/* Bytes are written into the SMC address space with the MSB first. */
data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
result = ci_set_smc_sram_address(smumgr, addr, limit);
result = ci_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result)
return result;
cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
src += 4;
byte_count -= 4;
......@@ -145,13 +145,13 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
data = 0;
result = ci_set_smc_sram_address(smumgr, addr, limit);
result = ci_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result)
return result;
original_data = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0);
original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
extra_shift = 8 * (4 - byte_count);
......@@ -165,61 +165,61 @@ static int ci_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add
data |= (original_data & ~((~0UL) << extra_shift));
result = ci_set_smc_sram_address(smumgr, addr, limit);
result = ci_set_smc_sram_address(hwmgr, addr, limit);
if (0 != result)
return result;
cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
}
return 0;
}
static int ci_program_jump_on_start(struct pp_smumgr *smumgr)
static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
{
static const unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 };
ci_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1);
ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
return 0;
}
bool ci_is_smc_ram_running(struct pp_smumgr *smumgr)
bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
{
return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
&& (0x20100 <= cgs_read_ind_register(smumgr->device,
&& (0x20100 <= cgs_read_ind_register(hwmgr->device,
CGS_IND_REG__SMC, ixSMC_PC_C)));
}
static int ci_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
uint32_t *value, uint32_t limit)
{
int result;
result = ci_set_smc_sram_address(smumgr, smc_addr, limit);
result = ci_set_smc_sram_address(hwmgr, smc_addr, limit);
if (result)
return result;
*value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0);
*value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
return 0;
}
int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{
int ret;
if (!ci_is_smc_ram_running(smumgr))
if (!ci_is_smc_ram_running(hwmgr))
return -EINVAL;
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
ret = SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP);
ret = SMUM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
if (ret != 1)
pr_info("\n failed to send message %x ret is %d\n", msg, ret);
......@@ -227,11 +227,11 @@ int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
return 0;
}
int ci_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter)
{
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
return ci_send_msg_to_smc(smumgr, msg);
cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
return ci_send_msg_to_smc(hwmgr, msg);
}
static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
......@@ -510,7 +510,7 @@ int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
data->dpm_level_enable_mask.sclk_dpm_enable_mask =
phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
result = ci_copy_bytes_to_smc(hwmgr->smumgr, array,
result = ci_copy_bytes_to_smc(hwmgr, array,
(u8 *)levels, array_size,
SMC_RAM_END);
......@@ -553,7 +553,7 @@ static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
const struct ci_pt_defaults *defaults = smu_data->power_tune_defaults;
uint32_t temp;
if (ci_read_smc_sram_dword(hwmgr->smumgr,
if (ci_read_smc_sram_dword(hwmgr,
fuse_table_offset +
offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
(uint32_t *)&temp, SMC_RAM_END))
......@@ -686,7 +686,7 @@ static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) {
if (ci_read_smc_sram_dword(hwmgr->smumgr,
if (ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, PmFuseTable),
&pm_fuse_table_offset, SMC_RAM_END)) {
......@@ -713,7 +713,7 @@ static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (ret)
return ret;
ret = ci_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
ret = ci_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
(uint8_t *)&smu_data->power_tune_table,
sizeof(struct SMU7_Discrete_PmFuses), SMC_RAM_END);
}
......@@ -1343,7 +1343,7 @@ int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
result = ci_copy_bytes_to_smc(hwmgr->smumgr,
result = ci_copy_bytes_to_smc(hwmgr,
level_array_address, (uint8_t *)levels, (uint32_t)level_array_size,
SMC_RAM_END);
......@@ -1705,7 +1705,7 @@ static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
if (0 == result) {
result = ci_copy_bytes_to_smc(
hwmgr->smumgr,
hwmgr,
smu_data->arb_table_start,
(uint8_t *)&arb_regs,
sizeof(SMU7_Discrete_MCArbDramTimingTable),
......@@ -1756,10 +1756,10 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
return result;
}
static int ci_populate_mc_reg_address(struct pp_smumgr *smumgr,
static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
SMU7_Discrete_MCRegisters *mc_reg_table)
{
const struct ci_smumgr *smu_data = (struct ci_smumgr *)smumgr->backend;
const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smumgr->backend;
uint32_t i, j;
......@@ -1796,12 +1796,12 @@ static void ci_convert_mc_registers(
}
static int ci_convert_mc_reg_table_entry_to_smc(
struct pp_smumgr *smumgr,
struct pp_hwmgr *hwmgr,
const uint32_t memory_clock,
SMU7_Discrete_MCRegisterSet *mc_reg_table_data
)
{
struct ci_smumgr *smu_data = (struct ci_smumgr *)(smumgr->backend);
struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend);
uint32_t i = 0;
for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
......@@ -1831,7 +1831,7 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
res = ci_convert_mc_reg_table_entry_to_smc(
hwmgr->smumgr,
hwmgr,
data->dpm_table.mclk_table.dpm_levels[i].value,
&mc_regs->data[i]
);
......@@ -1845,8 +1845,7 @@ static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
{
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct ci_smumgr *smu_data = (struct ci_smumgr *)(smumgr->backend);
struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend);
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
uint32_t address;
int32_t result;
......@@ -1864,7 +1863,7 @@ static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
address = smu_data->mc_reg_table_start + (uint32_t)offsetof(SMU7_Discrete_MCRegisters, data[0]);
return ci_copy_bytes_to_smc(hwmgr->smumgr, address,
return ci_copy_bytes_to_smc(hwmgr, address,
(uint8_t *)&smu_data->mc_regs.data[0],
sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
SMC_RAM_END);
......@@ -1873,11 +1872,10 @@ static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
{
int result;
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct ci_smumgr *smu_data = (struct ci_smumgr *)(smumgr->backend);
struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smumgr->backend);
memset(&smu_data->mc_regs, 0x00, sizeof(SMU7_Discrete_MCRegisters));
result = ci_populate_mc_reg_address(smumgr, &(smu_data->mc_regs));
result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize MCRegTable for the MC register addresses!", return result;);
......@@ -1885,7 +1883,7 @@ static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize MCRegTable for driver state!", return result;);
return ci_copy_bytes_to_smc(smumgr, smu_data->mc_reg_table_start,
return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start,
(uint8_t *)&smu_data->mc_regs, sizeof(SMU7_Discrete_MCRegisters), SMC_RAM_END);
}
......@@ -1930,17 +1928,17 @@ static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
return 0;
}
static int ci_start_smc(struct pp_smumgr *smumgr)
static int ci_start_smc(struct pp_hwmgr *hwmgr)
{
/* set smc instruct start point at 0x0 */
ci_program_jump_on_start(smumgr);
ci_program_jump_on_start(hwmgr);
/* enable smc clock */
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
SMUM_WAIT_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS,
SMUM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
INTERRUPTS_ENABLED, 1);
return 0;
......@@ -2105,7 +2103,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr)
table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
result = ci_copy_bytes_to_smc(hwmgr->smumgr, smu_data->dpm_table_start +
result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start +
offsetof(SMU7_Discrete_DpmTable, SystemFlags),
(uint8_t *)&(table->SystemFlags),
sizeof(SMU7_Discrete_DpmTable)-3 * sizeof(SMU7_PIDController),
......@@ -2122,7 +2120,7 @@ int ci_init_smc_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == result,
"Failed to populate PM fuses to SMC memory!", return result);
ci_start_smc(hwmgr->smumgr);
ci_start_smc(hwmgr);
return 0;
}
......@@ -2197,7 +2195,7 @@ int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
res = ci_copy_bytes_to_smc(hwmgr->smumgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
return 0;
}
......@@ -2233,7 +2231,7 @@ int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
result = ci_copy_bytes_to_smc(
hwmgr->smumgr,
hwmgr,
smu_data->dpm_table_start +
offsetof(SMU7_Discrete_DpmTable,
LowSclkInterruptT),
......@@ -2303,7 +2301,7 @@ uint32_t ci_get_mac_definition(uint32_t value)
return 0;
}
static int ci_load_smc_ucode(struct pp_smumgr *smumgr)
static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
{
uint32_t byte_count, start_addr;
uint8_t *src;
......@@ -2311,9 +2309,9 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr)
struct cgs_firmware_info info = {0};
cgs_get_firmware_info(smumgr->device, CGS_UCODE_ID_SMU, &info);
cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
smumgr->is_kicker = info.is_kicker;
hwmgr->smumgr->is_kicker = info.is_kicker;
byte_count = info.image_size;
src = (uint8_t *)info.kptr;
start_addr = info.ucode_start_address;
......@@ -2323,15 +2321,15 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr)
return -EINVAL;
}
cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, start_addr);
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
for (; byte_count >= 4; byte_count -= 4) {
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
src += 4;
}
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
if (0 != byte_count) {
pr_err("SMC size must be dividable by 4\n");
......@@ -2343,18 +2341,18 @@ static int ci_load_smc_ucode(struct pp_smumgr *smumgr)
static int ci_upload_firmware(struct pp_hwmgr *hwmgr)
{
if (ci_is_smc_ram_running(hwmgr->smumgr)) {
if (ci_is_smc_ram_running(hwmgr)) {
pr_info("smc is running, no need to load smc firmware\n");
return 0;
}
SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr->smumgr, SMC_IND, RCU_UC_EVENTS,
SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
boot_seq_done, 1);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL,
pre_fetcher_en, 1);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
return ci_load_smc_ucode(hwmgr->smumgr);
return ci_load_smc_ucode(hwmgr);
}
int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
......@@ -2369,7 +2367,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
if (ci_upload_firmware(hwmgr))
return -EINVAL;
result = ci_read_smc_sram_dword(hwmgr->smumgr,
result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, DpmTable),
&tmp, SMC_RAM_END);
......@@ -2379,7 +2377,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = ci_read_smc_sram_dword(hwmgr->smumgr,
result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, SoftRegisters),
&tmp, SMC_RAM_END);
......@@ -2391,7 +2389,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = ci_read_smc_sram_dword(hwmgr->smumgr,
result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, mcRegisterTable),
&tmp, SMC_RAM_END);
......@@ -2399,7 +2397,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
if (0 == result)
ci_data->mc_reg_table_start = tmp;
result = ci_read_smc_sram_dword(hwmgr->smumgr,
result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, FanTable),
&tmp, SMC_RAM_END);
......@@ -2409,7 +2407,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = ci_read_smc_sram_dword(hwmgr->smumgr,
result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
&tmp, SMC_RAM_END);
......@@ -2419,7 +2417,7 @@ int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = ci_read_smc_sram_dword(hwmgr->smumgr,
result = ci_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU7_Firmware_Header, Version),
&tmp, SMC_RAM_END);
......@@ -2726,7 +2724,7 @@ int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
{
return ci_is_smc_ram_running(hwmgr->smumgr);
return ci_is_smc_ram_running(hwmgr);
}
int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
......@@ -2750,6 +2748,6 @@ int ci_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
levels[i].DownH = request->down_hyst;
}
return ci_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
return ci_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
array_size, SMC_RAM_END);
}
......@@ -30,9 +30,9 @@ struct pp_smumgr;
struct pp_hwmgr;
struct amd_pp_profile;
int ci_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter);
int ci_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
int ci_init_smc_table(struct pp_hwmgr *hwmgr);
......
......@@ -30,7 +30,7 @@
#include "cgs_common.h"
#include "ci_smc.h"
static int ci_smu_init(struct pp_smumgr *smumgr)
static int ci_smu_init(struct pp_hwmgr *hwmgr)
{
int i;
struct ci_smumgr *ci_priv = NULL;
......@@ -43,20 +43,20 @@ static int ci_smu_init(struct pp_smumgr *smumgr)
for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
ci_priv->activity_target[i] = 30;
smumgr->backend = ci_priv;
hwmgr->smumgr->backend = ci_priv;
return 0;
}
static int ci_smu_fini(struct pp_smumgr *smumgr)
static int ci_smu_fini(struct pp_hwmgr *hwmgr)
{
kfree(smumgr->backend);
smumgr->backend = NULL;
cgs_rel_firmware(smumgr->device, CGS_UCODE_ID_SMU);
kfree(hwmgr->smumgr->backend);
hwmgr->smumgr->backend = NULL;
cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
return 0;
}
static int ci_start_smu(struct pp_smumgr *smumgr)
static int ci_start_smu(struct pp_hwmgr *hwmgr)
{
return 0;
}
......
......@@ -338,7 +338,7 @@ static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
uint32_t temp;
if (smu7_read_smc_sram_dword(hwmgr->smumgr,
if (smu7_read_smc_sram_dword(hwmgr,
fuse_table_offset +
offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
(uint32_t *)&temp, SMC_RAM_END))
......@@ -425,7 +425,7 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) {
if (smu7_read_smc_sram_dword(hwmgr->smumgr,
if (smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, PmFuseTable),
&pm_fuse_table_offset, SMC_RAM_END))
......@@ -473,7 +473,7 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
"Sidd Failed!", return -EINVAL);
if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
(uint8_t *)&smu_data->power_tune_table,
sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END))
PP_ASSERT_WITH_CODE(false,
......@@ -848,7 +848,7 @@ int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
levels[1].pcieDpmLevel = mid_pcie_level_enabled;
}
/* level count will send to smc once at init smc table and never change */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
(uint32_t)array_size, SMC_RAM_END);
return result;
......@@ -1032,7 +1032,7 @@ int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
PPSMC_DISPLAY_WATERMARK_HIGH;
/* level count will send to smc once at init smc table and never change */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
(uint32_t)array_size, SMC_RAM_END);
return result;
......@@ -1359,7 +1359,7 @@ static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
if (!result)
result = smu7_copy_bytes_to_smc(
hwmgr->smumgr,
hwmgr,
smu_data->smu7_data.arb_table_start,
(uint8_t *)&arb_regs,
sizeof(SMU73_Discrete_MCArbDramTimingTable),
......@@ -1683,9 +1683,9 @@ static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
return 0;
}
static int fiji_init_arb_table_index(struct pp_smumgr *smumgr)
static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
{
struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(smumgr->backend);
struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
uint32_t tmp;
int result;
......@@ -1697,7 +1697,7 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr)
* In reality this field should not be in that structure
* but in a soft register.
*/
result = smu7_read_smc_sram_dword(smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
if (result)
......@@ -1706,7 +1706,7 @@ static int fiji_init_arb_table_index(struct pp_smumgr *smumgr)
tmp &= 0x00FFFFFF;
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
return smu7_write_smc_sram_dword(smumgr,
return smu7_write_smc_sram_dword(hwmgr,
smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
}
......@@ -1771,7 +1771,7 @@ static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
}
}
if (mask)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_LedConfig,
mask);
return 0;
......@@ -1974,7 +1974,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
result = smu7_copy_bytes_to_smc(hwmgr,
smu_data->smu7_data.dpm_table_start +
offsetof(SMU73_Discrete_DpmTable, SystemFlags),
(uint8_t *)&(table->SystemFlags),
......@@ -1983,7 +1983,7 @@ int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == result,
"Failed to upload dpm data to SMC memory!", return result);
result = fiji_init_arb_table_index(hwmgr->smumgr);
result = fiji_init_arb_table_index(hwmgr);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to upload arb data to SMC memory!", return result);
......@@ -2093,20 +2093,20 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr->device, CGS_IND_REG__SMC,
CG_MULT_THERMAL_CTRL, TEMP_SEL);
res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start,
res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
SMC_RAM_END);
if (!res && hwmgr->thermal_controller.
advanceFanControlParameters.ucMinimumPWMLimit)
res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
res = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanMinPwm,
hwmgr->thermal_controller.
advanceFanControlParameters.ucMinimumPWMLimit);
if (!res && hwmgr->thermal_controller.
advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
res = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanSclkTarget,
hwmgr->thermal_controller.
advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
......@@ -2122,13 +2122,12 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
{
int ret;
struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS)
return 0;
ret = smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs);
ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
if (!ret)
/* If this param is not changed, this function could fire unnecessarily */
......@@ -2168,7 +2167,7 @@ int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
result = smu7_copy_bytes_to_smc(
hwmgr->smumgr,
hwmgr,
smu_data->smu7_data.dpm_table_start +
offsetof(SMU73_Discrete_DpmTable,
LowSclkInterruptThreshold),
......@@ -2269,7 +2268,7 @@ static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_UVDDPM) ||
phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDDPM_SetEnabledMask,
(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
return 0;
......@@ -2301,7 +2300,7 @@ static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_VCEDPM_SetEnabledMask,
(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
return 0;
......@@ -2328,7 +2327,7 @@ static int fiji_update_samu_smc_table(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SAMUDPM_SetEnabledMask,
(uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
return 0;
......@@ -2367,7 +2366,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
int result;
bool error = false;
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, DpmTable),
&tmp, SMC_RAM_END);
......@@ -2377,7 +2376,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, SoftRegisters),
&tmp, SMC_RAM_END);
......@@ -2389,7 +2388,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, mcRegisterTable),
&tmp, SMC_RAM_END);
......@@ -2397,7 +2396,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
if (!result)
smu_data->smu7_data.mc_reg_table_start = tmp;
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, FanTable),
&tmp, SMC_RAM_END);
......@@ -2407,7 +2406,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
&tmp, SMC_RAM_END);
......@@ -2417,7 +2416,7 @@ int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, Version),
&tmp, SMC_RAM_END);
......@@ -2482,6 +2481,6 @@ int fiji_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
levels[i].DownHyst = request->down_hyst;
}
return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
array_size, SMC_RAM_END);
}
......@@ -58,122 +58,122 @@ static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
{ 0xf811d047, 0x80380100, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000, 0, 0, 0x0c, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00 }
};
static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr)
static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
{
int result = 0;
/* Wait for smc boot up */
/* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
/* SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0); */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
result = smu7_upload_smu_firmware_image(smumgr);
result = smu7_upload_smu_firmware_image(hwmgr);
if (result)
return result;
/* Clear status */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMU_STATUS, 0);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for ROM firmware to initialize interrupt hendler */
/*SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND,
/*SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, SMC_IND,
SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
/* Set SMU Auto Start */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_INPUT_DATA, AUTO_START, 1);
/* Clear firmware interrupt enable flag */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0);
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS,
SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
INTERRUPTS_ENABLED, 1);
cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
SMUM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
/* Wait for done bit to be set */
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
SMU_STATUS, SMU_DONE, 0);
/* Check pass/failed indicator */
if (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
if (SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_STATUS, SMU_PASS) != 1) {
PP_ASSERT_WITH_CODE(false,
"SMU Firmware start failed!", return -1);
}
/* Wait for firmware to initialize */
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result;
}
static int fiji_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr)
static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
{
int result = 0;
/* wait for smc boot up */
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0);
/* Clear firmware interrupt enable flag */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0);
/* Assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
result = smu7_upload_smu_firmware_image(smumgr);
result = smu7_upload_smu_firmware_image(hwmgr);
if (result)
return result;
/* Set smc instruct start point at 0x0 */
smu7_program_jump_on_start(smumgr);
smu7_program_jump_on_start(hwmgr);
/* Enable clock */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for firmware to initialize */
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result;
}
static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
static int fiji_setup_pwr_virus(struct pp_hwmgr *hwmgr)
{
int i;
int result = -EINVAL;
uint32_t reg, data;
const PWR_Command_Table *pvirus = PwrVirusTable;
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) {
switch (pvirus->command) {
case PwrCmdWrite:
reg = pvirus->reg;
data = pvirus->data;
cgs_write_register(smumgr->device, reg, data);
cgs_write_register(hwmgr->device, reg, data);
break;
case PwrCmdEnd:
......@@ -192,13 +192,13 @@ static int fiji_setup_pwr_virus(struct pp_smumgr *smumgr)
return result;
}
static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)
{
int result = 0;
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
if (0 != smu_data->avfs.avfs_btc_param) {
if (0 != smu7_send_msg_to_smc_with_parameter(smumgr,
if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");
result = -EINVAL;
......@@ -206,23 +206,23 @@ static int fiji_start_avfs_btc(struct pp_smumgr *smumgr)
}
/* Soft-Reset to reset the engine before loading uCode */
/* halt */
cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000);
cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
/* reset everything */
cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
/* clear reset */
cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0);
cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
return result;
}
static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
{
int32_t vr_config;
uint32_t table_start;
uint32_t level_addr, vr_config_addr;
uint32_t level_size = sizeof(avfs_graphics_level);
PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(smumgr,
PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, DpmTable),
&table_start, 0x40000),
......@@ -237,7 +237,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
vr_config_addr = table_start +
offsetof(SMU73_Discrete_DpmTable, VRConfig);
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, vr_config_addr,
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,
(uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
"[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
"vr_config value over to SMC",
......@@ -245,7 +245,7 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(smumgr, level_addr,
PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,
(uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
"[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
return -1;);
......@@ -253,9 +253,9 @@ static int fiji_setup_graphics_level_structure(struct pp_smumgr *smumgr)
return 0;
}
static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool smu_started)
{
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
switch (smu_data->avfs.avfs_btc_status) {
case AVFS_BTC_COMPLETED_PREVIOUSLY:
......@@ -265,17 +265,17 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
if (!smu_started)
break;
smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(smumgr),
PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
"[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level"
" table over to SMU",
return -EINVAL;);
smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(smumgr),
PP_ASSERT_WITH_CODE(0 == fiji_setup_pwr_virus(hwmgr),
"[AVFS][fiji_avfs_event_mgr] Could not setup "
"Pwr Virus for AVFS ",
return -EINVAL;);
smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(smumgr),
PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),
"[AVFS][fiji_avfs_event_mgr] Failure at "
"fiji_start_avfs_btc. AVFS Disabled",
return -EINVAL;);
......@@ -293,64 +293,64 @@ static int fiji_avfs_event_mgr(struct pp_smumgr *smumgr, bool smu_started)
return 0;
}
static int fiji_start_smu(struct pp_smumgr *smumgr)
static int fiji_start_smu(struct pp_hwmgr *hwmgr)
{
int result = 0;
struct fiji_smumgr *priv = (struct fiji_smumgr *)(smumgr->backend);
struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
/* Only start SMC if SMC RAM is not running */
if (!(smu7_is_smc_ram_running(smumgr)
|| cgs_is_virtualization_enabled(smumgr->device))) {
fiji_avfs_event_mgr(smumgr, false);
if (!(smu7_is_smc_ram_running(hwmgr)
|| cgs_is_virtualization_enabled(hwmgr->device))) {
fiji_avfs_event_mgr(hwmgr, false);
/* Check if SMU is running in protected mode */
if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC,
SMU_FIRMWARE, SMU_MODE)) {
result = fiji_start_smu_in_non_protection_mode(smumgr);
result = fiji_start_smu_in_non_protection_mode(hwmgr);
if (result)
return result;
} else {
result = fiji_start_smu_in_protection_mode(smumgr);
result = fiji_start_smu_in_protection_mode(hwmgr);
if (result)
return result;
}
fiji_avfs_event_mgr(smumgr, true);
fiji_avfs_event_mgr(hwmgr, true);
}
/* To initialize all clock gating before RLC loaded and running.*/
cgs_set_clockgating_state(smumgr->device,
cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);
cgs_set_clockgating_state(smumgr->device,
cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);
cgs_set_clockgating_state(smumgr->device,
cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);
cgs_set_clockgating_state(smumgr->device,
cgs_set_clockgating_state(hwmgr->device,
AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);
/* Setup SoftRegsStart here for register lookup in case
* DummyBackEnd is used and ProcessFirmwareHeader is not executed
*/
smu7_read_smc_sram_dword(smumgr,
smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU73_Firmware_Header, SoftRegisters),
&(priv->smu7_data.soft_regs_start), 0x40000);
result = smu7_request_smu_load_fw(smumgr);
result = smu7_request_smu_load_fw(hwmgr);
return result;
}
static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
{
uint32_t efuse = 0;
uint32_t mask = (1 << ((AVFS_EN_MSB - AVFS_EN_LSB) + 1)) - 1;
if (cgs_is_virtualization_enabled(smumgr->device))
if (cgs_is_virtualization_enabled(hwmgr->device))
return 0;
if (!atomctrl_read_efuse(smumgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
if (!atomctrl_read_efuse(hwmgr->device, AVFS_EN_LSB, AVFS_EN_MSB,
mask, &efuse)) {
if (efuse)
return true;
......@@ -365,7 +365,7 @@ static bool fiji_is_hw_avfs_present(struct pp_smumgr *smumgr)
* @param smc_addr the address in the SMC RAM to access.
* @param value to write to the SMC SRAM.
*/
static int fiji_smu_init(struct pp_smumgr *smumgr)
static int fiji_smu_init(struct pp_hwmgr *hwmgr)
{
int i;
struct fiji_smumgr *fiji_priv = NULL;
......@@ -375,9 +375,9 @@ static int fiji_smu_init(struct pp_smumgr *smumgr)
if (fiji_priv == NULL)
return -ENOMEM;
smumgr->backend = fiji_priv;
hwmgr->smumgr->backend = fiji_priv;
if (smu7_init(smumgr))
if (smu7_init(hwmgr))
return -EINVAL;
for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
......
......@@ -163,7 +163,7 @@ static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offs
const struct iceland_pt_defaults *defaults = smu_data->power_tune_defaults;
uint32_t temp;
if (smu7_read_smc_sram_dword(hwmgr->smumgr,
if (smu7_read_smc_sram_dword(hwmgr,
fuse_table_offset +
offsetof(SMU71_Discrete_PmFuses, TdcWaterfallCtl),
(uint32_t *)&temp, SMC_RAM_END))
......@@ -264,7 +264,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) {
if (smu7_read_smc_sram_dword(hwmgr->smumgr,
if (smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, PmFuseTable),
&pm_fuse_table_offset, SMC_RAM_END))
......@@ -318,7 +318,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
"Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
return -EINVAL);
if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
(uint8_t *)&smu_data->power_tune_table,
sizeof(struct SMU71_Discrete_PmFuses), SMC_RAM_END))
PP_ASSERT_WITH_CODE(false,
......@@ -881,7 +881,7 @@ int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
/* level count will send to smc once at init smc table and never change*/
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress,
result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress,
(uint8_t *)levels, (uint32_t)level_array_size,
SMC_RAM_END);
......@@ -1246,7 +1246,7 @@ int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
/* level count will send to smc once at init smc table and never change*/
result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
result = smu7_copy_bytes_to_smc(hwmgr,
level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size,
SMC_RAM_END);
......@@ -1507,7 +1507,7 @@ static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
if (0 == result) {
result = smu7_copy_bytes_to_smc(
hwmgr->smumgr,
hwmgr,
smu_data->smu7_data.arb_table_start,
(uint8_t *)&arb_regs,
sizeof(SMU71_Discrete_MCArbDramTimingTable),
......@@ -1561,10 +1561,10 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
return result;
}
static int iceland_populate_mc_reg_address(struct pp_smumgr *smumgr,
static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
SMU71_Discrete_MCRegisters *mc_reg_table)
{
const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)smumgr->backend;
const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smumgr->backend;
uint32_t i, j;
......@@ -1601,13 +1601,12 @@ static void iceland_convert_mc_registers(
}
}
static int iceland_convert_mc_reg_table_entry_to_smc(
struct pp_smumgr *smumgr,
static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
const uint32_t memory_clock,
SMU71_Discrete_MCRegisterSet *mc_reg_table_data
)
{
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
uint32_t i = 0;
for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) {
......@@ -1637,7 +1636,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
res = iceland_convert_mc_reg_table_entry_to_smc(
hwmgr->smumgr,
hwmgr,
data->dpm_table.mclk_table.dpm_levels[i].value,
&mc_regs->data[i]
);
......@@ -1651,8 +1650,7 @@ static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
{
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
uint32_t address;
int32_t result;
......@@ -1671,7 +1669,7 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
address = smu_data->smu7_data.mc_reg_table_start + (uint32_t)offsetof(SMU71_Discrete_MCRegisters, data[0]);
return smu7_copy_bytes_to_smc(hwmgr->smumgr, address,
return smu7_copy_bytes_to_smc(hwmgr, address,
(uint8_t *)&smu_data->mc_regs.data[0],
sizeof(SMU71_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
SMC_RAM_END);
......@@ -1680,11 +1678,10 @@ static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
{
int result;
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend);
memset(&smu_data->mc_regs, 0x00, sizeof(SMU71_Discrete_MCRegisters));
result = iceland_populate_mc_reg_address(smumgr, &(smu_data->mc_regs));
result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize MCRegTable for the MC register addresses!", return result;);
......@@ -1692,7 +1689,7 @@ static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == result,
"Failed to initialize MCRegTable for driver state!", return result;);
return smu7_copy_bytes_to_smc(smumgr, smu_data->smu7_data.mc_reg_table_start,
return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
(uint8_t *)&smu_data->mc_regs, sizeof(SMU71_Discrete_MCRegisters), SMC_RAM_END);
}
......@@ -1944,7 +1941,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE);
/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.dpm_table_start +
result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
offsetof(SMU71_Discrete_DpmTable, SystemFlags),
(uint8_t *)&(table->SystemFlags),
sizeof(SMU71_Discrete_DpmTable)-3 * sizeof(SMU71_PIDController),
......@@ -1954,7 +1951,7 @@ int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
"Failed to upload dpm data to SMC memory!", return result;);
/* Upload all ulv setting to SMC memory.(dpm level, dpm level count etc) */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
result = smu7_copy_bytes_to_smc(hwmgr,
smu_data->smu7_data.ulv_setting_starts,
(uint8_t *)&(smu_data->ulv_setting),
sizeof(SMU71_Discrete_Ulv),
......@@ -2053,7 +2050,7 @@ int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
/* fan_table.FanControl_GL_Flag = 1; */
res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
return 0;
}
......@@ -2090,7 +2087,7 @@ int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
result = smu7_copy_bytes_to_smc(
hwmgr->smumgr,
hwmgr,
smu_data->smu7_data.dpm_table_start +
offsetof(SMU71_Discrete_DpmTable,
LowSclkInterruptThreshold),
......@@ -2177,7 +2174,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
int result;
bool error = false;
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, DpmTable),
&tmp, SMC_RAM_END);
......@@ -2188,7 +2185,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, SoftRegisters),
&tmp, SMC_RAM_END);
......@@ -2201,7 +2198,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, mcRegisterTable),
&tmp, SMC_RAM_END);
......@@ -2210,7 +2207,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
smu7_data->mc_reg_table_start = tmp;
}
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, FanTable),
&tmp, SMC_RAM_END);
......@@ -2221,7 +2218,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, mcArbDramTimingTable),
&tmp, SMC_RAM_END);
......@@ -2233,7 +2230,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, Version),
&tmp, SMC_RAM_END);
......@@ -2244,7 +2241,7 @@ int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU71_FIRMWARE_HEADER_LOCATION +
offsetof(SMU71_Firmware_Header, UlvSettings),
&tmp, SMC_RAM_END);
......
......@@ -39,55 +39,55 @@
#define ICELAND_SMC_SIZE 0x20000
static int iceland_start_smc(struct pp_smumgr *smumgr)
static int iceland_start_smc(struct pp_hwmgr *hwmgr)
{
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
return 0;
}
static void iceland_reset_smc(struct pp_smumgr *smumgr)
static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
{
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL,
rst_reg, 1);
}
static void iceland_stop_smc_clock(struct pp_smumgr *smumgr)
static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
{
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0,
ck_disable, 1);
}
static void iceland_start_smc_clock(struct pp_smumgr *smumgr)
static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
{
SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0,
ck_disable, 0);
}
static int iceland_smu_start_smc(struct pp_smumgr *smumgr)
static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
{
/* set smc instruct start point at 0x0 */
smu7_program_jump_on_start(smumgr);
smu7_program_jump_on_start(hwmgr);
/* enable smc clock */
iceland_start_smc_clock(smumgr);
iceland_start_smc_clock(hwmgr);
/* de-assert reset */
iceland_start_smc(smumgr);
iceland_start_smc(hwmgr);
SMUM_WAIT_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS,
SMUM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
INTERRUPTS_ENABLED, 1);
return 0;
}
static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
uint32_t length, const uint8_t *src,
uint32_t limit, uint32_t start_addr)
{
......@@ -96,17 +96,17 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, start_addr);
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
while (byte_count >= 4) {
data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
src += 4;
byte_count -= 4;
}
SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
SMUM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
......@@ -114,16 +114,16 @@ static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
}
static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr)
static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
{
uint32_t val;
struct cgs_firmware_info info = {0};
if (smumgr == NULL || smumgr->device == NULL)
if (hwmgr == NULL || hwmgr->device == NULL)
return -EINVAL;
/* load SMC firmware */
cgs_get_firmware_info(smumgr->device,
cgs_get_firmware_info(hwmgr->device,
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
if (info.image_size & 3) {
......@@ -137,56 +137,56 @@ static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr)
}
/* wait for smc boot up */
SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0);
/* clear firmware interrupt enable flag */
val = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC,
val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMC_SYSCON_MISC_CNTL);
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMC_SYSCON_MISC_CNTL, val | 1);
/* stop smc clock */
iceland_stop_smc_clock(smumgr);
iceland_stop_smc_clock(hwmgr);
/* reset smc */
iceland_reset_smc(smumgr);
iceland_upload_smc_firmware_data(smumgr, info.image_size,
iceland_reset_smc(hwmgr);
iceland_upload_smc_firmware_data(hwmgr, info.image_size,
(uint8_t *)info.kptr, ICELAND_SMC_SIZE,
info.ucode_start_address);
return 0;
}
static int iceland_request_smu_load_specific_fw(struct pp_smumgr *smumgr,
static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
uint32_t firmwareType)
{
return 0;
}
static int iceland_start_smu(struct pp_smumgr *smumgr)
static int iceland_start_smu(struct pp_hwmgr *hwmgr)
{
int result;
result = iceland_smu_upload_firmware_image(smumgr);
result = iceland_smu_upload_firmware_image(hwmgr);
if (result)
return result;
result = iceland_smu_start_smc(smumgr);
result = iceland_smu_start_smc(hwmgr);
if (result)
return result;
if (!smu7_is_smc_ram_running(smumgr)) {
if (!smu7_is_smc_ram_running(hwmgr)) {
pr_info("smu not running, upload firmware again \n");
result = iceland_smu_upload_firmware_image(smumgr);
result = iceland_smu_upload_firmware_image(hwmgr);
if (result)
return result;
result = iceland_smu_start_smc(smumgr);
result = iceland_smu_start_smc(hwmgr);
if (result)
return result;
}
result = smu7_request_smu_load_fw(smumgr);
result = smu7_request_smu_load_fw(hwmgr);
return result;
}
......@@ -198,7 +198,7 @@ static int iceland_start_smu(struct pp_smumgr *smumgr)
* @param smcAddress the address in the SMC RAM to access.
* @param value to write to the SMC SRAM.
*/
static int iceland_smu_init(struct pp_smumgr *smumgr)
static int iceland_smu_init(struct pp_hwmgr *hwmgr)
{
int i;
struct iceland_smumgr *iceland_priv = NULL;
......@@ -208,9 +208,9 @@ static int iceland_smu_init(struct pp_smumgr *smumgr)
if (iceland_priv == NULL)
return -ENOMEM;
smumgr->backend = iceland_priv;
hwmgr->smumgr->backend = iceland_priv;
if (smu7_init(smumgr))
if (smu7_init(hwmgr))
return -EINVAL;
for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
......
......@@ -231,7 +231,7 @@ static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of
const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
uint32_t temp;
if (smu7_read_smc_sram_dword(hwmgr->smumgr,
if (smu7_read_smc_sram_dword(hwmgr,
fuse_table_offset +
offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
(uint32_t *)&temp, SMC_RAM_END))
......@@ -315,7 +315,7 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) {
if (smu7_read_smc_sram_dword(hwmgr->smumgr,
if (smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, PmFuseTable),
&pm_fuse_table_offset, SMC_RAM_END))
......@@ -358,7 +358,7 @@ static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
"Sidd Failed!", return -EINVAL);
if (smu7_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
(uint8_t *)&smu_data->power_tune_table,
(sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
PP_ASSERT_WITH_CODE(false,
......@@ -484,7 +484,6 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct pp_smumgr *smumgr = hwmgr->smumgr;
state->CcPwrDynRm = 0;
state->CcPwrDynRm1 = 0;
......@@ -493,7 +492,7 @@ static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
if (smumgr->chip_id == CHIP_POLARIS12 || smumgr->is_kicker)
if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->smumgr->is_kicker)
state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
else
state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
......@@ -546,8 +545,7 @@ static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
SMU74_Discrete_DpmTable *table)
{
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
uint32_t i, ref_clk;
struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
......@@ -597,8 +595,7 @@ static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
uint32_t clock, SMU_SclkSetting *sclk_setting)
{
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
struct pp_atomctrl_clock_dividers_ai dividers;
uint32_t ref_clock;
......@@ -741,9 +738,8 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
*/
int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
{
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
......@@ -828,7 +824,7 @@ int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
levels[1].pcieDpmLevel = mid_pcie_level_enabled;
}
/* level count will send to smc once at init smc table and never change */
result = smu7_copy_bytes_to_smc(smumgr, array, (uint8_t *)levels,
result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
(uint32_t)array_size, SMC_RAM_END);
return result;
......@@ -890,9 +886,8 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
*/
int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
{
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
int result;
/* populate MCLK dpm table to SMU7 */
......@@ -933,7 +928,7 @@ int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
/* level count will send to smc once at init smc table and never change */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
(uint32_t)array_size, SMC_RAM_END);
return result;
......@@ -1191,9 +1186,8 @@ static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
{
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
uint32_t i, j;
int result = 0;
......@@ -1212,7 +1206,7 @@ static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
}
result = smu7_copy_bytes_to_smc(
hwmgr->smumgr,
hwmgr,
smu_data->smu7_data.arb_table_start,
(uint8_t *)&arb_regs,
sizeof(SMU74_Discrete_MCArbDramTimingTable),
......@@ -1311,9 +1305,8 @@ static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
{
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
uint8_t count, level;
......@@ -1344,8 +1337,7 @@ static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
{
uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
struct phm_ppt_v1_information *table_info =
......@@ -1472,8 +1464,7 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
int result = 0;
......@@ -1524,20 +1515,20 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
}
result = smu7_read_smc_sram_dword(smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
&tmp, SMC_RAM_END);
smu7_copy_bytes_to_smc(smumgr,
smu7_copy_bytes_to_smc(hwmgr,
tmp,
(uint8_t *)&AVFS_meanNsigma,
sizeof(AVFS_meanNsigma_t),
SMC_RAM_END);
result = smu7_read_smc_sram_dword(smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
&tmp, SMC_RAM_END);
smu7_copy_bytes_to_smc(smumgr,
smu7_copy_bytes_to_smc(hwmgr,
tmp,
(uint8_t *)&AVFS_SclkOffset,
sizeof(AVFS_Sclk_Offset_t),
......@@ -1559,9 +1550,9 @@ static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr)
static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
{
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
uint32_t tmp;
int result;
......@@ -1573,7 +1564,7 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr)
* In reality this field should not be in that structure
* but in a soft register.
*/
result = smu7_read_smc_sram_dword(smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
if (result)
......@@ -1582,7 +1573,7 @@ static int polaris10_init_arb_table_index(struct pp_smumgr *smumgr)
tmp &= 0x00FFFFFF;
tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
return smu7_write_smc_sram_dword(smumgr,
return smu7_write_smc_sram_dword(hwmgr,
smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
}
......@@ -1648,9 +1639,8 @@ static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr)
int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
{
int result;
struct pp_smumgr *smumgr = hwmgr->smumgr;
struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
......@@ -1842,7 +1832,7 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
/* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
result = smu7_copy_bytes_to_smc(hwmgr->smumgr,
result = smu7_copy_bytes_to_smc(hwmgr,
smu_data->smu7_data.dpm_table_start +
offsetof(SMU74_Discrete_DpmTable, SystemFlags),
(uint8_t *)&(table->SystemFlags),
......@@ -1851,7 +1841,7 @@ int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(0 == result,
"Failed to upload dpm data to SMC memory!", return result);
result = polaris10_init_arb_table_index(hwmgr->smumgr);
result = polaris10_init_arb_table_index(hwmgr);
PP_ASSERT_WITH_CODE(0 == result,
"Failed to upload arb data to SMC memory!", return result);
......@@ -1878,17 +1868,16 @@ static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
{
int ret;
struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr);
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smumgr->backend);
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
return 0;
ret = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
ret = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting);
ret = (smum_send_msg_to_smc(smumgr, PPSMC_MSG_EnableAvfs) == 0) ?
ret = (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs) == 0) ?
0 : -1;
if (!ret)
......@@ -1990,20 +1979,20 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr->device, CGS_IND_REG__SMC,
CG_MULT_THERMAL_CTRL, TEMP_SEL);
res = smu7_copy_bytes_to_smc(hwmgr->smumgr, smu_data->smu7_data.fan_table_start,
res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
(uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
SMC_RAM_END);
if (!res && hwmgr->thermal_controller.
advanceFanControlParameters.ucMinimumPWMLimit)
res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
res = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanMinPwm,
hwmgr->thermal_controller.
advanceFanControlParameters.ucMinimumPWMLimit);
if (!res && hwmgr->thermal_controller.
advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
res = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetFanSclkTarget,
hwmgr->thermal_controller.
advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
......@@ -2041,7 +2030,7 @@ static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_UVDDPM) ||
phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UVDDPM_SetEnabledMask,
(uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
return 0;
......@@ -2073,7 +2062,7 @@ static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_VCEDPM_SetEnabledMask,
(uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
return 0;
......@@ -2100,7 +2089,7 @@ static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_StablePState))
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SAMUDPM_SetEnabledMask,
(uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
return 0;
......@@ -2164,7 +2153,7 @@ int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
result = smu7_copy_bytes_to_smc(
hwmgr->smumgr,
hwmgr,
smu_data->smu7_data.dpm_table_start +
offsetof(SMU74_Discrete_DpmTable,
LowSclkInterruptThreshold),
......@@ -2258,7 +2247,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
int result;
bool error = false;
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, DpmTable),
&tmp, SMC_RAM_END);
......@@ -2268,7 +2257,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, SoftRegisters),
&tmp, SMC_RAM_END);
......@@ -2280,7 +2269,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, mcRegisterTable),
&tmp, SMC_RAM_END);
......@@ -2288,7 +2277,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
if (!result)
smu_data->smu7_data.mc_reg_table_start = tmp;
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, FanTable),
&tmp, SMC_RAM_END);
......@@ -2298,7 +2287,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
&tmp, SMC_RAM_END);
......@@ -2308,7 +2297,7 @@ int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
error |= (0 != result);
result = smu7_read_smc_sram_dword(hwmgr->smumgr,
result = smu7_read_smc_sram_dword(hwmgr,
SMU7_FIRMWARE_HEADER_LOCATION +
offsetof(SMU74_Firmware_Header, Version),
&tmp, SMC_RAM_END);
......@@ -2349,6 +2338,6 @@ int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
levels[i].DownHyst = request->down_hyst;
}
return smu7_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
array_size, SMC_RAM_END);
}
......@@ -51,11 +51,11 @@ struct rv_smumgr {
struct smu_table_array smu_tables;
};
int rv_read_arg_from_smc(struct pp_smumgr *smumgr, uint32_t *arg);
bool rv_is_smc_ram_running(struct pp_smumgr *smumgr);
int rv_copy_table_from_smc(struct pp_smumgr *smumgr,
int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
bool rv_is_smc_ram_running(struct pp_hwmgr *hwmgr);
int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id);
int rv_copy_table_to_smc(struct pp_smumgr *smumgr,
int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id);
......
......@@ -60,32 +60,32 @@ struct smu7_smumgr {
};
int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
uint32_t *dest, uint32_t byte_count, uint32_t limit);
int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit);
int smu7_program_jump_on_start(struct pp_smumgr *smumgr);
bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr);
int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg);
int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg,
int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr);
bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr);
int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg);
int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg,
uint32_t parameter);
int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr,
int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter);
int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr);
int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr);
int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr);
int smu7_wait_for_smc_inactive(struct pp_hwmgr *hwmgr);
enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type);
int smu7_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
uint32_t *value, uint32_t limit);
int smu7_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr,
int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
uint32_t value, uint32_t limit);
int smu7_request_smu_load_fw(struct pp_smumgr *smumgr);
int smu7_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type);
int smu7_reload_firmware(struct pp_smumgr *smumgr);
int smu7_upload_smu_firmware_image(struct pp_smumgr *smumgr);
int smu7_init(struct pp_smumgr *smumgr);
int smu7_smu_fini(struct pp_smumgr *smumgr);
int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
int smu7_init(struct pp_hwmgr *hwmgr);
int smu7_smu_fini(struct pp_hwmgr *hwmgr);
#endif
\ No newline at end of file
......@@ -37,125 +37,125 @@
#include "smu7_smumgr.h"
static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
{
int result;
/* Assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
result = smu7_upload_smu_firmware_image(smumgr);
result = smu7_upload_smu_firmware_image(hwmgr);
if (result)
return result;
/* Clear status */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixSMU_STATUS, 0);
/* Enable clock */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/* De-assert reset */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Set SMU Auto Start */
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_INPUT_DATA, AUTO_START, 1);
/* Clear firmware interrupt enable flag */
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0);
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
/**
* Call Test SMU message with 0x20000 offset to trigger SMU start
*/
smu7_send_msg_to_smc_offset(smumgr);
smu7_send_msg_to_smc_offset(hwmgr);
/* Wait for done bit to be set */
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
SMU_STATUS, SMU_DONE, 0);
/* Check pass/failed indicator */
if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
pr_err("SMU Firmware start failed\n");
return -EINVAL;
}
/* Wait for firmware to initialize */
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return 0;
}
static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr)
static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
{
int result = 0;
/* wait for smc boot up */
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0);
/*Clear firmware interrupt enable flag*/
cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixFIRMWARE_FLAGS, 0);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 1);
result = smu7_upload_smu_firmware_image(smumgr);
result = smu7_upload_smu_firmware_image(hwmgr);
if (result != 0)
return result;
/* Set smc instruct start point at 0x0 */
smu7_program_jump_on_start(smumgr);
smu7_program_jump_on_start(hwmgr);
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
/*De-assert reset*/
SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
SMUM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL, rst_reg, 0);
/* Wait for firmware to initialize */
SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
SMUM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
return result;
}
static int tonga_start_smu(struct pp_smumgr *smumgr)
static int tonga_start_smu(struct pp_hwmgr *hwmgr)
{
int result;
/* Only start SMC if SMC RAM is not running */
if (!(smu7_is_smc_ram_running(smumgr) ||
cgs_is_virtualization_enabled(smumgr->device))) {
if (!(smu7_is_smc_ram_running(hwmgr) ||
cgs_is_virtualization_enabled(hwmgr->device))) {
/*Check if SMU is running in protected mode*/
if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMU_FIRMWARE, SMU_MODE)) {
result = tonga_start_in_non_protection_mode(smumgr);
result = tonga_start_in_non_protection_mode(hwmgr);
if (result)
return result;
} else {
result = tonga_start_in_protection_mode(smumgr);
result = tonga_start_in_protection_mode(hwmgr);
if (result)
return result;
}
}
result = smu7_request_smu_load_fw(smumgr);
result = smu7_request_smu_load_fw(hwmgr);
return result;
}
......@@ -167,7 +167,7 @@ static int tonga_start_smu(struct pp_smumgr *smumgr)
* @param smcAddress the address in the SMC RAM to access.
* @param value to write to the SMC SRAM.
*/
static int tonga_smu_init(struct pp_smumgr *smumgr)
static int tonga_smu_init(struct pp_hwmgr *hwmgr)
{
struct tonga_smumgr *tonga_priv = NULL;
int i;
......@@ -176,9 +176,9 @@ static int tonga_smu_init(struct pp_smumgr *smumgr)
if (tonga_priv == NULL)
return -ENOMEM;
smumgr->backend = tonga_priv;
hwmgr->smumgr->backend = tonga_priv;
if (smu7_init(smumgr))
if (smu7_init(hwmgr))
return -EINVAL;
for (i = 0; i < SMU72_MAX_LEVELS_GRAPHICS; i++)
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册
反馈
建议
客服 返回
顶部