提交 ae65a26d 编写于 作者: M Monk Liu 提交者: Alex Deucher

drm/amdgpu:add META_DATA struct for CSA/SRIOV v2

META-DATA is used in GFX cmd submit, we have two
format suit for META-DATA-init, one is legacy and another
is for chained-ib preempt, which is used in vulkan
UMD.

v2: drop use CP version number to judge if chain-ib
supports or not, we wait for it mature
Signed-off-by: NMonk Liu <Monk.Liu@amd.com>
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 a1970a63
master alk-4.19.24 alk-4.19.30 alk-4.19.34 alk-4.19.36 alk-4.19.43 alk-4.19.48 alk-4.19.57 ck-4.19.67 ck-4.19.81 ck-4.19.91 github/fork/deepanshu1422/fix-typo-in-comment github/fork/haosdent/fix-typo linux-next v4.19.91 v4.19.90 v4.19.89 v4.19.88 v4.19.87 v4.19.86 v4.19.85 v4.19.84 v4.19.83 v4.19.82 v4.19.81 v4.19.80 v4.19.79 v4.19.78 v4.19.77 v4.19.76 v4.19.75 v4.19.74 v4.19.73 v4.19.72 v4.19.71 v4.19.70 v4.19.69 v4.19.68 v4.19.67 v4.19.66 v4.19.65 v4.19.64 v4.19.63 v4.19.62 v4.19.61 v4.19.60 v4.19.59 v4.19.58 v4.19.57 v4.19.56 v4.19.55 v4.19.54 v4.19.53 v4.19.52 v4.19.51 v4.19.50 v4.19.49 v4.19.48 v4.19.47 v4.19.46 v4.19.45 v4.19.44 v4.19.43 v4.19.42 v4.19.41 v4.19.40 v4.19.39 v4.19.38 v4.19.37 v4.19.36 v4.19.35 v4.19.34 v4.19.33 v4.19.32 v4.19.31 v4.19.30 v4.19.29 v4.19.28 v4.19.27 v4.19.26 v4.19.25 v4.19.24 v4.19.23 v4.19.22 v4.19.21 v4.19.20 v4.19.19 v4.19.18 v4.19.17 v4.19.16 v4.19.15 v4.19.14 v4.19.13 v4.19.12 v4.19.11 v4.19.10 v4.19.9 v4.19.8 v4.19.7 v4.19.6 v4.19.5 v4.19.4 v4.19.3 v4.19.2 v4.19.1 v4.19 v4.19-rc8 v4.19-rc7 v4.19-rc6 v4.19-rc5 v4.19-rc4 v4.19-rc3 v4.19-rc2 v4.19-rc1 ck-release-21 ck-release-20 ck-release-19.2 ck-release-19.1 ck-release-19 ck-release-18 ck-release-17.2 ck-release-17.1 ck-release-17 ck-release-16 ck-release-15.1 ck-release-15 ck-release-14 ck-release-13.2 ck-release-13 ck-release-12 ck-release-11 ck-release-10 ck-release-9 ck-release-7 alk-release-15 alk-release-14 alk-release-13.2 alk-release-13 alk-release-12 alk-release-11 alk-release-10 alk-release-9 alk-release-7
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......@@ -44,6 +44,7 @@ struct amdgpu_virt {
uint32_t caps;
struct amdgpu_bo *csa_obj;
uint64_t csa_vmid0_addr;
bool chained_ib_support;
uint32_t reg_val_offs;
struct mutex lock;
struct amdgpu_irq_src ack_irq;
......
......@@ -936,6 +936,13 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
goto out;
cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
/* chain ib ucode isn't formal released, just disable it by far
* TODO: when ucod ready we should use ucode version to judge if
* chain-ib support or not.
*/
adev->virt.chained_ib_support = false;
adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
......
......@@ -28,4 +28,116 @@ void vi_srbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
int vi_set_ip_blocks(struct amdgpu_device *adev);
struct amdgpu_ce_ib_state
{
uint32_t ce_ib_completion_status;
uint32_t ce_constegnine_count;
uint32_t ce_ibOffset_ib1;
uint32_t ce_ibOffset_ib2;
}; /* Total of 4 DWORD */
struct amdgpu_de_ib_state
{
uint32_t ib_completion_status;
uint32_t de_constEngine_count;
uint32_t ib_offset_ib1;
uint32_t ib_offset_ib2;
uint32_t preamble_begin_ib1;
uint32_t preamble_begin_ib2;
uint32_t preamble_end_ib1;
uint32_t preamble_end_ib2;
uint32_t draw_indirect_baseLo;
uint32_t draw_indirect_baseHi;
uint32_t disp_indirect_baseLo;
uint32_t disp_indirect_baseHi;
uint32_t gds_backup_addrlo;
uint32_t gds_backup_addrhi;
uint32_t index_base_addrlo;
uint32_t index_base_addrhi;
uint32_t sample_cntl;
}; /* Total of 17 DWORD */
struct amdgpu_ce_ib_state_chained_ib
{
/* section of non chained ib part */
uint32_t ce_ib_completion_status;
uint32_t ce_constegnine_count;
uint32_t ce_ibOffset_ib1;
uint32_t ce_ibOffset_ib2;
/* section of chained ib */
uint32_t ce_chainib_addrlo_ib1;
uint32_t ce_chainib_addrlo_ib2;
uint32_t ce_chainib_addrhi_ib1;
uint32_t ce_chainib_addrhi_ib2;
uint32_t ce_chainib_size_ib1;
uint32_t ce_chainib_size_ib2;
}; /* total 10 DWORD */
struct amdgpu_de_ib_state_chained_ib
{
/* section of non chained ib part */
uint32_t ib_completion_status;
uint32_t de_constEngine_count;
uint32_t ib_offset_ib1;
uint32_t ib_offset_ib2;
/* section of chained ib */
uint32_t chain_ib_addrlo_ib1;
uint32_t chain_ib_addrlo_ib2;
uint32_t chain_ib_addrhi_ib1;
uint32_t chain_ib_addrhi_ib2;
uint32_t chain_ib_size_ib1;
uint32_t chain_ib_size_ib2;
/* section of non chained ib part */
uint32_t preamble_begin_ib1;
uint32_t preamble_begin_ib2;
uint32_t preamble_end_ib1;
uint32_t preamble_end_ib2;
/* section of chained ib */
uint32_t chain_ib_pream_addrlo_ib1;
uint32_t chain_ib_pream_addrlo_ib2;
uint32_t chain_ib_pream_addrhi_ib1;
uint32_t chain_ib_pream_addrhi_ib2;
/* section of non chained ib part */
uint32_t draw_indirect_baseLo;
uint32_t draw_indirect_baseHi;
uint32_t disp_indirect_baseLo;
uint32_t disp_indirect_baseHi;
uint32_t gds_backup_addrlo;
uint32_t gds_backup_addrhi;
uint32_t index_base_addrlo;
uint32_t index_base_addrhi;
uint32_t sample_cntl;
}; /* Total of 27 DWORD */
struct amdgpu_gfx_meta_data
{
/* 4 DWORD, address must be 4KB aligned */
struct amdgpu_ce_ib_state ce_payload;
uint32_t reserved1[60];
/* 17 DWORD, address must be 64B aligned */
struct amdgpu_de_ib_state de_payload;
/* PFP IB base address which get pre-empted */
uint32_t DeIbBaseAddrLo;
uint32_t DeIbBaseAddrHi;
uint32_t reserved2[941];
}; /* Total of 4K Bytes */
struct amdgpu_gfx_meta_data_chained_ib
{
/* 10 DWORD, address must be 4KB aligned */
struct amdgpu_ce_ib_state_chained_ib ce_payload;
uint32_t reserved1[54];
/* 27 DWORD, address must be 64B aligned */
struct amdgpu_de_ib_state_chained_ib de_payload;
/* PFP IB base address which get pre-empted */
uint32_t DeIbBaseAddrLo;
uint32_t DeIbBaseAddrHi;
uint32_t reserved2[931];
}; /* Total of 4K Bytes */
#endif
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