提交 a571cb17 编写于 作者: P Peter Ujfalusi 提交者: Mark Brown

ASoC: tas2552: Configure the WCLK frequency based on the stream

Instead of hard wiring the WCLK frequency at probe time do it runtime.
The hard wired 88_96KHz was not even setting the correct bits since it was
defined as (1 << 6) which will  change the I2S_OUT_SEL bit and will leave
the amplifier configured for 8KHz.
At the same time clean up and fix the CFG3 register bits.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
上级 d20b098d
master alk-4.19.24 alk-4.19.30 alk-4.19.34 alk-4.19.36 alk-4.19.43 alk-4.19.48 alk-4.19.57 ck-4.19.67 ck-4.19.81 ck-4.19.91 github/fork/deepanshu1422/fix-typo-in-comment github/fork/haosdent/fix-typo linux-next v4.19.91 v4.19.90 v4.19.89 v4.19.88 v4.19.87 v4.19.86 v4.19.85 v4.19.84 v4.19.83 v4.19.82 v4.19.81 v4.19.80 v4.19.79 v4.19.78 v4.19.77 v4.19.76 v4.19.75 v4.19.74 v4.19.73 v4.19.72 v4.19.71 v4.19.70 v4.19.69 v4.19.68 v4.19.67 v4.19.66 v4.19.65 v4.19.64 v4.19.63 v4.19.62 v4.19.61 v4.19.60 v4.19.59 v4.19.58 v4.19.57 v4.19.56 v4.19.55 v4.19.54 v4.19.53 v4.19.52 v4.19.51 v4.19.50 v4.19.49 v4.19.48 v4.19.47 v4.19.46 v4.19.45 v4.19.44 v4.19.43 v4.19.42 v4.19.41 v4.19.40 v4.19.39 v4.19.38 v4.19.37 v4.19.36 v4.19.35 v4.19.34 v4.19.33 v4.19.32 v4.19.31 v4.19.30 v4.19.29 v4.19.28 v4.19.27 v4.19.26 v4.19.25 v4.19.24 v4.19.23 v4.19.22 v4.19.21 v4.19.20 v4.19.19 v4.19.18 v4.19.17 v4.19.16 v4.19.15 v4.19.14 v4.19.13 v4.19.12 v4.19.11 v4.19.10 v4.19.9 v4.19.8 v4.19.7 v4.19.6 v4.19.5 v4.19.4 v4.19.3 v4.19.2 v4.19.1 v4.19 v4.19-rc8 v4.19-rc7 v4.19-rc6 v4.19-rc5 v4.19-rc4 v4.19-rc3 v4.19-rc2 v4.19-rc1 ck-release-21 ck-release-20 ck-release-19.2 ck-release-19.1 ck-release-19 ck-release-18 ck-release-17.2 ck-release-17.1 ck-release-17 ck-release-16 ck-release-15.1 ck-release-15 ck-release-14 ck-release-13.2 ck-release-13 ck-release-12 ck-release-11 ck-release-10 ck-release-9 ck-release-7 alk-release-15 alk-release-14 alk-release-13.2 alk-release-13 alk-release-12 alk-release-11 alk-release-10 alk-release-9 alk-release-7
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......@@ -168,7 +168,7 @@ static int tas2552_hw_params(struct snd_pcm_substream *substream,
int d;
int cpf;
u8 p, j;
u8 ser_ctrl1_reg;
u8 ser_ctrl1_reg, wclk_rate;
switch (params_width(params)) {
case 16:
......@@ -206,6 +206,45 @@ static int tas2552_hw_params(struct snd_pcm_substream *substream,
TAS2552_WORDLENGTH_MASK | TAS2552_CLKSPERFRAME_MASK,
ser_ctrl1_reg);
switch (params_rate(params)) {
case 8000:
wclk_rate = TAS2552_WCLK_FREQ_8KHZ;
break;
case 11025:
case 12000:
wclk_rate = TAS2552_WCLK_FREQ_11_12KHZ;
break;
case 16000:
wclk_rate = TAS2552_WCLK_FREQ_16KHZ;
break;
case 22050:
case 24000:
wclk_rate = TAS2552_WCLK_FREQ_22_24KHZ;
break;
case 32000:
wclk_rate = TAS2552_WCLK_FREQ_32KHZ;
break;
case 44100:
case 48000:
wclk_rate = TAS2552_WCLK_FREQ_44_48KHZ;
break;
case 88200:
case 96000:
wclk_rate = TAS2552_WCLK_FREQ_88_96KHZ;
break;
case 176400:
case 192000:
wclk_rate = TAS2552_WCLK_FREQ_176_192KHZ;
break;
default:
dev_err(codec->dev, "Not supported sample rate: %d\n",
params_rate(params));
return -EINVAL;
}
snd_soc_update_bits(codec, TAS2552_CFG_3, TAS2552_WCLK_FREQ_MASK,
wclk_rate);
if (!tas2552->pll_clkin)
return -EINVAL;
......@@ -503,7 +542,7 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec)
snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_MUTE, TAS2552_MUTE);
snd_soc_write(codec, TAS2552_CFG_3, TAS2552_I2S_OUT_SEL |
TAS2552_DIN_SRC_SEL_AVG_L_R | TAS2552_88_96KHZ);
TAS2552_DIN_SRC_SEL_AVG_L_R);
snd_soc_write(codec, TAS2552_DOUT, TAS2552_PDM_DATA_I);
snd_soc_write(codec, TAS2552_OUTPUT_DATA, TAS2552_PDM_DATA_V_I | 0x8);
snd_soc_write(codec, TAS2552_BOOST_PT_CTRL, TAS2552_APT_DELAY_200 |
......
......@@ -62,6 +62,24 @@
#define TAS2552_LIM_EN (1 << 2)
#define TAS2552_IVSENSE_EN (1 << 1)
/* CFG3 Register Masks */
#define TAS2552_WCLK_FREQ_8KHZ (0x0 << 0)
#define TAS2552_WCLK_FREQ_11_12KHZ (0x1 << 0)
#define TAS2552_WCLK_FREQ_16KHZ (0x2 << 0)
#define TAS2552_WCLK_FREQ_22_24KHZ (0x3 << 0)
#define TAS2552_WCLK_FREQ_32KHZ (0x4 << 0)
#define TAS2552_WCLK_FREQ_44_48KHZ (0x5 << 0)
#define TAS2552_WCLK_FREQ_88_96KHZ (0x6 << 0)
#define TAS2552_WCLK_FREQ_176_192KHZ (0x7 << 0)
#define TAS2552_WCLK_FREQ_MASK TAS2552_WCLK_FREQ_176_192KHZ
#define TAS2552_DIN_SRC_SEL_MUTED (0x0 << 3)
#define TAS2552_DIN_SRC_SEL_LEFT (0x1 << 3)
#define TAS2552_DIN_SRC_SEL_RIGHT (0x2 << 3)
#define TAS2552_DIN_SRC_SEL_AVG_L_R (0x3 << 3)
#define TAS2552_PDM_IN_SEL (1 << 5)
#define TAS2552_I2S_OUT_SEL (1 << 6)
#define TAS2552_ANALOG_IN_SEL (1 << 7)
/* DOUT Register Masks */
#define TAS2552_SDOUT_TRISTATE (1 << 2)
......@@ -84,25 +102,6 @@
#define TAS2552_BCLKDIR (1 << 6)
#define TAS2552_WCLKDIR (1 << 7)
#define TAS2552_DIN_SRC_SEL_MUTED 0x00
#define TAS2552_DIN_SRC_SEL_LEFT (1 << 4)
#define TAS2552_DIN_SRC_SEL_RIGHT (1 << 5)
#define TAS2552_DIN_SRC_SEL_AVG_L_R (0x11 << 4)
#define TAS2552_PDM_IN_SEL (1 << 5)
#define TAS2552_I2S_OUT_SEL (1 << 6)
#define TAS2552_ANALOG_IN_SEL (1 << 7)
/* CFG3 WCLK Dividers */
#define TAS2552_8KHZ 0x00
#define TAS2552_11_12KHZ (1 << 1)
#define TAS2552_16KHZ (1 << 2)
#define TAS2552_22_24KHZ (1 << 3)
#define TAS2552_32KHZ (1 << 4)
#define TAS2552_44_48KHZ (1 << 5)
#define TAS2552_88_96KHZ (1 << 6)
#define TAS2552_176_192KHZ (1 << 7)
/* OUTPUT_DATA register */
#define TAS2552_PDM_DATA_I 0x00
#define TAS2552_PDM_DATA_V (1 << 6)
......
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