提交 73d43d00 编写于 作者: R Roland Stigge

Merge branch 'lpc32xx/fixup2' of...

Merge branch 'lpc32xx/fixup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into lpc32xx/tmp
上级 bb200029 cfac337b
master alk-4.19.24 alk-4.19.30 alk-4.19.34 alk-4.19.36 alk-4.19.43 alk-4.19.48 alk-4.19.57 ck-4.19.67 ck-4.19.81 ck-4.19.91 github/fork/deepanshu1422/fix-typo-in-comment github/fork/haosdent/fix-typo linux-next v4.19.91 v4.19.90 v4.19.89 v4.19.88 v4.19.87 v4.19.86 v4.19.85 v4.19.84 v4.19.83 v4.19.82 v4.19.81 v4.19.80 v4.19.79 v4.19.78 v4.19.77 v4.19.76 v4.19.75 v4.19.74 v4.19.73 v4.19.72 v4.19.71 v4.19.70 v4.19.69 v4.19.68 v4.19.67 v4.19.66 v4.19.65 v4.19.64 v4.19.63 v4.19.62 v4.19.61 v4.19.60 v4.19.59 v4.19.58 v4.19.57 v4.19.56 v4.19.55 v4.19.54 v4.19.53 v4.19.52 v4.19.51 v4.19.50 v4.19.49 v4.19.48 v4.19.47 v4.19.46 v4.19.45 v4.19.44 v4.19.43 v4.19.42 v4.19.41 v4.19.40 v4.19.39 v4.19.38 v4.19.37 v4.19.36 v4.19.35 v4.19.34 v4.19.33 v4.19.32 v4.19.31 v4.19.30 v4.19.29 v4.19.28 v4.19.27 v4.19.26 v4.19.25 v4.19.24 v4.19.23 v4.19.22 v4.19.21 v4.19.20 v4.19.19 v4.19.18 v4.19.17 v4.19.16 v4.19.15 v4.19.14 v4.19.13 v4.19.12 v4.19.11 v4.19.10 v4.19.9 v4.19.8 v4.19.7 v4.19.6 v4.19.5 v4.19.4 v4.19.3 v4.19.2 v4.19.1 v4.19 v4.19-rc8 v4.19-rc7 v4.19-rc6 v4.19-rc5 v4.19-rc4 v4.19-rc3 v4.19-rc2 v4.19-rc1 ck-release-21 ck-release-20 ck-release-19.2 ck-release-19.1 ck-release-19 ck-release-18 ck-release-17.2 ck-release-17.1 ck-release-17 ck-release-16 ck-release-15.1 ck-release-15 ck-release-14 ck-release-13.2 ck-release-13 ck-release-12 ck-release-11 ck-release-10 ck-release-9 ck-release-7 alk-release-15 alk-release-14 alk-release-13.2 alk-release-13 alk-release-12 alk-release-11 alk-release-10 alk-release-9 alk-release-7
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......@@ -591,42 +591,42 @@
/*
* Timer/counter register offsets
*/
#define LCP32XX_TIMER_IR(x) io_p2v((x) + 0x00)
#define LCP32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
#define LCP32XX_TIMER_TC(x) io_p2v((x) + 0x08)
#define LCP32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
#define LCP32XX_TIMER_PC(x) io_p2v((x) + 0x10)
#define LCP32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
#define LCP32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
#define LCP32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
#define LCP32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
#define LCP32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
#define LCP32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
#define LCP32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
#define LCP32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
#define LCP32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
#define LCP32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
#define LCP32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
#define LCP32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00)
#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08)
#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10)
#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
/*
* ir register definitions
*/
#define LCP32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
#define LCP32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
/*
* tcr register definitions
*/
#define LCP32XX_TIMER_CNTR_TCR_EN 0x1
#define LCP32XX_TIMER_CNTR_TCR_RESET 0x2
#define LPC32XX_TIMER_CNTR_TCR_EN 0x1
#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2
/*
* mcr register definitions
*/
#define LCP32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
#define LCP32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
#define LCP32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
/*
* Standard UART register offsets
......@@ -690,5 +690,8 @@
#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130)
#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134)
#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138)
#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
#endif
......@@ -13,7 +13,7 @@
/*
* LPC32XX CPU and system power management
*
* The LCP32XX has three CPU modes for controlling system power: run,
* The LPC32XX has three CPU modes for controlling system power: run,
* direct-run, and halt modes. When switching between halt and run modes,
* the CPU transistions through direct-run mode. For Linux, direct-run
* mode is not used in normal operation. Halt mode is used when the
......
......@@ -34,11 +34,11 @@
static int lpc32xx_clkevt_next_event(unsigned long delta,
struct clock_event_device *dev)
{
__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
return 0;
}
......@@ -58,7 +58,7 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
* disable the timer to wait for the first call to
* set_next_event().
*/
__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
break;
case CLOCK_EVT_MODE_UNUSED:
......@@ -81,8 +81,8 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
struct clock_event_device *evt = &lpc32xx_clkevt;
/* Clear match */
__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
evt->event_handler(evt);
......@@ -128,14 +128,14 @@ static void __init lpc32xx_timer_init(void)
clkrate = clkrate / clk_get_pclk_div();
/* Initial timer setup */
__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
__raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
LCP32XX_TIMER_CNTR_MCR_STOP(0) |
LCP32XX_TIMER_CNTR_MCR_RESET(0),
LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
__raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
LPC32XX_TIMER_CNTR_MCR_STOP(0) |
LPC32XX_TIMER_CNTR_MCR_RESET(0),
LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
/* Setup tick interrupt */
setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
......@@ -151,14 +151,14 @@ static void __init lpc32xx_timer_init(void)
clockevents_register_device(&lpc32xx_clkevt);
/* Use timer1 as clock source. */
__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
__raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
"lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
}
......
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