radeon.h 65.8 KB
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/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __RADEON_H__
#define __RADEON_H__

/* TODO: Here are things that needs to be done :
 *	- surface allocator & initializer : (bit like scratch reg) should
 *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
 *	  related to surface
 *	- WB : write back stuff (do it bit like scratch reg things)
 *	- Vblank : look at Jesse's rework and what we should do
 *	- r600/r700: gart & cp
 *	- cs : clean cs ioctl use bitmap & things like that.
 *	- power management stuff
 *	- Barrier in gart code
 *	- Unmappabled vram ?
 *	- TESTING, TESTING, TESTING
 */

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/* Initialization path:
 *  We expect that acceleration initialization might fail for various
 *  reasons even thought we work hard to make it works on most
 *  configurations. In order to still have a working userspace in such
 *  situation the init path must succeed up to the memory controller
 *  initialization point. Failure before this point are considered as
 *  fatal error. Here is the init callchain :
 *      radeon_device_init  perform common structure, mutex initialization
 *      asic_init           setup the GPU memory layout and perform all
 *                          one time initialization (failure in this
 *                          function are considered fatal)
 *      asic_startup        setup the GPU acceleration, in order to
 *                          follow guideline the first thing this
 *                          function should do is setting the GPU
 *                          memory controller (only MC setup failure
 *                          are considered as fatal)
 */

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#include <linux/atomic.h>
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#include <linux/wait.h>
#include <linux/list.h>
#include <linux/kref.h>

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#include <ttm/ttm_bo_api.h>
#include <ttm/ttm_bo_driver.h>
#include <ttm/ttm_placement.h>
#include <ttm/ttm_module.h>
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#include <ttm/ttm_execbuf_util.h>
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#include "radeon_family.h"
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#include "radeon_mode.h"
#include "radeon_reg.h"

/*
 * Modules parameters.
 */
extern int radeon_no_wb;
extern int radeon_modeset;
extern int radeon_dynclks;
extern int radeon_r4xx_atom;
extern int radeon_agpmode;
extern int radeon_vram_limit;
extern int radeon_gart_size;
extern int radeon_benchmarking;
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extern int radeon_testing;
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extern int radeon_connector_table;
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extern int radeon_tv;
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extern int radeon_audio;
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extern int radeon_disp_priority;
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extern int radeon_hw_i2c;
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extern int radeon_pcie_gen2;
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extern int radeon_msi;
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extern int radeon_lockup_timeout;
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extern int radeon_fastfb;
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/*
 * Copy from radeon_drv.h so we don't have to include both and have conflicting
 * symbol;
 */
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#define RADEON_MAX_USEC_TIMEOUT			100000	/* 100 ms */
#define RADEON_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
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/* RADEON_IB_POOL_SIZE must be a power of 2 */
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#define RADEON_IB_POOL_SIZE			16
#define RADEON_DEBUGFS_MAX_COMPONENTS		32
#define RADEONFB_CONN_LIMIT			4
#define RADEON_BIOS_NUM_SCRATCH			8
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/* max number of rings */
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#define RADEON_NUM_RINGS			6
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/* fence seq are set to this number when signaled */
#define RADEON_FENCE_SIGNALED_SEQ		0LL
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/* internal ring indices */
/* r1xx+ has gfx CP ring */
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#define RADEON_RING_TYPE_GFX_INDEX	0
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/* cayman has 2 compute CP rings */
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#define CAYMAN_RING_TYPE_CP1_INDEX	1
#define CAYMAN_RING_TYPE_CP2_INDEX	2
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/* R600+ has an async dma ring */
#define R600_RING_TYPE_DMA_INDEX		3
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/* cayman add a second async dma ring */
#define CAYMAN_RING_TYPE_DMA1_INDEX		4
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/* R600+ */
#define R600_RING_TYPE_UVD_INDEX	5

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/* hardcode those limit for now */
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#define RADEON_VA_IB_OFFSET			(1 << 20)
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#define RADEON_VA_RESERVED_SIZE			(8 << 20)
#define RADEON_IB_VM_MAX_SIZE			(64 << 10)
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/* reset flags */
#define RADEON_RESET_GFX			(1 << 0)
#define RADEON_RESET_COMPUTE			(1 << 1)
#define RADEON_RESET_DMA			(1 << 2)
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#define RADEON_RESET_CP				(1 << 3)
#define RADEON_RESET_GRBM			(1 << 4)
#define RADEON_RESET_DMA1			(1 << 5)
#define RADEON_RESET_RLC			(1 << 6)
#define RADEON_RESET_SEM			(1 << 7)
#define RADEON_RESET_IH				(1 << 8)
#define RADEON_RESET_VMC			(1 << 9)
#define RADEON_RESET_MC				(1 << 10)
#define RADEON_RESET_DISPLAY			(1 << 11)
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/*
 * Errata workarounds.
 */
enum radeon_pll_errata {
	CHIP_ERRATA_R300_CG             = 0x00000001,
	CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
	CHIP_ERRATA_PLL_DELAY           = 0x00000004
};


struct radeon_device;


/*
 * BIOS.
 */
bool radeon_get_bios(struct radeon_device *rdev);

/*
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 * Dummy page
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 */
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struct radeon_dummy_page {
	struct page	*page;
	dma_addr_t	addr;
};
int radeon_dummy_page_init(struct radeon_device *rdev);
void radeon_dummy_page_fini(struct radeon_device *rdev);

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/*
 * Clocks
 */
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struct radeon_clock {
	struct radeon_pll p1pll;
	struct radeon_pll p2pll;
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	struct radeon_pll dcpll;
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	struct radeon_pll spll;
	struct radeon_pll mpll;
	/* 10 Khz units */
	uint32_t default_mclk;
	uint32_t default_sclk;
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	uint32_t default_dispclk;
	uint32_t dp_extclk;
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	uint32_t max_pixel_clock;
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};

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/*
 * Power management
 */
int radeon_pm_init(struct radeon_device *rdev);
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void radeon_pm_fini(struct radeon_device *rdev);
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void radeon_pm_compute_clocks(struct radeon_device *rdev);
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void radeon_pm_suspend(struct radeon_device *rdev);
void radeon_pm_resume(struct radeon_device *rdev);
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void radeon_combios_get_power_modes(struct radeon_device *rdev);
void radeon_atombios_get_power_modes(struct radeon_device *rdev);
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int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
				   u8 clock_type,
				   u32 clock,
				   bool strobe_mode,
				   struct atom_clock_dividers *dividers);
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void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
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void rs690_pm_info(struct radeon_device *rdev);
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extern int rv6xx_get_temp(struct radeon_device *rdev);
extern int rv770_get_temp(struct radeon_device *rdev);
extern int evergreen_get_temp(struct radeon_device *rdev);
extern int sumo_get_temp(struct radeon_device *rdev);
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extern int si_get_temp(struct radeon_device *rdev);
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extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
				    unsigned *bankh, unsigned *mtaspect,
				    unsigned *tile_split);
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/*
 * Fences.
 */
struct radeon_fence_driver {
	uint32_t			scratch_reg;
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	uint64_t			gpu_addr;
	volatile uint32_t		*cpu_addr;
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	/* sync_seq is protected by ring emission lock */
	uint64_t			sync_seq[RADEON_NUM_RINGS];
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	atomic64_t			last_seq;
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	unsigned long			last_activity;
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	bool				initialized;
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};

struct radeon_fence {
	struct radeon_device		*rdev;
	struct kref			kref;
	/* protected by radeon_fence.lock */
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	uint64_t			seq;
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	/* RB, DMA, etc. */
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	unsigned			ring;
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};

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int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
int radeon_fence_driver_init(struct radeon_device *rdev);
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void radeon_fence_driver_fini(struct radeon_device *rdev);
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void radeon_fence_driver_force_completion(struct radeon_device *rdev);
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int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
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void radeon_fence_process(struct radeon_device *rdev, int ring);
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bool radeon_fence_signaled(struct radeon_fence *fence);
int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
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int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
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int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
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int radeon_fence_wait_any(struct radeon_device *rdev,
			  struct radeon_fence **fences,
			  bool intr);
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struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
void radeon_fence_unref(struct radeon_fence **fence);
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unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
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bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
						      struct radeon_fence *b)
{
	if (!a) {
		return b;
	}

	if (!b) {
		return a;
	}

	BUG_ON(a->ring != b->ring);

	if (a->seq > b->seq) {
		return a;
	} else {
		return b;
	}
}
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static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
					   struct radeon_fence *b)
{
	if (!a) {
		return false;
	}

	if (!b) {
		return true;
	}

	BUG_ON(a->ring != b->ring);

	return a->seq < b->seq;
}

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/*
 * Tiling registers
 */
struct radeon_surface_reg {
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	struct radeon_bo *bo;
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};

#define RADEON_GEM_MAX_SURFACES 8
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/*
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 * TTM.
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 */
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struct radeon_mman {
	struct ttm_bo_global_ref        bo_global_ref;
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	struct drm_global_reference	mem_global_ref;
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	struct ttm_bo_device		bdev;
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	bool				mem_global_referenced;
	bool				initialized;
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};

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/* bo virtual address in a specific vm */
struct radeon_bo_va {
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	/* protected by bo being reserved */
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	struct list_head		bo_list;
	uint64_t			soffset;
	uint64_t			eoffset;
	uint32_t			flags;
	bool				valid;
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	unsigned			ref_count;

	/* protected by vm mutex */
	struct list_head		vm_list;

	/* constant after initialization */
	struct radeon_vm		*vm;
	struct radeon_bo		*bo;
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};

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struct radeon_bo {
	/* Protected by gem.mutex */
	struct list_head		list;
	/* Protected by tbo.reserved */
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	u32				placements[3];
	struct ttm_placement		placement;
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	struct ttm_buffer_object	tbo;
	struct ttm_bo_kmap_obj		kmap;
	unsigned			pin_count;
	void				*kptr;
	u32				tiling_flags;
	u32				pitch;
	int				surface_reg;
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	/* list of all virtual address to which this bo
	 * is associated to
	 */
	struct list_head		va;
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	/* Constant after initialization */
	struct radeon_device		*rdev;
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	struct drm_gem_object		gem_base;
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	struct ttm_bo_kmap_obj		dma_buf_vmap;
	pid_t				pid;
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};
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#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
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struct radeon_bo_list {
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	struct ttm_validate_buffer tv;
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	struct radeon_bo	*bo;
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	uint64_t		gpu_offset;
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	bool			written;
	unsigned		domain;
	unsigned		alt_domain;
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	u32			tiling_flags;
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};

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int radeon_gem_debugfs_init(struct radeon_device *rdev);

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/* sub-allocation manager, it has to be protected by another lock.
 * By conception this is an helper for other part of the driver
 * like the indirect buffer or semaphore, which both have their
 * locking.
 *
 * Principe is simple, we keep a list of sub allocation in offset
 * order (first entry has offset == 0, last entry has the highest
 * offset).
 *
 * When allocating new object we first check if there is room at
 * the end total_size - (last_object_offset + last_object_size) >=
 * alloc_size. If so we allocate new object there.
 *
 * When there is not enough room at the end, we start waiting for
 * each sub object until we reach object_offset+object_size >=
 * alloc_size, this object then become the sub object we return.
 *
 * Alignment can't be bigger than page size.
 *
 * Hole are not considered for allocation to keep things simple.
 * Assumption is that there won't be hole (all object on same
 * alignment).
 */
struct radeon_sa_manager {
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	wait_queue_head_t	wq;
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	struct radeon_bo	*bo;
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	struct list_head	*hole;
	struct list_head	flist[RADEON_NUM_RINGS];
	struct list_head	olist;
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	unsigned		size;
	uint64_t		gpu_addr;
	void			*cpu_ptr;
	uint32_t		domain;
};

struct radeon_sa_bo;

/* sub-allocation buffer */
struct radeon_sa_bo {
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	struct list_head		olist;
	struct list_head		flist;
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	struct radeon_sa_manager	*manager;
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	unsigned			soffset;
	unsigned			eoffset;
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	struct radeon_fence		*fence;
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};

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/*
 * GEM objects.
 */
struct radeon_gem {
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	struct mutex		mutex;
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	struct list_head	objects;
};

int radeon_gem_init(struct radeon_device *rdev);
void radeon_gem_fini(struct radeon_device *rdev);
int radeon_gem_object_create(struct radeon_device *rdev, int size,
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				int alignment, int initial_domain,
				bool discardable, bool kernel,
				struct drm_gem_object **obj);
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int radeon_mode_dumb_create(struct drm_file *file_priv,
			    struct drm_device *dev,
			    struct drm_mode_create_dumb *args);
int radeon_mode_dumb_mmap(struct drm_file *filp,
			  struct drm_device *dev,
			  uint32_t handle, uint64_t *offset_p);
int radeon_mode_dumb_destroy(struct drm_file *file_priv,
			     struct drm_device *dev,
			     uint32_t handle);
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/*
 * Semaphores.
 */
/* everything here is constant */
struct radeon_semaphore {
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	struct radeon_sa_bo		*sa_bo;
	signed				waiters;
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	uint64_t			gpu_addr;
};

int radeon_semaphore_create(struct radeon_device *rdev,
			    struct radeon_semaphore **semaphore);
void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
				  struct radeon_semaphore *semaphore);
void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
				struct radeon_semaphore *semaphore);
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int radeon_semaphore_sync_rings(struct radeon_device *rdev,
				struct radeon_semaphore *semaphore,
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				int signaler, int waiter);
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void radeon_semaphore_free(struct radeon_device *rdev,
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			   struct radeon_semaphore **semaphore,
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			   struct radeon_fence *fence);
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/*
 * GART structures, functions & helpers
 */
struct radeon_mc;

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#define RADEON_GPU_PAGE_SIZE 4096
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#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
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#define RADEON_GPU_PAGE_SHIFT 12
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#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
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struct radeon_gart {
	dma_addr_t			table_addr;
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	struct radeon_bo		*robj;
	void				*ptr;
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	unsigned			num_gpu_pages;
	unsigned			num_cpu_pages;
	unsigned			table_size;
	struct page			**pages;
	dma_addr_t			*pages_addr;
	bool				ready;
};

int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
void radeon_gart_table_ram_free(struct radeon_device *rdev);
int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
void radeon_gart_table_vram_free(struct radeon_device *rdev);
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int radeon_gart_table_vram_pin(struct radeon_device *rdev);
void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
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int radeon_gart_init(struct radeon_device *rdev);
void radeon_gart_fini(struct radeon_device *rdev);
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
			int pages);
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
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		     int pages, struct page **pagelist,
		     dma_addr_t *dma_addr);
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void radeon_gart_restore(struct radeon_device *rdev);
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/*
 * GPU MC structures, functions & helpers
 */
struct radeon_mc {
	resource_size_t		aper_size;
	resource_size_t		aper_base;
	resource_size_t		agp_base;
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	/* for some chips with <= 32MB we need to lie
	 * about vram size near mc fb location */
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	u64			mc_vram_size;
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	u64			visible_vram_size;
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	u64			gtt_size;
	u64			gtt_start;
	u64			gtt_end;
	u64			vram_start;
	u64			vram_end;
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	unsigned		vram_width;
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	u64			real_vram_size;
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	int			vram_mtrr;
	bool			vram_is_ddr;
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	bool			igp_sideport_enabled;
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	u64                     gtt_base_align;
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	u64                     mc_mask;
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};

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bool radeon_combios_sideport_present(struct radeon_device *rdev);
bool radeon_atombios_sideport_present(struct radeon_device *rdev);
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/*
 * GPU scratch registers structures, functions & helpers
 */
struct radeon_scratch {
	unsigned		num_reg;
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	uint32_t                reg_base;
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	bool			free[32];
	uint32_t		reg[32];
};

int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);


/*
 * IRQS.
 */
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struct radeon_unpin_work {
	struct work_struct work;
	struct radeon_device *rdev;
	int crtc_id;
	struct radeon_fence *fence;
	struct drm_pending_vblank_event *event;
	struct radeon_bo *old_rbo;
	u64 new_crtc_base;
};

struct r500_irq_stat_regs {
	u32 disp_int;
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	u32 hdmi0_status;
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};

struct r600_irq_stat_regs {
	u32 disp_int;
	u32 disp_int_cont;
	u32 disp_int_cont2;
	u32 d1grph_int;
	u32 d2grph_int;
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	u32 hdmi0_status;
	u32 hdmi1_status;
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};

struct evergreen_irq_stat_regs {
	u32 disp_int;
	u32 disp_int_cont;
	u32 disp_int_cont2;
	u32 disp_int_cont3;
	u32 disp_int_cont4;
	u32 disp_int_cont5;
	u32 d1grph_int;
	u32 d2grph_int;
	u32 d3grph_int;
	u32 d4grph_int;
	u32 d5grph_int;
	u32 d6grph_int;
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	u32 afmt_status1;
	u32 afmt_status2;
	u32 afmt_status3;
	u32 afmt_status4;
	u32 afmt_status5;
	u32 afmt_status6;
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};

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struct cik_irq_stat_regs {
	u32 disp_int;
	u32 disp_int_cont;
	u32 disp_int_cont2;
	u32 disp_int_cont3;
	u32 disp_int_cont4;
	u32 disp_int_cont5;
	u32 disp_int_cont6;
};

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union radeon_irq_stat_regs {
	struct r500_irq_stat_regs r500;
	struct r600_irq_stat_regs r600;
	struct evergreen_irq_stat_regs evergreen;
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	struct cik_irq_stat_regs cik;
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};

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#define RADEON_MAX_HPD_PINS 6
#define RADEON_MAX_CRTCS 6
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#define RADEON_MAX_AFMT_BLOCKS 6
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struct radeon_irq {
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	bool				installed;
	spinlock_t			lock;
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	atomic_t			ring_int[RADEON_NUM_RINGS];
628
	bool				crtc_vblank_int[RADEON_MAX_CRTCS];
629
	atomic_t			pflip[RADEON_MAX_CRTCS];
630 631 632 633
	wait_queue_head_t		vblank_queue;
	bool				hpd[RADEON_MAX_HPD_PINS];
	bool				afmt[RADEON_MAX_AFMT_BLOCKS];
	union radeon_irq_stat_regs	stat_regs;
634 635 636 637
};

int radeon_irq_kms_init(struct radeon_device *rdev);
void radeon_irq_kms_fini(struct radeon_device *rdev);
638 639
void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
640 641
void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
642 643 644 645
void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
646 647

/*
648
 * CP & rings.
649
 */
650

651
struct radeon_ib {
652 653 654 655
	struct radeon_sa_bo		*sa_bo;
	uint32_t			length_dw;
	uint64_t			gpu_addr;
	uint32_t			*ptr;
656
	int				ring;
657
	struct radeon_fence		*fence;
658
	struct radeon_vm		*vm;
659
	bool				is_const_ib;
660
	struct radeon_fence		*sync_to[RADEON_NUM_RINGS];
661
	struct radeon_semaphore		*semaphore;
662 663
};

664
struct radeon_ring {
665
	struct radeon_bo	*ring_obj;
666 667
	volatile uint32_t	*ring;
	unsigned		rptr;
668 669
	unsigned		rptr_offs;
	unsigned		rptr_reg;
670
	unsigned		rptr_save_reg;
671 672
	u64			next_rptr_gpu_addr;
	volatile u32		*next_rptr_cpu_addr;
673 674
	unsigned		wptr;
	unsigned		wptr_old;
675
	unsigned		wptr_reg;
676 677 678
	unsigned		ring_size;
	unsigned		ring_free_dw;
	int			count_dw;
679 680
	unsigned long		last_activity;
	unsigned		last_rptr;
681 682 683 684
	uint64_t		gpu_addr;
	uint32_t		align_mask;
	uint32_t		ptr_mask;
	bool			ready;
685 686 687
	u32			ptr_reg_shift;
	u32			ptr_reg_mask;
	u32			nop;
688
	u32			idx;
689 690
	u64			last_semaphore_signal_addr;
	u64			last_semaphore_wait_addr;
691 692
};

693 694 695
/*
 * VM
 */
696

697
/* maximum number of VMIDs */
698 699
#define RADEON_NUM_VM	16

700 701 702 703 704 705 706 707
/* defines number of bits in page table versus page directory,
 * a page is 4KB so we have 12 bits offset, 9 bits in the page
 * table and the remaining 19 bits are in the page directory */
#define RADEON_VM_BLOCK_SIZE   9

/* number of entries in page table */
#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)

708 709 710
struct radeon_vm {
	struct list_head		list;
	struct list_head		va;
711
	unsigned			id;
712 713 714 715 716 717 718 719

	/* contains the page directory */
	struct radeon_sa_bo		*page_directory;
	uint64_t			pd_gpu_addr;

	/* array of page tables, one for each page directory entry */
	struct radeon_sa_bo		**page_tables;

720 721 722
	struct mutex			mutex;
	/* last fence for cs using this vm */
	struct radeon_fence		*fence;
723 724
	/* last flush or NULL if we still need to flush */
	struct radeon_fence		*last_flush;
725 726 727
};

struct radeon_vm_manager {
728
	struct mutex			lock;
729
	struct list_head		lru_vm;
730
	struct radeon_fence		*active[RADEON_NUM_VM];
731 732 733 734 735 736
	struct radeon_sa_manager	sa_manager;
	uint32_t			max_pfn;
	/* number of VMIDs */
	unsigned			nvm;
	/* vram base address for page table entry  */
	u64				vram_base_offset;
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	/* is vm enabled? */
	bool				enabled;
739 740 741 742 743 744 745 746 747
};

/*
 * file private structure
 */
struct radeon_fpriv {
	struct radeon_vm		vm;
};

748 749 750 751
/*
 * R6xx+ IH ring
 */
struct r600_ih {
752
	struct radeon_bo	*ring_obj;
753 754 755 756 757
	volatile uint32_t	*ring;
	unsigned		rptr;
	unsigned		ring_size;
	uint64_t		gpu_addr;
	uint32_t		ptr_mask;
758
	atomic_t		lock;
759 760 761
	bool                    enabled;
};

762 763 764 765 766 767 768 769 770 771
struct r600_blit_cp_primitives {
	void (*set_render_target)(struct radeon_device *rdev, int format,
				  int w, int h, u64 gpu_addr);
	void (*cp_set_surface_sync)(struct radeon_device *rdev,
				    u32 sync_type, u32 size,
				    u64 mc_addr);
	void (*set_shaders)(struct radeon_device *rdev);
	void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
	void (*set_tex_resource)(struct radeon_device *rdev,
				 int format, int w, int h, int pitch,
772
				 u64 gpu_addr, u32 size);
773 774 775 776 777 778
	void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
			     int x2, int y2);
	void (*draw_auto)(struct radeon_device *rdev);
	void (*set_default_state)(struct radeon_device *rdev);
};

779
struct r600_blit {
780
	struct radeon_bo	*shader_obj;
781 782 783 784
	struct r600_blit_cp_primitives primitives;
	int max_dim;
	int ring_size_common;
	int ring_size_per_loop;
785 786 787 788 789 790
	u64 shader_gpu_addr;
	u32 vs_offset, ps_offset;
	u32 state_offset;
	u32 state_len;
};

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/*
 * SI RLC stuff
 */
struct si_rlc {
	/* for power gating */
	struct radeon_bo	*save_restore_obj;
	uint64_t		save_restore_gpu_addr;
	/* for clear state */
	struct radeon_bo	*clear_state_obj;
	uint64_t		clear_state_gpu_addr;
};

803
int radeon_ib_get(struct radeon_device *rdev, int ring,
804 805
		  struct radeon_ib *ib, struct radeon_vm *vm,
		  unsigned size);
806
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
807
void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
808 809
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
		       struct radeon_ib *const_ib);
810 811
int radeon_ib_pool_init(struct radeon_device *rdev);
void radeon_ib_pool_fini(struct radeon_device *rdev);
812
int radeon_ib_ring_tests(struct radeon_device *rdev);
813
/* Ring access between begin & end cannot sleep */
814 815
bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
				      struct radeon_ring *ring);
816 817 818 819 820
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
821
void radeon_ring_undo(struct radeon_ring *ring);
822 823
void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
824
void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
825 826
void radeon_ring_lockup_update(struct radeon_ring *ring);
bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
827 828 829 830
unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
			    uint32_t **data);
int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
			unsigned size, uint32_t *data);
831
int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
832 833
		     unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
		     u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
834
void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
835 836


837 838 839 840 841
/* r600 async dma */
void r600_dma_stop(struct radeon_device *rdev);
int r600_dma_resume(struct radeon_device *rdev);
void r600_dma_fini(struct radeon_device *rdev);

842 843 844 845
void cayman_dma_stop(struct radeon_device *rdev);
int cayman_dma_resume(struct radeon_device *rdev);
void cayman_dma_fini(struct radeon_device *rdev);

846 847 848 849 850
/*
 * CS.
 */
struct radeon_cs_reloc {
	struct drm_gem_object		*gobj;
851 852
	struct radeon_bo		*robj;
	struct radeon_bo_list		lobj;
853 854 855 856 857 858 859
	uint32_t			handle;
	uint32_t			flags;
};

struct radeon_cs_chunk {
	uint32_t		chunk_id;
	uint32_t		length_dw;
860 861
	int			kpage_idx[2];
	uint32_t		*kpage[2];
862
	uint32_t		*kdata;
863 864 865
	void __user		*user_ptr;
	int			last_copied_page;
	int			last_page_index;
866 867 868
};

struct radeon_cs_parser {
869
	struct device		*dev;
870 871 872 873 874 875 876 877 878 879 880 881 882
	struct radeon_device	*rdev;
	struct drm_file		*filp;
	/* chunks */
	unsigned		nchunks;
	struct radeon_cs_chunk	*chunks;
	uint64_t		*chunks_array;
	/* IB */
	unsigned		idx;
	/* relocations */
	unsigned		nrelocs;
	struct radeon_cs_reloc	*relocs;
	struct radeon_cs_reloc	**relocs_ptr;
	struct list_head	validated;
883
	unsigned		dma_reloc_idx;
884 885 886
	/* indices of various chunks */
	int			chunk_ib_idx;
	int			chunk_relocs_idx;
887
	int			chunk_flags_idx;
888
	int			chunk_const_ib_idx;
889 890
	struct radeon_ib	ib;
	struct radeon_ib	const_ib;
891
	void			*track;
892
	unsigned		family;
893
	int			parser_error;
894 895 896
	u32			cs_flags;
	u32			ring;
	s32			priority;
897 898
};

899
extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
900
extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
901

902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921
struct radeon_cs_packet {
	unsigned	idx;
	unsigned	type;
	unsigned	reg;
	unsigned	opcode;
	int		count;
	unsigned	one_reg_wr;
};

typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
				      struct radeon_cs_packet *pkt,
				      unsigned idx, unsigned reg);
typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
				      struct radeon_cs_packet *pkt);


/*
 * AGP
 */
int radeon_agp_init(struct radeon_device *rdev);
922
void radeon_agp_resume(struct radeon_device *rdev);
923
void radeon_agp_suspend(struct radeon_device *rdev);
924 925 926 927 928 929 930
void radeon_agp_fini(struct radeon_device *rdev);


/*
 * Writeback
 */
struct radeon_wb {
931
	struct radeon_bo	*wb_obj;
932 933
	volatile uint32_t	*wb;
	uint64_t		gpu_addr;
934
	bool                    enabled;
935
	bool                    use_event;
936 937
};

938
#define RADEON_WB_SCRATCH_OFFSET 0
939
#define RADEON_WB_RING0_NEXT_RPTR 256
940
#define RADEON_WB_CP_RPTR_OFFSET 1024
941 942
#define RADEON_WB_CP1_RPTR_OFFSET 1280
#define RADEON_WB_CP2_RPTR_OFFSET 1536
943
#define R600_WB_DMA_RPTR_OFFSET   1792
944
#define R600_WB_IH_WPTR_OFFSET   2048
945
#define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
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Christian König 已提交
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#define R600_WB_UVD_RPTR_OFFSET  2560
947
#define R600_WB_EVENT_OFFSET     3072
948

949 950 951 952 953 954 955 956 957 958 959
/**
 * struct radeon_pm - power management datas
 * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
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Lucas De Marchi 已提交
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 * @sclk:          	GPU clock Mhz (core bandwidth depends of this clock)
961 962 963
 * @needed_bandwidth:   current bandwidth needs
 *
 * It keeps track of various data needed to take powermanagement decision.
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Lucas De Marchi 已提交
964
 * Bandwidth need is used to determine minimun clock of the GPU and memory.
965 966 967
 * Equation between gpu/memory clock and available bandwidth is hw dependent
 * (type of memory, bus size, efficiency, ...)
 */
968 969 970 971 972 973 974 975 976 977

enum radeon_pm_method {
	PM_METHOD_PROFILE,
	PM_METHOD_DYNPM,
};

enum radeon_dynpm_state {
	DYNPM_STATE_DISABLED,
	DYNPM_STATE_MINIMUM,
	DYNPM_STATE_PAUSED,
978 979
	DYNPM_STATE_ACTIVE,
	DYNPM_STATE_SUSPENDED,
980
};
981 982 983 984 985 986
enum radeon_dynpm_action {
	DYNPM_ACTION_NONE,
	DYNPM_ACTION_MINIMUM,
	DYNPM_ACTION_DOWNCLOCK,
	DYNPM_ACTION_UPCLOCK,
	DYNPM_ACTION_DEFAULT
987
};
988 989 990 991 992 993 994 995

enum radeon_voltage_type {
	VOLTAGE_NONE = 0,
	VOLTAGE_GPIO,
	VOLTAGE_VDDC,
	VOLTAGE_SW
};

996 997 998 999 1000 1001 1002 1003
enum radeon_pm_state_type {
	POWER_STATE_TYPE_DEFAULT,
	POWER_STATE_TYPE_POWERSAVE,
	POWER_STATE_TYPE_BATTERY,
	POWER_STATE_TYPE_BALANCED,
	POWER_STATE_TYPE_PERFORMANCE,
};

1004 1005 1006 1007
enum radeon_pm_profile_type {
	PM_PROFILE_DEFAULT,
	PM_PROFILE_AUTO,
	PM_PROFILE_LOW,
1008
	PM_PROFILE_MID,
1009 1010 1011 1012 1013
	PM_PROFILE_HIGH,
};

#define PM_PROFILE_DEFAULT_IDX 0
#define PM_PROFILE_LOW_SH_IDX  1
1014 1015 1016 1017 1018 1019
#define PM_PROFILE_MID_SH_IDX  2
#define PM_PROFILE_HIGH_SH_IDX 3
#define PM_PROFILE_LOW_MH_IDX  4
#define PM_PROFILE_MID_MH_IDX  5
#define PM_PROFILE_HIGH_MH_IDX 6
#define PM_PROFILE_MAX         7
1020 1021 1022 1023 1024 1025

struct radeon_pm_profile {
	int dpms_off_ps_idx;
	int dpms_on_ps_idx;
	int dpms_off_cm_idx;
	int dpms_on_cm_idx;
1026 1027
};

1028 1029 1030 1031 1032
enum radeon_int_thermal_type {
	THERMAL_TYPE_NONE,
	THERMAL_TYPE_RV6XX,
	THERMAL_TYPE_RV770,
	THERMAL_TYPE_EVERGREEN,
1033
	THERMAL_TYPE_SUMO,
1034
	THERMAL_TYPE_NI,
1035
	THERMAL_TYPE_SI,
1036
	THERMAL_TYPE_CI,
1037 1038
};

1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049
struct radeon_voltage {
	enum radeon_voltage_type type;
	/* gpio voltage */
	struct radeon_gpio_rec gpio;
	u32 delay; /* delay in usec from voltage drop to sclk change */
	bool active_high; /* voltage drop is active when bit is high */
	/* VDDC voltage */
	u8 vddc_id; /* index into vddc voltage table */
	u8 vddci_id; /* index into vddci voltage table */
	bool vddci_enabled;
	/* r6xx+ sw */
1050 1051 1052
	u16 voltage;
	/* evergreen+ vddci */
	u16 vddci;
1053 1054
};

1055 1056 1057
/* clock mode flags */
#define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)

1058 1059 1060 1061 1062 1063 1064
struct radeon_pm_clock_info {
	/* memory clock */
	u32 mclk;
	/* engine clock */
	u32 sclk;
	/* voltage info */
	struct radeon_voltage voltage;
1065
	/* standardized clock flags */
1066 1067 1068
	u32 flags;
};

1069
/* state flags */
1070
#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1071

1072
struct radeon_power_state {
1073
	enum radeon_pm_state_type type;
1074
	struct radeon_pm_clock_info *clock_info;
1075 1076 1077
	/* number of valid clock modes in this power state */
	int num_clock_modes;
	struct radeon_pm_clock_info *default_clock_mode;
1078 1079
	/* standardized state flags */
	u32 flags;
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Alex Deucher 已提交
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	u32 misc; /* vbios specific flags */
	u32 misc2; /* vbios specific flags */
	int pcie_lanes; /* pcie lanes */
1083 1084
};

1085 1086 1087 1088 1089
/*
 * Some modes are overclocked by very low value, accept them
 */
#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */

1090
struct radeon_pm {
1091
	struct mutex		mutex;
1092 1093
	/* write locked while reprogramming mclk */
	struct rw_semaphore	mclk_lock;
1094 1095
	u32			active_crtcs;
	int			active_crtc_count;
1096
	int			req_vblank;
1097
	bool			vblank_sync;
1098 1099 1100 1101 1102 1103 1104 1105 1106 1107
	fixed20_12		max_bandwidth;
	fixed20_12		igp_sideport_mclk;
	fixed20_12		igp_system_mclk;
	fixed20_12		igp_ht_link_clk;
	fixed20_12		igp_ht_link_width;
	fixed20_12		k8_bandwidth;
	fixed20_12		sideport_bandwidth;
	fixed20_12		ht_bandwidth;
	fixed20_12		core_bandwidth;
	fixed20_12		sclk;
1108
	fixed20_12		mclk;
1109
	fixed20_12		needed_bandwidth;
1110
	struct radeon_power_state *power_state;
1111 1112
	/* number of valid power states */
	int                     num_power_states;
1113 1114 1115 1116 1117 1118 1119
	int                     current_power_state_index;
	int                     current_clock_mode_index;
	int                     requested_power_state_index;
	int                     requested_clock_mode_index;
	int                     default_power_state_index;
	u32                     current_sclk;
	u32                     current_mclk;
1120 1121
	u16                     current_vddc;
	u16                     current_vddci;
1122 1123
	u32                     default_sclk;
	u32                     default_mclk;
1124 1125
	u16                     default_vddc;
	u16                     default_vddci;
1126
	struct radeon_i2c_chan *i2c_bus;
1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139
	/* selected pm method */
	enum radeon_pm_method     pm_method;
	/* dynpm power management */
	struct delayed_work	dynpm_idle_work;
	enum radeon_dynpm_state	dynpm_state;
	enum radeon_dynpm_action	dynpm_planned_action;
	unsigned long		dynpm_action_timeout;
	bool                    dynpm_can_upclock;
	bool                    dynpm_can_downclock;
	/* profile-based power management */
	enum radeon_pm_profile_type profile;
	int                     profile_index;
	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1140 1141 1142
	/* internal thermal controller on rv6xx+ */
	enum radeon_int_thermal_type int_thermal_type;
	struct device	        *int_hwmon_dev;
1143 1144
};

1145 1146 1147
int radeon_pm_get_type_index(struct radeon_device *rdev,
			     enum radeon_pm_state_type ps_type,
			     int instance);
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Christian König 已提交
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/*
 * UVD
 */
#define RADEON_MAX_UVD_HANDLES	10
#define RADEON_UVD_STACK_SIZE	(1024*1024)
#define RADEON_UVD_HEAP_SIZE	(1024*1024)

struct radeon_uvd {
	struct radeon_bo	*vcpu_bo;
	void			*cpu_addr;
	uint64_t		gpu_addr;
	atomic_t		handles[RADEON_MAX_UVD_HANDLES];
	struct drm_file		*filp[RADEON_MAX_UVD_HANDLES];
1161
	struct delayed_work	idle_work;
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Christian König 已提交
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};

int radeon_uvd_init(struct radeon_device *rdev);
void radeon_uvd_fini(struct radeon_device *rdev);
int radeon_uvd_suspend(struct radeon_device *rdev);
int radeon_uvd_resume(struct radeon_device *rdev);
int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
			      uint32_t handle, struct radeon_fence **fence);
int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
			       uint32_t handle, struct radeon_fence **fence);
void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
void radeon_uvd_free_handles(struct radeon_device *rdev,
			     struct drm_file *filp);
int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1176
void radeon_uvd_note_usage(struct radeon_device *rdev);
1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187
int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
				  unsigned vclk, unsigned dclk,
				  unsigned vco_min, unsigned vco_max,
				  unsigned fb_factor, unsigned fb_mask,
				  unsigned pd_min, unsigned pd_max,
				  unsigned pd_even,
				  unsigned *optimal_fb_div,
				  unsigned *optimal_vclk_div,
				  unsigned *optimal_dclk_div);
int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
                                unsigned cg_upll_func_cntl);
1188

1189 1190 1191 1192 1193 1194 1195 1196
struct r600_audio {
	int			channels;
	int			rate;
	int			bits_per_sample;
	u8			status_bits;
	u8			category_code;
};

1197 1198 1199
/*
 * Benchmarking
 */
1200
void radeon_benchmark(struct radeon_device *rdev, int test_number);
1201 1202


1203 1204 1205 1206
/*
 * Testing
 */
void radeon_test_moves(struct radeon_device *rdev);
1207
void radeon_test_ring_sync(struct radeon_device *rdev,
1208 1209
			   struct radeon_ring *cpA,
			   struct radeon_ring *cpB);
1210
void radeon_test_syncing(struct radeon_device *rdev);
1211 1212


1213 1214 1215
/*
 * Debugfs
 */
1216 1217 1218 1219 1220
struct radeon_debugfs {
	struct drm_info_list	*files;
	unsigned		num_files;
};

1221 1222 1223 1224 1225 1226 1227 1228 1229 1230
int radeon_debugfs_add_files(struct radeon_device *rdev,
			     struct drm_info_list *files,
			     unsigned nfiles);
int radeon_debugfs_fence_init(struct radeon_device *rdev);


/*
 * ASIC specific functions.
 */
struct radeon_asic {
1231
	int (*init)(struct radeon_device *rdev);
1232 1233 1234
	void (*fini)(struct radeon_device *rdev);
	int (*resume)(struct radeon_device *rdev);
	int (*suspend)(struct radeon_device *rdev);
1235
	void (*vga_set_state)(struct radeon_device *rdev, bool state);
1236
	int (*asic_reset)(struct radeon_device *rdev);
1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
	/* ioctl hw specific callback. Some hw might want to perform special
	 * operation on specific ioctl. For instance on wait idle some hw
	 * might want to perform and HDP flush through MMIO as it seems that
	 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
	 * through ring.
	 */
	void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
	/* check if 3D engine is idle */
	bool (*gui_idle)(struct radeon_device *rdev);
	/* wait for mc_idle */
	int (*mc_wait_for_idle)(struct radeon_device *rdev);
1248 1249
	/* get the reference clock */
	u32 (*get_xclk)(struct radeon_device *rdev);
1250 1251
	/* get the gpu clock counter */
	uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1252
	/* gart */
1253 1254 1255 1256
	struct {
		void (*tlb_flush)(struct radeon_device *rdev);
		int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
	} gart;
1257 1258 1259
	struct {
		int (*init)(struct radeon_device *rdev);
		void (*fini)(struct radeon_device *rdev);
1260 1261

		u32 pt_ring_index;
1262 1263 1264
		void (*set_page)(struct radeon_device *rdev,
				 struct radeon_ib *ib,
				 uint64_t pe,
1265 1266
				 uint64_t addr, unsigned count,
				 uint32_t incr, uint32_t flags);
1267
	} vm;
1268
	/* ring specific callbacks */
1269 1270
	struct {
		void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1271
		int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1272
		void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1273
		void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1274
				       struct radeon_semaphore *semaphore, bool emit_wait);
1275
		int (*cs_parse)(struct radeon_cs_parser *p);
1276 1277 1278
		void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
		int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
		int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1279
		bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1280
		void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1281
	} ring[RADEON_NUM_RINGS];
1282
	/* irqs */
1283 1284 1285 1286
	struct {
		int (*set)(struct radeon_device *rdev);
		int (*process)(struct radeon_device *rdev);
	} irq;
1287
	/* displays */
1288 1289 1290 1291 1292 1293 1294
	struct {
		/* display watermarks */
		void (*bandwidth_update)(struct radeon_device *rdev);
		/* get frame count */
		u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
		/* wait for vblank */
		void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1295 1296
		/* set backlight level */
		void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1297 1298
		/* get backlight level */
		u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1299 1300 1301
		/* audio callbacks */
		void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
		void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1302
	} display;
1303
	/* copy functions for bo handling */
1304 1305 1306 1307 1308
	struct {
		int (*blit)(struct radeon_device *rdev,
			    uint64_t src_offset,
			    uint64_t dst_offset,
			    unsigned num_gpu_pages,
1309
			    struct radeon_fence **fence);
1310 1311 1312 1313 1314
		u32 blit_ring_index;
		int (*dma)(struct radeon_device *rdev,
			   uint64_t src_offset,
			   uint64_t dst_offset,
			   unsigned num_gpu_pages,
1315
			   struct radeon_fence **fence);
1316 1317 1318 1319 1320 1321
		u32 dma_ring_index;
		/* method used for bo copy */
		int (*copy)(struct radeon_device *rdev,
			    uint64_t src_offset,
			    uint64_t dst_offset,
			    unsigned num_gpu_pages,
1322
			    struct radeon_fence **fence);
1323 1324 1325
		/* ring used for bo copies */
		u32 copy_ring_index;
	} copy;
1326
	/* surfaces */
1327 1328 1329 1330 1331 1332
	struct {
		int (*set_reg)(struct radeon_device *rdev, int reg,
				       uint32_t tiling_flags, uint32_t pitch,
				       uint32_t offset, uint32_t obj_size);
		void (*clear_reg)(struct radeon_device *rdev, int reg);
	} surface;
1333
	/* hotplug detect */
1334 1335 1336 1337 1338 1339
	struct {
		void (*init)(struct radeon_device *rdev);
		void (*fini)(struct radeon_device *rdev);
		bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
		void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	} hpd;
1340
	/* power management */
1341 1342 1343 1344 1345 1346
	struct {
		void (*misc)(struct radeon_device *rdev);
		void (*prepare)(struct radeon_device *rdev);
		void (*finish)(struct radeon_device *rdev);
		void (*init_profile)(struct radeon_device *rdev);
		void (*get_dynpm_state)(struct radeon_device *rdev);
1347 1348 1349 1350 1351 1352 1353
		uint32_t (*get_engine_clock)(struct radeon_device *rdev);
		void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
		uint32_t (*get_memory_clock)(struct radeon_device *rdev);
		void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
		int (*get_pcie_lanes)(struct radeon_device *rdev);
		void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
		void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1354
		int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1355
	} pm;
1356
	/* pageflipping */
1357 1358 1359 1360 1361
	struct {
		void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
		u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
		void (*post_page_flip)(struct radeon_device *rdev, int crtc);
	} pflip;
1362 1363
};

1364 1365 1366
/*
 * Asic structures
 */
1367
struct r100_asic {
1368 1369 1370
	const unsigned		*reg_safe_bm;
	unsigned		reg_safe_bm_size;
	u32			hdp_cntl;
1371 1372
};

1373
struct r300_asic {
1374 1375 1376 1377
	const unsigned		*reg_safe_bm;
	unsigned		reg_safe_bm_size;
	u32			resync_scratch;
	u32			hdp_cntl;
1378 1379 1380
};

struct r600_asic {
1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396
	unsigned		max_pipes;
	unsigned		max_tile_pipes;
	unsigned		max_simds;
	unsigned		max_backends;
	unsigned		max_gprs;
	unsigned		max_threads;
	unsigned		max_stack_entries;
	unsigned		max_hw_contexts;
	unsigned		max_gs_threads;
	unsigned		sx_max_export_size;
	unsigned		sx_max_export_pos_size;
	unsigned		sx_max_export_smx_size;
	unsigned		sq_num_cf_insts;
	unsigned		tiling_nbanks;
	unsigned		tiling_npipes;
	unsigned		tiling_group_size;
1397
	unsigned		tile_config;
1398
	unsigned		backend_map;
1399 1400 1401
};

struct rv770_asic {
1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421
	unsigned		max_pipes;
	unsigned		max_tile_pipes;
	unsigned		max_simds;
	unsigned		max_backends;
	unsigned		max_gprs;
	unsigned		max_threads;
	unsigned		max_stack_entries;
	unsigned		max_hw_contexts;
	unsigned		max_gs_threads;
	unsigned		sx_max_export_size;
	unsigned		sx_max_export_pos_size;
	unsigned		sx_max_export_smx_size;
	unsigned		sq_num_cf_insts;
	unsigned		sx_num_of_sets;
	unsigned		sc_prim_fifo_size;
	unsigned		sc_hiz_tile_fifo_size;
	unsigned		sc_earlyz_tile_fifo_fize;
	unsigned		tiling_nbanks;
	unsigned		tiling_npipes;
	unsigned		tiling_group_size;
1422
	unsigned		tile_config;
1423
	unsigned		backend_map;
1424 1425
};

1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447
struct evergreen_asic {
	unsigned num_ses;
	unsigned max_pipes;
	unsigned max_tile_pipes;
	unsigned max_simds;
	unsigned max_backends;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_stack_entries;
	unsigned max_hw_contexts;
	unsigned max_gs_threads;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned sq_num_cf_insts;
	unsigned sx_num_of_sets;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;
	unsigned tiling_nbanks;
	unsigned tiling_npipes;
	unsigned tiling_group_size;
1448
	unsigned tile_config;
1449
	unsigned backend_map;
1450 1451
};

1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489
struct cayman_asic {
	unsigned max_shader_engines;
	unsigned max_pipes_per_simd;
	unsigned max_tile_pipes;
	unsigned max_simds_per_se;
	unsigned max_backends_per_se;
	unsigned max_texture_channel_caches;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_gs_threads;
	unsigned max_stack_entries;
	unsigned sx_num_of_sets;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned max_hw_contexts;
	unsigned sq_num_cf_insts;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;

	unsigned num_shader_engines;
	unsigned num_shader_pipes_per_simd;
	unsigned num_tile_pipes;
	unsigned num_simds_per_se;
	unsigned num_backends_per_se;
	unsigned backend_disable_mask_per_asic;
	unsigned backend_map;
	unsigned num_texture_channel_caches;
	unsigned mem_max_burst_length_bytes;
	unsigned mem_row_size_in_kb;
	unsigned shader_engine_tile_size;
	unsigned num_gpus;
	unsigned multi_gpu_tile_size;

	unsigned tile_config;
};

1490 1491 1492
struct si_asic {
	unsigned max_shader_engines;
	unsigned max_tile_pipes;
A
Alex Deucher 已提交
1493 1494
	unsigned max_cu_per_sh;
	unsigned max_sh_per_se;
1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516
	unsigned max_backends_per_se;
	unsigned max_texture_channel_caches;
	unsigned max_gprs;
	unsigned max_gs_threads;
	unsigned max_hw_contexts;
	unsigned sc_prim_fifo_size_frontend;
	unsigned sc_prim_fifo_size_backend;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;

	unsigned num_tile_pipes;
	unsigned num_backends_per_se;
	unsigned backend_disable_mask_per_asic;
	unsigned backend_map;
	unsigned num_texture_channel_caches;
	unsigned mem_max_burst_length_bytes;
	unsigned mem_row_size_in_kb;
	unsigned shader_engine_tile_size;
	unsigned num_gpus;
	unsigned multi_gpu_tile_size;

	unsigned tile_config;
1517
	uint32_t tile_mode_array[32];
1518 1519
};

1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548
struct cik_asic {
	unsigned max_shader_engines;
	unsigned max_tile_pipes;
	unsigned max_cu_per_sh;
	unsigned max_sh_per_se;
	unsigned max_backends_per_se;
	unsigned max_texture_channel_caches;
	unsigned max_gprs;
	unsigned max_gs_threads;
	unsigned max_hw_contexts;
	unsigned sc_prim_fifo_size_frontend;
	unsigned sc_prim_fifo_size_backend;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;

	unsigned num_tile_pipes;
	unsigned num_backends_per_se;
	unsigned backend_disable_mask_per_asic;
	unsigned backend_map;
	unsigned num_texture_channel_caches;
	unsigned mem_max_burst_length_bytes;
	unsigned mem_row_size_in_kb;
	unsigned shader_engine_tile_size;
	unsigned num_gpus;
	unsigned multi_gpu_tile_size;

	unsigned tile_config;
};

1549 1550
union radeon_asic_config {
	struct r300_asic	r300;
1551
	struct r100_asic	r100;
1552 1553
	struct r600_asic	r600;
	struct rv770_asic	rv770;
1554
	struct evergreen_asic	evergreen;
1555
	struct cayman_asic	cayman;
1556
	struct si_asic		si;
1557
	struct cik_asic		cik;
1558 1559
};

D
Daniel Vetter 已提交
1560 1561 1562 1563 1564 1565
/*
 * asic initizalization from radeon_asic.c
 */
void radeon_agp_disable(struct radeon_device *rdev);
int radeon_asic_init(struct radeon_device *rdev);

1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589

/*
 * IOCTL.
 */
int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *filp);
int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp);
int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *filp);
1590 1591
int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
1592
int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1593 1594 1595 1596
int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp);
int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp);
1597

1598 1599
/* VRAM scratch page for HDP bug, default vram page */
struct r600_vram_scratch {
1600 1601
	struct radeon_bo		*robj;
	volatile uint32_t		*ptr;
1602
	u64				gpu_addr;
1603
};
1604

1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641
/*
 * ACPI
 */
struct radeon_atif_notification_cfg {
	bool enabled;
	int command_code;
};

struct radeon_atif_notifications {
	bool display_switch;
	bool expansion_mode_change;
	bool thermal_state;
	bool forced_power_state;
	bool system_power_state;
	bool display_conf_change;
	bool px_gfx_switch;
	bool brightness_change;
	bool dgpu_display_event;
};

struct radeon_atif_functions {
	bool system_params;
	bool sbios_requests;
	bool select_active_disp;
	bool lid_state;
	bool get_tv_standard;
	bool set_tv_standard;
	bool get_panel_expansion_mode;
	bool set_panel_expansion_mode;
	bool temperature_change;
	bool graphics_device_types;
};

struct radeon_atif {
	struct radeon_atif_notifications notifications;
	struct radeon_atif_functions functions;
	struct radeon_atif_notification_cfg notification_cfg;
1642
	struct radeon_encoder *encoder_for_bl;
1643
};
1644

1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655
struct radeon_atcs_functions {
	bool get_ext_state;
	bool pcie_perf_req;
	bool pcie_dev_rdy;
	bool pcie_bus_width;
};

struct radeon_atcs {
	struct radeon_atcs_functions functions;
};

1656 1657 1658 1659 1660 1661 1662
/*
 * Core structure, functions and helpers.
 */
typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);

struct radeon_device {
1663
	struct device			*dev;
1664 1665
	struct drm_device		*ddev;
	struct pci_dev			*pdev;
1666
	struct rw_semaphore		exclusive_lock;
1667
	/* ASIC */
1668
	union radeon_asic_config	config;
1669 1670 1671 1672 1673
	enum radeon_family		family;
	unsigned long			flags;
	int				usec_timeout;
	enum radeon_pll_errata		pll_errata;
	int				num_gb_pipes;
1674
	int				num_z_pipes;
1675 1676 1677 1678 1679
	int				disp_priority;
	/* BIOS */
	uint8_t				*bios;
	bool				is_atom_bios;
	uint16_t			bios_header_start;
1680
	struct radeon_bo		*stollen_vga_memory;
1681
	/* Register mmio */
1682 1683
	resource_size_t			rmmio_base;
	resource_size_t			rmmio_size;
1684 1685
	/* protects concurrent MM_INDEX/DATA based register access */
	spinlock_t mmio_idx_lock;
1686
	void __iomem			*rmmio;
1687 1688 1689 1690
	radeon_rreg_t			mc_rreg;
	radeon_wreg_t			mc_wreg;
	radeon_rreg_t			pll_rreg;
	radeon_wreg_t			pll_wreg;
1691
	uint32_t                        pcie_reg_mask;
1692 1693
	radeon_rreg_t			pciep_rreg;
	radeon_wreg_t			pciep_wreg;
1694 1695 1696
	/* io port */
	void __iomem                    *rio_mem;
	resource_size_t			rio_mem_size;
1697 1698 1699 1700 1701 1702
	struct radeon_clock             clock;
	struct radeon_mc		mc;
	struct radeon_gart		gart;
	struct radeon_mode_info		mode_info;
	struct radeon_scratch		scratch;
	struct radeon_mman		mman;
1703
	struct radeon_fence_driver	fence_drv[RADEON_NUM_RINGS];
1704
	wait_queue_head_t		fence_queue;
1705
	struct mutex			ring_lock;
1706
	struct radeon_ring		ring[RADEON_NUM_RINGS];
J
Jerome Glisse 已提交
1707 1708
	bool				ib_pool_ready;
	struct radeon_sa_manager	ring_tmp_bo;
1709 1710 1711
	struct radeon_irq		irq;
	struct radeon_asic		*asic;
	struct radeon_gem		gem;
1712
	struct radeon_pm		pm;
C
Christian König 已提交
1713
	struct radeon_uvd		uvd;
1714
	uint32_t			bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1715
	struct radeon_wb		wb;
1716
	struct radeon_dummy_page	dummy_page;
1717 1718
	bool				shutdown;
	bool				suspend;
D
Dave Airlie 已提交
1719
	bool				need_dma32;
1720
	bool				accel_working;
1721
	bool				fastfb_working; /* IGP feature*/
1722
	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1723 1724
	const struct firmware *me_fw;	/* all family ME firmware */
	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
1725
	const struct firmware *rlc_fw;	/* r6/700 RLC firmware */
1726
	const struct firmware *mc_fw;	/* NI MC firmware */
1727
	const struct firmware *ce_fw;	/* SI CE firmware */
C
Christian König 已提交
1728
	const struct firmware *uvd_fw;	/* UVD firmware */
1729
	const struct firmware *mec_fw;	/* CIK MEC firmware */
1730
	const struct firmware *sdma_fw;	/* CIK SDMA firmware */
1731
	struct r600_blit r600_blit;
1732
	struct r600_vram_scratch vram_scratch;
A
Alex Deucher 已提交
1733
	int msi_enabled; /* msi enabled */
1734
	struct r600_ih ih; /* r6/700 interrupt ring */
1735
	struct si_rlc rlc;
A
Alex Deucher 已提交
1736
	struct work_struct hotplug_work;
1737
	struct work_struct audio_work;
1738
	struct work_struct reset_work;
1739
	int num_crtc; /* number of crtcs */
1740
	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1741
	bool audio_enabled;
1742
	bool has_uvd;
1743
	struct r600_audio audio_status; /* audio stuff */
1744
	struct notifier_block acpi_nb;
1745
	/* only one userspace can use Hyperz features or CMASK at a time */
1746
	struct drm_file *hyperz_filp;
1747
	struct drm_file *cmask_filp;
1748 1749
	/* i2c buses */
	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1750 1751 1752
	/* debugfs */
	struct radeon_debugfs	debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
	unsigned 		debugfs_count;
1753 1754
	/* virtual memory */
	struct radeon_vm_manager	vm_manager;
1755
	struct mutex			gpu_clock_mutex;
1756 1757
	/* ACPI interface */
	struct radeon_atif		atif;
1758
	struct radeon_atcs		atcs;
1759 1760 1761 1762 1763 1764 1765 1766 1767
};

int radeon_device_init(struct radeon_device *rdev,
		       struct drm_device *ddev,
		       struct pci_dev *pdev,
		       uint32_t flags);
void radeon_device_fini(struct radeon_device *rdev);
int radeon_gpu_wait_for_idle(struct radeon_device *rdev);

1768 1769 1770 1771
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
		      bool always_indirect);
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
		  bool always_indirect);
1772 1773
u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1774

1775 1776 1777 1778
/*
 * Cast helper
 */
#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1779 1780 1781 1782

/*
 * Registers read & write functions.
 */
1783 1784 1785 1786
#define RREG8(reg) readb((rdev->rmmio) + (reg))
#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
#define RREG16(reg) readw((rdev->rmmio) + (reg))
#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1787 1788 1789 1790 1791
#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1792 1793 1794 1795 1796 1797
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1798 1799
#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1800 1801
#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1802 1803 1804 1805 1806 1807 1808
#define WREG32_P(reg, val, mask)				\
	do {							\
		uint32_t tmp_ = RREG32(reg);			\
		tmp_ &= (mask);					\
		tmp_ |= ((val) & ~(mask));			\
		WREG32(reg, tmp_);				\
	} while (0)
1809 1810
#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
1811 1812 1813 1814 1815 1816 1817
#define WREG32_PLL_P(reg, val, mask)				\
	do {							\
		uint32_t tmp_ = RREG32_PLL(reg);		\
		tmp_ &= (mask);					\
		tmp_ |= ((val) & ~(mask));			\
		WREG32_PLL(reg, tmp_);				\
	} while (0)
1818
#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1819 1820
#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1821

1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839
/*
 * Indirect registers accessor
 */
static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
{
	uint32_t r;

	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
	r = RREG32(RADEON_PCIE_DATA);
	return r;
}

static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
	WREG32(RADEON_PCIE_DATA, (v));
}

1840 1841 1842 1843 1844 1845
void r100_pll_errata_after_index(struct radeon_device *rdev);


/*
 * ASICs helpers.
 */
1846 1847
#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
			    (rdev->pdev->device == 0x5969))
1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863
#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
		(rdev->family == CHIP_RV200) || \
		(rdev->family == CHIP_RS100) || \
		(rdev->family == CHIP_RS200) || \
		(rdev->family == CHIP_RV250) || \
		(rdev->family == CHIP_RV280) || \
		(rdev->family == CHIP_RS300))
#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||	\
		(rdev->family == CHIP_RV350) ||			\
		(rdev->family == CHIP_R350)  ||			\
		(rdev->family == CHIP_RV380) ||			\
		(rdev->family == CHIP_R420)  ||			\
		(rdev->family == CHIP_R423)  ||			\
		(rdev->family == CHIP_RV410) ||			\
		(rdev->family == CHIP_RS400) ||			\
		(rdev->family == CHIP_RS480))
1864 1865 1866 1867 1868 1869 1870 1871
#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
		(rdev->ddev->pdev->device == 0x9443) || \
		(rdev->ddev->pdev->device == 0x944B) || \
		(rdev->ddev->pdev->device == 0x9506) || \
		(rdev->ddev->pdev->device == 0x9509) || \
		(rdev->ddev->pdev->device == 0x950F) || \
		(rdev->ddev->pdev->device == 0x689C) || \
		(rdev->ddev->pdev->device == 0x689D))
1872
#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1873 1874 1875 1876
#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||	\
			    (rdev->family == CHIP_RS690)  ||	\
			    (rdev->family == CHIP_RS740)  ||	\
			    (rdev->family >= CHIP_R600))
1877 1878
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1879
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1880 1881
#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
			     (rdev->flags & RADEON_IS_IGP))
1882
#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1883 1884 1885
#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
			     (rdev->flags & RADEON_IS_IGP))
A
Alex Deucher 已提交
1886
#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
1887
#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
1888
#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905

/*
 * BIOS helpers.
 */
#define RBIOS8(i) (rdev->bios[i])
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))

int radeon_combios_init(struct radeon_device *rdev);
void radeon_combios_fini(struct radeon_device *rdev);
int radeon_atombios_init(struct radeon_device *rdev);
void radeon_atombios_fini(struct radeon_device *rdev);


/*
 * RING helpers.
 */
1906
#if DRM_DEBUG_CODE == 0
1907
static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1908
{
1909 1910 1911 1912
	ring->ring[ring->wptr++] = v;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw--;
	ring->ring_free_dw--;
1913
}
1914 1915
#else
/* With debugging this is just too big to inline */
1916
void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1917
#endif
1918 1919 1920 1921

/*
 * ASICs macro.
 */
1922
#define radeon_init(rdev) (rdev)->asic->init((rdev))
1923 1924 1925
#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1926
#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1927
#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1928
#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1929 1930
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1931 1932
#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1933
#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
1934 1935 1936
#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1937
#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1938
#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1939
#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1940
#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
1941 1942
#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1943
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1944
#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1945
#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1946 1947
#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
1948 1949
#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1950 1951 1952 1953 1954 1955
#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1956 1957 1958 1959 1960 1961 1962
#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1963
#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
1964 1965
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1966
#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1967 1968 1969 1970
#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1971
#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1972 1973 1974 1975 1976
#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1977 1978 1979 1980 1981
#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1982
#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
1983
#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
1984

1985
/* Common functions */
1986
/* AGP */
1987
extern int radeon_gpu_reset(struct radeon_device *rdev);
1988
extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1989
extern void radeon_agp_disable(struct radeon_device *rdev);
1990 1991
extern int radeon_modeset_init(struct radeon_device *rdev);
extern void radeon_modeset_fini(struct radeon_device *rdev);
1992
extern bool radeon_card_posted(struct radeon_device *rdev);
1993
extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1994
extern void radeon_update_display_priority(struct radeon_device *rdev);
1995
extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1996
extern void radeon_scratch_init(struct radeon_device *rdev);
1997 1998 1999
extern void radeon_wb_fini(struct radeon_device *rdev);
extern int radeon_wb_init(struct radeon_device *rdev);
extern void radeon_wb_disable(struct radeon_device *rdev);
2000 2001
extern void radeon_surface_init(struct radeon_device *rdev);
extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2002
extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2003
extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2004
extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2005
extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2006 2007
extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2008 2009
extern int radeon_resume_kms(struct drm_device *dev);
extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
2010
extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2011 2012 2013
extern void radeon_program_register_sequence(struct radeon_device *rdev,
					     const u32 *registers,
					     const u32 array_size);
2014

2015 2016 2017 2018 2019
/*
 * vm
 */
int radeon_vm_manager_init(struct radeon_device *rdev);
void radeon_vm_manager_fini(struct radeon_device *rdev);
2020
void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2021
void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2022
int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
2023
void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
2024 2025 2026 2027 2028
struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
				       struct radeon_vm *vm, int ring);
void radeon_vm_fence(struct radeon_device *rdev,
		     struct radeon_vm *vm,
		     struct radeon_fence *fence);
2029
uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2030 2031 2032 2033 2034 2035
int radeon_vm_bo_update_pte(struct radeon_device *rdev,
			    struct radeon_vm *vm,
			    struct radeon_bo *bo,
			    struct ttm_mem_reg *mem);
void radeon_vm_bo_invalidate(struct radeon_device *rdev,
			     struct radeon_bo *bo);
2036 2037
struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
				       struct radeon_bo *bo);
2038 2039 2040 2041 2042 2043 2044
struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
				      struct radeon_vm *vm,
				      struct radeon_bo *bo);
int radeon_vm_bo_set_addr(struct radeon_device *rdev,
			  struct radeon_bo_va *bo_va,
			  uint64_t offset,
			  uint32_t flags);
2045
int radeon_vm_bo_rmv(struct radeon_device *rdev,
2046
		     struct radeon_bo_va *bo_va);
2047

2048 2049
/* audio */
void r600_audio_update_hdmi(struct work_struct *work);
2050

2051 2052 2053 2054 2055 2056
/*
 * R600 vram scratch functions
 */
int r600_vram_scratch_init(struct radeon_device *rdev);
void r600_vram_scratch_fini(struct radeon_device *rdev);

2057 2058 2059 2060 2061 2062 2063 2064 2065 2066
/*
 * r600 cs checking helper
 */
unsigned r600_mip_minify(unsigned size, unsigned level);
bool r600_fmt_is_valid_color(u32 format);
bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
int r600_fmt_get_blocksize(u32 format);
int r600_fmt_get_nblocksx(u32 format, u32 w);
int r600_fmt_get_nblocksy(u32 format, u32 h);

2067 2068 2069
/*
 * r600 functions used by radeon_encoder.c
 */
2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083
struct radeon_hdmi_acr {
	u32 clock;

	int n_32khz;
	int cts_32khz;

	int n_44_1khz;
	int cts_44_1khz;

	int n_48khz;
	int cts_48khz;

};

2084 2085
extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);

2086 2087 2088 2089 2090
extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
				     u32 tiling_pipe_num,
				     u32 max_rb_num,
				     u32 total_max_rb_num,
				     u32 enabled_rb_mask);
2091

2092 2093 2094 2095
/*
 * evergreen functions used by radeon_encoder.c
 */

2096
extern int ni_init_microcode(struct radeon_device *rdev);
2097
extern int ni_mc_load_microcode(struct radeon_device *rdev);
2098

2099 2100 2101 2102 2103 2104 2105 2106
/* radeon_acpi.c */
#if defined(CONFIG_ACPI)
extern int radeon_acpi_init(struct radeon_device *rdev);
extern void radeon_acpi_fini(struct radeon_device *rdev);
#else
static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
#endif
2107

2108 2109 2110
int radeon_cs_packet_parse(struct radeon_cs_parser *p,
			   struct radeon_cs_packet *pkt,
			   unsigned idx);
2111
bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2112 2113
void radeon_cs_dump_packet(struct radeon_cs_parser *p,
			   struct radeon_cs_packet *pkt);
2114 2115 2116
int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
				struct radeon_cs_reloc **cs_reloc,
				int nomm);
2117 2118 2119
int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
			       uint32_t *vline_start_end,
			       uint32_t *vline_status);
2120

2121 2122
#include "radeon_object.h"

2123
#endif