radeon.h 63.4 KB
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/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#ifndef __RADEON_H__
#define __RADEON_H__

/* TODO: Here are things that needs to be done :
 *	- surface allocator & initializer : (bit like scratch reg) should
 *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
 *	  related to surface
 *	- WB : write back stuff (do it bit like scratch reg things)
 *	- Vblank : look at Jesse's rework and what we should do
 *	- r600/r700: gart & cp
 *	- cs : clean cs ioctl use bitmap & things like that.
 *	- power management stuff
 *	- Barrier in gart code
 *	- Unmappabled vram ?
 *	- TESTING, TESTING, TESTING
 */

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/* Initialization path:
 *  We expect that acceleration initialization might fail for various
 *  reasons even thought we work hard to make it works on most
 *  configurations. In order to still have a working userspace in such
 *  situation the init path must succeed up to the memory controller
 *  initialization point. Failure before this point are considered as
 *  fatal error. Here is the init callchain :
 *      radeon_device_init  perform common structure, mutex initialization
 *      asic_init           setup the GPU memory layout and perform all
 *                          one time initialization (failure in this
 *                          function are considered fatal)
 *      asic_startup        setup the GPU acceleration, in order to
 *                          follow guideline the first thing this
 *                          function should do is setting the GPU
 *                          memory controller (only MC setup failure
 *                          are considered as fatal)
 */

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#include <linux/atomic.h>
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#include <linux/wait.h>
#include <linux/list.h>
#include <linux/kref.h>

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#include <ttm/ttm_bo_api.h>
#include <ttm/ttm_bo_driver.h>
#include <ttm/ttm_placement.h>
#include <ttm/ttm_module.h>
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#include <ttm/ttm_execbuf_util.h>
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#include "radeon_family.h"
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#include "radeon_mode.h"
#include "radeon_reg.h"

/*
 * Modules parameters.
 */
extern int radeon_no_wb;
extern int radeon_modeset;
extern int radeon_dynclks;
extern int radeon_r4xx_atom;
extern int radeon_agpmode;
extern int radeon_vram_limit;
extern int radeon_gart_size;
extern int radeon_benchmarking;
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extern int radeon_testing;
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extern int radeon_connector_table;
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extern int radeon_tv;
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extern int radeon_audio;
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extern int radeon_disp_priority;
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extern int radeon_hw_i2c;
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extern int radeon_pcie_gen2;
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extern int radeon_msi;
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extern int radeon_lockup_timeout;
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extern int radeon_fastfb;
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/*
 * Copy from radeon_drv.h so we don't have to include both and have conflicting
 * symbol;
 */
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#define RADEON_MAX_USEC_TIMEOUT			100000	/* 100 ms */
#define RADEON_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
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/* RADEON_IB_POOL_SIZE must be a power of 2 */
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#define RADEON_IB_POOL_SIZE			16
#define RADEON_DEBUGFS_MAX_COMPONENTS		32
#define RADEONFB_CONN_LIMIT			4
#define RADEON_BIOS_NUM_SCRATCH			8
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/* max number of rings */
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#define RADEON_NUM_RINGS			6
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/* fence seq are set to this number when signaled */
#define RADEON_FENCE_SIGNALED_SEQ		0LL
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/* internal ring indices */
/* r1xx+ has gfx CP ring */
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#define RADEON_RING_TYPE_GFX_INDEX	0
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/* cayman has 2 compute CP rings */
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#define CAYMAN_RING_TYPE_CP1_INDEX	1
#define CAYMAN_RING_TYPE_CP2_INDEX	2
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/* R600+ has an async dma ring */
#define R600_RING_TYPE_DMA_INDEX		3
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/* cayman add a second async dma ring */
#define CAYMAN_RING_TYPE_DMA1_INDEX		4
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/* R600+ */
#define R600_RING_TYPE_UVD_INDEX	5

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/* hardcode those limit for now */
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#define RADEON_VA_IB_OFFSET			(1 << 20)
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#define RADEON_VA_RESERVED_SIZE			(8 << 20)
#define RADEON_IB_VM_MAX_SIZE			(64 << 10)
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/* reset flags */
#define RADEON_RESET_GFX			(1 << 0)
#define RADEON_RESET_COMPUTE			(1 << 1)
#define RADEON_RESET_DMA			(1 << 2)
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#define RADEON_RESET_CP				(1 << 3)
#define RADEON_RESET_GRBM			(1 << 4)
#define RADEON_RESET_DMA1			(1 << 5)
#define RADEON_RESET_RLC			(1 << 6)
#define RADEON_RESET_SEM			(1 << 7)
#define RADEON_RESET_IH				(1 << 8)
#define RADEON_RESET_VMC			(1 << 9)
#define RADEON_RESET_MC				(1 << 10)
#define RADEON_RESET_DISPLAY			(1 << 11)
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/*
 * Errata workarounds.
 */
enum radeon_pll_errata {
	CHIP_ERRATA_R300_CG             = 0x00000001,
	CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
	CHIP_ERRATA_PLL_DELAY           = 0x00000004
};


struct radeon_device;


/*
 * BIOS.
 */
bool radeon_get_bios(struct radeon_device *rdev);

/*
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 * Dummy page
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 */
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struct radeon_dummy_page {
	struct page	*page;
	dma_addr_t	addr;
};
int radeon_dummy_page_init(struct radeon_device *rdev);
void radeon_dummy_page_fini(struct radeon_device *rdev);

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/*
 * Clocks
 */
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struct radeon_clock {
	struct radeon_pll p1pll;
	struct radeon_pll p2pll;
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	struct radeon_pll dcpll;
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	struct radeon_pll spll;
	struct radeon_pll mpll;
	/* 10 Khz units */
	uint32_t default_mclk;
	uint32_t default_sclk;
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	uint32_t default_dispclk;
	uint32_t dp_extclk;
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	uint32_t max_pixel_clock;
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};

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/*
 * Power management
 */
int radeon_pm_init(struct radeon_device *rdev);
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void radeon_pm_fini(struct radeon_device *rdev);
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void radeon_pm_compute_clocks(struct radeon_device *rdev);
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void radeon_pm_suspend(struct radeon_device *rdev);
void radeon_pm_resume(struct radeon_device *rdev);
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void radeon_combios_get_power_modes(struct radeon_device *rdev);
void radeon_atombios_get_power_modes(struct radeon_device *rdev);
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void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
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void rs690_pm_info(struct radeon_device *rdev);
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extern int rv6xx_get_temp(struct radeon_device *rdev);
extern int rv770_get_temp(struct radeon_device *rdev);
extern int evergreen_get_temp(struct radeon_device *rdev);
extern int sumo_get_temp(struct radeon_device *rdev);
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extern int si_get_temp(struct radeon_device *rdev);
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extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
				    unsigned *bankh, unsigned *mtaspect,
				    unsigned *tile_split);
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/*
 * Fences.
 */
struct radeon_fence_driver {
	uint32_t			scratch_reg;
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	uint64_t			gpu_addr;
	volatile uint32_t		*cpu_addr;
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	/* sync_seq is protected by ring emission lock */
	uint64_t			sync_seq[RADEON_NUM_RINGS];
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	atomic64_t			last_seq;
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	unsigned long			last_activity;
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	bool				initialized;
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};

struct radeon_fence {
	struct radeon_device		*rdev;
	struct kref			kref;
	/* protected by radeon_fence.lock */
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	uint64_t			seq;
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	/* RB, DMA, etc. */
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	unsigned			ring;
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};

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int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
int radeon_fence_driver_init(struct radeon_device *rdev);
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void radeon_fence_driver_fini(struct radeon_device *rdev);
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void radeon_fence_driver_force_completion(struct radeon_device *rdev);
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int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
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void radeon_fence_process(struct radeon_device *rdev, int ring);
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bool radeon_fence_signaled(struct radeon_fence *fence);
int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
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int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
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int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
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int radeon_fence_wait_any(struct radeon_device *rdev,
			  struct radeon_fence **fences,
			  bool intr);
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struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
void radeon_fence_unref(struct radeon_fence **fence);
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unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
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bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
						      struct radeon_fence *b)
{
	if (!a) {
		return b;
	}

	if (!b) {
		return a;
	}

	BUG_ON(a->ring != b->ring);

	if (a->seq > b->seq) {
		return a;
	} else {
		return b;
	}
}
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static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
					   struct radeon_fence *b)
{
	if (!a) {
		return false;
	}

	if (!b) {
		return true;
	}

	BUG_ON(a->ring != b->ring);

	return a->seq < b->seq;
}

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/*
 * Tiling registers
 */
struct radeon_surface_reg {
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	struct radeon_bo *bo;
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};

#define RADEON_GEM_MAX_SURFACES 8
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/*
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 * TTM.
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 */
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struct radeon_mman {
	struct ttm_bo_global_ref        bo_global_ref;
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	struct drm_global_reference	mem_global_ref;
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	struct ttm_bo_device		bdev;
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	bool				mem_global_referenced;
	bool				initialized;
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};

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/* bo virtual address in a specific vm */
struct radeon_bo_va {
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	/* protected by bo being reserved */
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	struct list_head		bo_list;
	uint64_t			soffset;
	uint64_t			eoffset;
	uint32_t			flags;
	bool				valid;
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	unsigned			ref_count;

	/* protected by vm mutex */
	struct list_head		vm_list;

	/* constant after initialization */
	struct radeon_vm		*vm;
	struct radeon_bo		*bo;
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};

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struct radeon_bo {
	/* Protected by gem.mutex */
	struct list_head		list;
	/* Protected by tbo.reserved */
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	u32				placements[3];
	struct ttm_placement		placement;
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	struct ttm_buffer_object	tbo;
	struct ttm_bo_kmap_obj		kmap;
	unsigned			pin_count;
	void				*kptr;
	u32				tiling_flags;
	u32				pitch;
	int				surface_reg;
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	/* list of all virtual address to which this bo
	 * is associated to
	 */
	struct list_head		va;
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	/* Constant after initialization */
	struct radeon_device		*rdev;
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	struct drm_gem_object		gem_base;
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	struct ttm_bo_kmap_obj dma_buf_vmap;
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};
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#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
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struct radeon_bo_list {
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	struct ttm_validate_buffer tv;
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	struct radeon_bo	*bo;
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	uint64_t		gpu_offset;
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	bool			written;
	unsigned		domain;
	unsigned		alt_domain;
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	u32			tiling_flags;
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};

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/* sub-allocation manager, it has to be protected by another lock.
 * By conception this is an helper for other part of the driver
 * like the indirect buffer or semaphore, which both have their
 * locking.
 *
 * Principe is simple, we keep a list of sub allocation in offset
 * order (first entry has offset == 0, last entry has the highest
 * offset).
 *
 * When allocating new object we first check if there is room at
 * the end total_size - (last_object_offset + last_object_size) >=
 * alloc_size. If so we allocate new object there.
 *
 * When there is not enough room at the end, we start waiting for
 * each sub object until we reach object_offset+object_size >=
 * alloc_size, this object then become the sub object we return.
 *
 * Alignment can't be bigger than page size.
 *
 * Hole are not considered for allocation to keep things simple.
 * Assumption is that there won't be hole (all object on same
 * alignment).
 */
struct radeon_sa_manager {
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	wait_queue_head_t	wq;
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	struct radeon_bo	*bo;
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	struct list_head	*hole;
	struct list_head	flist[RADEON_NUM_RINGS];
	struct list_head	olist;
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	unsigned		size;
	uint64_t		gpu_addr;
	void			*cpu_ptr;
	uint32_t		domain;
};

struct radeon_sa_bo;

/* sub-allocation buffer */
struct radeon_sa_bo {
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	struct list_head		olist;
	struct list_head		flist;
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	struct radeon_sa_manager	*manager;
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	unsigned			soffset;
	unsigned			eoffset;
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	struct radeon_fence		*fence;
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};

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/*
 * GEM objects.
 */
struct radeon_gem {
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	struct mutex		mutex;
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	struct list_head	objects;
};

int radeon_gem_init(struct radeon_device *rdev);
void radeon_gem_fini(struct radeon_device *rdev);
int radeon_gem_object_create(struct radeon_device *rdev, int size,
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				int alignment, int initial_domain,
				bool discardable, bool kernel,
				struct drm_gem_object **obj);
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int radeon_mode_dumb_create(struct drm_file *file_priv,
			    struct drm_device *dev,
			    struct drm_mode_create_dumb *args);
int radeon_mode_dumb_mmap(struct drm_file *filp,
			  struct drm_device *dev,
			  uint32_t handle, uint64_t *offset_p);
int radeon_mode_dumb_destroy(struct drm_file *file_priv,
			     struct drm_device *dev,
			     uint32_t handle);
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/*
 * Semaphores.
 */
/* everything here is constant */
struct radeon_semaphore {
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	struct radeon_sa_bo		*sa_bo;
	signed				waiters;
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	uint64_t			gpu_addr;
};

int radeon_semaphore_create(struct radeon_device *rdev,
			    struct radeon_semaphore **semaphore);
void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
				  struct radeon_semaphore *semaphore);
void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
				struct radeon_semaphore *semaphore);
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int radeon_semaphore_sync_rings(struct radeon_device *rdev,
				struct radeon_semaphore *semaphore,
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				int signaler, int waiter);
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void radeon_semaphore_free(struct radeon_device *rdev,
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			   struct radeon_semaphore **semaphore,
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			   struct radeon_fence *fence);
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/*
 * GART structures, functions & helpers
 */
struct radeon_mc;

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#define RADEON_GPU_PAGE_SIZE 4096
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#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
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#define RADEON_GPU_PAGE_SHIFT 12
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#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
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struct radeon_gart {
	dma_addr_t			table_addr;
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	struct radeon_bo		*robj;
	void				*ptr;
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	unsigned			num_gpu_pages;
	unsigned			num_cpu_pages;
	unsigned			table_size;
	struct page			**pages;
	dma_addr_t			*pages_addr;
	bool				ready;
};

int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
void radeon_gart_table_ram_free(struct radeon_device *rdev);
int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
void radeon_gart_table_vram_free(struct radeon_device *rdev);
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int radeon_gart_table_vram_pin(struct radeon_device *rdev);
void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
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int radeon_gart_init(struct radeon_device *rdev);
void radeon_gart_fini(struct radeon_device *rdev);
void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
			int pages);
int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
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		     int pages, struct page **pagelist,
		     dma_addr_t *dma_addr);
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void radeon_gart_restore(struct radeon_device *rdev);
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/*
 * GPU MC structures, functions & helpers
 */
struct radeon_mc {
	resource_size_t		aper_size;
	resource_size_t		aper_base;
	resource_size_t		agp_base;
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	/* for some chips with <= 32MB we need to lie
	 * about vram size near mc fb location */
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	u64			mc_vram_size;
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	u64			visible_vram_size;
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	u64			gtt_size;
	u64			gtt_start;
	u64			gtt_end;
	u64			vram_start;
	u64			vram_end;
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	unsigned		vram_width;
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	u64			real_vram_size;
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	int			vram_mtrr;
	bool			vram_is_ddr;
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	bool			igp_sideport_enabled;
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	u64                     gtt_base_align;
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	u64                     mc_mask;
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};

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bool radeon_combios_sideport_present(struct radeon_device *rdev);
bool radeon_atombios_sideport_present(struct radeon_device *rdev);
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/*
 * GPU scratch registers structures, functions & helpers
 */
struct radeon_scratch {
	unsigned		num_reg;
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	uint32_t                reg_base;
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	bool			free[32];
	uint32_t		reg[32];
};

int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);


/*
 * IRQS.
 */
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struct radeon_unpin_work {
	struct work_struct work;
	struct radeon_device *rdev;
	int crtc_id;
	struct radeon_fence *fence;
	struct drm_pending_vblank_event *event;
	struct radeon_bo *old_rbo;
	u64 new_crtc_base;
};

struct r500_irq_stat_regs {
	u32 disp_int;
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	u32 hdmi0_status;
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};

struct r600_irq_stat_regs {
	u32 disp_int;
	u32 disp_int_cont;
	u32 disp_int_cont2;
	u32 d1grph_int;
	u32 d2grph_int;
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	u32 hdmi0_status;
	u32 hdmi1_status;
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};

struct evergreen_irq_stat_regs {
	u32 disp_int;
	u32 disp_int_cont;
	u32 disp_int_cont2;
	u32 disp_int_cont3;
	u32 disp_int_cont4;
	u32 disp_int_cont5;
	u32 d1grph_int;
	u32 d2grph_int;
	u32 d3grph_int;
	u32 d4grph_int;
	u32 d5grph_int;
	u32 d6grph_int;
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	u32 afmt_status1;
	u32 afmt_status2;
	u32 afmt_status3;
	u32 afmt_status4;
	u32 afmt_status5;
	u32 afmt_status6;
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};

union radeon_irq_stat_regs {
	struct r500_irq_stat_regs r500;
	struct r600_irq_stat_regs r600;
	struct evergreen_irq_stat_regs evergreen;
};

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#define RADEON_MAX_HPD_PINS 6
#define RADEON_MAX_CRTCS 6
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#define RADEON_MAX_AFMT_BLOCKS 6
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struct radeon_irq {
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	bool				installed;
	spinlock_t			lock;
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	atomic_t			ring_int[RADEON_NUM_RINGS];
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	bool				crtc_vblank_int[RADEON_MAX_CRTCS];
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	atomic_t			pflip[RADEON_MAX_CRTCS];
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	wait_queue_head_t		vblank_queue;
	bool				hpd[RADEON_MAX_HPD_PINS];
	bool				afmt[RADEON_MAX_AFMT_BLOCKS];
	union radeon_irq_stat_regs	stat_regs;
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};

int radeon_irq_kms_init(struct radeon_device *rdev);
void radeon_irq_kms_fini(struct radeon_device *rdev);
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void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
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void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
623 624 625 626
void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
627 628

/*
629
 * CP & rings.
630
 */
631

632
struct radeon_ib {
633 634 635 636
	struct radeon_sa_bo		*sa_bo;
	uint32_t			length_dw;
	uint64_t			gpu_addr;
	uint32_t			*ptr;
637
	int				ring;
638
	struct radeon_fence		*fence;
639
	struct radeon_vm		*vm;
640
	bool				is_const_ib;
641
	struct radeon_fence		*sync_to[RADEON_NUM_RINGS];
642
	struct radeon_semaphore		*semaphore;
643 644
};

645
struct radeon_ring {
646
	struct radeon_bo	*ring_obj;
647 648
	volatile uint32_t	*ring;
	unsigned		rptr;
649 650
	unsigned		rptr_offs;
	unsigned		rptr_reg;
651
	unsigned		rptr_save_reg;
652 653
	u64			next_rptr_gpu_addr;
	volatile u32		*next_rptr_cpu_addr;
654 655
	unsigned		wptr;
	unsigned		wptr_old;
656
	unsigned		wptr_reg;
657 658 659
	unsigned		ring_size;
	unsigned		ring_free_dw;
	int			count_dw;
660 661
	unsigned long		last_activity;
	unsigned		last_rptr;
662 663 664 665
	uint64_t		gpu_addr;
	uint32_t		align_mask;
	uint32_t		ptr_mask;
	bool			ready;
666 667 668
	u32			ptr_reg_shift;
	u32			ptr_reg_mask;
	u32			nop;
669
	u32			idx;
670 671
	u64			last_semaphore_signal_addr;
	u64			last_semaphore_wait_addr;
672 673
};

674 675 676
/*
 * VM
 */
677

678
/* maximum number of VMIDs */
679 680
#define RADEON_NUM_VM	16

681 682 683 684 685 686 687 688
/* defines number of bits in page table versus page directory,
 * a page is 4KB so we have 12 bits offset, 9 bits in the page
 * table and the remaining 19 bits are in the page directory */
#define RADEON_VM_BLOCK_SIZE   9

/* number of entries in page table */
#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)

689 690 691
struct radeon_vm {
	struct list_head		list;
	struct list_head		va;
692
	unsigned			id;
693 694 695 696 697 698 699 700

	/* contains the page directory */
	struct radeon_sa_bo		*page_directory;
	uint64_t			pd_gpu_addr;

	/* array of page tables, one for each page directory entry */
	struct radeon_sa_bo		**page_tables;

701 702 703
	struct mutex			mutex;
	/* last fence for cs using this vm */
	struct radeon_fence		*fence;
704 705
	/* last flush or NULL if we still need to flush */
	struct radeon_fence		*last_flush;
706 707 708
};

struct radeon_vm_manager {
709
	struct mutex			lock;
710
	struct list_head		lru_vm;
711
	struct radeon_fence		*active[RADEON_NUM_VM];
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	struct radeon_sa_manager	sa_manager;
	uint32_t			max_pfn;
	/* number of VMIDs */
	unsigned			nvm;
	/* vram base address for page table entry  */
	u64				vram_base_offset;
718 719
	/* is vm enabled? */
	bool				enabled;
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};

/*
 * file private structure
 */
struct radeon_fpriv {
	struct radeon_vm		vm;
};

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/*
 * R6xx+ IH ring
 */
struct r600_ih {
733
	struct radeon_bo	*ring_obj;
734 735 736 737 738
	volatile uint32_t	*ring;
	unsigned		rptr;
	unsigned		ring_size;
	uint64_t		gpu_addr;
	uint32_t		ptr_mask;
739
	atomic_t		lock;
740 741 742
	bool                    enabled;
};

743 744 745 746 747 748 749 750 751 752
struct r600_blit_cp_primitives {
	void (*set_render_target)(struct radeon_device *rdev, int format,
				  int w, int h, u64 gpu_addr);
	void (*cp_set_surface_sync)(struct radeon_device *rdev,
				    u32 sync_type, u32 size,
				    u64 mc_addr);
	void (*set_shaders)(struct radeon_device *rdev);
	void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
	void (*set_tex_resource)(struct radeon_device *rdev,
				 int format, int w, int h, int pitch,
753
				 u64 gpu_addr, u32 size);
754 755 756 757 758 759
	void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
			     int x2, int y2);
	void (*draw_auto)(struct radeon_device *rdev);
	void (*set_default_state)(struct radeon_device *rdev);
};

760
struct r600_blit {
761
	struct radeon_bo	*shader_obj;
762 763 764 765
	struct r600_blit_cp_primitives primitives;
	int max_dim;
	int ring_size_common;
	int ring_size_per_loop;
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	u64 shader_gpu_addr;
	u32 vs_offset, ps_offset;
	u32 state_offset;
	u32 state_len;
};

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/*
 * SI RLC stuff
 */
struct si_rlc {
	/* for power gating */
	struct radeon_bo	*save_restore_obj;
	uint64_t		save_restore_gpu_addr;
	/* for clear state */
	struct radeon_bo	*clear_state_obj;
	uint64_t		clear_state_gpu_addr;
};

784
int radeon_ib_get(struct radeon_device *rdev, int ring,
785 786
		  struct radeon_ib *ib, struct radeon_vm *vm,
		  unsigned size);
787
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
788
void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
789 790
int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
		       struct radeon_ib *const_ib);
791 792
int radeon_ib_pool_init(struct radeon_device *rdev);
void radeon_ib_pool_fini(struct radeon_device *rdev);
793
int radeon_ib_ring_tests(struct radeon_device *rdev);
794
/* Ring access between begin & end cannot sleep */
795 796
bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
				      struct radeon_ring *ring);
797 798 799 800 801
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
802
void radeon_ring_undo(struct radeon_ring *ring);
803 804
void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
805
void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
806 807
void radeon_ring_lockup_update(struct radeon_ring *ring);
bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
808 809 810 811
unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
			    uint32_t **data);
int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
			unsigned size, uint32_t *data);
812
int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
813 814
		     unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
		     u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
815
void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
816 817


818 819 820 821 822
/* r600 async dma */
void r600_dma_stop(struct radeon_device *rdev);
int r600_dma_resume(struct radeon_device *rdev);
void r600_dma_fini(struct radeon_device *rdev);

823 824 825 826
void cayman_dma_stop(struct radeon_device *rdev);
int cayman_dma_resume(struct radeon_device *rdev);
void cayman_dma_fini(struct radeon_device *rdev);

827 828 829 830 831
/*
 * CS.
 */
struct radeon_cs_reloc {
	struct drm_gem_object		*gobj;
832 833
	struct radeon_bo		*robj;
	struct radeon_bo_list		lobj;
834 835 836 837 838 839 840
	uint32_t			handle;
	uint32_t			flags;
};

struct radeon_cs_chunk {
	uint32_t		chunk_id;
	uint32_t		length_dw;
841 842
	int			kpage_idx[2];
	uint32_t		*kpage[2];
843
	uint32_t		*kdata;
844 845 846
	void __user		*user_ptr;
	int			last_copied_page;
	int			last_page_index;
847 848 849
};

struct radeon_cs_parser {
850
	struct device		*dev;
851 852 853 854 855 856 857 858 859 860 861 862 863
	struct radeon_device	*rdev;
	struct drm_file		*filp;
	/* chunks */
	unsigned		nchunks;
	struct radeon_cs_chunk	*chunks;
	uint64_t		*chunks_array;
	/* IB */
	unsigned		idx;
	/* relocations */
	unsigned		nrelocs;
	struct radeon_cs_reloc	*relocs;
	struct radeon_cs_reloc	**relocs_ptr;
	struct list_head	validated;
864
	unsigned		dma_reloc_idx;
865 866 867
	/* indices of various chunks */
	int			chunk_ib_idx;
	int			chunk_relocs_idx;
868
	int			chunk_flags_idx;
869
	int			chunk_const_ib_idx;
870 871
	struct radeon_ib	ib;
	struct radeon_ib	const_ib;
872
	void			*track;
873
	unsigned		family;
874
	int			parser_error;
875 876 877
	u32			cs_flags;
	u32			ring;
	s32			priority;
878 879
};

880
extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
881
extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
882

883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902
struct radeon_cs_packet {
	unsigned	idx;
	unsigned	type;
	unsigned	reg;
	unsigned	opcode;
	int		count;
	unsigned	one_reg_wr;
};

typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
				      struct radeon_cs_packet *pkt,
				      unsigned idx, unsigned reg);
typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
				      struct radeon_cs_packet *pkt);


/*
 * AGP
 */
int radeon_agp_init(struct radeon_device *rdev);
903
void radeon_agp_resume(struct radeon_device *rdev);
904
void radeon_agp_suspend(struct radeon_device *rdev);
905 906 907 908 909 910 911
void radeon_agp_fini(struct radeon_device *rdev);


/*
 * Writeback
 */
struct radeon_wb {
912
	struct radeon_bo	*wb_obj;
913 914
	volatile uint32_t	*wb;
	uint64_t		gpu_addr;
915
	bool                    enabled;
916
	bool                    use_event;
917 918
};

919
#define RADEON_WB_SCRATCH_OFFSET 0
920
#define RADEON_WB_RING0_NEXT_RPTR 256
921
#define RADEON_WB_CP_RPTR_OFFSET 1024
922 923
#define RADEON_WB_CP1_RPTR_OFFSET 1280
#define RADEON_WB_CP2_RPTR_OFFSET 1536
924
#define R600_WB_DMA_RPTR_OFFSET   1792
925
#define R600_WB_IH_WPTR_OFFSET   2048
926
#define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
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Christian König 已提交
927
#define R600_WB_UVD_RPTR_OFFSET  2560
928
#define R600_WB_EVENT_OFFSET     3072
929

930 931 932 933 934 935 936 937 938 939 940
/**
 * struct radeon_pm - power management datas
 * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
L
Lucas De Marchi 已提交
941
 * @sclk:          	GPU clock Mhz (core bandwidth depends of this clock)
942 943 944
 * @needed_bandwidth:   current bandwidth needs
 *
 * It keeps track of various data needed to take powermanagement decision.
L
Lucas De Marchi 已提交
945
 * Bandwidth need is used to determine minimun clock of the GPU and memory.
946 947 948
 * Equation between gpu/memory clock and available bandwidth is hw dependent
 * (type of memory, bus size, efficiency, ...)
 */
949 950 951 952 953 954 955 956 957 958

enum radeon_pm_method {
	PM_METHOD_PROFILE,
	PM_METHOD_DYNPM,
};

enum radeon_dynpm_state {
	DYNPM_STATE_DISABLED,
	DYNPM_STATE_MINIMUM,
	DYNPM_STATE_PAUSED,
959 960
	DYNPM_STATE_ACTIVE,
	DYNPM_STATE_SUSPENDED,
961
};
962 963 964 965 966 967
enum radeon_dynpm_action {
	DYNPM_ACTION_NONE,
	DYNPM_ACTION_MINIMUM,
	DYNPM_ACTION_DOWNCLOCK,
	DYNPM_ACTION_UPCLOCK,
	DYNPM_ACTION_DEFAULT
968
};
969 970 971 972 973 974 975 976

enum radeon_voltage_type {
	VOLTAGE_NONE = 0,
	VOLTAGE_GPIO,
	VOLTAGE_VDDC,
	VOLTAGE_SW
};

977 978 979 980 981 982 983 984
enum radeon_pm_state_type {
	POWER_STATE_TYPE_DEFAULT,
	POWER_STATE_TYPE_POWERSAVE,
	POWER_STATE_TYPE_BATTERY,
	POWER_STATE_TYPE_BALANCED,
	POWER_STATE_TYPE_PERFORMANCE,
};

985 986 987 988
enum radeon_pm_profile_type {
	PM_PROFILE_DEFAULT,
	PM_PROFILE_AUTO,
	PM_PROFILE_LOW,
989
	PM_PROFILE_MID,
990 991 992 993 994
	PM_PROFILE_HIGH,
};

#define PM_PROFILE_DEFAULT_IDX 0
#define PM_PROFILE_LOW_SH_IDX  1
995 996 997 998 999 1000
#define PM_PROFILE_MID_SH_IDX  2
#define PM_PROFILE_HIGH_SH_IDX 3
#define PM_PROFILE_LOW_MH_IDX  4
#define PM_PROFILE_MID_MH_IDX  5
#define PM_PROFILE_HIGH_MH_IDX 6
#define PM_PROFILE_MAX         7
1001 1002 1003 1004 1005 1006

struct radeon_pm_profile {
	int dpms_off_ps_idx;
	int dpms_on_ps_idx;
	int dpms_off_cm_idx;
	int dpms_on_cm_idx;
1007 1008
};

1009 1010 1011 1012 1013
enum radeon_int_thermal_type {
	THERMAL_TYPE_NONE,
	THERMAL_TYPE_RV6XX,
	THERMAL_TYPE_RV770,
	THERMAL_TYPE_EVERGREEN,
1014
	THERMAL_TYPE_SUMO,
1015
	THERMAL_TYPE_NI,
1016
	THERMAL_TYPE_SI,
1017 1018
};

1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029
struct radeon_voltage {
	enum radeon_voltage_type type;
	/* gpio voltage */
	struct radeon_gpio_rec gpio;
	u32 delay; /* delay in usec from voltage drop to sclk change */
	bool active_high; /* voltage drop is active when bit is high */
	/* VDDC voltage */
	u8 vddc_id; /* index into vddc voltage table */
	u8 vddci_id; /* index into vddci voltage table */
	bool vddci_enabled;
	/* r6xx+ sw */
1030 1031 1032
	u16 voltage;
	/* evergreen+ vddci */
	u16 vddci;
1033 1034
};

1035 1036 1037
/* clock mode flags */
#define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)

1038 1039 1040 1041 1042 1043 1044
struct radeon_pm_clock_info {
	/* memory clock */
	u32 mclk;
	/* engine clock */
	u32 sclk;
	/* voltage info */
	struct radeon_voltage voltage;
1045
	/* standardized clock flags */
1046 1047 1048
	u32 flags;
};

1049
/* state flags */
1050
#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1051

1052
struct radeon_power_state {
1053
	enum radeon_pm_state_type type;
1054
	struct radeon_pm_clock_info *clock_info;
1055 1056 1057
	/* number of valid clock modes in this power state */
	int num_clock_modes;
	struct radeon_pm_clock_info *default_clock_mode;
1058 1059
	/* standardized state flags */
	u32 flags;
A
Alex Deucher 已提交
1060 1061 1062
	u32 misc; /* vbios specific flags */
	u32 misc2; /* vbios specific flags */
	int pcie_lanes; /* pcie lanes */
1063 1064
};

1065 1066 1067 1068 1069
/*
 * Some modes are overclocked by very low value, accept them
 */
#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */

1070
struct radeon_pm {
1071
	struct mutex		mutex;
1072 1073
	/* write locked while reprogramming mclk */
	struct rw_semaphore	mclk_lock;
1074 1075
	u32			active_crtcs;
	int			active_crtc_count;
1076
	int			req_vblank;
1077
	bool			vblank_sync;
1078 1079 1080 1081 1082 1083 1084 1085 1086 1087
	fixed20_12		max_bandwidth;
	fixed20_12		igp_sideport_mclk;
	fixed20_12		igp_system_mclk;
	fixed20_12		igp_ht_link_clk;
	fixed20_12		igp_ht_link_width;
	fixed20_12		k8_bandwidth;
	fixed20_12		sideport_bandwidth;
	fixed20_12		ht_bandwidth;
	fixed20_12		core_bandwidth;
	fixed20_12		sclk;
1088
	fixed20_12		mclk;
1089
	fixed20_12		needed_bandwidth;
1090
	struct radeon_power_state *power_state;
1091 1092
	/* number of valid power states */
	int                     num_power_states;
1093 1094 1095 1096 1097 1098 1099
	int                     current_power_state_index;
	int                     current_clock_mode_index;
	int                     requested_power_state_index;
	int                     requested_clock_mode_index;
	int                     default_power_state_index;
	u32                     current_sclk;
	u32                     current_mclk;
1100 1101
	u16                     current_vddc;
	u16                     current_vddci;
1102 1103
	u32                     default_sclk;
	u32                     default_mclk;
1104 1105
	u16                     default_vddc;
	u16                     default_vddci;
1106
	struct radeon_i2c_chan *i2c_bus;
1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119
	/* selected pm method */
	enum radeon_pm_method     pm_method;
	/* dynpm power management */
	struct delayed_work	dynpm_idle_work;
	enum radeon_dynpm_state	dynpm_state;
	enum radeon_dynpm_action	dynpm_planned_action;
	unsigned long		dynpm_action_timeout;
	bool                    dynpm_can_upclock;
	bool                    dynpm_can_downclock;
	/* profile-based power management */
	enum radeon_pm_profile_type profile;
	int                     profile_index;
	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1120 1121 1122
	/* internal thermal controller on rv6xx+ */
	enum radeon_int_thermal_type int_thermal_type;
	struct device	        *int_hwmon_dev;
1123 1124
};

1125 1126 1127
int radeon_pm_get_type_index(struct radeon_device *rdev,
			     enum radeon_pm_state_type ps_type,
			     int instance);
C
Christian König 已提交
1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154
/*
 * UVD
 */
#define RADEON_MAX_UVD_HANDLES	10
#define RADEON_UVD_STACK_SIZE	(1024*1024)
#define RADEON_UVD_HEAP_SIZE	(1024*1024)

struct radeon_uvd {
	struct radeon_bo	*vcpu_bo;
	void			*cpu_addr;
	uint64_t		gpu_addr;
	atomic_t		handles[RADEON_MAX_UVD_HANDLES];
	struct drm_file		*filp[RADEON_MAX_UVD_HANDLES];
};

int radeon_uvd_init(struct radeon_device *rdev);
void radeon_uvd_fini(struct radeon_device *rdev);
int radeon_uvd_suspend(struct radeon_device *rdev);
int radeon_uvd_resume(struct radeon_device *rdev);
int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
			      uint32_t handle, struct radeon_fence **fence);
int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
			       uint32_t handle, struct radeon_fence **fence);
void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
void radeon_uvd_free_handles(struct radeon_device *rdev,
			     struct drm_file *filp);
int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1155

1156 1157 1158 1159 1160 1161 1162 1163
struct r600_audio {
	int			channels;
	int			rate;
	int			bits_per_sample;
	u8			status_bits;
	u8			category_code;
};

1164 1165 1166
/*
 * Benchmarking
 */
1167
void radeon_benchmark(struct radeon_device *rdev, int test_number);
1168 1169


1170 1171 1172 1173
/*
 * Testing
 */
void radeon_test_moves(struct radeon_device *rdev);
1174
void radeon_test_ring_sync(struct radeon_device *rdev,
1175 1176
			   struct radeon_ring *cpA,
			   struct radeon_ring *cpB);
1177
void radeon_test_syncing(struct radeon_device *rdev);
1178 1179


1180 1181 1182
/*
 * Debugfs
 */
1183 1184 1185 1186 1187
struct radeon_debugfs {
	struct drm_info_list	*files;
	unsigned		num_files;
};

1188 1189 1190 1191 1192 1193 1194 1195 1196 1197
int radeon_debugfs_add_files(struct radeon_device *rdev,
			     struct drm_info_list *files,
			     unsigned nfiles);
int radeon_debugfs_fence_init(struct radeon_device *rdev);


/*
 * ASIC specific functions.
 */
struct radeon_asic {
1198
	int (*init)(struct radeon_device *rdev);
1199 1200 1201
	void (*fini)(struct radeon_device *rdev);
	int (*resume)(struct radeon_device *rdev);
	int (*suspend)(struct radeon_device *rdev);
1202
	void (*vga_set_state)(struct radeon_device *rdev, bool state);
1203
	int (*asic_reset)(struct radeon_device *rdev);
1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214
	/* ioctl hw specific callback. Some hw might want to perform special
	 * operation on specific ioctl. For instance on wait idle some hw
	 * might want to perform and HDP flush through MMIO as it seems that
	 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
	 * through ring.
	 */
	void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
	/* check if 3D engine is idle */
	bool (*gui_idle)(struct radeon_device *rdev);
	/* wait for mc_idle */
	int (*mc_wait_for_idle)(struct radeon_device *rdev);
1215 1216
	/* get the reference clock */
	u32 (*get_xclk)(struct radeon_device *rdev);
1217 1218
	/* get the gpu clock counter */
	uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1219
	/* gart */
1220 1221 1222 1223
	struct {
		void (*tlb_flush)(struct radeon_device *rdev);
		int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
	} gart;
1224 1225 1226
	struct {
		int (*init)(struct radeon_device *rdev);
		void (*fini)(struct radeon_device *rdev);
1227 1228

		u32 pt_ring_index;
1229 1230 1231
		void (*set_page)(struct radeon_device *rdev,
				 struct radeon_ib *ib,
				 uint64_t pe,
1232 1233
				 uint64_t addr, unsigned count,
				 uint32_t incr, uint32_t flags);
1234
	} vm;
1235
	/* ring specific callbacks */
1236 1237
	struct {
		void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1238
		int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1239
		void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1240
		void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1241
				       struct radeon_semaphore *semaphore, bool emit_wait);
1242
		int (*cs_parse)(struct radeon_cs_parser *p);
1243 1244 1245
		void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
		int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
		int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1246
		bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1247
		void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1248
	} ring[RADEON_NUM_RINGS];
1249
	/* irqs */
1250 1251 1252 1253
	struct {
		int (*set)(struct radeon_device *rdev);
		int (*process)(struct radeon_device *rdev);
	} irq;
1254
	/* displays */
1255 1256 1257 1258 1259 1260 1261
	struct {
		/* display watermarks */
		void (*bandwidth_update)(struct radeon_device *rdev);
		/* get frame count */
		u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
		/* wait for vblank */
		void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1262 1263
		/* set backlight level */
		void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1264 1265
		/* get backlight level */
		u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1266
	} display;
1267
	/* copy functions for bo handling */
1268 1269 1270 1271 1272
	struct {
		int (*blit)(struct radeon_device *rdev,
			    uint64_t src_offset,
			    uint64_t dst_offset,
			    unsigned num_gpu_pages,
1273
			    struct radeon_fence **fence);
1274 1275 1276 1277 1278
		u32 blit_ring_index;
		int (*dma)(struct radeon_device *rdev,
			   uint64_t src_offset,
			   uint64_t dst_offset,
			   unsigned num_gpu_pages,
1279
			   struct radeon_fence **fence);
1280 1281 1282 1283 1284 1285
		u32 dma_ring_index;
		/* method used for bo copy */
		int (*copy)(struct radeon_device *rdev,
			    uint64_t src_offset,
			    uint64_t dst_offset,
			    unsigned num_gpu_pages,
1286
			    struct radeon_fence **fence);
1287 1288 1289
		/* ring used for bo copies */
		u32 copy_ring_index;
	} copy;
1290
	/* surfaces */
1291 1292 1293 1294 1295 1296
	struct {
		int (*set_reg)(struct radeon_device *rdev, int reg,
				       uint32_t tiling_flags, uint32_t pitch,
				       uint32_t offset, uint32_t obj_size);
		void (*clear_reg)(struct radeon_device *rdev, int reg);
	} surface;
1297
	/* hotplug detect */
1298 1299 1300 1301 1302 1303
	struct {
		void (*init)(struct radeon_device *rdev);
		void (*fini)(struct radeon_device *rdev);
		bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
		void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
	} hpd;
1304
	/* power management */
1305 1306 1307 1308 1309 1310
	struct {
		void (*misc)(struct radeon_device *rdev);
		void (*prepare)(struct radeon_device *rdev);
		void (*finish)(struct radeon_device *rdev);
		void (*init_profile)(struct radeon_device *rdev);
		void (*get_dynpm_state)(struct radeon_device *rdev);
1311 1312 1313 1314 1315 1316 1317
		uint32_t (*get_engine_clock)(struct radeon_device *rdev);
		void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
		uint32_t (*get_memory_clock)(struct radeon_device *rdev);
		void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
		int (*get_pcie_lanes)(struct radeon_device *rdev);
		void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
		void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1318
		int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1319
	} pm;
1320
	/* pageflipping */
1321 1322 1323 1324 1325
	struct {
		void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
		u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
		void (*post_page_flip)(struct radeon_device *rdev, int crtc);
	} pflip;
1326 1327
};

1328 1329 1330
/*
 * Asic structures
 */
1331
struct r100_asic {
1332 1333 1334
	const unsigned		*reg_safe_bm;
	unsigned		reg_safe_bm_size;
	u32			hdp_cntl;
1335 1336
};

1337
struct r300_asic {
1338 1339 1340 1341
	const unsigned		*reg_safe_bm;
	unsigned		reg_safe_bm_size;
	u32			resync_scratch;
	u32			hdp_cntl;
1342 1343 1344
};

struct r600_asic {
1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360
	unsigned		max_pipes;
	unsigned		max_tile_pipes;
	unsigned		max_simds;
	unsigned		max_backends;
	unsigned		max_gprs;
	unsigned		max_threads;
	unsigned		max_stack_entries;
	unsigned		max_hw_contexts;
	unsigned		max_gs_threads;
	unsigned		sx_max_export_size;
	unsigned		sx_max_export_pos_size;
	unsigned		sx_max_export_smx_size;
	unsigned		sq_num_cf_insts;
	unsigned		tiling_nbanks;
	unsigned		tiling_npipes;
	unsigned		tiling_group_size;
1361
	unsigned		tile_config;
1362
	unsigned		backend_map;
1363 1364 1365
};

struct rv770_asic {
1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385
	unsigned		max_pipes;
	unsigned		max_tile_pipes;
	unsigned		max_simds;
	unsigned		max_backends;
	unsigned		max_gprs;
	unsigned		max_threads;
	unsigned		max_stack_entries;
	unsigned		max_hw_contexts;
	unsigned		max_gs_threads;
	unsigned		sx_max_export_size;
	unsigned		sx_max_export_pos_size;
	unsigned		sx_max_export_smx_size;
	unsigned		sq_num_cf_insts;
	unsigned		sx_num_of_sets;
	unsigned		sc_prim_fifo_size;
	unsigned		sc_hiz_tile_fifo_size;
	unsigned		sc_earlyz_tile_fifo_fize;
	unsigned		tiling_nbanks;
	unsigned		tiling_npipes;
	unsigned		tiling_group_size;
1386
	unsigned		tile_config;
1387
	unsigned		backend_map;
1388 1389
};

1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411
struct evergreen_asic {
	unsigned num_ses;
	unsigned max_pipes;
	unsigned max_tile_pipes;
	unsigned max_simds;
	unsigned max_backends;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_stack_entries;
	unsigned max_hw_contexts;
	unsigned max_gs_threads;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned sq_num_cf_insts;
	unsigned sx_num_of_sets;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;
	unsigned tiling_nbanks;
	unsigned tiling_npipes;
	unsigned tiling_group_size;
1412
	unsigned tile_config;
1413
	unsigned backend_map;
1414 1415
};

1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453
struct cayman_asic {
	unsigned max_shader_engines;
	unsigned max_pipes_per_simd;
	unsigned max_tile_pipes;
	unsigned max_simds_per_se;
	unsigned max_backends_per_se;
	unsigned max_texture_channel_caches;
	unsigned max_gprs;
	unsigned max_threads;
	unsigned max_gs_threads;
	unsigned max_stack_entries;
	unsigned sx_num_of_sets;
	unsigned sx_max_export_size;
	unsigned sx_max_export_pos_size;
	unsigned sx_max_export_smx_size;
	unsigned max_hw_contexts;
	unsigned sq_num_cf_insts;
	unsigned sc_prim_fifo_size;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;

	unsigned num_shader_engines;
	unsigned num_shader_pipes_per_simd;
	unsigned num_tile_pipes;
	unsigned num_simds_per_se;
	unsigned num_backends_per_se;
	unsigned backend_disable_mask_per_asic;
	unsigned backend_map;
	unsigned num_texture_channel_caches;
	unsigned mem_max_burst_length_bytes;
	unsigned mem_row_size_in_kb;
	unsigned shader_engine_tile_size;
	unsigned num_gpus;
	unsigned multi_gpu_tile_size;

	unsigned tile_config;
};

1454 1455 1456
struct si_asic {
	unsigned max_shader_engines;
	unsigned max_tile_pipes;
A
Alex Deucher 已提交
1457 1458
	unsigned max_cu_per_sh;
	unsigned max_sh_per_se;
1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482
	unsigned max_backends_per_se;
	unsigned max_texture_channel_caches;
	unsigned max_gprs;
	unsigned max_gs_threads;
	unsigned max_hw_contexts;
	unsigned sc_prim_fifo_size_frontend;
	unsigned sc_prim_fifo_size_backend;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;

	unsigned num_tile_pipes;
	unsigned num_backends_per_se;
	unsigned backend_disable_mask_per_asic;
	unsigned backend_map;
	unsigned num_texture_channel_caches;
	unsigned mem_max_burst_length_bytes;
	unsigned mem_row_size_in_kb;
	unsigned shader_engine_tile_size;
	unsigned num_gpus;
	unsigned multi_gpu_tile_size;

	unsigned tile_config;
};

1483 1484
union radeon_asic_config {
	struct r300_asic	r300;
1485
	struct r100_asic	r100;
1486 1487
	struct r600_asic	r600;
	struct rv770_asic	rv770;
1488
	struct evergreen_asic	evergreen;
1489
	struct cayman_asic	cayman;
1490
	struct si_asic		si;
1491 1492
};

D
Daniel Vetter 已提交
1493 1494 1495 1496 1497 1498
/*
 * asic initizalization from radeon_asic.c
 */
void radeon_agp_disable(struct radeon_device *rdev);
int radeon_asic_init(struct radeon_device *rdev);

1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522

/*
 * IOCTL.
 */
int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *filp);
int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp);
int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *filp);
1523 1524
int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *filp);
1525
int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1526 1527 1528 1529
int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp);
int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
				struct drm_file *filp);
1530

1531 1532
/* VRAM scratch page for HDP bug, default vram page */
struct r600_vram_scratch {
1533 1534
	struct radeon_bo		*robj;
	volatile uint32_t		*ptr;
1535
	u64				gpu_addr;
1536
};
1537

1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574
/*
 * ACPI
 */
struct radeon_atif_notification_cfg {
	bool enabled;
	int command_code;
};

struct radeon_atif_notifications {
	bool display_switch;
	bool expansion_mode_change;
	bool thermal_state;
	bool forced_power_state;
	bool system_power_state;
	bool display_conf_change;
	bool px_gfx_switch;
	bool brightness_change;
	bool dgpu_display_event;
};

struct radeon_atif_functions {
	bool system_params;
	bool sbios_requests;
	bool select_active_disp;
	bool lid_state;
	bool get_tv_standard;
	bool set_tv_standard;
	bool get_panel_expansion_mode;
	bool set_panel_expansion_mode;
	bool temperature_change;
	bool graphics_device_types;
};

struct radeon_atif {
	struct radeon_atif_notifications notifications;
	struct radeon_atif_functions functions;
	struct radeon_atif_notification_cfg notification_cfg;
1575
	struct radeon_encoder *encoder_for_bl;
1576
};
1577

1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588
struct radeon_atcs_functions {
	bool get_ext_state;
	bool pcie_perf_req;
	bool pcie_dev_rdy;
	bool pcie_bus_width;
};

struct radeon_atcs {
	struct radeon_atcs_functions functions;
};

1589 1590 1591 1592 1593 1594 1595
/*
 * Core structure, functions and helpers.
 */
typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);

struct radeon_device {
1596
	struct device			*dev;
1597 1598
	struct drm_device		*ddev;
	struct pci_dev			*pdev;
1599
	struct rw_semaphore		exclusive_lock;
1600
	/* ASIC */
1601
	union radeon_asic_config	config;
1602 1603 1604 1605 1606
	enum radeon_family		family;
	unsigned long			flags;
	int				usec_timeout;
	enum radeon_pll_errata		pll_errata;
	int				num_gb_pipes;
1607
	int				num_z_pipes;
1608 1609 1610 1611 1612
	int				disp_priority;
	/* BIOS */
	uint8_t				*bios;
	bool				is_atom_bios;
	uint16_t			bios_header_start;
1613
	struct radeon_bo		*stollen_vga_memory;
1614
	/* Register mmio */
1615 1616
	resource_size_t			rmmio_base;
	resource_size_t			rmmio_size;
1617 1618
	/* protects concurrent MM_INDEX/DATA based register access */
	spinlock_t mmio_idx_lock;
1619
	void __iomem			*rmmio;
1620 1621 1622 1623
	radeon_rreg_t			mc_rreg;
	radeon_wreg_t			mc_wreg;
	radeon_rreg_t			pll_rreg;
	radeon_wreg_t			pll_wreg;
1624
	uint32_t                        pcie_reg_mask;
1625 1626
	radeon_rreg_t			pciep_rreg;
	radeon_wreg_t			pciep_wreg;
1627 1628 1629
	/* io port */
	void __iomem                    *rio_mem;
	resource_size_t			rio_mem_size;
1630 1631 1632 1633 1634 1635
	struct radeon_clock             clock;
	struct radeon_mc		mc;
	struct radeon_gart		gart;
	struct radeon_mode_info		mode_info;
	struct radeon_scratch		scratch;
	struct radeon_mman		mman;
1636
	struct radeon_fence_driver	fence_drv[RADEON_NUM_RINGS];
1637
	wait_queue_head_t		fence_queue;
1638
	struct mutex			ring_lock;
1639
	struct radeon_ring		ring[RADEON_NUM_RINGS];
J
Jerome Glisse 已提交
1640 1641
	bool				ib_pool_ready;
	struct radeon_sa_manager	ring_tmp_bo;
1642 1643 1644
	struct radeon_irq		irq;
	struct radeon_asic		*asic;
	struct radeon_gem		gem;
1645
	struct radeon_pm		pm;
C
Christian König 已提交
1646
	struct radeon_uvd		uvd;
1647
	uint32_t			bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1648
	struct radeon_wb		wb;
1649
	struct radeon_dummy_page	dummy_page;
1650 1651
	bool				shutdown;
	bool				suspend;
D
Dave Airlie 已提交
1652
	bool				need_dma32;
1653
	bool				accel_working;
1654
	bool				fastfb_working; /* IGP feature*/
1655
	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1656 1657
	const struct firmware *me_fw;	/* all family ME firmware */
	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
1658
	const struct firmware *rlc_fw;	/* r6/700 RLC firmware */
1659
	const struct firmware *mc_fw;	/* NI MC firmware */
1660
	const struct firmware *ce_fw;	/* SI CE firmware */
C
Christian König 已提交
1661
	const struct firmware *uvd_fw;	/* UVD firmware */
1662
	struct r600_blit r600_blit;
1663
	struct r600_vram_scratch vram_scratch;
A
Alex Deucher 已提交
1664
	int msi_enabled; /* msi enabled */
1665
	struct r600_ih ih; /* r6/700 interrupt ring */
1666
	struct si_rlc rlc;
A
Alex Deucher 已提交
1667
	struct work_struct hotplug_work;
1668
	struct work_struct audio_work;
1669
	int num_crtc; /* number of crtcs */
1670
	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1671 1672
	bool audio_enabled;
	struct r600_audio audio_status; /* audio stuff */
1673
	struct notifier_block acpi_nb;
1674
	/* only one userspace can use Hyperz features or CMASK at a time */
1675
	struct drm_file *hyperz_filp;
1676
	struct drm_file *cmask_filp;
1677 1678
	/* i2c buses */
	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1679 1680 1681
	/* debugfs */
	struct radeon_debugfs	debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
	unsigned 		debugfs_count;
1682 1683
	/* virtual memory */
	struct radeon_vm_manager	vm_manager;
1684
	struct mutex			gpu_clock_mutex;
1685 1686
	/* ACPI interface */
	struct radeon_atif		atif;
1687
	struct radeon_atcs		atcs;
1688 1689 1690 1691 1692 1693 1694 1695 1696
};

int radeon_device_init(struct radeon_device *rdev,
		       struct drm_device *ddev,
		       struct pci_dev *pdev,
		       uint32_t flags);
void radeon_device_fini(struct radeon_device *rdev);
int radeon_gpu_wait_for_idle(struct radeon_device *rdev);

1697 1698 1699 1700
uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
		      bool always_indirect);
void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
		  bool always_indirect);
1701 1702
u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1703

1704 1705 1706 1707
/*
 * Cast helper
 */
#define to_radeon_fence(p) ((struct radeon_fence *)(p))
1708 1709 1710 1711

/*
 * Registers read & write functions.
 */
1712 1713 1714 1715
#define RREG8(reg) readb((rdev->rmmio) + (reg))
#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
#define RREG16(reg) readw((rdev->rmmio) + (reg))
#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1716 1717 1718 1719 1720
#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
1721 1722 1723 1724 1725 1726
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1727 1728
#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1729 1730
#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744
#define WREG32_P(reg, val, mask)				\
	do {							\
		uint32_t tmp_ = RREG32(reg);			\
		tmp_ &= (mask);					\
		tmp_ |= ((val) & ~(mask));			\
		WREG32(reg, tmp_);				\
	} while (0)
#define WREG32_PLL_P(reg, val, mask)				\
	do {							\
		uint32_t tmp_ = RREG32_PLL(reg);		\
		tmp_ &= (mask);					\
		tmp_ |= ((val) & ~(mask));			\
		WREG32_PLL(reg, tmp_);				\
	} while (0)
1745
#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
1746 1747
#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1748

1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766
/*
 * Indirect registers accessor
 */
static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
{
	uint32_t r;

	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
	r = RREG32(RADEON_PCIE_DATA);
	return r;
}

static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
	WREG32(RADEON_PCIE_DATA, (v));
}

1767 1768 1769 1770 1771 1772
void r100_pll_errata_after_index(struct radeon_device *rdev);


/*
 * ASICs helpers.
 */
1773 1774
#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
			    (rdev->pdev->device == 0x5969))
1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790
#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
		(rdev->family == CHIP_RV200) || \
		(rdev->family == CHIP_RS100) || \
		(rdev->family == CHIP_RS200) || \
		(rdev->family == CHIP_RV250) || \
		(rdev->family == CHIP_RV280) || \
		(rdev->family == CHIP_RS300))
#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||	\
		(rdev->family == CHIP_RV350) ||			\
		(rdev->family == CHIP_R350)  ||			\
		(rdev->family == CHIP_RV380) ||			\
		(rdev->family == CHIP_R420)  ||			\
		(rdev->family == CHIP_R423)  ||			\
		(rdev->family == CHIP_RV410) ||			\
		(rdev->family == CHIP_RS400) ||			\
		(rdev->family == CHIP_RS480))
1791 1792 1793 1794 1795 1796 1797 1798
#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
		(rdev->ddev->pdev->device == 0x9443) || \
		(rdev->ddev->pdev->device == 0x944B) || \
		(rdev->ddev->pdev->device == 0x9506) || \
		(rdev->ddev->pdev->device == 0x9509) || \
		(rdev->ddev->pdev->device == 0x950F) || \
		(rdev->ddev->pdev->device == 0x689C) || \
		(rdev->ddev->pdev->device == 0x689D))
1799
#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1800 1801 1802 1803
#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||	\
			    (rdev->family == CHIP_RS690)  ||	\
			    (rdev->family == CHIP_RS740)  ||	\
			    (rdev->family >= CHIP_R600))
1804 1805
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1806
#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1807 1808
#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
			     (rdev->flags & RADEON_IS_IGP))
1809
#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1810 1811 1812
#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
			     (rdev->flags & RADEON_IS_IGP))
A
Alex Deucher 已提交
1813
#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830

/*
 * BIOS helpers.
 */
#define RBIOS8(i) (rdev->bios[i])
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))

int radeon_combios_init(struct radeon_device *rdev);
void radeon_combios_fini(struct radeon_device *rdev);
int radeon_atombios_init(struct radeon_device *rdev);
void radeon_atombios_fini(struct radeon_device *rdev);


/*
 * RING helpers.
 */
1831
#if DRM_DEBUG_CODE == 0
1832
static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
1833
{
1834 1835 1836 1837
	ring->ring[ring->wptr++] = v;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw--;
	ring->ring_free_dw--;
1838
}
1839 1840
#else
/* With debugging this is just too big to inline */
1841
void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1842
#endif
1843 1844 1845 1846

/*
 * ASICs macro.
 */
1847
#define radeon_init(rdev) (rdev)->asic->init((rdev))
1848 1849 1850
#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1851
#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
1852
#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1853
#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1854 1855
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1856 1857
#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1858
#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
1859 1860 1861
#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
1862
#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
1863
#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
1864
#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
1865
#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
1866 1867
#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
1868
#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1869
#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1870
#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1871 1872
#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1873 1874 1875 1876 1877 1878
#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
1879 1880 1881 1882 1883 1884 1885
#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
1886
#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
1887 1888
#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
1889
#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
1890 1891 1892 1893
#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
1894
#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1895 1896 1897 1898 1899
#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1900 1901 1902 1903 1904
#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
1905
#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
1906
#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
1907

1908
/* Common functions */
1909
/* AGP */
1910
extern int radeon_gpu_reset(struct radeon_device *rdev);
1911
extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1912
extern void radeon_agp_disable(struct radeon_device *rdev);
1913 1914
extern int radeon_modeset_init(struct radeon_device *rdev);
extern void radeon_modeset_fini(struct radeon_device *rdev);
1915
extern bool radeon_card_posted(struct radeon_device *rdev);
1916
extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1917
extern void radeon_update_display_priority(struct radeon_device *rdev);
1918
extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1919
extern void radeon_scratch_init(struct radeon_device *rdev);
1920 1921 1922
extern void radeon_wb_fini(struct radeon_device *rdev);
extern int radeon_wb_init(struct radeon_device *rdev);
extern void radeon_wb_disable(struct radeon_device *rdev);
1923 1924
extern void radeon_surface_init(struct radeon_device *rdev);
extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1925
extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1926
extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1927
extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1928
extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1929 1930
extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1931 1932
extern int radeon_resume_kms(struct drm_device *dev);
extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1933
extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1934

1935 1936 1937 1938 1939
/*
 * vm
 */
int radeon_vm_manager_init(struct radeon_device *rdev);
void radeon_vm_manager_fini(struct radeon_device *rdev);
1940
void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
1941
void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1942
int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
1943
void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
1944 1945 1946 1947 1948
struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
				       struct radeon_vm *vm, int ring);
void radeon_vm_fence(struct radeon_device *rdev,
		     struct radeon_vm *vm,
		     struct radeon_fence *fence);
1949
uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
1950 1951 1952 1953 1954 1955
int radeon_vm_bo_update_pte(struct radeon_device *rdev,
			    struct radeon_vm *vm,
			    struct radeon_bo *bo,
			    struct ttm_mem_reg *mem);
void radeon_vm_bo_invalidate(struct radeon_device *rdev,
			     struct radeon_bo *bo);
1956 1957
struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
				       struct radeon_bo *bo);
1958 1959 1960 1961 1962 1963 1964
struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
				      struct radeon_vm *vm,
				      struct radeon_bo *bo);
int radeon_vm_bo_set_addr(struct radeon_device *rdev,
			  struct radeon_bo_va *bo_va,
			  uint64_t offset,
			  uint32_t flags);
1965
int radeon_vm_bo_rmv(struct radeon_device *rdev,
1966
		     struct radeon_bo_va *bo_va);
1967

1968 1969
/* audio */
void r600_audio_update_hdmi(struct work_struct *work);
1970

1971 1972 1973 1974 1975 1976
/*
 * R600 vram scratch functions
 */
int r600_vram_scratch_init(struct radeon_device *rdev);
void r600_vram_scratch_fini(struct radeon_device *rdev);

1977 1978 1979 1980 1981 1982 1983 1984 1985 1986
/*
 * r600 cs checking helper
 */
unsigned r600_mip_minify(unsigned size, unsigned level);
bool r600_fmt_is_valid_color(u32 format);
bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
int r600_fmt_get_blocksize(u32 format);
int r600_fmt_get_nblocksx(u32 format, u32 w);
int r600_fmt_get_nblocksy(u32 format, u32 h);

1987 1988 1989
/*
 * r600 functions used by radeon_encoder.c
 */
1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003
struct radeon_hdmi_acr {
	u32 clock;

	int n_32khz;
	int cts_32khz;

	int n_44_1khz;
	int cts_44_1khz;

	int n_48khz;
	int cts_48khz;

};

2004 2005
extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);

2006 2007
extern void r600_hdmi_enable(struct drm_encoder *encoder);
extern void r600_hdmi_disable(struct drm_encoder *encoder);
2008
extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
2009 2010 2011 2012 2013
extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
				     u32 tiling_pipe_num,
				     u32 max_rb_num,
				     u32 total_max_rb_num,
				     u32 enabled_rb_mask);
2014

2015 2016 2017 2018 2019 2020
/*
 * evergreen functions used by radeon_encoder.c
 */

extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);

2021
extern int ni_init_microcode(struct radeon_device *rdev);
2022
extern int ni_mc_load_microcode(struct radeon_device *rdev);
2023

2024 2025 2026 2027 2028 2029 2030 2031
/* radeon_acpi.c */
#if defined(CONFIG_ACPI)
extern int radeon_acpi_init(struct radeon_device *rdev);
extern void radeon_acpi_fini(struct radeon_device *rdev);
#else
static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
#endif
2032

2033 2034 2035
int radeon_cs_packet_parse(struct radeon_cs_parser *p,
			   struct radeon_cs_packet *pkt,
			   unsigned idx);
2036
bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2037 2038
void radeon_cs_dump_packet(struct radeon_cs_parser *p,
			   struct radeon_cs_packet *pkt);
2039 2040 2041
int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
				struct radeon_cs_reloc **cs_reloc,
				int nomm);
2042 2043 2044
int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
			       uint32_t *vline_start_end,
			       uint32_t *vline_status);
2045

2046 2047
#include "radeon_object.h"

2048
#endif