intel-iommu.c 119.3 KB
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/*
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 * Copyright © 2006-2014 Intel Corporation.
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 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
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 * Authors: David Woodhouse <dwmw2@infradead.org>,
 *          Ashok Raj <ashok.raj@intel.com>,
 *          Shaohua Li <shaohua.li@intel.com>,
 *          Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
 *          Fenghua Yu <fenghua.yu@intel.com>
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 */

#include <linux/init.h>
#include <linux/bitmap.h>
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#include <linux/debugfs.h>
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#include <linux/export.h>
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#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <linux/dmar.h>
#include <linux/dma-mapping.h>
#include <linux/mempool.h>
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#include <linux/memory.h>
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#include <linux/timer.h>
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#include <linux/iova.h>
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#include <linux/iommu.h>
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#include <linux/intel-iommu.h>
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#include <linux/syscore_ops.h>
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#include <linux/tboot.h>
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#include <linux/dmi.h>
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#include <linux/pci-ats.h>
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#include <linux/memblock.h>
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#include <linux/dma-contiguous.h>
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#include <asm/irq_remapping.h>
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#include <asm/cacheflush.h>
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#include <asm/iommu.h>
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#include "irq_remapping.h"

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#define ROOT_SIZE		VTD_PAGE_SIZE
#define CONTEXT_SIZE		VTD_PAGE_SIZE

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#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
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#define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB)
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#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
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#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
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#define IOAPIC_RANGE_START	(0xfee00000)
#define IOAPIC_RANGE_END	(0xfeefffff)
#define IOVA_START_ADDR		(0x1000)

#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48

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#define MAX_AGAW_WIDTH 64
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#define MAX_AGAW_PFN_WIDTH	(MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
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#define __DOMAIN_MAX_PFN(gaw)  ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)

/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
   to match. That way, we can use 'unsigned long' for PFNs with impunity. */
#define DOMAIN_MAX_PFN(gaw)	((unsigned long) min_t(uint64_t, \
				__DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
#define DOMAIN_MAX_ADDR(gaw)	(((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
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/* IO virtual address start page frame number */
#define IOVA_START_PFN		(1)

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#define IOVA_PFN(addr)		((addr) >> PAGE_SHIFT)
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#define DMA_32BIT_PFN		IOVA_PFN(DMA_BIT_MASK(32))
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#define DMA_64BIT_PFN		IOVA_PFN(DMA_BIT_MASK(64))
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/* page table handling */
#define LEVEL_STRIDE		(9)
#define LEVEL_MASK		(((u64)1 << LEVEL_STRIDE) - 1)

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/*
 * This bitmap is used to advertise the page sizes our hardware support
 * to the IOMMU core, which will then use this information to split
 * physically contiguous memory regions it is mapping into page sizes
 * that we support.
 *
 * Traditionally the IOMMU core just handed us the mappings directly,
 * after making sure the size is an order of a 4KiB page and that the
 * mapping has natural alignment.
 *
 * To retain this behavior, we currently advertise that we support
 * all page sizes that are an order of 4KiB.
 *
 * If at some point we'd like to utilize the IOMMU core's new behavior,
 * we could change this to advertise the real page sizes we support.
 */
#define INTEL_IOMMU_PGSIZES	(~0xFFFUL)

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static inline int agaw_to_level(int agaw)
{
	return agaw + 2;
}

static inline int agaw_to_width(int agaw)
{
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	return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
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}

static inline int width_to_agaw(int width)
{
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	return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
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}

static inline unsigned int level_to_offset_bits(int level)
{
	return (level - 1) * LEVEL_STRIDE;
}

static inline int pfn_level_offset(unsigned long pfn, int level)
{
	return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
}

static inline unsigned long level_mask(int level)
{
	return -1UL << level_to_offset_bits(level);
}

static inline unsigned long level_size(int level)
{
	return 1UL << level_to_offset_bits(level);
}

static inline unsigned long align_to_level(unsigned long pfn, int level)
{
	return (pfn + level_size(level) - 1) & level_mask(level);
}
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static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
{
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	return  1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
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}

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/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
   are never going to work. */
static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
{
	return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
}

static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
{
	return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
}
static inline unsigned long page_to_dma_pfn(struct page *pg)
{
	return mm_to_dma_pfn(page_to_pfn(pg));
}
static inline unsigned long virt_to_dma_pfn(void *p)
{
	return page_to_dma_pfn(virt_to_page(p));
}

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/* global iommu list, set NULL for ignored DMAR units */
static struct intel_iommu **g_iommus;

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static void __init check_tylersburg_isoch(void);
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static int rwbf_quirk;

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/*
 * set to 1 to panic kernel if can't successfully enable VT-d
 * (used when kernel is launched w/ TXT)
 */
static int force_on = 0;

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/*
 * 0: Present
 * 1-11: Reserved
 * 12-63: Context Ptr (12 - (haw-1))
 * 64-127: Reserved
 */
struct root_entry {
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	u64	lo;
	u64	hi;
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};
#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))


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/*
 * low 64 bits:
 * 0: present
 * 1: fault processing disable
 * 2-3: translation type
 * 12-63: address space root
 * high 64 bits:
 * 0-2: address width
 * 3-6: aval
 * 8-23: domain id
 */
struct context_entry {
	u64 lo;
	u64 hi;
};
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static inline bool context_present(struct context_entry *context)
{
	return (context->lo & 1);
}
static inline void context_set_present(struct context_entry *context)
{
	context->lo |= 1;
}

static inline void context_set_fault_enable(struct context_entry *context)
{
	context->lo &= (((u64)-1) << 2) | 1;
}

static inline void context_set_translation_type(struct context_entry *context,
						unsigned long value)
{
	context->lo &= (((u64)-1) << 4) | 3;
	context->lo |= (value & 3) << 2;
}

static inline void context_set_address_root(struct context_entry *context,
					    unsigned long value)
{
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	context->lo &= ~VTD_PAGE_MASK;
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	context->lo |= value & VTD_PAGE_MASK;
}

static inline void context_set_address_width(struct context_entry *context,
					     unsigned long value)
{
	context->hi |= value & 7;
}

static inline void context_set_domain_id(struct context_entry *context,
					 unsigned long value)
{
	context->hi |= (value & ((1 << 16) - 1)) << 8;
}

static inline void context_clear_entry(struct context_entry *context)
{
	context->lo = 0;
	context->hi = 0;
}
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/*
 * 0: readable
 * 1: writable
 * 2-6: reserved
 * 7: super page
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 * 8-10: available
 * 11: snoop behavior
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 * 12-63: Host physcial address
 */
struct dma_pte {
	u64 val;
};

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static inline void dma_clear_pte(struct dma_pte *pte)
{
	pte->val = 0;
}

static inline u64 dma_pte_addr(struct dma_pte *pte)
{
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#ifdef CONFIG_64BIT
	return pte->val & VTD_PAGE_MASK;
#else
	/* Must have a full atomic 64-bit read */
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	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
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#endif
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}

static inline bool dma_pte_present(struct dma_pte *pte)
{
	return (pte->val & 3) != 0;
}
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static inline bool dma_pte_superpage(struct dma_pte *pte)
{
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	return (pte->val & DMA_PTE_LARGE_PAGE);
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}

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static inline int first_pte_in_page(struct dma_pte *pte)
{
	return !((unsigned long)pte & ~VTD_PAGE_MASK);
}

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/*
 * This domain is a statically identity mapping domain.
 *	1. This domain creats a static 1:1 mapping to all usable memory.
 * 	2. It maps to each iommu if successful.
 *	3. Each iommu mapps to this domain if successful.
 */
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static struct dmar_domain *si_domain;
static int hw_pass_through = 1;
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/* domain represents a virtual machine, more than one devices
 * across iommus may be owned in one domain, e.g. kvm guest.
 */
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#define DOMAIN_FLAG_VIRTUAL_MACHINE	(1 << 0)
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/* si_domain contains mulitple devices */
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#define DOMAIN_FLAG_STATIC_IDENTITY	(1 << 1)
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struct dmar_domain {
	int	id;			/* domain id */
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	int	nid;			/* node id */
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	DECLARE_BITMAP(iommu_bmp, DMAR_UNITS_SUPPORTED);
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					/* bitmap of iommus this domain uses*/
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	struct list_head devices;	/* all devices' list */
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	struct iova_domain iovad;	/* iova's that belong to this domain */

	struct dma_pte	*pgd;		/* virtual address */
	int		gaw;		/* max guest address width */

	/* adjusted guest address width, 0 is level 2 30-bit */
	int		agaw;

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	int		flags;		/* flags to find out type of domain */
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	int		iommu_coherency;/* indicate coherency of iommu access */
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	int		iommu_snooping; /* indicate snooping control feature*/
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	int		iommu_count;	/* reference count of iommu */
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	int		iommu_superpage;/* Level of superpages supported:
					   0 == 4KiB (no superpages), 1 == 2MiB,
					   2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
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	spinlock_t	iommu_lock;	/* protect iommu set in domain */
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	u64		max_addr;	/* maximum mapped address */
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	struct iommu_domain domain;	/* generic domain data structure for
					   iommu core */
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};

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/* PCI domain-device relationship */
struct device_domain_info {
	struct list_head link;	/* link to domain siblings */
	struct list_head global; /* link to global list */
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	u8 bus;			/* PCI bus number */
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	u8 devfn;		/* PCI devfn number */
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	struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
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	struct intel_iommu *iommu; /* IOMMU used by this device */
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	struct dmar_domain *domain; /* pointer to domain */
};

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struct dmar_rmrr_unit {
	struct list_head list;		/* list of rmrr units	*/
	struct acpi_dmar_header *hdr;	/* ACPI header		*/
	u64	base_address;		/* reserved base address*/
	u64	end_address;		/* reserved end address */
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	struct dmar_dev_scope *devices;	/* target devices */
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	int	devices_cnt;		/* target device count */
};

struct dmar_atsr_unit {
	struct list_head list;		/* list of ATSR units */
	struct acpi_dmar_header *hdr;	/* ACPI header */
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	struct dmar_dev_scope *devices;	/* target devices */
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	int devices_cnt;		/* target device count */
	u8 include_all:1;		/* include all ports */
};

static LIST_HEAD(dmar_atsr_units);
static LIST_HEAD(dmar_rmrr_units);

#define for_each_rmrr_units(rmrr) \
	list_for_each_entry(rmrr, &dmar_rmrr_units, list)

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static void flush_unmaps_timeout(unsigned long data);

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static DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
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#define HIGH_WATER_MARK 250
struct deferred_flush_tables {
	int next;
	struct iova *iova[HIGH_WATER_MARK];
	struct dmar_domain *domain[HIGH_WATER_MARK];
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	struct page *freelist[HIGH_WATER_MARK];
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};

static struct deferred_flush_tables *deferred_flush;

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/* bitmap for indexing intel_iommus */
static int g_num_of_iommus;

static DEFINE_SPINLOCK(async_umap_flush_lock);
static LIST_HEAD(unmaps_to_do);

static int timer_on;
static long list_size;

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static void domain_exit(struct dmar_domain *domain);
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static void domain_remove_dev_info(struct dmar_domain *domain);
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static void domain_remove_one_dev_info(struct dmar_domain *domain,
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				       struct device *dev);
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static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
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					   struct device *dev);
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static int domain_detach_iommu(struct dmar_domain *domain,
			       struct intel_iommu *iommu);
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#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
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int dmar_disabled = 0;
#else
int dmar_disabled = 1;
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#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
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int intel_iommu_enabled = 0;
EXPORT_SYMBOL_GPL(intel_iommu_enabled);

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static int dmar_map_gfx = 1;
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static int dmar_forcedac;
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static int intel_iommu_strict;
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static int intel_iommu_superpage = 1;
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static int intel_iommu_ecs = 1;

/* We only actually use ECS when PASID support (on the new bit 40)
 * is also advertised. Some early implementations — the ones with
 * PASID support on bit 28 — have issues even when we *only* use
 * extended root/context tables. */
#define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \
			    ecap_pasid(iommu->ecap))
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int intel_iommu_gfx_mapped;
EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);

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#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
static DEFINE_SPINLOCK(device_domain_lock);
static LIST_HEAD(device_domain_list);

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static const struct iommu_ops intel_iommu_ops;
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/* Convert generic 'struct iommu_domain to private struct dmar_domain */
static struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
{
	return container_of(dom, struct dmar_domain, domain);
}

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static int __init intel_iommu_setup(char *str)
{
	if (!str)
		return -EINVAL;
	while (*str) {
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		if (!strncmp(str, "on", 2)) {
			dmar_disabled = 0;
			printk(KERN_INFO "Intel-IOMMU: enabled\n");
		} else if (!strncmp(str, "off", 3)) {
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			dmar_disabled = 1;
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			printk(KERN_INFO "Intel-IOMMU: disabled\n");
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		} else if (!strncmp(str, "igfx_off", 8)) {
			dmar_map_gfx = 0;
			printk(KERN_INFO
				"Intel-IOMMU: disable GFX device mapping\n");
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		} else if (!strncmp(str, "forcedac", 8)) {
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			printk(KERN_INFO
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				"Intel-IOMMU: Forcing DAC for PCI devices\n");
			dmar_forcedac = 1;
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		} else if (!strncmp(str, "strict", 6)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable batched IOTLB flush\n");
			intel_iommu_strict = 1;
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		} else if (!strncmp(str, "sp_off", 6)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable supported super page\n");
			intel_iommu_superpage = 0;
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		} else if (!strncmp(str, "ecs_off", 7)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable extended context table support\n");
			intel_iommu_ecs = 0;
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		}

		str += strcspn(str, ",");
		while (*str == ',')
			str++;
	}
	return 0;
}
__setup("intel_iommu=", intel_iommu_setup);

static struct kmem_cache *iommu_domain_cache;
static struct kmem_cache *iommu_devinfo_cache;

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static inline void *alloc_pgtable_page(int node)
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{
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	struct page *page;
	void *vaddr = NULL;
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	page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
	if (page)
		vaddr = page_address(page);
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	return vaddr;
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}

static inline void free_pgtable_page(void *vaddr)
{
	free_page((unsigned long)vaddr);
}

static inline void *alloc_domain_mem(void)
{
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	return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
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}

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static void free_domain_mem(void *vaddr)
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{
	kmem_cache_free(iommu_domain_cache, vaddr);
}

static inline void * alloc_devinfo_mem(void)
{
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	return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
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}

static inline void free_devinfo_mem(void *vaddr)
{
	kmem_cache_free(iommu_devinfo_cache, vaddr);
}

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static inline int domain_type_is_vm(struct dmar_domain *domain)
{
	return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE;
}

static inline int domain_type_is_vm_or_si(struct dmar_domain *domain)
{
	return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE |
				DOMAIN_FLAG_STATIC_IDENTITY);
}
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static inline int domain_pfn_supported(struct dmar_domain *domain,
				       unsigned long pfn)
{
	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;

	return !(addr_width < BITS_PER_LONG && pfn >> addr_width);
}

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static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
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{
	unsigned long sagaw;
	int agaw = -1;

	sagaw = cap_sagaw(iommu->cap);
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	for (agaw = width_to_agaw(max_gaw);
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	     agaw >= 0; agaw--) {
		if (test_bit(agaw, &sagaw))
			break;
	}

	return agaw;
}

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/*
 * Calculate max SAGAW for each iommu.
 */
int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
}

/*
 * calculate agaw for each iommu.
 * "SAGAW" may be different across iommus, use a default agaw, and
 * get a supported less agaw for iommus that don't support the default agaw.
 */
int iommu_calculate_agaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
}

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/* This functionin only returns single iommu in a domain */
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static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
{
	int iommu_id;

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	/* si_domain and vm domain should not get here. */
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	BUG_ON(domain_type_is_vm_or_si(domain));
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	iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
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	if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
		return NULL;

	return g_iommus[iommu_id];
}

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static void domain_update_iommu_coherency(struct dmar_domain *domain)
{
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	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
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	bool found = false;
	int i;
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	domain->iommu_coherency = 1;
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	for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
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		found = true;
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		if (!ecap_coherent(g_iommus[i]->ecap)) {
			domain->iommu_coherency = 0;
			break;
		}
	}
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	if (found)
		return;

	/* No hardware attached; use lowest common denominator */
	rcu_read_lock();
	for_each_active_iommu(iommu, drhd) {
		if (!ecap_coherent(iommu->ecap)) {
			domain->iommu_coherency = 0;
			break;
		}
	}
	rcu_read_unlock();
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}

625
static int domain_update_iommu_snooping(struct intel_iommu *skip)
626
{
627 628 629
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
	int ret = 1;
630

631 632 633 634 635 636 637
	rcu_read_lock();
	for_each_active_iommu(iommu, drhd) {
		if (iommu != skip) {
			if (!ecap_sc_support(iommu->ecap)) {
				ret = 0;
				break;
			}
638 639
		}
	}
640 641 642
	rcu_read_unlock();

	return ret;
643 644
}

645
static int domain_update_iommu_superpage(struct intel_iommu *skip)
646
{
647
	struct dmar_drhd_unit *drhd;
648
	struct intel_iommu *iommu;
649
	int mask = 0xf;
650 651

	if (!intel_iommu_superpage) {
652
		return 0;
653 654
	}

655
	/* set iommu_superpage to the smallest common denominator */
656
	rcu_read_lock();
657
	for_each_active_iommu(iommu, drhd) {
658 659 660 661
		if (iommu != skip) {
			mask &= cap_super_page_val(iommu->cap);
			if (!mask)
				break;
662 663
		}
	}
664 665
	rcu_read_unlock();

666
	return fls(mask);
667 668
}

669 670 671 672
/* Some capabilities may be different across iommus */
static void domain_update_iommu_cap(struct dmar_domain *domain)
{
	domain_update_iommu_coherency(domain);
673 674
	domain->iommu_snooping = domain_update_iommu_snooping(NULL);
	domain->iommu_superpage = domain_update_iommu_superpage(NULL);
675 676
}

677 678 679 680 681 682 683
static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu,
						       u8 bus, u8 devfn, int alloc)
{
	struct root_entry *root = &iommu->root_entry[bus];
	struct context_entry *context;
	u64 *entry;

684
	if (ecs_enabled(iommu)) {
685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710
		if (devfn >= 0x80) {
			devfn -= 0x80;
			entry = &root->hi;
		}
		devfn *= 2;
	}
	entry = &root->lo;
	if (*entry & 1)
		context = phys_to_virt(*entry & VTD_PAGE_MASK);
	else {
		unsigned long phy_addr;
		if (!alloc)
			return NULL;

		context = alloc_pgtable_page(iommu->node);
		if (!context)
			return NULL;

		__iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
		phy_addr = virt_to_phys((void *)context);
		*entry = phy_addr | 1;
		__iommu_flush_cache(iommu, entry, sizeof(*entry));
	}
	return &context[devfn];
}

711 712 713 714 715
static int iommu_dummy(struct device *dev)
{
	return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
}

716
static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
717 718
{
	struct dmar_drhd_unit *drhd = NULL;
719
	struct intel_iommu *iommu;
720 721
	struct device *tmp;
	struct pci_dev *ptmp, *pdev = NULL;
722
	u16 segment = 0;
723 724
	int i;

725 726 727
	if (iommu_dummy(dev))
		return NULL;

728 729 730
	if (dev_is_pci(dev)) {
		pdev = to_pci_dev(dev);
		segment = pci_domain_nr(pdev->bus);
731
	} else if (has_acpi_companion(dev))
732 733
		dev = &ACPI_COMPANION(dev)->dev;

734
	rcu_read_lock();
735
	for_each_active_iommu(iommu, drhd) {
736
		if (pdev && segment != drhd->segment)
737
			continue;
738

739
		for_each_active_dev_scope(drhd->devices,
740 741 742 743
					  drhd->devices_cnt, i, tmp) {
			if (tmp == dev) {
				*bus = drhd->devices[i].bus;
				*devfn = drhd->devices[i].devfn;
744
				goto out;
745 746 747 748 749 750 751 752 753 754
			}

			if (!pdev || !dev_is_pci(tmp))
				continue;

			ptmp = to_pci_dev(tmp);
			if (ptmp->subordinate &&
			    ptmp->subordinate->number <= pdev->bus->number &&
			    ptmp->subordinate->busn_res.end >= pdev->bus->number)
				goto got_pdev;
755
		}
756

757 758 759 760
		if (pdev && drhd->include_all) {
		got_pdev:
			*bus = pdev->bus->number;
			*devfn = pdev->devfn;
761
			goto out;
762
		}
763
	}
764
	iommu = NULL;
765
 out:
766
	rcu_read_unlock();
767

768
	return iommu;
769 770
}

W
Weidong Han 已提交
771 772 773 774 775 776 777
static void domain_flush_cache(struct dmar_domain *domain,
			       void *addr, int size)
{
	if (!domain->iommu_coherency)
		clflush_cache_range(addr, size);
}

778 779 780
static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct context_entry *context;
781
	int ret = 0;
782 783 784
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
785 786 787
	context = iommu_context_addr(iommu, bus, devfn, 0);
	if (context)
		ret = context_present(context);
788 789 790 791 792 793 794 795 796 797
	spin_unlock_irqrestore(&iommu->lock, flags);
	return ret;
}

static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct context_entry *context;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
798
	context = iommu_context_addr(iommu, bus, devfn, 0);
799
	if (context) {
800 801
		context_clear_entry(context);
		__iommu_flush_cache(iommu, context, sizeof(*context));
802 803 804 805 806 807 808 809 810 811 812 813 814 815 816
	}
	spin_unlock_irqrestore(&iommu->lock, flags);
}

static void free_context_table(struct intel_iommu *iommu)
{
	int i;
	unsigned long flags;
	struct context_entry *context;

	spin_lock_irqsave(&iommu->lock, flags);
	if (!iommu->root_entry) {
		goto out;
	}
	for (i = 0; i < ROOT_ENTRY_NR; i++) {
817
		context = iommu_context_addr(iommu, i, 0, 0);
818 819
		if (context)
			free_pgtable_page(context);
820

821
		if (!ecs_enabled(iommu))
822 823 824 825 826 827
			continue;

		context = iommu_context_addr(iommu, i, 0x80, 0);
		if (context)
			free_pgtable_page(context);

828 829 830 831 832 833 834
	}
	free_pgtable_page(iommu->root_entry);
	iommu->root_entry = NULL;
out:
	spin_unlock_irqrestore(&iommu->lock, flags);
}

835
static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
836
				      unsigned long pfn, int *target_level)
837 838 839
{
	struct dma_pte *parent, *pte = NULL;
	int level = agaw_to_level(domain->agaw);
840
	int offset;
841 842

	BUG_ON(!domain->pgd);
843

844
	if (!domain_pfn_supported(domain, pfn))
845 846 847
		/* Address beyond IOMMU's addressing capabilities. */
		return NULL;

848 849
	parent = domain->pgd;

850
	while (1) {
851 852
		void *tmp_page;

853
		offset = pfn_level_offset(pfn, level);
854
		pte = &parent[offset];
855
		if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
856
			break;
857
		if (level == *target_level)
858 859
			break;

860
		if (!dma_pte_present(pte)) {
861 862
			uint64_t pteval;

863
			tmp_page = alloc_pgtable_page(domain->nid);
864

865
			if (!tmp_page)
866
				return NULL;
867

868
			domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
869
			pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
870
			if (cmpxchg64(&pte->val, 0ULL, pteval))
871 872
				/* Someone else set it while we were thinking; use theirs. */
				free_pgtable_page(tmp_page);
873
			else
874
				domain_flush_cache(domain, pte, sizeof(*pte));
875
		}
876 877 878
		if (level == 1)
			break;

879
		parent = phys_to_virt(dma_pte_addr(pte));
880 881 882
		level--;
	}

883 884 885
	if (!*target_level)
		*target_level = level;

886 887 888
	return pte;
}

889

890
/* return address's pte at specific level */
891 892
static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
					 unsigned long pfn,
893
					 int level, int *large_page)
894 895 896 897 898 899 900
{
	struct dma_pte *parent, *pte = NULL;
	int total = agaw_to_level(domain->agaw);
	int offset;

	parent = domain->pgd;
	while (level <= total) {
901
		offset = pfn_level_offset(pfn, total);
902 903 904 905
		pte = &parent[offset];
		if (level == total)
			return pte;

906 907
		if (!dma_pte_present(pte)) {
			*large_page = total;
908
			break;
909 910
		}

911
		if (dma_pte_superpage(pte)) {
912 913 914 915
			*large_page = total;
			return pte;
		}

916
		parent = phys_to_virt(dma_pte_addr(pte));
917 918 919 920 921 922
		total--;
	}
	return NULL;
}

/* clear last level pte, a tlb flush should be followed */
923
static void dma_pte_clear_range(struct dmar_domain *domain,
924 925
				unsigned long start_pfn,
				unsigned long last_pfn)
926
{
927
	unsigned int large_page = 1;
928
	struct dma_pte *first_pte, *pte;
929

930 931
	BUG_ON(!domain_pfn_supported(domain, start_pfn));
	BUG_ON(!domain_pfn_supported(domain, last_pfn));
932
	BUG_ON(start_pfn > last_pfn);
933

934
	/* we don't need lock here; nobody else touches the iova range */
935
	do {
936 937
		large_page = 1;
		first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
938
		if (!pte) {
939
			start_pfn = align_to_level(start_pfn + 1, large_page + 1);
940 941
			continue;
		}
942
		do {
943
			dma_clear_pte(pte);
944
			start_pfn += lvl_to_nr_pages(large_page);
945
			pte++;
946 947
		} while (start_pfn <= last_pfn && !first_pte_in_page(pte));

948 949
		domain_flush_cache(domain, first_pte,
				   (void *)pte - (void *)first_pte);
950 951

	} while (start_pfn && start_pfn <= last_pfn);
952 953
}

954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976
static void dma_pte_free_level(struct dmar_domain *domain, int level,
			       struct dma_pte *pte, unsigned long pfn,
			       unsigned long start_pfn, unsigned long last_pfn)
{
	pfn = max(start_pfn, pfn);
	pte = &pte[pfn_level_offset(pfn, level)];

	do {
		unsigned long level_pfn;
		struct dma_pte *level_pte;

		if (!dma_pte_present(pte) || dma_pte_superpage(pte))
			goto next;

		level_pfn = pfn & level_mask(level - 1);
		level_pte = phys_to_virt(dma_pte_addr(pte));

		if (level > 2)
			dma_pte_free_level(domain, level - 1, level_pte,
					   level_pfn, start_pfn, last_pfn);

		/* If range covers entire pagetable, free it */
		if (!(start_pfn > level_pfn ||
977
		      last_pfn < level_pfn + level_size(level) - 1)) {
978 979 980 981 982 983 984 985 986
			dma_clear_pte(pte);
			domain_flush_cache(domain, pte, sizeof(*pte));
			free_pgtable_page(level_pte);
		}
next:
		pfn += level_size(level);
	} while (!first_pte_in_page(++pte) && pfn <= last_pfn);
}

987 988
/* free page table pages. last level pte should already be cleared */
static void dma_pte_free_pagetable(struct dmar_domain *domain,
989 990
				   unsigned long start_pfn,
				   unsigned long last_pfn)
991
{
992 993
	BUG_ON(!domain_pfn_supported(domain, start_pfn));
	BUG_ON(!domain_pfn_supported(domain, last_pfn));
994
	BUG_ON(start_pfn > last_pfn);
995

996 997
	dma_pte_clear_range(domain, start_pfn, last_pfn);

998
	/* We don't need lock here; nobody else touches the iova range */
999 1000
	dma_pte_free_level(domain, agaw_to_level(domain->agaw),
			   domain->pgd, 0, start_pfn, last_pfn);
1001

1002
	/* free pgd */
1003
	if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1004 1005 1006 1007 1008
		free_pgtable_page(domain->pgd);
		domain->pgd = NULL;
	}
}

1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027
/* When a page at a given level is being unlinked from its parent, we don't
   need to *modify* it at all. All we need to do is make a list of all the
   pages which can be freed just as soon as we've flushed the IOTLB and we
   know the hardware page-walk will no longer touch them.
   The 'pte' argument is the *parent* PTE, pointing to the page that is to
   be freed. */
static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
					    int level, struct dma_pte *pte,
					    struct page *freelist)
{
	struct page *pg;

	pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
	pg->freelist = freelist;
	freelist = pg;

	if (level == 1)
		return freelist;

1028 1029
	pte = page_address(pg);
	do {
1030 1031 1032
		if (dma_pte_present(pte) && !dma_pte_superpage(pte))
			freelist = dma_pte_list_pagetables(domain, level - 1,
							   pte, freelist);
1033 1034
		pte++;
	} while (!first_pte_in_page(pte));
1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096

	return freelist;
}

static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
					struct dma_pte *pte, unsigned long pfn,
					unsigned long start_pfn,
					unsigned long last_pfn,
					struct page *freelist)
{
	struct dma_pte *first_pte = NULL, *last_pte = NULL;

	pfn = max(start_pfn, pfn);
	pte = &pte[pfn_level_offset(pfn, level)];

	do {
		unsigned long level_pfn;

		if (!dma_pte_present(pte))
			goto next;

		level_pfn = pfn & level_mask(level);

		/* If range covers entire pagetable, free it */
		if (start_pfn <= level_pfn &&
		    last_pfn >= level_pfn + level_size(level) - 1) {
			/* These suborbinate page tables are going away entirely. Don't
			   bother to clear them; we're just going to *free* them. */
			if (level > 1 && !dma_pte_superpage(pte))
				freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);

			dma_clear_pte(pte);
			if (!first_pte)
				first_pte = pte;
			last_pte = pte;
		} else if (level > 1) {
			/* Recurse down into a level that isn't *entirely* obsolete */
			freelist = dma_pte_clear_level(domain, level - 1,
						       phys_to_virt(dma_pte_addr(pte)),
						       level_pfn, start_pfn, last_pfn,
						       freelist);
		}
next:
		pfn += level_size(level);
	} while (!first_pte_in_page(++pte) && pfn <= last_pfn);

	if (first_pte)
		domain_flush_cache(domain, first_pte,
				   (void *)++last_pte - (void *)first_pte);

	return freelist;
}

/* We can't just free the pages because the IOMMU may still be walking
   the page tables, and may have cached the intermediate levels. The
   pages can only be freed after the IOTLB flush has been done. */
struct page *domain_unmap(struct dmar_domain *domain,
			  unsigned long start_pfn,
			  unsigned long last_pfn)
{
	struct page *freelist = NULL;

1097 1098
	BUG_ON(!domain_pfn_supported(domain, start_pfn));
	BUG_ON(!domain_pfn_supported(domain, last_pfn));
1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126
	BUG_ON(start_pfn > last_pfn);

	/* we don't need lock here; nobody else touches the iova range */
	freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
				       domain->pgd, 0, start_pfn, last_pfn, NULL);

	/* free pgd */
	if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
		struct page *pgd_page = virt_to_page(domain->pgd);
		pgd_page->freelist = freelist;
		freelist = pgd_page;

		domain->pgd = NULL;
	}

	return freelist;
}

void dma_free_pagelist(struct page *freelist)
{
	struct page *pg;

	while ((pg = freelist)) {
		freelist = pg->freelist;
		free_pgtable_page(page_address(pg));
	}
}

1127 1128 1129 1130 1131 1132
/* iommu handling */
static int iommu_alloc_root_entry(struct intel_iommu *iommu)
{
	struct root_entry *root;
	unsigned long flags;

1133
	root = (struct root_entry *)alloc_pgtable_page(iommu->node);
1134 1135 1136
	if (!root) {
		pr_err("IOMMU: allocating root entry for %s failed\n",
			iommu->name);
1137
		return -ENOMEM;
1138
	}
1139

F
Fenghua Yu 已提交
1140
	__iommu_flush_cache(iommu, root, ROOT_SIZE);
1141 1142 1143 1144 1145 1146 1147 1148 1149 1150

	spin_lock_irqsave(&iommu->lock, flags);
	iommu->root_entry = root;
	spin_unlock_irqrestore(&iommu->lock, flags);

	return 0;
}

static void iommu_set_root_entry(struct intel_iommu *iommu)
{
1151
	u64 addr;
1152
	u32 sts;
1153 1154
	unsigned long flag;

1155
	addr = virt_to_phys(iommu->root_entry);
1156
	if (ecs_enabled(iommu))
1157
		addr |= DMA_RTADDR_RTT;
1158

1159
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1160
	dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr);
1161

1162
	writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
1163 1164 1165

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1166
		      readl, (sts & DMA_GSTS_RTPS), sts);
1167

1168
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1169 1170 1171 1172 1173 1174 1175
}

static void iommu_flush_write_buffer(struct intel_iommu *iommu)
{
	u32 val;
	unsigned long flag;

1176
	if (!rwbf_quirk && !cap_rwbf(iommu->cap))
1177 1178
		return;

1179
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1180
	writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
1181 1182 1183

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1184
		      readl, (!(val & DMA_GSTS_WBFS)), val);
1185

1186
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1187 1188 1189
}

/* return value determine if we need a write buffer flush */
1190 1191 1192
static void __iommu_flush_context(struct intel_iommu *iommu,
				  u16 did, u16 source_id, u8 function_mask,
				  u64 type)
1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212
{
	u64 val = 0;
	unsigned long flag;

	switch (type) {
	case DMA_CCMD_GLOBAL_INVL:
		val = DMA_CCMD_GLOBAL_INVL;
		break;
	case DMA_CCMD_DOMAIN_INVL:
		val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
		break;
	case DMA_CCMD_DEVICE_INVL:
		val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
			| DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
		break;
	default:
		BUG();
	}
	val |= DMA_CCMD_ICC;

1213
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1214 1215 1216 1217 1218 1219
	dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
		dmar_readq, (!(val & DMA_CCMD_ICC)), val);

1220
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1221 1222 1223
}

/* return value determine if we need a write buffer flush */
1224 1225
static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
				u64 addr, unsigned int size_order, u64 type)
1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240
{
	int tlb_offset = ecap_iotlb_offset(iommu->ecap);
	u64 val = 0, val_iva = 0;
	unsigned long flag;

	switch (type) {
	case DMA_TLB_GLOBAL_FLUSH:
		/* global flush doesn't need set IVA_REG */
		val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
		break;
	case DMA_TLB_DSI_FLUSH:
		val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
		break;
	case DMA_TLB_PSI_FLUSH:
		val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1241
		/* IH bit is passed in as part of address */
1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258
		val_iva = size_order | addr;
		break;
	default:
		BUG();
	}
	/* Note: set drain read/write */
#if 0
	/*
	 * This is probably to be super secure.. Looks like we can
	 * ignore it without any impact.
	 */
	if (cap_read_drain(iommu->cap))
		val |= DMA_TLB_READ_DRAIN;
#endif
	if (cap_write_drain(iommu->cap))
		val |= DMA_TLB_WRITE_DRAIN;

1259
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1260 1261 1262 1263 1264 1265 1266 1267 1268
	/* Note: Only uses first TLB reg currently */
	if (val_iva)
		dmar_writeq(iommu->reg + tlb_offset, val_iva);
	dmar_writeq(iommu->reg + tlb_offset + 8, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, tlb_offset + 8,
		dmar_readq, (!(val & DMA_TLB_IVT)), val);

1269
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1270 1271 1272 1273 1274 1275

	/* check IOTLB invalidation granularity */
	if (DMA_TLB_IAIG(val) == 0)
		printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
	if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
		pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
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1276 1277
			(unsigned long long)DMA_TLB_IIRG(type),
			(unsigned long long)DMA_TLB_IAIG(val));
1278 1279
}

1280 1281 1282
static struct device_domain_info *
iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
			 u8 bus, u8 devfn)
Y
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1283
{
1284
	bool found = false;
Y
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1285 1286
	unsigned long flags;
	struct device_domain_info *info;
1287
	struct pci_dev *pdev;
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1288 1289 1290 1291 1292 1293 1294 1295 1296

	if (!ecap_dev_iotlb_support(iommu->ecap))
		return NULL;

	if (!iommu->qi)
		return NULL;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link)
1297 1298
		if (info->iommu == iommu && info->bus == bus &&
		    info->devfn == devfn) {
1299
			found = true;
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1300 1301 1302 1303
			break;
		}
	spin_unlock_irqrestore(&device_domain_lock, flags);

1304
	if (!found || !info->dev || !dev_is_pci(info->dev))
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1305 1306
		return NULL;

1307 1308 1309
	pdev = to_pci_dev(info->dev);

	if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS))
Y
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1310 1311
		return NULL;

1312
	if (!dmar_find_matched_atsr_unit(pdev))
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1313 1314 1315 1316 1317 1318
		return NULL;

	return info;
}

static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1319
{
1320
	if (!info || !dev_is_pci(info->dev))
Y
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1321 1322
		return;

1323
	pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT);
Y
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1324 1325 1326 1327
}

static void iommu_disable_dev_iotlb(struct device_domain_info *info)
{
1328 1329
	if (!info->dev || !dev_is_pci(info->dev) ||
	    !pci_ats_enabled(to_pci_dev(info->dev)))
Y
Yu Zhao 已提交
1330 1331
		return;

1332
	pci_disable_ats(to_pci_dev(info->dev));
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1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343
}

static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
				  u64 addr, unsigned mask)
{
	u16 sid, qdep;
	unsigned long flags;
	struct device_domain_info *info;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link) {
1344 1345 1346 1347 1348 1349
		struct pci_dev *pdev;
		if (!info->dev || !dev_is_pci(info->dev))
			continue;

		pdev = to_pci_dev(info->dev);
		if (!pci_ats_enabled(pdev))
Y
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1350 1351 1352
			continue;

		sid = info->bus << 8 | info->devfn;
1353
		qdep = pci_ats_queue_depth(pdev);
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1354 1355 1356 1357 1358
		qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

1359
static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1360
				  unsigned long pfn, unsigned int pages, int ih, int map)
1361
{
1362
	unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1363
	uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1364 1365 1366

	BUG_ON(pages == 0);

1367 1368
	if (ih)
		ih = 1 << 6;
1369
	/*
1370 1371
	 * Fallback to domain selective flush if no PSI support or the size is
	 * too big.
1372 1373 1374
	 * PSI requires page size to be 2 ^ x, and the base address is naturally
	 * aligned to the size
	 */
1375 1376
	if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
		iommu->flush.flush_iotlb(iommu, did, 0, 0,
1377
						DMA_TLB_DSI_FLUSH);
1378
	else
1379
		iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
1380
						DMA_TLB_PSI_FLUSH);
1381 1382

	/*
1383 1384
	 * In caching mode, changes of pages from non-present to present require
	 * flush. However, device IOTLB doesn't need to be flushed in this case.
1385
	 */
1386
	if (!cap_caching_mode(iommu->cap) || !map)
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1387
		iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1388 1389
}

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1390 1391 1392 1393 1394
static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
{
	u32 pmen;
	unsigned long flags;

1395
	raw_spin_lock_irqsave(&iommu->register_lock, flags);
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1396 1397 1398 1399 1400 1401 1402 1403
	pmen = readl(iommu->reg + DMAR_PMEN_REG);
	pmen &= ~DMA_PMEN_EPM;
	writel(pmen, iommu->reg + DMAR_PMEN_REG);

	/* wait for the protected region status bit to clear */
	IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
		readl, !(pmen & DMA_PMEN_PRS), pmen);

1404
	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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1405 1406
}

1407
static void iommu_enable_translation(struct intel_iommu *iommu)
1408 1409 1410 1411
{
	u32 sts;
	unsigned long flags;

1412
	raw_spin_lock_irqsave(&iommu->register_lock, flags);
1413 1414
	iommu->gcmd |= DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1415 1416 1417

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1418
		      readl, (sts & DMA_GSTS_TES), sts);
1419

1420
	raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1421 1422
}

1423
static void iommu_disable_translation(struct intel_iommu *iommu)
1424 1425 1426 1427
{
	u32 sts;
	unsigned long flag;

1428
	raw_spin_lock_irqsave(&iommu->register_lock, flag);
1429 1430 1431 1432 1433
	iommu->gcmd &= ~DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1434
		      readl, (!(sts & DMA_GSTS_TES)), sts);
1435

1436
	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1437 1438
}

1439

1440 1441 1442 1443 1444 1445
static int iommu_init_domains(struct intel_iommu *iommu)
{
	unsigned long ndomains;
	unsigned long nlongs;

	ndomains = cap_ndoms(iommu->cap);
1446 1447
	pr_debug("IOMMU%d: Number of Domains supported <%ld>\n",
		 iommu->seq_id, ndomains);
1448 1449
	nlongs = BITS_TO_LONGS(ndomains);

1450 1451
	spin_lock_init(&iommu->lock);

1452 1453 1454 1455 1456
	/* TBD: there might be 64K domains,
	 * consider other allocation for future chip
	 */
	iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
	if (!iommu->domain_ids) {
1457 1458
		pr_err("IOMMU%d: allocating domain id array failed\n",
		       iommu->seq_id);
1459 1460 1461 1462 1463
		return -ENOMEM;
	}
	iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
			GFP_KERNEL);
	if (!iommu->domains) {
1464 1465 1466 1467
		pr_err("IOMMU%d: allocating domain array failed\n",
		       iommu->seq_id);
		kfree(iommu->domain_ids);
		iommu->domain_ids = NULL;
1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479
		return -ENOMEM;
	}

	/*
	 * if Caching mode is set, then invalid translations are tagged
	 * with domainid 0. Hence we need to pre-allocate it.
	 */
	if (cap_caching_mode(iommu->cap))
		set_bit(0, iommu->domain_ids);
	return 0;
}

1480
static void disable_dmar_iommu(struct intel_iommu *iommu)
1481 1482
{
	struct dmar_domain *domain;
1483
	int i;
1484

1485
	if ((iommu->domains) && (iommu->domain_ids)) {
1486
		for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
1487 1488 1489 1490 1491 1492 1493
			/*
			 * Domain id 0 is reserved for invalid translation
			 * if hardware supports caching mode.
			 */
			if (cap_caching_mode(iommu->cap) && i == 0)
				continue;

1494 1495
			domain = iommu->domains[i];
			clear_bit(i, iommu->domain_ids);
1496 1497
			if (domain_detach_iommu(domain, iommu) == 0 &&
			    !domain_type_is_vm(domain))
1498
				domain_exit(domain);
1499
		}
1500 1501 1502 1503
	}

	if (iommu->gcmd & DMA_GCMD_TE)
		iommu_disable_translation(iommu);
1504
}
1505

1506 1507 1508 1509 1510 1511 1512 1513
static void free_dmar_iommu(struct intel_iommu *iommu)
{
	if ((iommu->domains) && (iommu->domain_ids)) {
		kfree(iommu->domains);
		kfree(iommu->domain_ids);
		iommu->domains = NULL;
		iommu->domain_ids = NULL;
	}
1514

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Weidong Han 已提交
1515 1516
	g_iommus[iommu->seq_id] = NULL;

1517 1518 1519 1520
	/* free context mapping */
	free_context_table(iommu);
}

1521
static struct dmar_domain *alloc_domain(int flags)
1522
{
1523 1524
	/* domain id for virtual machine, it won't be set in context */
	static atomic_t vm_domid = ATOMIC_INIT(0);
1525 1526 1527 1528 1529 1530
	struct dmar_domain *domain;

	domain = alloc_domain_mem();
	if (!domain)
		return NULL;

1531
	memset(domain, 0, sizeof(*domain));
1532
	domain->nid = -1;
1533
	domain->flags = flags;
1534 1535
	spin_lock_init(&domain->iommu_lock);
	INIT_LIST_HEAD(&domain->devices);
1536
	if (flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1537
		domain->id = atomic_inc_return(&vm_domid);
1538 1539 1540 1541

	return domain;
}

1542 1543
static int __iommu_attach_domain(struct dmar_domain *domain,
				 struct intel_iommu *iommu)
1544 1545 1546 1547
{
	int num;
	unsigned long ndomains;

1548 1549
	ndomains = cap_ndoms(iommu->cap);
	num = find_first_zero_bit(iommu->domain_ids, ndomains);
1550 1551 1552 1553 1554
	if (num < ndomains) {
		set_bit(num, iommu->domain_ids);
		iommu->domains[num] = domain;
	} else {
		num = -ENOSPC;
1555 1556
	}

1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567
	return num;
}

static int iommu_attach_domain(struct dmar_domain *domain,
			       struct intel_iommu *iommu)
{
	int num;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	num = __iommu_attach_domain(domain, iommu);
1568
	spin_unlock_irqrestore(&iommu->lock, flags);
1569 1570
	if (num < 0)
		pr_err("IOMMU: no free domain ids\n");
1571

1572
	return num;
1573 1574
}

1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588
static int iommu_attach_vm_domain(struct dmar_domain *domain,
				  struct intel_iommu *iommu)
{
	int num;
	unsigned long ndomains;

	ndomains = cap_ndoms(iommu->cap);
	for_each_set_bit(num, iommu->domain_ids, ndomains)
		if (iommu->domains[num] == domain)
			return num;

	return __iommu_attach_domain(domain, iommu);
}

1589 1590
static void iommu_detach_domain(struct dmar_domain *domain,
				struct intel_iommu *iommu)
1591 1592
{
	unsigned long flags;
1593
	int num, ndomains;
1594

1595
	spin_lock_irqsave(&iommu->lock, flags);
1596 1597 1598 1599 1600 1601 1602 1603
	if (domain_type_is_vm_or_si(domain)) {
		ndomains = cap_ndoms(iommu->cap);
		for_each_set_bit(num, iommu->domain_ids, ndomains) {
			if (iommu->domains[num] == domain) {
				clear_bit(num, iommu->domain_ids);
				iommu->domains[num] = NULL;
				break;
			}
1604
		}
1605 1606 1607
	} else {
		clear_bit(domain->id, iommu->domain_ids);
		iommu->domains[domain->id] = NULL;
1608
	}
1609
	spin_unlock_irqrestore(&iommu->lock, flags);
1610 1611
}

1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642
static void domain_attach_iommu(struct dmar_domain *domain,
			       struct intel_iommu *iommu)
{
	unsigned long flags;

	spin_lock_irqsave(&domain->iommu_lock, flags);
	if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
		domain->iommu_count++;
		if (domain->iommu_count == 1)
			domain->nid = iommu->node;
		domain_update_iommu_cap(domain);
	}
	spin_unlock_irqrestore(&domain->iommu_lock, flags);
}

static int domain_detach_iommu(struct dmar_domain *domain,
			       struct intel_iommu *iommu)
{
	unsigned long flags;
	int count = INT_MAX;

	spin_lock_irqsave(&domain->iommu_lock, flags);
	if (test_and_clear_bit(iommu->seq_id, domain->iommu_bmp)) {
		count = --domain->iommu_count;
		domain_update_iommu_cap(domain);
	}
	spin_unlock_irqrestore(&domain->iommu_lock, flags);

	return count;
}

1643
static struct iova_domain reserved_iova_list;
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Mark Gross 已提交
1644
static struct lock_class_key reserved_rbtree_key;
1645

1646
static int dmar_init_reserved_ranges(void)
1647 1648 1649 1650 1651
{
	struct pci_dev *pdev = NULL;
	struct iova *iova;
	int i;

1652 1653
	init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN,
			DMA_32BIT_PFN);
1654

M
Mark Gross 已提交
1655 1656 1657
	lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
		&reserved_rbtree_key);

1658 1659 1660
	/* IOAPIC ranges shouldn't be accessed by DMA */
	iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
		IOVA_PFN(IOAPIC_RANGE_END));
1661
	if (!iova) {
1662
		printk(KERN_ERR "Reserve IOAPIC range failed\n");
1663 1664
		return -ENODEV;
	}
1665 1666 1667 1668 1669 1670 1671 1672 1673

	/* Reserve all PCI MMIO to avoid peer-to-peer access */
	for_each_pci_dev(pdev) {
		struct resource *r;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			r = &pdev->resource[i];
			if (!r->flags || !(r->flags & IORESOURCE_MEM))
				continue;
1674 1675 1676
			iova = reserve_iova(&reserved_iova_list,
					    IOVA_PFN(r->start),
					    IOVA_PFN(r->end));
1677
			if (!iova) {
1678
				printk(KERN_ERR "Reserve iova failed\n");
1679 1680
				return -ENODEV;
			}
1681 1682
		}
	}
1683
	return 0;
1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710
}

static void domain_reserve_special_ranges(struct dmar_domain *domain)
{
	copy_reserved_iova(&reserved_iova_list, &domain->iovad);
}

static inline int guestwidth_to_adjustwidth(int gaw)
{
	int agaw;
	int r = (gaw - 12) % 9;

	if (r == 0)
		agaw = gaw;
	else
		agaw = gaw + 9 - r;
	if (agaw > 64)
		agaw = 64;
	return agaw;
}

static int domain_init(struct dmar_domain *domain, int guest_width)
{
	struct intel_iommu *iommu;
	int adjust_width, agaw;
	unsigned long sagaw;

1711 1712
	init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
			DMA_32BIT_PFN);
1713 1714 1715
	domain_reserve_special_ranges(domain);

	/* calculate AGAW */
1716
	iommu = domain_get_iommu(domain);
1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731
	if (guest_width > cap_mgaw(iommu->cap))
		guest_width = cap_mgaw(iommu->cap);
	domain->gaw = guest_width;
	adjust_width = guestwidth_to_adjustwidth(guest_width);
	agaw = width_to_agaw(adjust_width);
	sagaw = cap_sagaw(iommu->cap);
	if (!test_bit(agaw, &sagaw)) {
		/* hardware doesn't support it, choose a bigger one */
		pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
		agaw = find_next_bit(&sagaw, 5, agaw);
		if (agaw >= 5)
			return -ENODEV;
	}
	domain->agaw = agaw;

W
Weidong Han 已提交
1732 1733 1734 1735 1736
	if (ecap_coherent(iommu->ecap))
		domain->iommu_coherency = 1;
	else
		domain->iommu_coherency = 0;

1737 1738 1739 1740 1741
	if (ecap_sc_support(iommu->ecap))
		domain->iommu_snooping = 1;
	else
		domain->iommu_snooping = 0;

1742 1743 1744 1745 1746
	if (intel_iommu_superpage)
		domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
	else
		domain->iommu_superpage = 0;

1747
	domain->nid = iommu->node;
1748

1749
	/* always allocate the top pgd */
1750
	domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
1751 1752
	if (!domain->pgd)
		return -ENOMEM;
F
Fenghua Yu 已提交
1753
	__iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1754 1755 1756 1757 1758
	return 0;
}

static void domain_exit(struct dmar_domain *domain)
{
1759
	struct page *freelist = NULL;
1760
	int i;
1761 1762 1763 1764 1765

	/* Domain 0 is reserved, so dont process it */
	if (!domain)
		return;

1766 1767 1768 1769
	/* Flush any lazy unmaps that may reference this domain */
	if (!intel_iommu_strict)
		flush_unmaps_timeout(0);

1770
	/* remove associated devices */
1771
	domain_remove_dev_info(domain);
1772

1773 1774 1775
	/* destroy iovas */
	put_iova_domain(&domain->iovad);

1776
	freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1777

1778
	/* clear attached or cached domains */
1779
	rcu_read_lock();
1780 1781
	for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus)
		iommu_detach_domain(domain, g_iommus[i]);
1782
	rcu_read_unlock();
1783

1784 1785
	dma_free_pagelist(freelist);

1786 1787 1788
	free_domain_mem(domain);
}

1789 1790 1791
static int domain_context_mapping_one(struct dmar_domain *domain,
				      struct intel_iommu *iommu,
				      u8 bus, u8 devfn, int translation)
1792 1793 1794
{
	struct context_entry *context;
	unsigned long flags;
1795 1796 1797
	struct dma_pte *pgd;
	int id;
	int agaw;
Y
Yu Zhao 已提交
1798
	struct device_domain_info *info = NULL;
1799 1800 1801

	pr_debug("Set context mapping for %02x:%02x.%d\n",
		bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
F
Fenghua Yu 已提交
1802

1803
	BUG_ON(!domain->pgd);
F
Fenghua Yu 已提交
1804 1805
	BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
	       translation != CONTEXT_TT_MULTI_LEVEL);
W
Weidong Han 已提交
1806

1807 1808 1809
	spin_lock_irqsave(&iommu->lock, flags);
	context = iommu_context_addr(iommu, bus, devfn, 1);
	spin_unlock_irqrestore(&iommu->lock, flags);
1810 1811 1812
	if (!context)
		return -ENOMEM;
	spin_lock_irqsave(&iommu->lock, flags);
1813
	if (context_present(context)) {
1814 1815 1816 1817
		spin_unlock_irqrestore(&iommu->lock, flags);
		return 0;
	}

1818 1819 1820
	id = domain->id;
	pgd = domain->pgd;

1821
	if (domain_type_is_vm_or_si(domain)) {
1822 1823
		if (domain_type_is_vm(domain)) {
			id = iommu_attach_vm_domain(domain, iommu);
1824
			if (id < 0) {
1825
				spin_unlock_irqrestore(&iommu->lock, flags);
1826
				pr_err("IOMMU: no free domain ids\n");
1827 1828 1829 1830 1831 1832
				return -EFAULT;
			}
		}

		/* Skip top levels of page tables for
		 * iommu which has less agaw than default.
1833
		 * Unnecessary for PT mode.
1834
		 */
1835 1836 1837 1838 1839 1840 1841
		if (translation != CONTEXT_TT_PASS_THROUGH) {
			for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
				pgd = phys_to_virt(dma_pte_addr(pgd));
				if (!dma_pte_present(pgd)) {
					spin_unlock_irqrestore(&iommu->lock, flags);
					return -ENOMEM;
				}
1842 1843 1844 1845 1846
			}
		}
	}

	context_set_domain_id(context, id);
F
Fenghua Yu 已提交
1847

Y
Yu Zhao 已提交
1848
	if (translation != CONTEXT_TT_PASS_THROUGH) {
1849
		info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
Y
Yu Zhao 已提交
1850 1851 1852
		translation = info ? CONTEXT_TT_DEV_IOTLB :
				     CONTEXT_TT_MULTI_LEVEL;
	}
F
Fenghua Yu 已提交
1853 1854 1855 1856
	/*
	 * In pass through mode, AW must be programmed to indicate the largest
	 * AGAW value supported by hardware. And ASR is ignored by hardware.
	 */
Y
Yu Zhao 已提交
1857
	if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
F
Fenghua Yu 已提交
1858
		context_set_address_width(context, iommu->msagaw);
Y
Yu Zhao 已提交
1859 1860 1861 1862
	else {
		context_set_address_root(context, virt_to_phys(pgd));
		context_set_address_width(context, iommu->agaw);
	}
F
Fenghua Yu 已提交
1863 1864

	context_set_translation_type(context, translation);
1865 1866
	context_set_fault_enable(context);
	context_set_present(context);
W
Weidong Han 已提交
1867
	domain_flush_cache(domain, context, sizeof(*context));
1868

1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879
	/*
	 * It's a non-present to present mapping. If hardware doesn't cache
	 * non-present entry we only need to flush the write-buffer. If the
	 * _does_ cache non-present entries, then it does so in the special
	 * domain #0, which we have to flush:
	 */
	if (cap_caching_mode(iommu->cap)) {
		iommu->flush.flush_context(iommu, 0,
					   (((u16)bus) << 8) | devfn,
					   DMA_CCMD_MASK_NOBIT,
					   DMA_CCMD_DEVICE_INVL);
1880
		iommu->flush.flush_iotlb(iommu, id, 0, 0, DMA_TLB_DSI_FLUSH);
1881
	} else {
1882
		iommu_flush_write_buffer(iommu);
1883
	}
Y
Yu Zhao 已提交
1884
	iommu_enable_dev_iotlb(info);
1885
	spin_unlock_irqrestore(&iommu->lock, flags);
1886

1887 1888
	domain_attach_iommu(domain, iommu);

1889 1890 1891
	return 0;
}

1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907
struct domain_context_mapping_data {
	struct dmar_domain *domain;
	struct intel_iommu *iommu;
	int translation;
};

static int domain_context_mapping_cb(struct pci_dev *pdev,
				     u16 alias, void *opaque)
{
	struct domain_context_mapping_data *data = opaque;

	return domain_context_mapping_one(data->domain, data->iommu,
					  PCI_BUS_NUM(alias), alias & 0xff,
					  data->translation);
}

1908
static int
1909 1910
domain_context_mapping(struct dmar_domain *domain, struct device *dev,
		       int translation)
1911
{
1912
	struct intel_iommu *iommu;
1913
	u8 bus, devfn;
1914
	struct domain_context_mapping_data data;
1915

1916
	iommu = device_to_iommu(dev, &bus, &devfn);
1917 1918
	if (!iommu)
		return -ENODEV;
1919

1920 1921
	if (!dev_is_pci(dev))
		return domain_context_mapping_one(domain, iommu, bus, devfn,
F
Fenghua Yu 已提交
1922
						  translation);
1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937

	data.domain = domain;
	data.iommu = iommu;
	data.translation = translation;

	return pci_for_each_dma_alias(to_pci_dev(dev),
				      &domain_context_mapping_cb, &data);
}

static int domain_context_mapped_cb(struct pci_dev *pdev,
				    u16 alias, void *opaque)
{
	struct intel_iommu *iommu = opaque;

	return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff);
1938 1939
}

1940
static int domain_context_mapped(struct device *dev)
1941
{
W
Weidong Han 已提交
1942
	struct intel_iommu *iommu;
1943
	u8 bus, devfn;
W
Weidong Han 已提交
1944

1945
	iommu = device_to_iommu(dev, &bus, &devfn);
W
Weidong Han 已提交
1946 1947
	if (!iommu)
		return -ENODEV;
1948

1949 1950
	if (!dev_is_pci(dev))
		return device_context_mapped(iommu, bus, devfn);
1951

1952 1953
	return !pci_for_each_dma_alias(to_pci_dev(dev),
				       domain_context_mapped_cb, iommu);
1954 1955
}

1956 1957 1958 1959 1960 1961 1962 1963
/* Returns a number of VTD pages, but aligned to MM page size */
static inline unsigned long aligned_nrpages(unsigned long host_addr,
					    size_t size)
{
	host_addr &= ~PAGE_MASK;
	return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
}

1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991
/* Return largest possible superpage level for a given mapping */
static inline int hardware_largepage_caps(struct dmar_domain *domain,
					  unsigned long iov_pfn,
					  unsigned long phy_pfn,
					  unsigned long pages)
{
	int support, level = 1;
	unsigned long pfnmerge;

	support = domain->iommu_superpage;

	/* To use a large page, the virtual *and* physical addresses
	   must be aligned to 2MiB/1GiB/etc. Lower bits set in either
	   of them will mean we have to use smaller pages. So just
	   merge them and check both at once. */
	pfnmerge = iov_pfn | phy_pfn;

	while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
		pages >>= VTD_STRIDE_SHIFT;
		if (!pages)
			break;
		pfnmerge >>= VTD_STRIDE_SHIFT;
		level++;
		support--;
	}
	return level;
}

1992 1993 1994
static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
			    struct scatterlist *sg, unsigned long phys_pfn,
			    unsigned long nr_pages, int prot)
1995 1996
{
	struct dma_pte *first_pte = NULL, *pte = NULL;
1997
	phys_addr_t uninitialized_var(pteval);
1998
	unsigned long sg_res = 0;
1999 2000
	unsigned int largepage_lvl = 0;
	unsigned long lvl_pages = 0;
2001

2002
	BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1));
2003 2004 2005 2006 2007 2008

	if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
		return -EINVAL;

	prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;

2009 2010
	if (!sg) {
		sg_res = nr_pages;
2011 2012 2013
		pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
	}

2014
	while (nr_pages > 0) {
2015 2016
		uint64_t tmp;

2017
		if (!sg_res) {
2018
			sg_res = aligned_nrpages(sg->offset, sg->length);
2019 2020 2021
			sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
			sg->dma_length = sg->length;
			pteval = page_to_phys(sg_page(sg)) | prot;
2022
			phys_pfn = pteval >> VTD_PAGE_SHIFT;
2023
		}
2024

2025
		if (!pte) {
2026 2027
			largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);

2028
			first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
2029 2030
			if (!pte)
				return -ENOMEM;
2031
			/* It is large page*/
2032
			if (largepage_lvl > 1) {
2033
				pteval |= DMA_PTE_LARGE_PAGE;
2034 2035 2036 2037 2038 2039
				lvl_pages = lvl_to_nr_pages(largepage_lvl);
				/*
				 * Ensure that old small page tables are
				 * removed to make room for superpage,
				 * if they exist.
				 */
2040
				dma_pte_free_pagetable(domain, iov_pfn,
2041
						       iov_pfn + lvl_pages - 1);
2042
			} else {
2043
				pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
2044
			}
2045

2046 2047 2048 2049
		}
		/* We don't need lock here, nobody else
		 * touches the iova range
		 */
2050
		tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
2051
		if (tmp) {
2052
			static int dumps = 5;
2053 2054
			printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
			       iov_pfn, tmp, (unsigned long long)pteval);
2055 2056 2057 2058 2059 2060
			if (dumps) {
				dumps--;
				debug_dma_dump_mappings(NULL);
			}
			WARN_ON(1);
		}
2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083

		lvl_pages = lvl_to_nr_pages(largepage_lvl);

		BUG_ON(nr_pages < lvl_pages);
		BUG_ON(sg_res < lvl_pages);

		nr_pages -= lvl_pages;
		iov_pfn += lvl_pages;
		phys_pfn += lvl_pages;
		pteval += lvl_pages * VTD_PAGE_SIZE;
		sg_res -= lvl_pages;

		/* If the next PTE would be the first in a new page, then we
		   need to flush the cache on the entries we've just written.
		   And then we'll need to recalculate 'pte', so clear it and
		   let it get set again in the if (!pte) block above.

		   If we're done (!nr_pages) we need to flush the cache too.

		   Also if we've been setting superpages, we may need to
		   recalculate 'pte' and switch back to smaller pages for the
		   end of the mapping, if the trailing size is not enough to
		   use another superpage (i.e. sg_res < lvl_pages). */
2084
		pte++;
2085 2086
		if (!nr_pages || first_pte_in_page(pte) ||
		    (largepage_lvl > 1 && sg_res < lvl_pages)) {
2087 2088 2089 2090
			domain_flush_cache(domain, first_pte,
					   (void *)pte - (void *)first_pte);
			pte = NULL;
		}
2091 2092

		if (!sg_res && nr_pages)
2093 2094 2095 2096 2097
			sg = sg_next(sg);
	}
	return 0;
}

2098 2099 2100
static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
				    struct scatterlist *sg, unsigned long nr_pages,
				    int prot)
2101
{
2102 2103
	return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
}
2104

2105 2106 2107 2108 2109
static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
				     unsigned long phys_pfn, unsigned long nr_pages,
				     int prot)
{
	return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
2110 2111
}

2112
static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
2113
{
2114 2115
	if (!iommu)
		return;
2116 2117 2118

	clear_context_table(iommu, bus, devfn);
	iommu->flush.flush_context(iommu, 0, 0, 0,
2119
					   DMA_CCMD_GLOBAL_INVL);
2120
	iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2121 2122
}

2123 2124 2125 2126 2127 2128
static inline void unlink_domain_info(struct device_domain_info *info)
{
	assert_spin_locked(&device_domain_lock);
	list_del(&info->link);
	list_del(&info->global);
	if (info->dev)
2129
		info->dev->archdata.iommu = NULL;
2130 2131
}

2132 2133
static void domain_remove_dev_info(struct dmar_domain *domain)
{
2134
	struct device_domain_info *info, *tmp;
2135
	unsigned long flags;
2136 2137

	spin_lock_irqsave(&device_domain_lock, flags);
2138
	list_for_each_entry_safe(info, tmp, &domain->devices, link) {
2139
		unlink_domain_info(info);
2140 2141
		spin_unlock_irqrestore(&device_domain_lock, flags);

Y
Yu Zhao 已提交
2142
		iommu_disable_dev_iotlb(info);
2143
		iommu_detach_dev(info->iommu, info->bus, info->devfn);
2144

2145
		if (domain_type_is_vm(domain)) {
2146
			iommu_detach_dependent_devices(info->iommu, info->dev);
2147
			domain_detach_iommu(domain, info->iommu);
2148 2149 2150
		}

		free_devinfo_mem(info);
2151 2152 2153 2154 2155 2156 2157
		spin_lock_irqsave(&device_domain_lock, flags);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

/*
 * find_domain
2158
 * Note: we use struct device->archdata.iommu stores the info
2159
 */
2160
static struct dmar_domain *find_domain(struct device *dev)
2161 2162 2163 2164
{
	struct device_domain_info *info;

	/* No lock here, assumes no domain exit in normal case */
2165
	info = dev->archdata.iommu;
2166 2167 2168 2169 2170
	if (info)
		return info->domain;
	return NULL;
}

2171
static inline struct device_domain_info *
2172 2173 2174 2175 2176
dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
{
	struct device_domain_info *info;

	list_for_each_entry(info, &device_domain_list, global)
2177
		if (info->iommu->segment == segment && info->bus == bus &&
2178
		    info->devfn == devfn)
2179
			return info;
2180 2181 2182 2183

	return NULL;
}

2184
static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu,
2185
						int bus, int devfn,
2186 2187
						struct device *dev,
						struct dmar_domain *domain)
2188
{
2189
	struct dmar_domain *found = NULL;
2190 2191 2192 2193 2194
	struct device_domain_info *info;
	unsigned long flags;

	info = alloc_devinfo_mem();
	if (!info)
2195
		return NULL;
2196 2197 2198 2199 2200

	info->bus = bus;
	info->devfn = devfn;
	info->dev = dev;
	info->domain = domain;
2201
	info->iommu = iommu;
2202 2203 2204

	spin_lock_irqsave(&device_domain_lock, flags);
	if (dev)
2205
		found = find_domain(dev);
2206 2207
	else {
		struct device_domain_info *info2;
2208
		info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn);
2209 2210 2211
		if (info2)
			found = info2->domain;
	}
2212 2213 2214
	if (found) {
		spin_unlock_irqrestore(&device_domain_lock, flags);
		free_devinfo_mem(info);
2215 2216
		/* Caller must free the original domain */
		return found;
2217 2218
	}

2219 2220 2221 2222 2223 2224 2225
	list_add(&info->link, &domain->devices);
	list_add(&info->global, &device_domain_list);
	if (dev)
		dev->archdata.iommu = info;
	spin_unlock_irqrestore(&device_domain_lock, flags);

	return domain;
2226 2227
}

2228 2229 2230 2231 2232 2233
static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque)
{
	*(u16 *)opaque = alias;
	return 0;
}

2234
/* domain is initialized */
2235
static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw)
2236
{
2237 2238
	struct dmar_domain *domain, *tmp;
	struct intel_iommu *iommu;
2239
	struct device_domain_info *info;
2240
	u16 dma_alias;
2241
	unsigned long flags;
2242
	u8 bus, devfn;
2243

2244
	domain = find_domain(dev);
2245 2246 2247
	if (domain)
		return domain;

2248 2249 2250 2251
	iommu = device_to_iommu(dev, &bus, &devfn);
	if (!iommu)
		return NULL;

2252 2253
	if (dev_is_pci(dev)) {
		struct pci_dev *pdev = to_pci_dev(dev);
2254

2255 2256 2257 2258 2259 2260 2261 2262 2263
		pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias);

		spin_lock_irqsave(&device_domain_lock, flags);
		info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus),
						      PCI_BUS_NUM(dma_alias),
						      dma_alias & 0xff);
		if (info) {
			iommu = info->iommu;
			domain = info->domain;
2264
		}
2265
		spin_unlock_irqrestore(&device_domain_lock, flags);
2266

2267 2268 2269 2270
		/* DMA alias already has a domain, uses it */
		if (info)
			goto found_domain;
	}
2271

2272
	/* Allocate and initialize new domain for the device */
2273
	domain = alloc_domain(0);
2274
	if (!domain)
2275
		return NULL;
2276 2277
	domain->id = iommu_attach_domain(domain, iommu);
	if (domain->id < 0) {
2278
		free_domain_mem(domain);
2279
		return NULL;
2280
	}
2281
	domain_attach_iommu(domain, iommu);
2282 2283 2284
	if (domain_init(domain, gaw)) {
		domain_exit(domain);
		return NULL;
2285
	}
2286

2287 2288 2289 2290 2291 2292 2293 2294 2295 2296
	/* register PCI DMA alias device */
	if (dev_is_pci(dev)) {
		tmp = dmar_insert_dev_info(iommu, PCI_BUS_NUM(dma_alias),
					   dma_alias & 0xff, NULL, domain);

		if (!tmp || tmp != domain) {
			domain_exit(domain);
			domain = tmp;
		}

2297
		if (!domain)
2298
			return NULL;
2299 2300 2301
	}

found_domain:
2302 2303 2304 2305 2306 2307
	tmp = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);

	if (!tmp || tmp != domain) {
		domain_exit(domain);
		domain = tmp;
	}
2308 2309

	return domain;
2310 2311
}

2312
static int iommu_identity_mapping;
2313 2314 2315
#define IDENTMAP_ALL		1
#define IDENTMAP_GFX		2
#define IDENTMAP_AZALIA		4
2316

2317 2318 2319
static int iommu_domain_identity_map(struct dmar_domain *domain,
				     unsigned long long start,
				     unsigned long long end)
2320
{
2321 2322 2323 2324 2325
	unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
	unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;

	if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
			  dma_to_mm_pfn(last_vpfn))) {
2326
		printk(KERN_ERR "IOMMU: reserve iova failed\n");
2327
		return -ENOMEM;
2328 2329
	}

2330 2331
	pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
		 start, end, domain->id);
2332 2333 2334 2335
	/*
	 * RMRR range might have overlap with physical memory range,
	 * clear it first
	 */
2336
	dma_pte_clear_range(domain, first_vpfn, last_vpfn);
2337

2338 2339
	return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
				  last_vpfn - first_vpfn + 1,
2340
				  DMA_PTE_READ|DMA_PTE_WRITE);
2341 2342
}

2343
static int iommu_prepare_identity_map(struct device *dev,
2344 2345 2346 2347 2348 2349
				      unsigned long long start,
				      unsigned long long end)
{
	struct dmar_domain *domain;
	int ret;

2350
	domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2351 2352 2353
	if (!domain)
		return -ENOMEM;

2354 2355 2356 2357 2358 2359
	/* For _hardware_ passthrough, don't bother. But for software
	   passthrough, we do it anyway -- it may indicate a memory
	   range which is reserved in E820, so which didn't get set
	   up to start with in si_domain */
	if (domain == si_domain && hw_pass_through) {
		printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2360
		       dev_name(dev), start, end);
2361 2362 2363 2364 2365
		return 0;
	}

	printk(KERN_INFO
	       "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2366
	       dev_name(dev), start, end);
2367
	
2368 2369 2370 2371 2372 2373 2374 2375 2376 2377
	if (end < start) {
		WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
			"BIOS vendor: %s; Ver: %s; Product Version: %s\n",
			dmi_get_system_info(DMI_BIOS_VENDOR),
			dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		ret = -EIO;
		goto error;
	}

2378 2379 2380 2381 2382 2383 2384 2385 2386 2387
	if (end >> agaw_to_width(domain->agaw)) {
		WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
		     agaw_to_width(domain->agaw),
		     dmi_get_system_info(DMI_BIOS_VENDOR),
		     dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		ret = -EIO;
		goto error;
	}
2388

2389
	ret = iommu_domain_identity_map(domain, start, end);
2390 2391 2392 2393
	if (ret)
		goto error;

	/* context entry init */
2394
	ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
2395 2396 2397 2398 2399 2400
	if (ret)
		goto error;

	return 0;

 error:
2401 2402 2403 2404 2405
	domain_exit(domain);
	return ret;
}

static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2406
					 struct device *dev)
2407
{
2408
	if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2409
		return 0;
2410 2411
	return iommu_prepare_identity_map(dev, rmrr->base_address,
					  rmrr->end_address);
2412 2413
}

2414
#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
2415 2416 2417 2418 2419 2420 2421 2422 2423
static inline void iommu_prepare_isa(void)
{
	struct pci_dev *pdev;
	int ret;

	pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
	if (!pdev)
		return;

2424
	printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2425
	ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
2426 2427

	if (ret)
2428 2429
		printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
		       "floppy might not work\n");
2430

2431
	pci_dev_put(pdev);
2432 2433 2434 2435 2436 2437
}
#else
static inline void iommu_prepare_isa(void)
{
	return;
}
2438
#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
2439

2440
static int md_domain_init(struct dmar_domain *domain, int guest_width);
2441

2442
static int __init si_domain_init(int hw)
2443 2444 2445
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
2446
	int nid, ret = 0;
2447
	bool first = true;
2448

2449
	si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY);
2450 2451 2452 2453 2454
	if (!si_domain)
		return -EFAULT;

	for_each_active_iommu(iommu, drhd) {
		ret = iommu_attach_domain(si_domain, iommu);
2455
		if (ret < 0) {
2456 2457
			domain_exit(si_domain);
			return -EFAULT;
2458 2459 2460 2461 2462 2463
		} else if (first) {
			si_domain->id = ret;
			first = false;
		} else if (si_domain->id != ret) {
			domain_exit(si_domain);
			return -EFAULT;
2464
		}
2465
		domain_attach_iommu(si_domain, iommu);
2466 2467 2468 2469 2470 2471 2472
	}

	if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
		domain_exit(si_domain);
		return -EFAULT;
	}

2473 2474
	pr_debug("IOMMU: identity mapping domain is domain %d\n",
		 si_domain->id);
2475

2476 2477 2478
	if (hw)
		return 0;

2479
	for_each_online_node(nid) {
2480 2481 2482 2483 2484 2485 2486 2487 2488
		unsigned long start_pfn, end_pfn;
		int i;

		for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
			ret = iommu_domain_identity_map(si_domain,
					PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
			if (ret)
				return ret;
		}
2489 2490
	}

2491 2492 2493
	return 0;
}

2494
static int identity_mapping(struct device *dev)
2495 2496 2497 2498 2499 2500
{
	struct device_domain_info *info;

	if (likely(!iommu_identity_mapping))
		return 0;

2501
	info = dev->archdata.iommu;
2502 2503
	if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
		return (info->domain == si_domain);
2504 2505 2506 2507 2508

	return 0;
}

static int domain_add_dev_info(struct dmar_domain *domain,
2509
			       struct device *dev, int translation)
2510
{
2511
	struct dmar_domain *ndomain;
2512
	struct intel_iommu *iommu;
2513
	u8 bus, devfn;
2514
	int ret;
2515

2516
	iommu = device_to_iommu(dev, &bus, &devfn);
2517 2518 2519
	if (!iommu)
		return -ENODEV;

2520
	ndomain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
2521 2522
	if (ndomain != domain)
		return -EBUSY;
2523

2524
	ret = domain_context_mapping(domain, dev, translation);
2525
	if (ret) {
2526
		domain_remove_one_dev_info(domain, dev);
2527 2528 2529
		return ret;
	}

2530 2531 2532
	return 0;
}

2533
static bool device_has_rmrr(struct device *dev)
2534 2535
{
	struct dmar_rmrr_unit *rmrr;
2536
	struct device *tmp;
2537 2538
	int i;

2539
	rcu_read_lock();
2540
	for_each_rmrr_units(rmrr) {
2541 2542 2543 2544 2545 2546
		/*
		 * Return TRUE if this RMRR contains the device that
		 * is passed in.
		 */
		for_each_active_dev_scope(rmrr->devices,
					  rmrr->devices_cnt, i, tmp)
2547
			if (tmp == dev) {
2548
				rcu_read_unlock();
2549
				return true;
2550
			}
2551
	}
2552
	rcu_read_unlock();
2553 2554 2555
	return false;
}

2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572
/*
 * There are a couple cases where we need to restrict the functionality of
 * devices associated with RMRRs.  The first is when evaluating a device for
 * identity mapping because problems exist when devices are moved in and out
 * of domains and their respective RMRR information is lost.  This means that
 * a device with associated RMRRs will never be in a "passthrough" domain.
 * The second is use of the device through the IOMMU API.  This interface
 * expects to have full control of the IOVA space for the device.  We cannot
 * satisfy both the requirement that RMRR access is maintained and have an
 * unencumbered IOVA space.  We also have no ability to quiesce the device's
 * use of the RMRR space or even inform the IOMMU API user of the restriction.
 * We therefore prevent devices associated with an RMRR from participating in
 * the IOMMU API, which eliminates them from device assignment.
 *
 * In both cases we assume that PCI USB devices with RMRRs have them largely
 * for historical reasons and that the RMRR space is not actively used post
 * boot.  This exclusion may change if vendors begin to abuse it.
2573 2574 2575 2576
 *
 * The same exception is made for graphics devices, with the requirement that
 * any use of the RMRR regions will be torn down before assigning the device
 * to a guest.
2577 2578 2579 2580 2581 2582 2583 2584 2585
 */
static bool device_is_rmrr_locked(struct device *dev)
{
	if (!device_has_rmrr(dev))
		return false;

	if (dev_is_pci(dev)) {
		struct pci_dev *pdev = to_pci_dev(dev);

2586
		if (IS_USB_DEVICE(pdev) || IS_GFX_DEVICE(pdev))
2587 2588 2589 2590 2591 2592
			return false;
	}

	return true;
}

2593
static int iommu_should_identity_map(struct device *dev, int startup)
2594
{
2595

2596 2597
	if (dev_is_pci(dev)) {
		struct pci_dev *pdev = to_pci_dev(dev);
2598

2599
		if (device_is_rmrr_locked(dev))
2600
			return 0;
2601

2602 2603
		if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
			return 1;
2604

2605 2606
		if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
			return 1;
2607

2608
		if (!(iommu_identity_mapping & IDENTMAP_ALL))
2609
			return 0;
2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633

		/*
		 * We want to start off with all devices in the 1:1 domain, and
		 * take them out later if we find they can't access all of memory.
		 *
		 * However, we can't do this for PCI devices behind bridges,
		 * because all PCI devices behind the same bridge will end up
		 * with the same source-id on their transactions.
		 *
		 * Practically speaking, we can't change things around for these
		 * devices at run-time, because we can't be sure there'll be no
		 * DMA transactions in flight for any of their siblings.
		 *
		 * So PCI devices (unless they're on the root bus) as well as
		 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
		 * the 1:1 domain, just in _case_ one of their siblings turns out
		 * not to be able to map all of memory.
		 */
		if (!pci_is_pcie(pdev)) {
			if (!pci_is_root_bus(pdev->bus))
				return 0;
			if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
				return 0;
		} else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
2634
			return 0;
2635 2636 2637 2638
	} else {
		if (device_has_rmrr(dev))
			return 0;
	}
2639

2640
	/*
2641
	 * At boot time, we don't yet know if devices will be 64-bit capable.
2642
	 * Assume that they will — if they turn out not to be, then we can
2643 2644
	 * take them out of the 1:1 domain later.
	 */
2645 2646 2647 2648 2649
	if (!startup) {
		/*
		 * If the device's dma_mask is less than the system's memory
		 * size then this is not a candidate for identity mapping.
		 */
2650
		u64 dma_mask = *dev->dma_mask;
2651

2652 2653 2654
		if (dev->coherent_dma_mask &&
		    dev->coherent_dma_mask < dma_mask)
			dma_mask = dev->coherent_dma_mask;
2655

2656
		return dma_mask >= dma_get_required_mask(dev);
2657
	}
2658 2659 2660 2661

	return 1;
}

2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682
static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw)
{
	int ret;

	if (!iommu_should_identity_map(dev, 1))
		return 0;

	ret = domain_add_dev_info(si_domain, dev,
				  hw ? CONTEXT_TT_PASS_THROUGH :
				       CONTEXT_TT_MULTI_LEVEL);
	if (!ret)
		pr_info("IOMMU: %s identity mapping for device %s\n",
			hw ? "hardware" : "software", dev_name(dev));
	else if (ret == -ENODEV)
		/* device not associated with an iommu */
		ret = 0;

	return ret;
}


2683
static int __init iommu_prepare_static_identity_mapping(int hw)
2684 2685
{
	struct pci_dev *pdev = NULL;
2686 2687 2688 2689 2690
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;
	struct device *dev;
	int i;
	int ret = 0;
2691

2692
	ret = si_domain_init(hw);
2693 2694 2695 2696
	if (ret)
		return -EFAULT;

	for_each_pci_dev(pdev) {
2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715
		ret = dev_prepare_static_identity_mapping(&pdev->dev, hw);
		if (ret)
			return ret;
	}

	for_each_active_iommu(iommu, drhd)
		for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) {
			struct acpi_device_physical_node *pn;
			struct acpi_device *adev;

			if (dev->bus != &acpi_bus_type)
				continue;
				
			adev= to_acpi_device(dev);
			mutex_lock(&adev->physical_node_lock);
			list_for_each_entry(pn, &adev->physical_node_list, node) {
				ret = dev_prepare_static_identity_mapping(pn->dev, hw);
				if (ret)
					break;
2716
			}
2717 2718 2719
			mutex_unlock(&adev->physical_node_lock);
			if (ret)
				return ret;
2720
		}
2721 2722 2723 2724

	return 0;
}

2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759
static void intel_iommu_init_qi(struct intel_iommu *iommu)
{
	/*
	 * Start from the sane iommu hardware state.
	 * If the queued invalidation is already initialized by us
	 * (for example, while enabling interrupt-remapping) then
	 * we got the things already rolling from a sane state.
	 */
	if (!iommu->qi) {
		/*
		 * Clear any previous faults.
		 */
		dmar_fault(-1, iommu);
		/*
		 * Disable queued invalidation if supported and already enabled
		 * before OS handover.
		 */
		dmar_disable_qi(iommu);
	}

	if (dmar_enable_qi(iommu)) {
		/*
		 * Queued Invalidate not enabled, use Register Based Invalidate
		 */
		iommu->flush.flush_context = __iommu_flush_context;
		iommu->flush.flush_iotlb = __iommu_flush_iotlb;
		pr_info("IOMMU: %s using Register based invalidation\n",
			iommu->name);
	} else {
		iommu->flush.flush_context = qi_flush_context;
		iommu->flush.flush_iotlb = qi_flush_iotlb;
		pr_info("IOMMU: %s using Queued invalidation\n", iommu->name);
	}
}

2760
static int __init init_dmars(void)
2761 2762 2763
{
	struct dmar_drhd_unit *drhd;
	struct dmar_rmrr_unit *rmrr;
2764
	struct device *dev;
2765
	struct intel_iommu *iommu;
2766
	int i, ret;
2767

2768 2769 2770 2771 2772 2773 2774
	/*
	 * for each drhd
	 *    allocate root
	 *    initialize and program root entry to not present
	 * endfor
	 */
	for_each_drhd_unit(drhd) {
M
mark gross 已提交
2775 2776 2777 2778 2779
		/*
		 * lock not needed as this is only incremented in the single
		 * threaded kernel __init code path all other access are read
		 * only
		 */
2780
		if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) {
2781 2782 2783 2784
			g_num_of_iommus++;
			continue;
		}
		printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
2785
			  DMAR_UNITS_SUPPORTED);
M
mark gross 已提交
2786 2787
	}

2788 2789 2790 2791
	/* Preallocate enough resources for IOMMU hot-addition */
	if (g_num_of_iommus < DMAR_UNITS_SUPPORTED)
		g_num_of_iommus = DMAR_UNITS_SUPPORTED;

W
Weidong Han 已提交
2792 2793 2794 2795 2796 2797 2798 2799
	g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
			GFP_KERNEL);
	if (!g_iommus) {
		printk(KERN_ERR "Allocating global iommu array failed\n");
		ret = -ENOMEM;
		goto error;
	}

2800 2801 2802
	deferred_flush = kzalloc(g_num_of_iommus *
		sizeof(struct deferred_flush_tables), GFP_KERNEL);
	if (!deferred_flush) {
M
mark gross 已提交
2803
		ret = -ENOMEM;
2804
		goto free_g_iommus;
M
mark gross 已提交
2805 2806
	}

2807
	for_each_active_iommu(iommu, drhd) {
W
Weidong Han 已提交
2808
		g_iommus[iommu->seq_id] = iommu;
2809

2810 2811
		ret = iommu_init_domains(iommu);
		if (ret)
2812
			goto free_iommu;
2813

2814 2815 2816
		/*
		 * TBD:
		 * we could share the same root & context tables
L
Lucas De Marchi 已提交
2817
		 * among all IOMMU's. Need to Split it later.
2818 2819
		 */
		ret = iommu_alloc_root_entry(iommu);
2820
		if (ret)
2821
			goto free_iommu;
F
Fenghua Yu 已提交
2822
		if (!ecap_pass_through(iommu->ecap))
2823
			hw_pass_through = 0;
2824 2825
	}

2826 2827
	for_each_active_iommu(iommu, drhd)
		intel_iommu_init_qi(iommu);
2828

2829
	if (iommu_pass_through)
2830 2831
		iommu_identity_mapping |= IDENTMAP_ALL;

2832
#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
2833
	iommu_identity_mapping |= IDENTMAP_GFX;
2834
#endif
2835 2836 2837

	check_tylersburg_isoch();

2838
	/*
2839 2840 2841
	 * If pass through is not set or not enabled, setup context entries for
	 * identity mappings for rmrr, gfx, and isa and may fall back to static
	 * identity mapping if iommu_identity_mapping is set.
2842
	 */
2843 2844
	if (iommu_identity_mapping) {
		ret = iommu_prepare_static_identity_mapping(hw_pass_through);
F
Fenghua Yu 已提交
2845
		if (ret) {
2846
			printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
2847
			goto free_iommu;
2848 2849 2850
		}
	}
	/*
2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862
	 * For each rmrr
	 *   for each dev attached to rmrr
	 *   do
	 *     locate drhd for dev, alloc domain for dev
	 *     allocate free domain
	 *     allocate page table entries for rmrr
	 *     if context not allocated for bus
	 *           allocate and init context
	 *           set present in root table for this bus
	 *     init context with domain, translation etc
	 *    endfor
	 * endfor
2863
	 */
2864 2865
	printk(KERN_INFO "IOMMU: Setting RMRR:\n");
	for_each_rmrr_units(rmrr) {
2866 2867
		/* some BIOS lists non-exist devices in DMAR table. */
		for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
2868
					  i, dev) {
2869
			ret = iommu_prepare_rmrr_dev(rmrr, dev);
2870 2871 2872
			if (ret)
				printk(KERN_ERR
				       "IOMMU: mapping reserved region failed\n");
2873
		}
F
Fenghua Yu 已提交
2874
	}
2875

2876 2877
	iommu_prepare_isa();

2878 2879 2880 2881 2882 2883 2884
	/*
	 * for each drhd
	 *   enable fault log
	 *   global invalidate context cache
	 *   global invalidate iotlb
	 *   enable translation
	 */
2885
	for_each_iommu(iommu, drhd) {
2886 2887 2888 2889 2890 2891
		if (drhd->ignored) {
			/*
			 * we always have to disable PMRs or DMA may fail on
			 * this device
			 */
			if (force_on)
2892
				iommu_disable_protect_mem_regions(iommu);
2893
			continue;
2894
		}
2895 2896 2897

		iommu_flush_write_buffer(iommu);

2898 2899
		ret = dmar_set_interrupt(iommu);
		if (ret)
2900
			goto free_iommu;
2901

2902 2903
		iommu_set_root_entry(iommu);

2904
		iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2905
		iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2906
		iommu_enable_translation(iommu);
2907
		iommu_disable_protect_mem_regions(iommu);
2908 2909 2910
	}

	return 0;
2911 2912

free_iommu:
2913 2914
	for_each_active_iommu(iommu, drhd) {
		disable_dmar_iommu(iommu);
2915
		free_dmar_iommu(iommu);
2916
	}
2917
	kfree(deferred_flush);
2918
free_g_iommus:
W
Weidong Han 已提交
2919
	kfree(g_iommus);
2920
error:
2921 2922 2923
	return ret;
}

2924
/* This takes a number of _MM_ pages, not VTD pages */
2925 2926 2927
static struct iova *intel_alloc_iova(struct device *dev,
				     struct dmar_domain *domain,
				     unsigned long nrpages, uint64_t dma_mask)
2928 2929 2930
{
	struct iova *iova = NULL;

2931 2932 2933 2934
	/* Restrict dma_mask to the width that the iommu can handle */
	dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);

	if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2935 2936
		/*
		 * First try to allocate an io virtual address in
2937
		 * DMA_BIT_MASK(32) and if that fails then try allocating
J
Joe Perches 已提交
2938
		 * from higher range
2939
		 */
2940 2941 2942 2943 2944 2945 2946 2947
		iova = alloc_iova(&domain->iovad, nrpages,
				  IOVA_PFN(DMA_BIT_MASK(32)), 1);
		if (iova)
			return iova;
	}
	iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
	if (unlikely(!iova)) {
		printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2948
		       nrpages, dev_name(dev));
2949 2950 2951 2952 2953 2954
		return NULL;
	}

	return iova;
}

2955
static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
2956 2957 2958 2959
{
	struct dmar_domain *domain;
	int ret;

2960
	domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2961
	if (!domain) {
2962 2963
		printk(KERN_ERR "Allocating domain for %s failed",
		       dev_name(dev));
A
Al Viro 已提交
2964
		return NULL;
2965 2966 2967
	}

	/* make sure context mapping is ok */
2968 2969
	if (unlikely(!domain_context_mapped(dev))) {
		ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
2970
		if (ret) {
2971 2972
			printk(KERN_ERR "Domain context map for %s failed",
			       dev_name(dev));
A
Al Viro 已提交
2973
			return NULL;
2974
		}
2975 2976
	}

2977 2978 2979
	return domain;
}

2980
static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
2981 2982 2983 2984
{
	struct device_domain_info *info;

	/* No lock here, assumes no domain exit in normal case */
2985
	info = dev->archdata.iommu;
2986 2987 2988 2989 2990 2991
	if (likely(info))
		return info->domain;

	return __get_valid_domain_for_dev(dev);
}

2992
/* Check if the dev needs to go through non-identity map and unmap process.*/
2993
static int iommu_no_mapping(struct device *dev)
2994 2995 2996
{
	int found;

2997
	if (iommu_dummy(dev))
2998 2999
		return 1;

3000
	if (!iommu_identity_mapping)
3001
		return 0;
3002

3003
	found = identity_mapping(dev);
3004
	if (found) {
3005
		if (iommu_should_identity_map(dev, 0))
3006 3007 3008 3009 3010 3011
			return 1;
		else {
			/*
			 * 32 bit DMA is removed from si_domain and fall back
			 * to non-identity mapping.
			 */
3012
			domain_remove_one_dev_info(si_domain, dev);
3013
			printk(KERN_INFO "32bit %s uses non-identity mapping\n",
3014
			       dev_name(dev));
3015 3016 3017 3018 3019 3020 3021
			return 0;
		}
	} else {
		/*
		 * In case of a detached 64 bit DMA device from vm, the device
		 * is put into si_domain for identity mapping.
		 */
3022
		if (iommu_should_identity_map(dev, 0)) {
3023
			int ret;
3024
			ret = domain_add_dev_info(si_domain, dev,
3025 3026 3027
						  hw_pass_through ?
						  CONTEXT_TT_PASS_THROUGH :
						  CONTEXT_TT_MULTI_LEVEL);
3028 3029
			if (!ret) {
				printk(KERN_INFO "64bit %s uses identity mapping\n",
3030
				       dev_name(dev));
3031 3032 3033 3034 3035
				return 1;
			}
		}
	}

3036
	return 0;
3037 3038
}

3039
static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
3040
				     size_t size, int dir, u64 dma_mask)
3041 3042
{
	struct dmar_domain *domain;
F
Fenghua Yu 已提交
3043
	phys_addr_t start_paddr;
3044 3045
	struct iova *iova;
	int prot = 0;
I
Ingo Molnar 已提交
3046
	int ret;
3047
	struct intel_iommu *iommu;
3048
	unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
3049 3050

	BUG_ON(dir == DMA_NONE);
3051

3052
	if (iommu_no_mapping(dev))
I
Ingo Molnar 已提交
3053
		return paddr;
3054

3055
	domain = get_valid_domain_for_dev(dev);
3056 3057 3058
	if (!domain)
		return 0;

3059
	iommu = domain_get_iommu(domain);
3060
	size = aligned_nrpages(paddr, size);
3061

3062
	iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask);
3063 3064 3065
	if (!iova)
		goto error;

3066 3067 3068 3069 3070
	/*
	 * Check if DMAR supports zero-length reads on write only
	 * mappings..
	 */
	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3071
			!cap_zlr(iommu->cap))
3072 3073 3074 3075
		prot |= DMA_PTE_READ;
	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
		prot |= DMA_PTE_WRITE;
	/*
I
Ingo Molnar 已提交
3076
	 * paddr - (paddr + size) might be partial page, we should map the whole
3077
	 * page.  Note: if two part of one page are separately mapped, we
I
Ingo Molnar 已提交
3078
	 * might have two guest_addr mapping to the same host paddr, but this
3079 3080
	 * is not a big problem
	 */
3081
	ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
3082
				 mm_to_dma_pfn(paddr_pfn), size, prot);
3083 3084 3085
	if (ret)
		goto error;

3086 3087
	/* it's a non-present to present mapping. Only flush if caching mode */
	if (cap_caching_mode(iommu->cap))
3088
		iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1);
3089
	else
3090
		iommu_flush_write_buffer(iommu);
3091

3092 3093 3094
	start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
	start_paddr += paddr & ~PAGE_MASK;
	return start_paddr;
3095 3096

error:
3097 3098
	if (iova)
		__free_iova(&domain->iovad, iova);
3099
	printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
3100
		dev_name(dev), size, (unsigned long long)paddr, dir);
3101 3102 3103
	return 0;
}

3104 3105 3106 3107
static dma_addr_t intel_map_page(struct device *dev, struct page *page,
				 unsigned long offset, size_t size,
				 enum dma_data_direction dir,
				 struct dma_attrs *attrs)
3108
{
3109
	return __intel_map_single(dev, page_to_phys(page) + offset, size,
3110
				  dir, *dev->dma_mask);
3111 3112
}

M
mark gross 已提交
3113 3114
static void flush_unmaps(void)
{
3115
	int i, j;
M
mark gross 已提交
3116 3117 3118 3119 3120

	timer_on = 0;

	/* just flush them all */
	for (i = 0; i < g_num_of_iommus; i++) {
3121 3122 3123
		struct intel_iommu *iommu = g_iommus[i];
		if (!iommu)
			continue;
3124

3125 3126 3127
		if (!deferred_flush[i].next)
			continue;

3128 3129 3130
		/* In caching mode, global flushes turn emulation expensive */
		if (!cap_caching_mode(iommu->cap))
			iommu->flush.flush_iotlb(iommu, 0, 0, 0,
Y
Yu Zhao 已提交
3131
					 DMA_TLB_GLOBAL_FLUSH);
3132
		for (j = 0; j < deferred_flush[i].next; j++) {
Y
Yu Zhao 已提交
3133 3134
			unsigned long mask;
			struct iova *iova = deferred_flush[i].iova[j];
3135 3136 3137 3138 3139
			struct dmar_domain *domain = deferred_flush[i].domain[j];

			/* On real hardware multiple invalidations are expensive */
			if (cap_caching_mode(iommu->cap))
				iommu_flush_iotlb_psi(iommu, domain->id,
3140
					iova->pfn_lo, iova_size(iova),
3141
					!deferred_flush[i].freelist[j], 0);
3142
			else {
3143
				mask = ilog2(mm_to_dma_pfn(iova_size(iova)));
3144 3145 3146
				iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
						(uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
			}
Y
Yu Zhao 已提交
3147
			__free_iova(&deferred_flush[i].domain[j]->iovad, iova);
3148 3149
			if (deferred_flush[i].freelist[j])
				dma_free_pagelist(deferred_flush[i].freelist[j]);
3150
		}
3151
		deferred_flush[i].next = 0;
M
mark gross 已提交
3152 3153 3154 3155 3156 3157 3158
	}

	list_size = 0;
}

static void flush_unmaps_timeout(unsigned long data)
{
3159 3160 3161
	unsigned long flags;

	spin_lock_irqsave(&async_umap_flush_lock, flags);
M
mark gross 已提交
3162
	flush_unmaps();
3163
	spin_unlock_irqrestore(&async_umap_flush_lock, flags);
M
mark gross 已提交
3164 3165
}

3166
static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
M
mark gross 已提交
3167 3168
{
	unsigned long flags;
3169
	int next, iommu_id;
3170
	struct intel_iommu *iommu;
M
mark gross 已提交
3171 3172

	spin_lock_irqsave(&async_umap_flush_lock, flags);
3173 3174 3175
	if (list_size == HIGH_WATER_MARK)
		flush_unmaps();

3176 3177
	iommu = domain_get_iommu(dom);
	iommu_id = iommu->seq_id;
3178

3179 3180 3181
	next = deferred_flush[iommu_id].next;
	deferred_flush[iommu_id].domain[next] = dom;
	deferred_flush[iommu_id].iova[next] = iova;
3182
	deferred_flush[iommu_id].freelist[next] = freelist;
3183
	deferred_flush[iommu_id].next++;
M
mark gross 已提交
3184 3185 3186 3187 3188 3189 3190 3191 3192

	if (!timer_on) {
		mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
		timer_on = 1;
	}
	list_size++;
	spin_unlock_irqrestore(&async_umap_flush_lock, flags);
}

3193
static void intel_unmap(struct device *dev, dma_addr_t dev_addr)
3194
{
3195
	struct dmar_domain *domain;
3196
	unsigned long start_pfn, last_pfn;
3197
	struct iova *iova;
3198
	struct intel_iommu *iommu;
3199
	struct page *freelist;
3200

3201
	if (iommu_no_mapping(dev))
3202
		return;
3203

3204
	domain = find_domain(dev);
3205 3206
	BUG_ON(!domain);

3207 3208
	iommu = domain_get_iommu(domain);

3209
	iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
3210 3211
	if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
		      (unsigned long long)dev_addr))
3212 3213
		return;

3214 3215
	start_pfn = mm_to_dma_pfn(iova->pfn_lo);
	last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
3216

3217
	pr_debug("Device %s unmapping: pfn %lx-%lx\n",
3218
		 dev_name(dev), start_pfn, last_pfn);
3219

3220
	freelist = domain_unmap(domain, start_pfn, last_pfn);
3221

M
mark gross 已提交
3222
	if (intel_iommu_strict) {
3223
		iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
3224
				      last_pfn - start_pfn + 1, !freelist, 0);
M
mark gross 已提交
3225 3226
		/* free iova */
		__free_iova(&domain->iovad, iova);
3227
		dma_free_pagelist(freelist);
M
mark gross 已提交
3228
	} else {
3229
		add_unmap(domain, iova, freelist);
M
mark gross 已提交
3230 3231 3232 3233 3234
		/*
		 * queue up the release of the unmap to save the 1/6th of the
		 * cpu used up by the iotlb flush operation...
		 */
	}
3235 3236
}

3237 3238 3239 3240 3241 3242 3243
static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
			     size_t size, enum dma_data_direction dir,
			     struct dma_attrs *attrs)
{
	intel_unmap(dev, dev_addr);
}

3244
static void *intel_alloc_coherent(struct device *dev, size_t size,
3245 3246
				  dma_addr_t *dma_handle, gfp_t flags,
				  struct dma_attrs *attrs)
3247
{
A
Akinobu Mita 已提交
3248
	struct page *page = NULL;
3249 3250
	int order;

F
Fenghua Yu 已提交
3251
	size = PAGE_ALIGN(size);
3252
	order = get_order(size);
3253

3254
	if (!iommu_no_mapping(dev))
3255
		flags &= ~(GFP_DMA | GFP_DMA32);
3256 3257
	else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) {
		if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
3258 3259 3260 3261
			flags |= GFP_DMA;
		else
			flags |= GFP_DMA32;
	}
3262

A
Akinobu Mita 已提交
3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276
	if (flags & __GFP_WAIT) {
		unsigned int count = size >> PAGE_SHIFT;

		page = dma_alloc_from_contiguous(dev, count, order);
		if (page && iommu_no_mapping(dev) &&
		    page_to_phys(page) + size > dev->coherent_dma_mask) {
			dma_release_from_contiguous(dev, page, count);
			page = NULL;
		}
	}

	if (!page)
		page = alloc_pages(flags, order);
	if (!page)
3277
		return NULL;
A
Akinobu Mita 已提交
3278
	memset(page_address(page), 0, size);
3279

A
Akinobu Mita 已提交
3280
	*dma_handle = __intel_map_single(dev, page_to_phys(page), size,
3281
					 DMA_BIDIRECTIONAL,
3282
					 dev->coherent_dma_mask);
3283
	if (*dma_handle)
A
Akinobu Mita 已提交
3284 3285 3286 3287
		return page_address(page);
	if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
		__free_pages(page, order);

3288 3289 3290
	return NULL;
}

3291
static void intel_free_coherent(struct device *dev, size_t size, void *vaddr,
3292
				dma_addr_t dma_handle, struct dma_attrs *attrs)
3293 3294
{
	int order;
A
Akinobu Mita 已提交
3295
	struct page *page = virt_to_page(vaddr);
3296

F
Fenghua Yu 已提交
3297
	size = PAGE_ALIGN(size);
3298 3299
	order = get_order(size);

3300
	intel_unmap(dev, dma_handle);
A
Akinobu Mita 已提交
3301 3302
	if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
		__free_pages(page, order);
3303 3304
}

3305
static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist,
3306 3307
			   int nelems, enum dma_data_direction dir,
			   struct dma_attrs *attrs)
3308
{
3309
	intel_unmap(dev, sglist[0].dma_address);
3310 3311 3312
}

static int intel_nontranslate_map_sg(struct device *hddev,
F
FUJITA Tomonori 已提交
3313
	struct scatterlist *sglist, int nelems, int dir)
3314 3315
{
	int i;
F
FUJITA Tomonori 已提交
3316
	struct scatterlist *sg;
3317

F
FUJITA Tomonori 已提交
3318
	for_each_sg(sglist, sg, nelems, i) {
F
FUJITA Tomonori 已提交
3319
		BUG_ON(!sg_page(sg));
3320
		sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
F
FUJITA Tomonori 已提交
3321
		sg->dma_length = sg->length;
3322 3323 3324 3325
	}
	return nelems;
}

3326
static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems,
3327
			enum dma_data_direction dir, struct dma_attrs *attrs)
3328 3329 3330
{
	int i;
	struct dmar_domain *domain;
3331 3332 3333 3334
	size_t size = 0;
	int prot = 0;
	struct iova *iova = NULL;
	int ret;
F
FUJITA Tomonori 已提交
3335
	struct scatterlist *sg;
3336
	unsigned long start_vpfn;
3337
	struct intel_iommu *iommu;
3338 3339

	BUG_ON(dir == DMA_NONE);
3340 3341
	if (iommu_no_mapping(dev))
		return intel_nontranslate_map_sg(dev, sglist, nelems, dir);
3342

3343
	domain = get_valid_domain_for_dev(dev);
3344 3345 3346
	if (!domain)
		return 0;

3347 3348
	iommu = domain_get_iommu(domain);

3349
	for_each_sg(sglist, sg, nelems, i)
3350
		size += aligned_nrpages(sg->offset, sg->length);
3351

3352 3353
	iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size),
				*dev->dma_mask);
3354
	if (!iova) {
F
FUJITA Tomonori 已提交
3355
		sglist->dma_length = 0;
3356 3357 3358 3359 3360 3361 3362 3363
		return 0;
	}

	/*
	 * Check if DMAR supports zero-length reads on write only
	 * mappings..
	 */
	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
3364
			!cap_zlr(iommu->cap))
3365 3366 3367 3368
		prot |= DMA_PTE_READ;
	if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
		prot |= DMA_PTE_WRITE;

3369
	start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
3370

3371
	ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
3372 3373 3374 3375 3376
	if (unlikely(ret)) {
		dma_pte_free_pagetable(domain, start_vpfn,
				       start_vpfn + size - 1);
		__free_iova(&domain->iovad, iova);
		return 0;
3377 3378
	}

3379 3380
	/* it's a non-present to present mapping. Only flush if caching mode */
	if (cap_caching_mode(iommu->cap))
3381
		iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1);
3382
	else
3383
		iommu_flush_write_buffer(iommu);
3384

3385 3386 3387
	return nelems;
}

3388 3389 3390 3391 3392
static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
	return !dma_addr;
}

3393
struct dma_map_ops intel_dma_ops = {
3394 3395
	.alloc = intel_alloc_coherent,
	.free = intel_free_coherent,
3396 3397
	.map_sg = intel_map_sg,
	.unmap_sg = intel_unmap_sg,
3398 3399
	.map_page = intel_map_page,
	.unmap_page = intel_unmap_page,
3400
	.mapping_error = intel_mapping_error,
3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454
};

static inline int iommu_domain_cache_init(void)
{
	int ret = 0;

	iommu_domain_cache = kmem_cache_create("iommu_domain",
					 sizeof(struct dmar_domain),
					 0,
					 SLAB_HWCACHE_ALIGN,

					 NULL);
	if (!iommu_domain_cache) {
		printk(KERN_ERR "Couldn't create iommu_domain cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static inline int iommu_devinfo_cache_init(void)
{
	int ret = 0;

	iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
					 sizeof(struct device_domain_info),
					 0,
					 SLAB_HWCACHE_ALIGN,
					 NULL);
	if (!iommu_devinfo_cache) {
		printk(KERN_ERR "Couldn't create devinfo cache\n");
		ret = -ENOMEM;
	}

	return ret;
}

static int __init iommu_init_mempool(void)
{
	int ret;
	ret = iommu_iova_cache_init();
	if (ret)
		return ret;

	ret = iommu_domain_cache_init();
	if (ret)
		goto domain_error;

	ret = iommu_devinfo_cache_init();
	if (!ret)
		return ret;

	kmem_cache_destroy(iommu_domain_cache);
domain_error:
3455
	iommu_iova_cache_destroy();
3456 3457 3458 3459 3460 3461 3462 3463

	return -ENOMEM;
}

static void __init iommu_exit_mempool(void)
{
	kmem_cache_destroy(iommu_devinfo_cache);
	kmem_cache_destroy(iommu_domain_cache);
3464
	iommu_iova_cache_destroy();
3465 3466
}

3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494
static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
{
	struct dmar_drhd_unit *drhd;
	u32 vtbar;
	int rc;

	/* We know that this device on this chipset has its own IOMMU.
	 * If we find it under a different IOMMU, then the BIOS is lying
	 * to us. Hope that the IOMMU for this device is actually
	 * disabled, and it needs no translation...
	 */
	rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
	if (rc) {
		/* "can't" happen */
		dev_info(&pdev->dev, "failed to run vt-d quirk\n");
		return;
	}
	vtbar &= 0xffff0000;

	/* we know that the this iommu should be at offset 0xa000 from vtbar */
	drhd = dmar_find_matched_drhd_unit(pdev);
	if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
			    TAINT_FIRMWARE_WORKAROUND,
			    "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
		pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
}
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);

3495 3496 3497
static void __init init_no_remapping_devices(void)
{
	struct dmar_drhd_unit *drhd;
3498
	struct device *dev;
3499
	int i;
3500 3501 3502

	for_each_drhd_unit(drhd) {
		if (!drhd->include_all) {
3503 3504 3505
			for_each_active_dev_scope(drhd->devices,
						  drhd->devices_cnt, i, dev)
				break;
3506
			/* ignore DMAR unit if no devices exist */
3507 3508 3509 3510 3511
			if (i == drhd->devices_cnt)
				drhd->ignored = 1;
		}
	}

3512 3513
	for_each_active_drhd_unit(drhd) {
		if (drhd->include_all)
3514 3515
			continue;

3516 3517
		for_each_active_dev_scope(drhd->devices,
					  drhd->devices_cnt, i, dev)
3518
			if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
3519 3520 3521 3522
				break;
		if (i < drhd->devices_cnt)
			continue;

3523 3524 3525 3526 3527 3528
		/* This IOMMU has *only* gfx devices. Either bypass it or
		   set the gfx_mapped flag, as appropriate */
		if (dmar_map_gfx) {
			intel_iommu_gfx_mapped = 1;
		} else {
			drhd->ignored = 1;
3529 3530
			for_each_active_dev_scope(drhd->devices,
						  drhd->devices_cnt, i, dev)
3531
				dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3532 3533 3534 3535
		}
	}
}

3536 3537 3538 3539 3540 3541 3542 3543 3544 3545
#ifdef CONFIG_SUSPEND
static int init_iommu_hw(void)
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;

	for_each_active_iommu(iommu, drhd)
		if (iommu->qi)
			dmar_reenable_qi(iommu);

3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556
	for_each_iommu(iommu, drhd) {
		if (drhd->ignored) {
			/*
			 * we always have to disable PMRs or DMA may fail on
			 * this device
			 */
			if (force_on)
				iommu_disable_protect_mem_regions(iommu);
			continue;
		}
	
3557 3558 3559 3560 3561
		iommu_flush_write_buffer(iommu);

		iommu_set_root_entry(iommu);

		iommu->flush.flush_context(iommu, 0, 0, 0,
3562
					   DMA_CCMD_GLOBAL_INVL);
3563 3564
		iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
		iommu_enable_translation(iommu);
3565
		iommu_disable_protect_mem_regions(iommu);
3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577
	}

	return 0;
}

static void iommu_flush_all(void)
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu;

	for_each_active_iommu(iommu, drhd) {
		iommu->flush.flush_context(iommu, 0, 0, 0,
3578
					   DMA_CCMD_GLOBAL_INVL);
3579
		iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3580
					 DMA_TLB_GLOBAL_FLUSH);
3581 3582 3583
	}
}

3584
static int iommu_suspend(void)
3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	unsigned long flag;

	for_each_active_iommu(iommu, drhd) {
		iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
						 GFP_ATOMIC);
		if (!iommu->iommu_state)
			goto nomem;
	}

	iommu_flush_all();

	for_each_active_iommu(iommu, drhd) {
		iommu_disable_translation(iommu);

3602
		raw_spin_lock_irqsave(&iommu->register_lock, flag);
3603 3604 3605 3606 3607 3608 3609 3610 3611 3612

		iommu->iommu_state[SR_DMAR_FECTL_REG] =
			readl(iommu->reg + DMAR_FECTL_REG);
		iommu->iommu_state[SR_DMAR_FEDATA_REG] =
			readl(iommu->reg + DMAR_FEDATA_REG);
		iommu->iommu_state[SR_DMAR_FEADDR_REG] =
			readl(iommu->reg + DMAR_FEADDR_REG);
		iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
			readl(iommu->reg + DMAR_FEUADDR_REG);

3613
		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3614 3615 3616 3617 3618 3619 3620 3621 3622 3623
	}
	return 0;

nomem:
	for_each_active_iommu(iommu, drhd)
		kfree(iommu->iommu_state);

	return -ENOMEM;
}

3624
static void iommu_resume(void)
3625 3626 3627 3628 3629 3630
{
	struct dmar_drhd_unit *drhd;
	struct intel_iommu *iommu = NULL;
	unsigned long flag;

	if (init_iommu_hw()) {
3631 3632 3633 3634
		if (force_on)
			panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
		else
			WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3635
		return;
3636 3637 3638 3639
	}

	for_each_active_iommu(iommu, drhd) {

3640
		raw_spin_lock_irqsave(&iommu->register_lock, flag);
3641 3642 3643 3644 3645 3646 3647 3648 3649 3650

		writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
			iommu->reg + DMAR_FECTL_REG);
		writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
			iommu->reg + DMAR_FEDATA_REG);
		writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
			iommu->reg + DMAR_FEADDR_REG);
		writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
			iommu->reg + DMAR_FEUADDR_REG);

3651
		raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
3652 3653 3654 3655 3656 3657
	}

	for_each_active_iommu(iommu, drhd)
		kfree(iommu->iommu_state);
}

3658
static struct syscore_ops iommu_syscore_ops = {
3659 3660 3661 3662
	.resume		= iommu_resume,
	.suspend	= iommu_suspend,
};

3663
static void __init init_iommu_pm_ops(void)
3664
{
3665
	register_syscore_ops(&iommu_syscore_ops);
3666 3667 3668
}

#else
3669
static inline void init_iommu_pm_ops(void) {}
3670 3671
#endif	/* CONFIG_PM */

3672

3673
int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg)
3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685
{
	struct acpi_dmar_reserved_memory *rmrr;
	struct dmar_rmrr_unit *rmrru;

	rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
	if (!rmrru)
		return -ENOMEM;

	rmrru->hdr = header;
	rmrr = (struct acpi_dmar_reserved_memory *)header;
	rmrru->base_address = rmrr->base_address;
	rmrru->end_address = rmrr->end_address;
3686 3687 3688 3689 3690 3691 3692
	rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
				((void *)rmrr) + rmrr->header.length,
				&rmrru->devices_cnt);
	if (rmrru->devices_cnt && rmrru->devices == NULL) {
		kfree(rmrru);
		return -ENOMEM;
	}
3693

3694
	list_add(&rmrru->list, &dmar_rmrr_units);
3695

3696
	return 0;
3697 3698
}

3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717
static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr)
{
	struct dmar_atsr_unit *atsru;
	struct acpi_dmar_atsr *tmp;

	list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
		tmp = (struct acpi_dmar_atsr *)atsru->hdr;
		if (atsr->segment != tmp->segment)
			continue;
		if (atsr->header.length != tmp->header.length)
			continue;
		if (memcmp(atsr, tmp, atsr->header.length) == 0)
			return atsru;
	}

	return NULL;
}

int dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg)
3718 3719 3720 3721
{
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

3722 3723 3724
	if (system_state != SYSTEM_BOOTING && !intel_iommu_enabled)
		return 0;

3725
	atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3726 3727 3728 3729 3730
	atsru = dmar_find_atsr(atsr);
	if (atsru)
		return 0;

	atsru = kzalloc(sizeof(*atsru) + hdr->length, GFP_KERNEL);
3731 3732 3733
	if (!atsru)
		return -ENOMEM;

3734 3735 3736 3737 3738 3739 3740
	/*
	 * If memory is allocated from slab by ACPI _DSM method, we need to
	 * copy the memory content because the memory buffer will be freed
	 * on return.
	 */
	atsru->hdr = (void *)(atsru + 1);
	memcpy(atsru->hdr, hdr, hdr->length);
3741
	atsru->include_all = atsr->flags & 0x1;
3742 3743 3744 3745 3746 3747 3748 3749 3750
	if (!atsru->include_all) {
		atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
				(void *)atsr + atsr->header.length,
				&atsru->devices_cnt);
		if (atsru->devices_cnt && atsru->devices == NULL) {
			kfree(atsru);
			return -ENOMEM;
		}
	}
3751

3752
	list_add_rcu(&atsru->list, &dmar_atsr_units);
3753 3754 3755 3756

	return 0;
}

3757 3758 3759 3760 3761 3762
static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
{
	dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
	kfree(atsru);
}

3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798
int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg)
{
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	atsr = container_of(hdr, struct acpi_dmar_atsr, header);
	atsru = dmar_find_atsr(atsr);
	if (atsru) {
		list_del_rcu(&atsru->list);
		synchronize_rcu();
		intel_iommu_free_atsr(atsru);
	}

	return 0;
}

int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg)
{
	int i;
	struct device *dev;
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	atsr = container_of(hdr, struct acpi_dmar_atsr, header);
	atsru = dmar_find_atsr(atsr);
	if (!atsru)
		return 0;

	if (!atsru->include_all && atsru->devices && atsru->devices_cnt)
		for_each_active_dev_scope(atsru->devices, atsru->devices_cnt,
					  i, dev)
			return -EBUSY;

	return 0;
}

3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874
static int intel_iommu_add(struct dmar_drhd_unit *dmaru)
{
	int sp, ret = 0;
	struct intel_iommu *iommu = dmaru->iommu;

	if (g_iommus[iommu->seq_id])
		return 0;

	if (hw_pass_through && !ecap_pass_through(iommu->ecap)) {
		pr_warn("IOMMU: %s doesn't support hardware pass through.\n",
			iommu->name);
		return -ENXIO;
	}
	if (!ecap_sc_support(iommu->ecap) &&
	    domain_update_iommu_snooping(iommu)) {
		pr_warn("IOMMU: %s doesn't support snooping.\n",
			iommu->name);
		return -ENXIO;
	}
	sp = domain_update_iommu_superpage(iommu) - 1;
	if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) {
		pr_warn("IOMMU: %s doesn't support large page.\n",
			iommu->name);
		return -ENXIO;
	}

	/*
	 * Disable translation if already enabled prior to OS handover.
	 */
	if (iommu->gcmd & DMA_GCMD_TE)
		iommu_disable_translation(iommu);

	g_iommus[iommu->seq_id] = iommu;
	ret = iommu_init_domains(iommu);
	if (ret == 0)
		ret = iommu_alloc_root_entry(iommu);
	if (ret)
		goto out;

	if (dmaru->ignored) {
		/*
		 * we always have to disable PMRs or DMA may fail on this device
		 */
		if (force_on)
			iommu_disable_protect_mem_regions(iommu);
		return 0;
	}

	intel_iommu_init_qi(iommu);
	iommu_flush_write_buffer(iommu);
	ret = dmar_set_interrupt(iommu);
	if (ret)
		goto disable_iommu;

	iommu_set_root_entry(iommu);
	iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
	iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
	iommu_enable_translation(iommu);

	if (si_domain) {
		ret = iommu_attach_domain(si_domain, iommu);
		if (ret < 0 || si_domain->id != ret)
			goto disable_iommu;
		domain_attach_iommu(si_domain, iommu);
	}

	iommu_disable_protect_mem_regions(iommu);
	return 0;

disable_iommu:
	disable_dmar_iommu(iommu);
out:
	free_dmar_iommu(iommu);
	return ret;
}

3875 3876
int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
{
3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892
	int ret = 0;
	struct intel_iommu *iommu = dmaru->iommu;

	if (!intel_iommu_enabled)
		return 0;
	if (iommu == NULL)
		return -EINVAL;

	if (insert) {
		ret = intel_iommu_add(dmaru);
	} else {
		disable_dmar_iommu(iommu);
		free_dmar_iommu(iommu);
	}

	return ret;
3893 3894
}

3895 3896 3897 3898 3899 3900 3901 3902 3903
static void intel_iommu_free_dmars(void)
{
	struct dmar_rmrr_unit *rmrru, *rmrr_n;
	struct dmar_atsr_unit *atsru, *atsr_n;

	list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
		list_del(&rmrru->list);
		dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
		kfree(rmrru);
3904 3905
	}

3906 3907 3908 3909
	list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
		list_del(&atsru->list);
		intel_iommu_free_atsr(atsru);
	}
3910 3911 3912 3913
}

int dmar_find_matched_atsr_unit(struct pci_dev *dev)
{
3914
	int i, ret = 1;
3915
	struct pci_bus *bus;
3916 3917
	struct pci_dev *bridge = NULL;
	struct device *tmp;
3918 3919 3920 3921 3922
	struct acpi_dmar_atsr *atsr;
	struct dmar_atsr_unit *atsru;

	dev = pci_physfn(dev);
	for (bus = dev->bus; bus; bus = bus->parent) {
3923
		bridge = bus->self;
3924
		if (!bridge || !pci_is_pcie(bridge) ||
3925
		    pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
3926
			return 0;
3927
		if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
3928 3929
			break;
	}
3930 3931
	if (!bridge)
		return 0;
3932

3933
	rcu_read_lock();
3934 3935 3936 3937 3938
	list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
		atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
		if (atsr->segment != pci_domain_nr(dev->bus))
			continue;

3939
		for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
3940
			if (tmp == &bridge->dev)
3941
				goto out;
3942 3943

		if (atsru->include_all)
3944
			goto out;
3945
	}
3946 3947
	ret = 0;
out:
3948
	rcu_read_unlock();
3949

3950
	return ret;
3951 3952
}

3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971
int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
{
	int ret = 0;
	struct dmar_rmrr_unit *rmrru;
	struct dmar_atsr_unit *atsru;
	struct acpi_dmar_atsr *atsr;
	struct acpi_dmar_reserved_memory *rmrr;

	if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
		return 0;

	list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
		rmrr = container_of(rmrru->hdr,
				    struct acpi_dmar_reserved_memory, header);
		if (info->event == BUS_NOTIFY_ADD_DEVICE) {
			ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
				((void *)rmrr) + rmrr->header.length,
				rmrr->segment, rmrru->devices,
				rmrru->devices_cnt);
3972
			if(ret < 0)
3973 3974
				return ret;
		} else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3975 3976
			dmar_remove_dev_scope(info, rmrr->segment,
				rmrru->devices, rmrru->devices_cnt);
3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003
		}
	}

	list_for_each_entry(atsru, &dmar_atsr_units, list) {
		if (atsru->include_all)
			continue;

		atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
		if (info->event == BUS_NOTIFY_ADD_DEVICE) {
			ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
					(void *)atsr + atsr->header.length,
					atsr->segment, atsru->devices,
					atsru->devices_cnt);
			if (ret > 0)
				break;
			else if(ret < 0)
				return ret;
		} else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
			if (dmar_remove_dev_scope(info, atsr->segment,
					atsru->devices, atsru->devices_cnt))
				break;
		}
	}

	return 0;
}

F
Fenghua Yu 已提交
4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015
/*
 * Here we only respond to action of unbound device from driver.
 *
 * Added device is not attached to its DMAR domain here yet. That will happen
 * when mapping the device to iova.
 */
static int device_notifier(struct notifier_block *nb,
				  unsigned long action, void *data)
{
	struct device *dev = data;
	struct dmar_domain *domain;

4016
	if (iommu_dummy(dev))
4017 4018
		return 0;

4019
	if (action != BUS_NOTIFY_REMOVED_DEVICE)
4020 4021
		return 0;

4022
	domain = find_domain(dev);
F
Fenghua Yu 已提交
4023 4024 4025
	if (!domain)
		return 0;

4026
	down_read(&dmar_global_lock);
4027
	domain_remove_one_dev_info(domain, dev);
4028
	if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices))
4029
		domain_exit(domain);
4030
	up_read(&dmar_global_lock);
4031

F
Fenghua Yu 已提交
4032 4033 4034 4035 4036 4037 4038
	return 0;
}

static struct notifier_block device_nb = {
	.notifier_call = device_notifier,
};

4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064
static int intel_iommu_memory_notifier(struct notifier_block *nb,
				       unsigned long val, void *v)
{
	struct memory_notify *mhp = v;
	unsigned long long start, end;
	unsigned long start_vpfn, last_vpfn;

	switch (val) {
	case MEM_GOING_ONLINE:
		start = mhp->start_pfn << PAGE_SHIFT;
		end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
		if (iommu_domain_identity_map(si_domain, start, end)) {
			pr_warn("dmar: failed to build identity map for [%llx-%llx]\n",
				start, end);
			return NOTIFY_BAD;
		}
		break;

	case MEM_OFFLINE:
	case MEM_CANCEL_ONLINE:
		start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
		last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
		while (start_vpfn <= last_vpfn) {
			struct iova *iova;
			struct dmar_drhd_unit *drhd;
			struct intel_iommu *iommu;
4065
			struct page *freelist;
4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081

			iova = find_iova(&si_domain->iovad, start_vpfn);
			if (iova == NULL) {
				pr_debug("dmar: failed get IOVA for PFN %lx\n",
					 start_vpfn);
				break;
			}

			iova = split_and_remove_iova(&si_domain->iovad, iova,
						     start_vpfn, last_vpfn);
			if (iova == NULL) {
				pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n",
					start_vpfn, last_vpfn);
				return NOTIFY_BAD;
			}

4082 4083 4084
			freelist = domain_unmap(si_domain, iova->pfn_lo,
					       iova->pfn_hi);

4085 4086 4087
			rcu_read_lock();
			for_each_active_iommu(iommu, drhd)
				iommu_flush_iotlb_psi(iommu, si_domain->id,
4088
					iova->pfn_lo, iova_size(iova),
4089
					!freelist, 0);
4090
			rcu_read_unlock();
4091
			dma_free_pagelist(freelist);
4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106

			start_vpfn = iova->pfn_hi + 1;
			free_iova_mem(iova);
		}
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block intel_iommu_memory_nb = {
	.notifier_call = intel_iommu_memory_notifier,
	.priority = 0
};

4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163

static ssize_t intel_iommu_show_version(struct device *dev,
					struct device_attribute *attr,
					char *buf)
{
	struct intel_iommu *iommu = dev_get_drvdata(dev);
	u32 ver = readl(iommu->reg + DMAR_VER_REG);
	return sprintf(buf, "%d:%d\n",
		       DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver));
}
static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL);

static ssize_t intel_iommu_show_address(struct device *dev,
					struct device_attribute *attr,
					char *buf)
{
	struct intel_iommu *iommu = dev_get_drvdata(dev);
	return sprintf(buf, "%llx\n", iommu->reg_phys);
}
static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL);

static ssize_t intel_iommu_show_cap(struct device *dev,
				    struct device_attribute *attr,
				    char *buf)
{
	struct intel_iommu *iommu = dev_get_drvdata(dev);
	return sprintf(buf, "%llx\n", iommu->cap);
}
static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL);

static ssize_t intel_iommu_show_ecap(struct device *dev,
				    struct device_attribute *attr,
				    char *buf)
{
	struct intel_iommu *iommu = dev_get_drvdata(dev);
	return sprintf(buf, "%llx\n", iommu->ecap);
}
static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL);

static struct attribute *intel_iommu_attrs[] = {
	&dev_attr_version.attr,
	&dev_attr_address.attr,
	&dev_attr_cap.attr,
	&dev_attr_ecap.attr,
	NULL,
};

static struct attribute_group intel_iommu_group = {
	.name = "intel-iommu",
	.attrs = intel_iommu_attrs,
};

const struct attribute_group *intel_iommu_groups[] = {
	&intel_iommu_group,
	NULL,
};

4164 4165
int __init intel_iommu_init(void)
{
4166
	int ret = -ENODEV;
4167
	struct dmar_drhd_unit *drhd;
4168
	struct intel_iommu *iommu;
4169

4170 4171 4172
	/* VT-d is required for a TXT/tboot launch, so enforce that */
	force_on = tboot_force_iommu();

4173 4174 4175 4176 4177 4178 4179
	if (iommu_init_mempool()) {
		if (force_on)
			panic("tboot: Failed to initialize iommu memory\n");
		return -ENOMEM;
	}

	down_write(&dmar_global_lock);
4180 4181 4182
	if (dmar_table_init()) {
		if (force_on)
			panic("tboot: Failed to initialize DMAR table\n");
4183
		goto out_free_dmar;
4184
	}
4185

4186 4187 4188
	/*
	 * Disable translation if already enabled prior to OS handover.
	 */
4189
	for_each_active_iommu(iommu, drhd)
4190 4191 4192
		if (iommu->gcmd & DMA_GCMD_TE)
			iommu_disable_translation(iommu);

4193
	if (dmar_dev_scope_init() < 0) {
4194 4195
		if (force_on)
			panic("tboot: Failed to initialize DMAR device scope\n");
4196
		goto out_free_dmar;
4197
	}
4198

4199
	if (no_iommu || dmar_disabled)
4200
		goto out_free_dmar;
4201

4202 4203 4204 4205 4206 4207
	if (list_empty(&dmar_rmrr_units))
		printk(KERN_INFO "DMAR: No RMRR found\n");

	if (list_empty(&dmar_atsr_units))
		printk(KERN_INFO "DMAR: No ATSR found\n");

4208 4209 4210
	if (dmar_init_reserved_ranges()) {
		if (force_on)
			panic("tboot: Failed to reserve iommu ranges\n");
4211
		goto out_free_reserved_range;
4212
	}
4213 4214 4215

	init_no_remapping_devices();

4216
	ret = init_dmars();
4217
	if (ret) {
4218 4219
		if (force_on)
			panic("tboot: Failed to initialize DMARs\n");
4220
		printk(KERN_ERR "IOMMU: dmar init failed\n");
4221
		goto out_free_reserved_range;
4222
	}
4223
	up_write(&dmar_global_lock);
4224 4225 4226
	printk(KERN_INFO
	"PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");

M
mark gross 已提交
4227
	init_timer(&unmap_timer);
4228 4229 4230
#ifdef CONFIG_SWIOTLB
	swiotlb = 0;
#endif
4231
	dma_ops = &intel_dma_ops;
F
Fenghua Yu 已提交
4232

4233
	init_iommu_pm_ops();
4234

4235 4236 4237 4238 4239
	for_each_active_iommu(iommu, drhd)
		iommu->iommu_dev = iommu_device_create(NULL, iommu,
						       intel_iommu_groups,
						       iommu->name);

4240
	bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
F
Fenghua Yu 已提交
4241
	bus_register_notifier(&pci_bus_type, &device_nb);
4242 4243
	if (si_domain && !hw_pass_through)
		register_memory_notifier(&intel_iommu_memory_nb);
F
Fenghua Yu 已提交
4244

4245 4246
	intel_iommu_enabled = 1;

4247
	return 0;
4248 4249 4250 4251 4252

out_free_reserved_range:
	put_iova_domain(&reserved_iova_list);
out_free_dmar:
	intel_iommu_free_dmars();
4253 4254
	up_write(&dmar_global_lock);
	iommu_exit_mempool();
4255
	return ret;
4256
}
4257

4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271
static int iommu_detach_dev_cb(struct pci_dev *pdev, u16 alias, void *opaque)
{
	struct intel_iommu *iommu = opaque;

	iommu_detach_dev(iommu, PCI_BUS_NUM(alias), alias & 0xff);
	return 0;
}

/*
 * NB - intel-iommu lacks any sort of reference counting for the users of
 * dependent devices.  If multiple endpoints have intersecting dependent
 * devices, unbinding the driver from any one of them will possibly leave
 * the others unable to operate.
 */
4272
static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
4273
					   struct device *dev)
4274
{
4275
	if (!iommu || !dev || !dev_is_pci(dev))
4276 4277
		return;

4278
	pci_for_each_dma_alias(to_pci_dev(dev), &iommu_detach_dev_cb, iommu);
4279 4280
}

4281
static void domain_remove_one_dev_info(struct dmar_domain *domain,
4282
				       struct device *dev)
4283
{
4284
	struct device_domain_info *info, *tmp;
4285 4286
	struct intel_iommu *iommu;
	unsigned long flags;
4287
	bool found = false;
4288
	u8 bus, devfn;
4289

4290
	iommu = device_to_iommu(dev, &bus, &devfn);
4291 4292 4293 4294
	if (!iommu)
		return;

	spin_lock_irqsave(&device_domain_lock, flags);
4295
	list_for_each_entry_safe(info, tmp, &domain->devices, link) {
4296 4297
		if (info->iommu == iommu && info->bus == bus &&
		    info->devfn == devfn) {
4298
			unlink_domain_info(info);
4299 4300
			spin_unlock_irqrestore(&device_domain_lock, flags);

Y
Yu Zhao 已提交
4301
			iommu_disable_dev_iotlb(info);
4302
			iommu_detach_dev(iommu, info->bus, info->devfn);
4303
			iommu_detach_dependent_devices(iommu, dev);
4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317
			free_devinfo_mem(info);

			spin_lock_irqsave(&device_domain_lock, flags);

			if (found)
				break;
			else
				continue;
		}

		/* if there is no other devices under the same iommu
		 * owned by this domain, clear this iommu in iommu_bmp
		 * update iommu count and coherency
		 */
4318
		if (info->iommu == iommu)
4319
			found = true;
4320 4321
	}

4322 4323
	spin_unlock_irqrestore(&device_domain_lock, flags);

4324
	if (found == 0) {
4325 4326 4327
		domain_detach_iommu(domain, iommu);
		if (!domain_type_is_vm_or_si(domain))
			iommu_detach_domain(domain, iommu);
4328 4329 4330
	}
}

4331
static int md_domain_init(struct dmar_domain *domain, int guest_width)
4332 4333 4334
{
	int adjust_width;

4335 4336
	init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN,
			DMA_32BIT_PFN);
4337 4338 4339 4340 4341 4342 4343 4344
	domain_reserve_special_ranges(domain);

	/* calculate AGAW */
	domain->gaw = guest_width;
	adjust_width = guestwidth_to_adjustwidth(guest_width);
	domain->agaw = width_to_agaw(adjust_width);

	domain->iommu_coherency = 0;
4345
	domain->iommu_snooping = 0;
4346
	domain->iommu_superpage = 0;
4347
	domain->max_addr = 0;
4348 4349

	/* always allocate the top pgd */
4350
	domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
4351 4352 4353 4354 4355 4356
	if (!domain->pgd)
		return -ENOMEM;
	domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
	return 0;
}

4357
static struct iommu_domain *intel_iommu_domain_alloc(unsigned type)
K
Kay, Allen M 已提交
4358
{
4359
	struct dmar_domain *dmar_domain;
4360 4361 4362 4363
	struct iommu_domain *domain;

	if (type != IOMMU_DOMAIN_UNMANAGED)
		return NULL;
K
Kay, Allen M 已提交
4364

4365
	dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE);
4366
	if (!dmar_domain) {
K
Kay, Allen M 已提交
4367
		printk(KERN_ERR
4368
			"intel_iommu_domain_init: dmar_domain == NULL\n");
4369
		return NULL;
K
Kay, Allen M 已提交
4370
	}
4371
	if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
K
Kay, Allen M 已提交
4372
		printk(KERN_ERR
4373
			"intel_iommu_domain_init() failed\n");
4374
		domain_exit(dmar_domain);
4375
		return NULL;
K
Kay, Allen M 已提交
4376
	}
4377
	domain_update_iommu_cap(dmar_domain);
4378

4379
	domain = &dmar_domain->domain;
4380 4381 4382 4383
	domain->geometry.aperture_start = 0;
	domain->geometry.aperture_end   = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
	domain->geometry.force_aperture = true;

4384
	return domain;
K
Kay, Allen M 已提交
4385 4386
}

4387
static void intel_iommu_domain_free(struct iommu_domain *domain)
K
Kay, Allen M 已提交
4388
{
4389
	domain_exit(to_dmar_domain(domain));
K
Kay, Allen M 已提交
4390 4391
}

4392 4393
static int intel_iommu_attach_device(struct iommu_domain *domain,
				     struct device *dev)
K
Kay, Allen M 已提交
4394
{
4395
	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4396 4397
	struct intel_iommu *iommu;
	int addr_width;
4398
	u8 bus, devfn;
4399

4400 4401 4402 4403 4404
	if (device_is_rmrr_locked(dev)) {
		dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement.  Contact your platform vendor.\n");
		return -EPERM;
	}

4405 4406
	/* normally dev is not mapped */
	if (unlikely(domain_context_mapped(dev))) {
4407 4408
		struct dmar_domain *old_domain;

4409
		old_domain = find_domain(dev);
4410
		if (old_domain) {
4411
			if (domain_type_is_vm_or_si(dmar_domain))
4412
				domain_remove_one_dev_info(old_domain, dev);
4413 4414
			else
				domain_remove_dev_info(old_domain);
4415 4416 4417 4418

			if (!domain_type_is_vm_or_si(old_domain) &&
			     list_empty(&old_domain->devices))
				domain_exit(old_domain);
4419 4420 4421
		}
	}

4422
	iommu = device_to_iommu(dev, &bus, &devfn);
4423 4424 4425 4426 4427
	if (!iommu)
		return -ENODEV;

	/* check if this iommu agaw is sufficient for max mapped address */
	addr_width = agaw_to_width(iommu->agaw);
4428 4429 4430 4431 4432
	if (addr_width > cap_mgaw(iommu->cap))
		addr_width = cap_mgaw(iommu->cap);

	if (dmar_domain->max_addr > (1LL << addr_width)) {
		printk(KERN_ERR "%s: iommu width (%d) is not "
4433
		       "sufficient for the mapped address (%llx)\n",
4434
		       __func__, addr_width, dmar_domain->max_addr);
4435 4436
		return -EFAULT;
	}
4437 4438 4439 4440 4441 4442 4443 4444 4445 4446
	dmar_domain->gaw = addr_width;

	/*
	 * Knock out extra levels of page tables if necessary
	 */
	while (iommu->agaw < dmar_domain->agaw) {
		struct dma_pte *pte;

		pte = dmar_domain->pgd;
		if (dma_pte_present(pte)) {
4447 4448
			dmar_domain->pgd = (struct dma_pte *)
				phys_to_virt(dma_pte_addr(pte));
4449
			free_pgtable_page(pte);
4450 4451 4452
		}
		dmar_domain->agaw--;
	}
4453

4454
	return domain_add_dev_info(dmar_domain, dev, CONTEXT_TT_MULTI_LEVEL);
K
Kay, Allen M 已提交
4455 4456
}

4457 4458
static void intel_iommu_detach_device(struct iommu_domain *domain,
				      struct device *dev)
K
Kay, Allen M 已提交
4459
{
4460
	domain_remove_one_dev_info(to_dmar_domain(domain), dev);
4461
}
4462

4463 4464
static int intel_iommu_map(struct iommu_domain *domain,
			   unsigned long iova, phys_addr_t hpa,
4465
			   size_t size, int iommu_prot)
4466
{
4467
	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4468
	u64 max_addr;
4469
	int prot = 0;
4470
	int ret;
4471

4472 4473 4474 4475
	if (iommu_prot & IOMMU_READ)
		prot |= DMA_PTE_READ;
	if (iommu_prot & IOMMU_WRITE)
		prot |= DMA_PTE_WRITE;
4476 4477
	if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
		prot |= DMA_PTE_SNP;
4478

4479
	max_addr = iova + size;
4480
	if (dmar_domain->max_addr < max_addr) {
4481 4482 4483
		u64 end;

		/* check if minimum agaw is sufficient for mapped address */
4484
		end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
4485
		if (end < max_addr) {
4486
			printk(KERN_ERR "%s: iommu width (%d) is not "
4487
			       "sufficient for the mapped address (%llx)\n",
4488
			       __func__, dmar_domain->gaw, max_addr);
4489 4490
			return -EFAULT;
		}
4491
		dmar_domain->max_addr = max_addr;
4492
	}
4493 4494
	/* Round up size to next multiple of PAGE_SIZE, if it and
	   the low bits of hpa would take us onto the next page */
4495
	size = aligned_nrpages(hpa, size);
4496 4497
	ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
				 hpa >> VTD_PAGE_SHIFT, size, prot);
4498
	return ret;
K
Kay, Allen M 已提交
4499 4500
}

4501
static size_t intel_iommu_unmap(struct iommu_domain *domain,
4502
				unsigned long iova, size_t size)
K
Kay, Allen M 已提交
4503
{
4504
	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
4505 4506 4507 4508 4509
	struct page *freelist = NULL;
	struct intel_iommu *iommu;
	unsigned long start_pfn, last_pfn;
	unsigned int npages;
	int iommu_id, num, ndomains, level = 0;
4510 4511 4512 4513 4514 4515 4516 4517

	/* Cope with horrid API which requires us to unmap more than the
	   size argument if it happens to be a large-page mapping. */
	if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level))
		BUG();

	if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
		size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4518

4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541
	start_pfn = iova >> VTD_PAGE_SHIFT;
	last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;

	freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);

	npages = last_pfn - start_pfn + 1;

	for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) {
               iommu = g_iommus[iommu_id];

               /*
                * find bit position of dmar_domain
                */
               ndomains = cap_ndoms(iommu->cap);
               for_each_set_bit(num, iommu->domain_ids, ndomains) {
                       if (iommu->domains[num] == dmar_domain)
                               iommu_flush_iotlb_psi(iommu, num, start_pfn,
						     npages, !freelist, 0);
	       }

	}

	dma_free_pagelist(freelist);
4542

4543 4544
	if (dmar_domain->max_addr == iova + size)
		dmar_domain->max_addr = iova;
4545

4546
	return size;
K
Kay, Allen M 已提交
4547 4548
}

4549
static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
4550
					    dma_addr_t iova)
K
Kay, Allen M 已提交
4551
{
4552
	struct dmar_domain *dmar_domain = to_dmar_domain(domain);
K
Kay, Allen M 已提交
4553
	struct dma_pte *pte;
4554
	int level = 0;
4555
	u64 phys = 0;
K
Kay, Allen M 已提交
4556

4557
	pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
K
Kay, Allen M 已提交
4558
	if (pte)
4559
		phys = dma_pte_addr(pte);
K
Kay, Allen M 已提交
4560

4561
	return phys;
K
Kay, Allen M 已提交
4562
}
4563

4564
static bool intel_iommu_capable(enum iommu_cap cap)
S
Sheng Yang 已提交
4565 4566
{
	if (cap == IOMMU_CAP_CACHE_COHERENCY)
4567
		return domain_update_iommu_snooping(NULL) == 1;
4568
	if (cap == IOMMU_CAP_INTR_REMAP)
4569
		return irq_remapping_enabled == 1;
S
Sheng Yang 已提交
4570

4571
	return false;
S
Sheng Yang 已提交
4572 4573
}

4574 4575
static int intel_iommu_add_device(struct device *dev)
{
4576
	struct intel_iommu *iommu;
4577
	struct iommu_group *group;
4578
	u8 bus, devfn;
4579

4580 4581
	iommu = device_to_iommu(dev, &bus, &devfn);
	if (!iommu)
4582 4583
		return -ENODEV;

4584
	iommu_device_link(iommu->iommu_dev, dev);
4585

4586
	group = iommu_group_get_for_dev(dev);
4587

4588 4589
	if (IS_ERR(group))
		return PTR_ERR(group);
4590

4591
	iommu_group_put(group);
4592
	return 0;
4593
}
4594

4595 4596
static void intel_iommu_remove_device(struct device *dev)
{
4597 4598 4599 4600 4601 4602 4603
	struct intel_iommu *iommu;
	u8 bus, devfn;

	iommu = device_to_iommu(dev, &bus, &devfn);
	if (!iommu)
		return;

4604
	iommu_group_remove_device(dev);
4605 4606

	iommu_device_unlink(iommu->iommu_dev, dev);
4607 4608
}

4609
static const struct iommu_ops intel_iommu_ops = {
4610
	.capable	= intel_iommu_capable,
4611 4612
	.domain_alloc	= intel_iommu_domain_alloc,
	.domain_free	= intel_iommu_domain_free,
4613 4614
	.attach_dev	= intel_iommu_attach_device,
	.detach_dev	= intel_iommu_detach_device,
4615 4616
	.map		= intel_iommu_map,
	.unmap		= intel_iommu_unmap,
O
Olav Haugan 已提交
4617
	.map_sg		= default_iommu_map_sg,
4618
	.iova_to_phys	= intel_iommu_iova_to_phys,
4619 4620
	.add_device	= intel_iommu_add_device,
	.remove_device	= intel_iommu_remove_device,
4621
	.pgsize_bitmap	= INTEL_IOMMU_PGSIZES,
4622
};
4623

4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638
static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
{
	/* G4x/GM45 integrated gfx dmar support is totally busted. */
	printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
	dmar_map_gfx = 0;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);

4639
static void quirk_iommu_rwbf(struct pci_dev *dev)
4640 4641 4642
{
	/*
	 * Mobile 4 Series Chipset neglects to set RWBF capability,
4643
	 * but needs it. Same seems to hold for the desktop versions.
4644 4645 4646 4647 4648 4649
	 */
	printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
	rwbf_quirk = 1;
}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
4650 4651 4652 4653 4654 4655
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
4656

4657 4658 4659 4660 4661 4662 4663 4664 4665 4666
#define GGC 0x52
#define GGC_MEMORY_SIZE_MASK	(0xf << 8)
#define GGC_MEMORY_SIZE_NONE	(0x0 << 8)
#define GGC_MEMORY_SIZE_1M	(0x1 << 8)
#define GGC_MEMORY_SIZE_2M	(0x3 << 8)
#define GGC_MEMORY_VT_ENABLED	(0x8 << 8)
#define GGC_MEMORY_SIZE_2M_VT	(0x9 << 8)
#define GGC_MEMORY_SIZE_3M_VT	(0xa << 8)
#define GGC_MEMORY_SIZE_4M_VT	(0xb << 8)

4667
static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
4668 4669 4670
{
	unsigned short ggc;

4671
	if (pci_read_config_word(dev, GGC, &ggc))
4672 4673
		return;

4674
	if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
4675 4676
		printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
		dmar_map_gfx = 0;
4677 4678 4679 4680 4681
	} else if (dmar_map_gfx) {
		/* we have to ensure the gfx device is idle before we flush */
		printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
		intel_iommu_strict = 1;
       }
4682 4683 4684 4685 4686 4687
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);

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/* On Tylersburg chipsets, some BIOSes have been known to enable the
   ISOCH DMAR unit for the Azalia sound device, but not give it any
   TLB entries, which causes it to deadlock. Check for that.  We do
   this in a function called from init_dmars(), instead of in a PCI
   quirk, because we don't want to print the obnoxious "BIOS broken"
   message if VT-d is actually disabled.
*/
static void __init check_tylersburg_isoch(void)
{
	struct pci_dev *pdev;
	uint32_t vtisochctrl;

	/* If there's no Azalia in the system anyway, forget it. */
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
	if (!pdev)
		return;
	pci_dev_put(pdev);

	/* System Management Registers. Might be hidden, in which case
	   we can't do the sanity check. But that's OK, because the
	   known-broken BIOSes _don't_ actually hide it, so far. */
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
	if (!pdev)
		return;

	if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
		pci_dev_put(pdev);
		return;
	}

	pci_dev_put(pdev);

	/* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
	if (vtisochctrl & 1)
		return;

	/* Drop all bits other than the number of TLB entries */
	vtisochctrl &= 0x1c;

	/* If we have the recommended number of TLB entries (16), fine. */
	if (vtisochctrl == 0x10)
		return;

	/* Zero TLB entries? You get to ride the short bus to school. */
	if (!vtisochctrl) {
		WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
		     "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
		     dmi_get_system_info(DMI_BIOS_VENDOR),
		     dmi_get_system_info(DMI_BIOS_VERSION),
		     dmi_get_system_info(DMI_PRODUCT_VERSION));
		iommu_identity_mapping |= IDENTMAP_AZALIA;
		return;
	}
	
	printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
	       vtisochctrl);
}