pci.c 78.5 KB
Newer Older
L
Linus Torvalds 已提交
1 2 3 4 5 6 7 8 9 10 11 12 13
/*
 *	PCI Bus Services, see include/linux/pci.h for further explanation.
 *
 *	Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
 *	David Mosberger-Tang
 *
 *	Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
 */

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pci.h>
14
#include <linux/pm.h>
15
#include <linux/slab.h>
L
Linus Torvalds 已提交
16 17
#include <linux/module.h>
#include <linux/spinlock.h>
T
Tim Schmielau 已提交
18
#include <linux/string.h>
19
#include <linux/log2.h>
S
Shaohua Li 已提交
20
#include <linux/pci-aspm.h>
21
#include <linux/pm_wakeup.h>
22
#include <linux/interrupt.h>
23
#include <linux/device.h>
24
#include <linux/pm_runtime.h>
25
#include <asm/setup.h>
26
#include "pci.h"
L
Linus Torvalds 已提交
27

A
Alan Stern 已提交
28 29 30 31 32
const char *pci_power_names[] = {
	"error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
};
EXPORT_SYMBOL_GPL(pci_power_names);

33 34 35 36 37 38
int isa_dma_bridge_buggy;
EXPORT_SYMBOL(isa_dma_bridge_buggy);

int pci_pci_problems;
EXPORT_SYMBOL(pci_pci_problems);

39 40 41 42 43 44 45 46 47 48 49
unsigned int pci_pm_d3_delay;

static void pci_dev_d3_sleep(struct pci_dev *dev)
{
	unsigned int delay = dev->d3_delay;

	if (delay < pci_pm_d3_delay)
		delay = pci_pm_d3_delay;

	msleep(delay);
}
L
Linus Torvalds 已提交
50

51 52 53 54
#ifdef CONFIG_PCI_DOMAINS
int pci_domains_supported = 1;
#endif

55 56 57 58 59 60
#define DEFAULT_CARDBUS_IO_SIZE		(256)
#define DEFAULT_CARDBUS_MEM_SIZE	(64*1024*1024)
/* pci=cbmemsize=nnM,cbiosize=nn can override this */
unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;

61 62 63 64 65 66
#define DEFAULT_HOTPLUG_IO_SIZE		(256)
#define DEFAULT_HOTPLUG_MEM_SIZE	(2*1024*1024)
/* pci=hpmemsize=nnM,hpiosize=nn can override this */
unsigned long pci_hotplug_io_size  = DEFAULT_HOTPLUG_IO_SIZE;
unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;

67 68 69 70 71 72
/*
 * The default CLS is used if arch didn't set CLS explicitly and not
 * all pci devices agree on the same value.  Arch can override either
 * the dfl or actual value as it sees fit.  Don't forget this is
 * measured in 32-bit words, not bytes.
 */
73
u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
74 75
u8 pci_cache_line_size;

L
Linus Torvalds 已提交
76 77 78 79 80 81 82
/**
 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
 * @bus: pointer to PCI bus structure to search
 *
 * Given a PCI bus, returns the highest PCI bus number present in the set
 * including the given PCI bus and its list of child PCI buses.
 */
83
unsigned char pci_bus_max_busnr(struct pci_bus* bus)
L
Linus Torvalds 已提交
84 85 86 87
{
	struct list_head *tmp;
	unsigned char max, n;

88
	max = bus->subordinate;
L
Linus Torvalds 已提交
89 90 91 92 93 94 95
	list_for_each(tmp, &bus->children) {
		n = pci_bus_max_busnr(pci_bus_b(tmp));
		if(n > max)
			max = n;
	}
	return max;
}
96
EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
L
Linus Torvalds 已提交
97

A
Andrew Morton 已提交
98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
#ifdef CONFIG_HAS_IOMEM
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
{
	/*
	 * Make sure the BAR is actually a memory resource, not an IO resource
	 */
	if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
		WARN_ON(1);
		return NULL;
	}
	return ioremap_nocache(pci_resource_start(pdev, bar),
				     pci_resource_len(pdev, bar));
}
EXPORT_SYMBOL_GPL(pci_ioremap_bar);
#endif

114
#if 0
L
Linus Torvalds 已提交
115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
/**
 * pci_max_busnr - returns maximum PCI bus number
 *
 * Returns the highest PCI bus number present in the system global list of
 * PCI buses.
 */
unsigned char __devinit
pci_max_busnr(void)
{
	struct pci_bus *bus = NULL;
	unsigned char max, n;

	max = 0;
	while ((bus = pci_find_next_bus(bus)) != NULL) {
		n = pci_bus_max_busnr(bus);
		if(n > max)
			max = n;
	}
	return max;
}

136 137
#endif  /*  0  */

138 139 140 141
#define PCI_FIND_CAP_TTL	48

static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
				   u8 pos, int cap, int *ttl)
142 143 144
{
	u8 id;

145
	while ((*ttl)--) {
146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
		pci_bus_read_config_byte(bus, devfn, pos, &pos);
		if (pos < 0x40)
			break;
		pos &= ~3;
		pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
					 &id);
		if (id == 0xff)
			break;
		if (id == cap)
			return pos;
		pos += PCI_CAP_LIST_NEXT;
	}
	return 0;
}

161 162 163 164 165 166 167 168
static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
			       u8 pos, int cap)
{
	int ttl = PCI_FIND_CAP_TTL;

	return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
}

169 170 171 172 173 174 175
int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
{
	return __pci_find_next_cap(dev->bus, dev->devfn,
				   pos + PCI_CAP_LIST_NEXT, cap);
}
EXPORT_SYMBOL_GPL(pci_find_next_capability);

176 177
static int __pci_bus_find_cap_start(struct pci_bus *bus,
				    unsigned int devfn, u8 hdr_type)
L
Linus Torvalds 已提交
178 179 180 181 182 183 184 185 186 187
{
	u16 status;

	pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
	if (!(status & PCI_STATUS_CAP_LIST))
		return 0;

	switch (hdr_type) {
	case PCI_HEADER_TYPE_NORMAL:
	case PCI_HEADER_TYPE_BRIDGE:
188
		return PCI_CAPABILITY_LIST;
L
Linus Torvalds 已提交
189
	case PCI_HEADER_TYPE_CARDBUS:
190
		return PCI_CB_CAPABILITY_LIST;
L
Linus Torvalds 已提交
191 192 193
	default:
		return 0;
	}
194 195

	return 0;
L
Linus Torvalds 已提交
196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218
}

/**
 * pci_find_capability - query for devices' capabilities 
 * @dev: PCI device to query
 * @cap: capability code
 *
 * Tell if a device supports a given PCI capability.
 * Returns the address of the requested capability structure within the
 * device's PCI configuration space or 0 in case the device does not
 * support it.  Possible values for @cap:
 *
 *  %PCI_CAP_ID_PM           Power Management 
 *  %PCI_CAP_ID_AGP          Accelerated Graphics Port 
 *  %PCI_CAP_ID_VPD          Vital Product Data 
 *  %PCI_CAP_ID_SLOTID       Slot Identification 
 *  %PCI_CAP_ID_MSI          Message Signalled Interrupts
 *  %PCI_CAP_ID_CHSWP        CompactPCI HotSwap 
 *  %PCI_CAP_ID_PCIX         PCI-X
 *  %PCI_CAP_ID_EXP          PCI Express
 */
int pci_find_capability(struct pci_dev *dev, int cap)
{
219 220 221 222 223 224 225
	int pos;

	pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
	if (pos)
		pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);

	return pos;
L
Linus Torvalds 已提交
226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242
}

/**
 * pci_bus_find_capability - query for devices' capabilities 
 * @bus:   the PCI bus to query
 * @devfn: PCI device to query
 * @cap:   capability code
 *
 * Like pci_find_capability() but works for pci devices that do not have a
 * pci_dev structure set up yet. 
 *
 * Returns the address of the requested capability structure within the
 * device's PCI configuration space or 0 in case the device does not
 * support it.
 */
int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
{
243
	int pos;
L
Linus Torvalds 已提交
244 245 246 247
	u8 hdr_type;

	pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);

248 249 250 251 252
	pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
	if (pos)
		pos = __pci_find_next_cap(bus, devfn, pos, cap);

	return pos;
L
Linus Torvalds 已提交
253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271
}

/**
 * pci_find_ext_capability - Find an extended capability
 * @dev: PCI device to query
 * @cap: capability code
 *
 * Returns the address of the requested extended capability structure
 * within the device's PCI configuration space or 0 if the device does
 * not support it.  Possible values for @cap:
 *
 *  %PCI_EXT_CAP_ID_ERR		Advanced Error Reporting
 *  %PCI_EXT_CAP_ID_VC		Virtual Channel
 *  %PCI_EXT_CAP_ID_DSN		Device Serial Number
 *  %PCI_EXT_CAP_ID_PWR		Power Budgeting
 */
int pci_find_ext_capability(struct pci_dev *dev, int cap)
{
	u32 header;
272 273
	int ttl;
	int pos = PCI_CFG_SPACE_SIZE;
L
Linus Torvalds 已提交
274

275 276 277 278
	/* minimum 8 bytes per capability */
	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;

	if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
L
Linus Torvalds 已提交
279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295
		return 0;

	if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
		return 0;

	/*
	 * If we have no capabilities, this is indicated by cap ID,
	 * cap version and next pointer all being 0.
	 */
	if (header == 0)
		return 0;

	while (ttl-- > 0) {
		if (PCI_EXT_CAP_ID(header) == cap)
			return pos;

		pos = PCI_EXT_CAP_NEXT(header);
296
		if (pos < PCI_CFG_SPACE_SIZE)
L
Linus Torvalds 已提交
297 298 299 300 301 302 303 304
			break;

		if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
			break;
	}

	return 0;
}
305
EXPORT_SYMBOL_GPL(pci_find_ext_capability);
L
Linus Torvalds 已提交
306

307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349
/**
 * pci_bus_find_ext_capability - find an extended capability
 * @bus:   the PCI bus to query
 * @devfn: PCI device to query
 * @cap:   capability code
 *
 * Like pci_find_ext_capability() but works for pci devices that do not have a
 * pci_dev structure set up yet.
 *
 * Returns the address of the requested capability structure within the
 * device's PCI configuration space or 0 in case the device does not
 * support it.
 */
int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
				int cap)
{
	u32 header;
	int ttl;
	int pos = PCI_CFG_SPACE_SIZE;

	/* minimum 8 bytes per capability */
	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;

	if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
		return 0;
	if (header == 0xffffffff || header == 0)
		return 0;

	while (ttl-- > 0) {
		if (PCI_EXT_CAP_ID(header) == cap)
			return pos;

		pos = PCI_EXT_CAP_NEXT(header);
		if (pos < PCI_CFG_SPACE_SIZE)
			break;

		if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
			break;
	}

	return 0;
}

350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369
static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
{
	int rc, ttl = PCI_FIND_CAP_TTL;
	u8 cap, mask;

	if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
		mask = HT_3BIT_CAP_MASK;
	else
		mask = HT_5BIT_CAP_MASK;

	pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
				      PCI_CAP_ID_HT, &ttl);
	while (pos) {
		rc = pci_read_config_byte(dev, pos + 3, &cap);
		if (rc != PCIBIOS_SUCCESSFUL)
			return 0;

		if ((cap & mask) == ht_cap)
			return pos;

370 371
		pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
					      pos + PCI_CAP_LIST_NEXT,
372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418
					      PCI_CAP_ID_HT, &ttl);
	}

	return 0;
}
/**
 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
 * @dev: PCI device to query
 * @pos: Position from which to continue searching
 * @ht_cap: Hypertransport capability code
 *
 * To be used in conjunction with pci_find_ht_capability() to search for
 * all capabilities matching @ht_cap. @pos should always be a value returned
 * from pci_find_ht_capability().
 *
 * NB. To be 100% safe against broken PCI devices, the caller should take
 * steps to avoid an infinite loop.
 */
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
{
	return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
}
EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);

/**
 * pci_find_ht_capability - query a device's Hypertransport capabilities
 * @dev: PCI device to query
 * @ht_cap: Hypertransport capability code
 *
 * Tell if a device supports a given Hypertransport capability.
 * Returns an address within the device's PCI configuration space
 * or 0 in case the device does not support the request capability.
 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
 * which has a Hypertransport capability matching @ht_cap.
 */
int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
{
	int pos;

	pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
	if (pos)
		pos = __pci_find_next_ht_cap(dev, pos, ht_cap);

	return pos;
}
EXPORT_SYMBOL_GPL(pci_find_ht_capability);

L
Linus Torvalds 已提交
419 420 421 422 423 424 425 426 427 428 429 430 431 432
/**
 * pci_find_parent_resource - return resource region of parent bus of given region
 * @dev: PCI device structure contains resources to be searched
 * @res: child resource record for which parent is sought
 *
 *  For given resource region of given device, return the resource
 *  region of parent bus the given region is contained in or where
 *  it should be allocated from.
 */
struct resource *
pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
{
	const struct pci_bus *bus = dev->bus;
	int i;
433
	struct resource *best = NULL, *r;
L
Linus Torvalds 已提交
434

435
	pci_bus_for_each_resource(bus, r, i) {
L
Linus Torvalds 已提交
436 437 438 439 440 441 442 443
		if (!r)
			continue;
		if (res->start && !(res->start >= r->start && res->end <= r->end))
			continue;	/* Not contained */
		if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
			continue;	/* Wrong type */
		if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
			return r;	/* Exact match */
444 445 446 447 448 449
		/* We can't insert a non-prefetch resource inside a prefetchable parent .. */
		if (r->flags & IORESOURCE_PREFETCH)
			continue;
		/* .. but we can put a prefetchable resource inside a non-prefetchable one */
		if (!best)
			best = r;
L
Linus Torvalds 已提交
450 451 452 453
	}
	return best;
}

454 455 456 457 458 459 460
/**
 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
 * @dev: PCI device to have its BARs restored
 *
 * Restore the BAR values for a given device, so as to make it
 * accessible by its driver.
 */
461
static void
462 463
pci_restore_bars(struct pci_dev *dev)
{
464
	int i;
465

466
	for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
467
		pci_update_resource(dev, i);
468 469
}

470 471 472 473
static struct pci_platform_pm_ops *pci_platform_pm;

int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
{
474 475
	if (!ops->is_manageable || !ops->set_state || !ops->choose_state
	    || !ops->sleep_wake || !ops->can_wakeup)
476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496
		return -EINVAL;
	pci_platform_pm = ops;
	return 0;
}

static inline bool platform_pci_power_manageable(struct pci_dev *dev)
{
	return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
}

static inline int platform_pci_set_power_state(struct pci_dev *dev,
                                                pci_power_t t)
{
	return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
}

static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
{
	return pci_platform_pm ?
			pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
}
R
Randy Dunlap 已提交
497

498 499 500 501 502 503 504 505 506 507 508
static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
{
	return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
}

static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
{
	return pci_platform_pm ?
			pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
}

509 510 511 512 513 514
static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
{
	return pci_platform_pm ?
			pci_platform_pm->run_wake(dev, enable) : -ENODEV;
}

L
Linus Torvalds 已提交
515
/**
516 517 518 519
 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
 *                           given PCI device
 * @dev: PCI device to handle.
 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
L
Linus Torvalds 已提交
520
 *
521 522 523 524 525 526
 * RETURN VALUE:
 * -EINVAL if the requested state is invalid.
 * -EIO if device does not support PCI PM or its PM capabilities register has a
 * wrong version, or device doesn't support the requested state.
 * 0 if device already is in the requested state.
 * 0 if device's power state has been successfully changed.
L
Linus Torvalds 已提交
527
 */
528
static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
L
Linus Torvalds 已提交
529
{
530
	u16 pmcsr;
531
	bool need_restore = false;
L
Linus Torvalds 已提交
532

533 534 535 536
	/* Check if we're already there */
	if (dev->current_state == state)
		return 0;

537
	if (!dev->pm_cap)
538 539
		return -EIO;

540 541 542
	if (state < PCI_D0 || state > PCI_D3hot)
		return -EINVAL;

L
Linus Torvalds 已提交
543 544 545 546
	/* Validate current state:
	 * Can enter D0 from any state, but if we can only go deeper 
	 * to sleep if we're already in a low power state
	 */
547
	if (state != PCI_D0 && dev->current_state <= PCI_D3cold
548
	    && dev->current_state > state) {
549 550
		dev_err(&dev->dev, "invalid power transition "
			"(from state %d to %d)\n", dev->current_state, state);
L
Linus Torvalds 已提交
551
		return -EINVAL;
552
	}
L
Linus Torvalds 已提交
553 554

	/* check if this device supports the desired state */
555 556
	if ((state == PCI_D1 && !dev->d1_support)
	   || (state == PCI_D2 && !dev->d2_support))
557
		return -EIO;
L
Linus Torvalds 已提交
558

559
	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
560

561
	/* If we're (effectively) in D3, force entire word to 0.
L
Linus Torvalds 已提交
562 563 564
	 * This doesn't affect PME_Status, disables PME_En, and
	 * sets PowerState to 0.
	 */
565
	switch (dev->current_state) {
566 567 568 569 570 571
	case PCI_D0:
	case PCI_D1:
	case PCI_D2:
		pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
		pmcsr |= state;
		break;
572 573
	case PCI_D3hot:
	case PCI_D3cold:
574 575
	case PCI_UNKNOWN: /* Boot-up */
		if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
576
		 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
577
			need_restore = true;
578 579
		/* Fall-through: force to D0 */
	default:
580
		pmcsr = 0;
581
		break;
L
Linus Torvalds 已提交
582 583 584
	}

	/* enter specified state */
585
	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
L
Linus Torvalds 已提交
586 587 588 589

	/* Mandatory power management transition delays */
	/* see PCI PM 1.1 5.6.1 table 18 */
	if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
590
		pci_dev_d3_sleep(dev);
L
Linus Torvalds 已提交
591
	else if (state == PCI_D2 || dev->current_state == PCI_D2)
592
		udelay(PCI_PM_D2_DELAY);
L
Linus Torvalds 已提交
593

594 595 596 597 598
	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
	dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
	if (dev->current_state != state && printk_ratelimit())
		dev_info(&dev->dev, "Refused to change power state, "
			"currently in D%d\n", dev->current_state);
599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614

	/* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
	 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
	 * from D3hot to D0 _may_ perform an internal reset, thereby
	 * going to "D0 Uninitialized" rather than "D0 Initialized".
	 * For example, at least some versions of the 3c905B and the
	 * 3c556B exhibit this behaviour.
	 *
	 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
	 * devices in a D3hot state at boot.  Consequently, we need to
	 * restore at least the BARs so that the device will be
	 * accessible to its driver.
	 */
	if (need_restore)
		pci_restore_bars(dev);

615
	if (dev->bus->self)
S
Shaohua Li 已提交
616 617
		pcie_aspm_pm_state_change(dev->bus->self);

L
Linus Torvalds 已提交
618 619 620
	return 0;
}

621 622 623 624
/**
 * pci_update_current_state - Read PCI power state of given device from its
 *                            PCI PM registers and cache it
 * @dev: PCI device to handle.
625
 * @state: State to cache in case the device doesn't have the PM capability
626
 */
627
void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
628
{
629
	if (dev->pm_cap) {
630 631
		u16 pmcsr;

632
		pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
633
		dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
634 635
	} else {
		dev->current_state = state;
636 637 638
	}
}

639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654
/**
 * pci_platform_power_transition - Use platform to change device power state
 * @dev: PCI device to handle.
 * @state: State to put the device into.
 */
static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
{
	int error;

	if (platform_pci_power_manageable(dev)) {
		error = platform_pci_set_power_state(dev, state);
		if (!error)
			pci_update_current_state(dev, state);
	} else {
		error = -ENODEV;
		/* Fall back to PCI_D0 if native PM is not supported */
655 656
		if (!dev->pm_cap)
			dev->current_state = PCI_D0;
657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681
	}

	return error;
}

/**
 * __pci_start_power_transition - Start power transition of a PCI device
 * @dev: PCI device to handle.
 * @state: State to put the device into.
 */
static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
{
	if (state == PCI_D0)
		pci_platform_power_transition(dev, PCI_D0);
}

/**
 * __pci_complete_power_transition - Complete power transition of a PCI device
 * @dev: PCI device to handle.
 * @state: State to put the device into.
 *
 * This function should not be called directly by device drivers.
 */
int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
{
682
	return state >= PCI_D0 ?
683 684 685 686
			pci_platform_power_transition(dev, state) : -EINVAL;
}
EXPORT_SYMBOL_GPL(__pci_complete_power_transition);

687 688 689 690 691
/**
 * pci_set_power_state - Set the power state of a PCI device
 * @dev: PCI device to handle.
 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
 *
692
 * Transition a device to a new power state, using the platform firmware and/or
693 694 695 696 697 698 699 700 701 702 703
 * the device's PCI PM registers.
 *
 * RETURN VALUE:
 * -EINVAL if the requested state is invalid.
 * -EIO if device does not support PCI PM or its PM capabilities register has a
 * wrong version, or device doesn't support the requested state.
 * 0 if device already is in the requested state.
 * 0 if device's power state has been successfully changed.
 */
int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
{
704
	int error;
705 706 707 708 709 710 711 712 713 714 715 716 717 718

	/* bound the state we're entering */
	if (state > PCI_D3hot)
		state = PCI_D3hot;
	else if (state < PCI_D0)
		state = PCI_D0;
	else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
		/*
		 * If the device or the parent bridge do not support PCI PM,
		 * ignore the request if we're doing anything other than putting
		 * it into D0 (which would only happen on boot).
		 */
		return 0;

719 720
	__pci_start_power_transition(dev, state);

721 722 723 724
	/* This device is quirked not to be put into D3, so
	   don't put it in D3 */
	if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
		return 0;
725

726
	error = pci_raw_set_power_state(dev, state);
727

728 729
	if (!__pci_complete_power_transition(dev, state))
		error = 0;
730 731 732 733

	return error;
}

L
Linus Torvalds 已提交
734 735 736 737 738 739 740 741 742 743 744 745
/**
 * pci_choose_state - Choose the power state of a PCI device
 * @dev: PCI device to be suspended
 * @state: target sleep state for the whole system. This is the value
 *	that is passed to suspend() function.
 *
 * Returns PCI power state suitable for given device and given system
 * message.
 */

pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
{
746
	pci_power_t ret;
747

L
Linus Torvalds 已提交
748 749 750
	if (!pci_find_capability(dev, PCI_CAP_ID_PM))
		return PCI_D0;

751 752 753
	ret = platform_pci_choose_state(dev);
	if (ret != PCI_POWER_ERROR)
		return ret;
754 755 756 757 758

	switch (state.event) {
	case PM_EVENT_ON:
		return PCI_D0;
	case PM_EVENT_FREEZE:
759 760
	case PM_EVENT_PRETHAW:
		/* REVISIT both freeze and pre-thaw "should" use D0 */
761
	case PM_EVENT_SUSPEND:
762
	case PM_EVENT_HIBERNATE:
763
		return PCI_D3hot;
L
Linus Torvalds 已提交
764
	default:
765 766
		dev_info(&dev->dev, "unrecognized suspend event %d\n",
			 state.event);
L
Linus Torvalds 已提交
767 768 769 770 771 772 773
		BUG();
	}
	return PCI_D0;
}

EXPORT_SYMBOL(pci_choose_state);

774 775
#define PCI_EXP_SAVE_REGS	7

776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797
#define pcie_cap_has_devctl(type, flags)	1
#define pcie_cap_has_lnkctl(type, flags)		\
		((flags & PCI_EXP_FLAGS_VERS) > 1 ||	\
		 (type == PCI_EXP_TYPE_ROOT_PORT ||	\
		  type == PCI_EXP_TYPE_ENDPOINT ||	\
		  type == PCI_EXP_TYPE_LEG_END))
#define pcie_cap_has_sltctl(type, flags)		\
		((flags & PCI_EXP_FLAGS_VERS) > 1 ||	\
		 ((type == PCI_EXP_TYPE_ROOT_PORT) ||	\
		  (type == PCI_EXP_TYPE_DOWNSTREAM &&	\
		   (flags & PCI_EXP_FLAGS_SLOT))))
#define pcie_cap_has_rtctl(type, flags)			\
		((flags & PCI_EXP_FLAGS_VERS) > 1 ||	\
		 (type == PCI_EXP_TYPE_ROOT_PORT ||	\
		  type == PCI_EXP_TYPE_RC_EC))
#define pcie_cap_has_devctl2(type, flags)		\
		((flags & PCI_EXP_FLAGS_VERS) > 1)
#define pcie_cap_has_lnkctl2(type, flags)		\
		((flags & PCI_EXP_FLAGS_VERS) > 1)
#define pcie_cap_has_sltctl2(type, flags)		\
		((flags & PCI_EXP_FLAGS_VERS) > 1)

798 799 800 801 802
static int pci_save_pcie_state(struct pci_dev *dev)
{
	int pos, i = 0;
	struct pci_cap_saved_state *save_state;
	u16 *cap;
803
	u16 flags;
804

805 806
	pos = pci_pcie_cap(dev);
	if (!pos)
807 808
		return 0;

809
	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
810
	if (!save_state) {
811
		dev_err(&dev->dev, "buffer not found in %s\n", __func__);
812 813 814 815
		return -ENOMEM;
	}
	cap = (u16 *)&save_state->data[0];

816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831
	pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);

	if (pcie_cap_has_devctl(dev->pcie_type, flags))
		pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
	if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
		pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
	if (pcie_cap_has_sltctl(dev->pcie_type, flags))
		pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
	if (pcie_cap_has_rtctl(dev->pcie_type, flags))
		pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
	if (pcie_cap_has_devctl2(dev->pcie_type, flags))
		pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
	if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
		pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
	if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
		pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
832

833 834 835 836 837 838 839 840
	return 0;
}

static void pci_restore_pcie_state(struct pci_dev *dev)
{
	int i = 0, pos;
	struct pci_cap_saved_state *save_state;
	u16 *cap;
841
	u16 flags;
842 843 844 845 846 847 848

	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
	if (!save_state || pos <= 0)
		return;
	cap = (u16 *)&save_state->data[0];

849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864
	pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);

	if (pcie_cap_has_devctl(dev->pcie_type, flags))
		pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
	if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
		pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
	if (pcie_cap_has_sltctl(dev->pcie_type, flags))
		pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
	if (pcie_cap_has_rtctl(dev->pcie_type, flags))
		pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
	if (pcie_cap_has_devctl2(dev->pcie_type, flags))
		pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
	if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
		pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
	if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
		pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
865 866
}

S
Stephen Hemminger 已提交
867 868 869

static int pci_save_pcix_state(struct pci_dev *dev)
{
870
	int pos;
S
Stephen Hemminger 已提交
871 872 873 874 875 876
	struct pci_cap_saved_state *save_state;

	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
	if (pos <= 0)
		return 0;

877
	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
S
Stephen Hemminger 已提交
878
	if (!save_state) {
879
		dev_err(&dev->dev, "buffer not found in %s\n", __func__);
S
Stephen Hemminger 已提交
880 881 882
		return -ENOMEM;
	}

883 884
	pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);

S
Stephen Hemminger 已提交
885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903
	return 0;
}

static void pci_restore_pcix_state(struct pci_dev *dev)
{
	int i = 0, pos;
	struct pci_cap_saved_state *save_state;
	u16 *cap;

	save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
	if (!save_state || pos <= 0)
		return;
	cap = (u16 *)&save_state->data[0];

	pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
}


L
Linus Torvalds 已提交
904 905 906 907 908 909 910 911 912 913
/**
 * pci_save_state - save the PCI configuration space of a device before suspending
 * @dev: - PCI device that we're dealing with
 */
int
pci_save_state(struct pci_dev *dev)
{
	int i;
	/* XXX: 100% dword access ok here? */
	for (i = 0; i < 16; i++)
914
		pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
915
	dev->state_saved = true;
916 917
	if ((i = pci_save_pcie_state(dev)) != 0)
		return i;
S
Stephen Hemminger 已提交
918 919
	if ((i = pci_save_pcix_state(dev)) != 0)
		return i;
L
Linus Torvalds 已提交
920 921 922 923 924 925 926 927 928 929 930
	return 0;
}

/** 
 * pci_restore_state - Restore the saved state of a PCI device
 * @dev: - PCI device that we're dealing with
 */
int 
pci_restore_state(struct pci_dev *dev)
{
	int i;
A
Al Viro 已提交
931
	u32 val;
L
Linus Torvalds 已提交
932

A
Alek Du 已提交
933 934
	if (!dev->state_saved)
		return 0;
935

936 937 938
	/* PCI Express register must be restored first */
	pci_restore_pcie_state(dev);

939 940 941 942 943
	/*
	 * The Base Address register should be programmed before the command
	 * register(s)
	 */
	for (i = 15; i >= 0; i--) {
944 945
		pci_read_config_dword(dev, i * 4, &val);
		if (val != dev->saved_config_space[i]) {
946 947 948
			dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
				"space at offset %#x (was %#x, writing %#x)\n",
				i, val, (int)dev->saved_config_space[i]);
949 950 951 952
			pci_write_config_dword(dev,i * 4,
				dev->saved_config_space[i]);
		}
	}
S
Stephen Hemminger 已提交
953
	pci_restore_pcix_state(dev);
954
	pci_restore_msi_state(dev);
Y
Yu Zhao 已提交
955
	pci_restore_iov_state(dev);
956

957 958
	dev->state_saved = false;

L
Linus Torvalds 已提交
959 960 961
	return 0;
}

962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977
static int do_pci_enable_device(struct pci_dev *dev, int bars)
{
	int err;

	err = pci_set_power_state(dev, PCI_D0);
	if (err < 0 && err != -EIO)
		return err;
	err = pcibios_enable_device(dev, bars);
	if (err < 0)
		return err;
	pci_fixup_device(pci_fixup_enable, dev);

	return 0;
}

/**
978
 * pci_reenable_device - Resume abandoned device
979 980 981 982 983
 * @dev: PCI device to be resumed
 *
 *  Note this function is a backend of pci_default_resume and is not supposed
 *  to be called by normal code, write proper resume handler and use it instead.
 */
984
int pci_reenable_device(struct pci_dev *dev)
985
{
986
	if (pci_is_enabled(dev))
987 988 989 990
		return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
	return 0;
}

991 992
static int __pci_enable_device_flags(struct pci_dev *dev,
				     resource_size_t flags)
L
Linus Torvalds 已提交
993 994
{
	int err;
995
	int i, bars = 0;
L
Linus Torvalds 已提交
996

997 998 999
	if (atomic_add_return(1, &dev->enable_cnt) > 1)
		return 0;		/* already enabled */

1000 1001 1002 1003
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
		if (dev->resource[i].flags & flags)
			bars |= (1 << i);

1004
	err = do_pci_enable_device(dev, bars);
1005
	if (err < 0)
1006
		atomic_dec(&dev->enable_cnt);
1007
	return err;
L
Linus Torvalds 已提交
1008 1009
}

1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035
/**
 * pci_enable_device_io - Initialize a device for use with IO space
 * @dev: PCI device to be initialized
 *
 *  Initialize device before it's used by a driver. Ask low-level code
 *  to enable I/O resources. Wake up the device if it was suspended.
 *  Beware, this function can fail.
 */
int pci_enable_device_io(struct pci_dev *dev)
{
	return __pci_enable_device_flags(dev, IORESOURCE_IO);
}

/**
 * pci_enable_device_mem - Initialize a device for use with Memory space
 * @dev: PCI device to be initialized
 *
 *  Initialize device before it's used by a driver. Ask low-level code
 *  to enable Memory resources. Wake up the device if it was suspended.
 *  Beware, this function can fail.
 */
int pci_enable_device_mem(struct pci_dev *dev)
{
	return __pci_enable_device_flags(dev, IORESOURCE_MEM);
}

1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048
/**
 * pci_enable_device - Initialize device before it's used by a driver.
 * @dev: PCI device to be initialized
 *
 *  Initialize device before it's used by a driver. Ask low-level code
 *  to enable I/O and memory. Wake up the device if it was suspended.
 *  Beware, this function can fail.
 *
 *  Note we don't actually enable the device many times if we call
 *  this function repeatedly (we just increment the count).
 */
int pci_enable_device(struct pci_dev *dev)
{
1049
	return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1050 1051
}

T
Tejun Heo 已提交
1052 1053 1054 1055 1056 1057 1058
/*
 * Managed PCI resources.  This manages device on/off, intx/msi/msix
 * on/off and BAR regions.  pci_dev itself records msi/msix status, so
 * there's no need to track it separately.  pci_devres is initialized
 * when a device is enabled using managed PCI device enable interface.
 */
struct pci_devres {
1059 1060
	unsigned int enabled:1;
	unsigned int pinned:1;
T
Tejun Heo 已提交
1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083
	unsigned int orig_intx:1;
	unsigned int restore_intx:1;
	u32 region_mask;
};

static void pcim_release(struct device *gendev, void *res)
{
	struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
	struct pci_devres *this = res;
	int i;

	if (dev->msi_enabled)
		pci_disable_msi(dev);
	if (dev->msix_enabled)
		pci_disable_msix(dev);

	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
		if (this->region_mask & (1 << i))
			pci_release_region(dev, i);

	if (this->restore_intx)
		pci_intx(dev, this->orig_intx);

1084
	if (this->enabled && !this->pinned)
T
Tejun Heo 已提交
1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122
		pci_disable_device(dev);
}

static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
{
	struct pci_devres *dr, *new_dr;

	dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
	if (dr)
		return dr;

	new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
	if (!new_dr)
		return NULL;
	return devres_get(&pdev->dev, new_dr, NULL, NULL);
}

static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
{
	if (pci_is_managed(pdev))
		return devres_find(&pdev->dev, pcim_release, NULL, NULL);
	return NULL;
}

/**
 * pcim_enable_device - Managed pci_enable_device()
 * @pdev: PCI device to be initialized
 *
 * Managed pci_enable_device().
 */
int pcim_enable_device(struct pci_dev *pdev)
{
	struct pci_devres *dr;
	int rc;

	dr = get_pci_dr(pdev);
	if (unlikely(!dr))
		return -ENOMEM;
1123 1124
	if (dr->enabled)
		return 0;
T
Tejun Heo 已提交
1125 1126 1127 1128

	rc = pci_enable_device(pdev);
	if (!rc) {
		pdev->is_managed = 1;
1129
		dr->enabled = 1;
T
Tejun Heo 已提交
1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146
	}
	return rc;
}

/**
 * pcim_pin_device - Pin managed PCI device
 * @pdev: PCI device to pin
 *
 * Pin managed PCI device @pdev.  Pinned device won't be disabled on
 * driver detach.  @pdev must have been enabled with
 * pcim_enable_device().
 */
void pcim_pin_device(struct pci_dev *pdev)
{
	struct pci_devres *dr;

	dr = find_pci_dr(pdev);
1147
	WARN_ON(!dr || !dr->enabled);
T
Tejun Heo 已提交
1148
	if (dr)
1149
		dr->pinned = 1;
T
Tejun Heo 已提交
1150 1151
}

L
Linus Torvalds 已提交
1152 1153 1154 1155 1156 1157 1158 1159 1160 1161
/**
 * pcibios_disable_device - disable arch specific PCI resources for device dev
 * @dev: the PCI device to disable
 *
 * Disables architecture specific PCI resources for the device. This
 * is the default implementation. Architecture implementations can
 * override this.
 */
void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}

1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183
static void do_pci_disable_device(struct pci_dev *dev)
{
	u16 pci_command;

	pci_read_config_word(dev, PCI_COMMAND, &pci_command);
	if (pci_command & PCI_COMMAND_MASTER) {
		pci_command &= ~PCI_COMMAND_MASTER;
		pci_write_config_word(dev, PCI_COMMAND, pci_command);
	}

	pcibios_disable_device(dev);
}

/**
 * pci_disable_enabled_device - Disable device without updating enable_cnt
 * @dev: PCI device to disable
 *
 * NOTE: This function is a backend of PCI power management routines and is
 * not supposed to be called drivers.
 */
void pci_disable_enabled_device(struct pci_dev *dev)
{
1184
	if (pci_is_enabled(dev))
1185 1186 1187
		do_pci_disable_device(dev);
}

L
Linus Torvalds 已提交
1188 1189 1190 1191 1192 1193
/**
 * pci_disable_device - Disable PCI device after use
 * @dev: PCI device to be disabled
 *
 * Signal to the system that the PCI device is not in use by the system
 * anymore.  This only involves disabling PCI bus-mastering, if active.
1194 1195
 *
 * Note we don't actually disable the device until all callers of
1196
 * pci_enable_device() have called pci_disable_device().
L
Linus Torvalds 已提交
1197 1198 1199 1200
 */
void
pci_disable_device(struct pci_dev *dev)
{
T
Tejun Heo 已提交
1201
	struct pci_devres *dr;
1202

T
Tejun Heo 已提交
1203 1204
	dr = find_pci_dr(dev);
	if (dr)
1205
		dr->enabled = 0;
T
Tejun Heo 已提交
1206

1207 1208 1209
	if (atomic_sub_return(1, &dev->enable_cnt) != 0)
		return;

1210
	do_pci_disable_device(dev);
L
Linus Torvalds 已提交
1211

1212
	dev->is_busmaster = 0;
L
Linus Torvalds 已提交
1213 1214
}

B
Brian King 已提交
1215 1216
/**
 * pcibios_set_pcie_reset_state - set reset state for device dev
1217
 * @dev: the PCIe device reset
B
Brian King 已提交
1218 1219 1220
 * @state: Reset state to enter into
 *
 *
1221
 * Sets the PCIe reset state for the device. This is the default
B
Brian King 已提交
1222 1223 1224 1225 1226 1227 1228 1229 1230 1231
 * implementation. Architecture implementations can override this.
 */
int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
							enum pcie_reset_state state)
{
	return -EINVAL;
}

/**
 * pci_set_pcie_reset_state - set reset state for device dev
1232
 * @dev: the PCIe device reset
B
Brian King 已提交
1233 1234 1235 1236 1237 1238 1239 1240 1241 1242
 * @state: Reset state to enter into
 *
 *
 * Sets the PCI reset state for the device.
 */
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
{
	return pcibios_set_pcie_reset_state(dev, state);
}

1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277
/**
 * pci_check_pme_status - Check if given device has generated PME.
 * @dev: Device to check.
 *
 * Check the PME status of the device and if set, clear it and clear PME enable
 * (if set).  Return 'true' if PME status and PME enable were both set or
 * 'false' otherwise.
 */
bool pci_check_pme_status(struct pci_dev *dev)
{
	int pmcsr_pos;
	u16 pmcsr;
	bool ret = false;

	if (!dev->pm_cap)
		return false;

	pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
	pci_read_config_word(dev, pmcsr_pos, &pmcsr);
	if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
		return false;

	/* Clear PME status. */
	pmcsr |= PCI_PM_CTRL_PME_STATUS;
	if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
		/* Disable PME to avoid interrupt flood. */
		pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
		ret = true;
	}

	pci_write_config_word(dev, pmcsr_pos, pmcsr);

	return ret;
}

1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293
/*
 * Time to wait before the system can be put into a sleep state after reporting
 * a wakeup event signaled by a PCI device.
 */
#define PCI_WAKEUP_COOLDOWN	100

/**
 * pci_wakeup_event - Report a wakeup event related to a given PCI device.
 * @dev: Device to report the wakeup event for.
 */
void pci_wakeup_event(struct pci_dev *dev)
{
	if (device_may_wakeup(&dev->dev))
		pm_wakeup_event(&dev->dev, PCI_WAKEUP_COOLDOWN);
}

1294 1295 1296 1297 1298 1299 1300 1301 1302 1303
/**
 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
 * @dev: Device to handle.
 * @ign: Ignored.
 *
 * Check if @dev has generated PME and queue a resume request for it in that
 * case.
 */
static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
{
1304
	if (pci_check_pme_status(dev)) {
1305
		pm_request_resume(&dev->dev);
1306 1307
		pci_wakeup_event(dev);
	}
1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320
	return 0;
}

/**
 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
 * @bus: Top bus of the subtree to walk.
 */
void pci_pme_wakeup_bus(struct pci_bus *bus)
{
	if (bus)
		pci_walk_bus(bus, pci_pme_wakeup, NULL);
}

1321 1322 1323 1324 1325
/**
 * pci_pme_capable - check the capability of PCI device to generate PME#
 * @dev: PCI device to handle.
 * @state: PCI state from which device will issue PME#.
 */
1326
bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1327
{
1328
	if (!dev->pm_cap)
1329 1330
		return false;

1331
	return !!(dev->pme_support & (1 << state));
1332 1333 1334 1335 1336 1337 1338 1339 1340 1341
}

/**
 * pci_pme_active - enable or disable PCI device's PME# function
 * @dev: PCI device to handle.
 * @enable: 'true' to enable PME# generation; 'false' to disable it.
 *
 * The caller must verify that the device is capable of generating PME# before
 * calling this function with @enable equal to 'true'.
 */
1342
void pci_pme_active(struct pci_dev *dev, bool enable)
1343 1344 1345
{
	u16 pmcsr;

1346
	if (!dev->pm_cap)
1347 1348
		return;

1349
	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1350 1351 1352 1353 1354
	/* Clear PME_Status by writing 1 to it and enable PME# */
	pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
	if (!enable)
		pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;

1355
	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1356

B
Bjorn Helgaas 已提交
1357
	dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1358 1359 1360
			enable ? "enabled" : "disabled");
}

L
Linus Torvalds 已提交
1361
/**
1362
 * __pci_enable_wake - enable PCI device as wakeup event source
1363 1364
 * @dev: PCI device affected
 * @state: PCI state from which device will issue wakeup events
1365
 * @runtime: True if the events are to be generated at run time
1366 1367 1368 1369 1370 1371 1372
 * @enable: True to enable event generation; false to disable
 *
 * This enables the device as a wakeup event source, or disables it.
 * When such events involves platform-specific hooks, those hooks are
 * called automatically by this routine.
 *
 * Devices with legacy power management (no standard PCI PM capabilities)
1373
 * always require such platform hooks.
1374
 *
1375 1376 1377 1378 1379
 * RETURN VALUE:
 * 0 is returned on success
 * -EINVAL is returned if device is not supposed to wake up the system
 * Error code depending on the platform is returned if both the platform and
 * the native mechanism fail to enable the generation of wake-up events
L
Linus Torvalds 已提交
1380
 */
1381 1382
int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
		      bool runtime, bool enable)
L
Linus Torvalds 已提交
1383
{
1384
	int ret = 0;
1385

1386
	if (enable && !runtime && !device_may_wakeup(&dev->dev))
1387
		return -EINVAL;
L
Linus Torvalds 已提交
1388

1389 1390 1391 1392
	/* Don't do the same thing twice in a row for one device. */
	if (!!enable == !!dev->wakeup_prepared)
		return 0;

1393 1394 1395 1396
	/*
	 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
	 * Anderson we should be doing PME# wake enable followed by ACPI wake
	 * enable.  To disable wake-up we call the platform first, for symmetry.
1397
	 */
L
Linus Torvalds 已提交
1398

1399 1400
	if (enable) {
		int error;
L
Linus Torvalds 已提交
1401

1402 1403 1404 1405
		if (pci_pme_capable(dev, state))
			pci_pme_active(dev, true);
		else
			ret = 1;
1406 1407
		error = runtime ? platform_pci_run_wake(dev, true) :
					platform_pci_sleep_wake(dev, true);
1408 1409
		if (ret)
			ret = error;
1410 1411
		if (!ret)
			dev->wakeup_prepared = true;
1412
	} else {
1413 1414 1415 1416
		if (runtime)
			platform_pci_run_wake(dev, false);
		else
			platform_pci_sleep_wake(dev, false);
1417
		pci_pme_active(dev, false);
1418
		dev->wakeup_prepared = false;
1419
	}
L
Linus Torvalds 已提交
1420

1421
	return ret;
1422
}
1423
EXPORT_SYMBOL(__pci_enable_wake);
L
Linus Torvalds 已提交
1424

1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445
/**
 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
 * @dev: PCI device to prepare
 * @enable: True to enable wake-up event generation; false to disable
 *
 * Many drivers want the device to wake up the system from D3_hot or D3_cold
 * and this function allows them to set that up cleanly - pci_enable_wake()
 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
 * ordering constraints.
 *
 * This function only returns error code if the device is not capable of
 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
 * enable wake-up power for it.
 */
int pci_wake_from_d3(struct pci_dev *dev, bool enable)
{
	return pci_pme_capable(dev, PCI_D3cold) ?
			pci_enable_wake(dev, PCI_D3cold, enable) :
			pci_enable_wake(dev, PCI_D3hot, enable);
}

1446
/**
J
Jesse Barnes 已提交
1447 1448 1449 1450 1451 1452
 * pci_target_state - find an appropriate low power state for a given PCI dev
 * @dev: PCI device
 *
 * Use underlying platform code to find a supported low power state for @dev.
 * If the platform can't manage @dev, return the deepest state from which it
 * can generate wake events, based on any available PME info.
1453
 */
1454
pci_power_t pci_target_state(struct pci_dev *dev)
1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475
{
	pci_power_t target_state = PCI_D3hot;

	if (platform_pci_power_manageable(dev)) {
		/*
		 * Call the platform to choose the target state of the device
		 * and enable wake-up from this state if supported.
		 */
		pci_power_t state = platform_pci_choose_state(dev);

		switch (state) {
		case PCI_POWER_ERROR:
		case PCI_UNKNOWN:
			break;
		case PCI_D1:
		case PCI_D2:
			if (pci_no_d1d2(dev))
				break;
		default:
			target_state = state;
		}
1476 1477
	} else if (!dev->pm_cap) {
		target_state = PCI_D0;
1478 1479 1480 1481 1482 1483
	} else if (device_may_wakeup(&dev->dev)) {
		/*
		 * Find the deepest state from which the device can generate
		 * wake-up events, make it the target state and enable device
		 * to generate PME#.
		 */
1484 1485 1486 1487
		if (dev->pme_support) {
			while (target_state
			      && !(dev->pme_support & (1 << target_state)))
				target_state--;
1488 1489 1490
		}
	}

1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509
	return target_state;
}

/**
 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
 * @dev: Device to handle.
 *
 * Choose the power state appropriate for the device depending on whether
 * it can wake up the system and/or is power manageable by the platform
 * (PCI_D3hot is the default) and put the device into that state.
 */
int pci_prepare_to_sleep(struct pci_dev *dev)
{
	pci_power_t target_state = pci_target_state(dev);
	int error;

	if (target_state == PCI_POWER_ERROR)
		return -EIO;

1510
	pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1511

1512 1513 1514 1515 1516 1517 1518 1519 1520
	error = pci_set_power_state(dev, target_state);

	if (error)
		pci_enable_wake(dev, target_state, false);

	return error;
}

/**
R
Randy Dunlap 已提交
1521
 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1522 1523
 * @dev: Device to handle.
 *
T
Thomas Weber 已提交
1524
 * Disable device's system wake-up capability and put it into D0.
1525 1526 1527 1528 1529 1530 1531
 */
int pci_back_from_sleep(struct pci_dev *dev)
{
	pci_enable_wake(dev, PCI_D0, false);
	return pci_set_power_state(dev, PCI_D0);
}

1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
/**
 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
 * @dev: PCI device being suspended.
 *
 * Prepare @dev to generate wake-up events at run time and put it into a low
 * power state.
 */
int pci_finish_runtime_suspend(struct pci_dev *dev)
{
	pci_power_t target_state = pci_target_state(dev);
	int error;

	if (target_state == PCI_POWER_ERROR)
		return -EIO;

	__pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));

	error = pci_set_power_state(dev, target_state);

	if (error)
		__pci_enable_wake(dev, target_state, true, false);

	return error;
}

1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591
/**
 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
 * @dev: Device to check.
 *
 * Return true if the device itself is cabable of generating wake-up events
 * (through the platform or using the native PCIe PME) or if the device supports
 * PME and one of its upstream bridges can generate wake-up events.
 */
bool pci_dev_run_wake(struct pci_dev *dev)
{
	struct pci_bus *bus = dev->bus;

	if (device_run_wake(&dev->dev))
		return true;

	if (!dev->pme_support)
		return false;

	while (bus->parent) {
		struct pci_dev *bridge = bus->self;

		if (device_run_wake(&bridge->dev))
			return true;

		bus = bus->parent;
	}

	/* We have reached the root bus. */
	if (bus->bridge)
		return device_run_wake(bus->bridge);

	return false;
}
EXPORT_SYMBOL_GPL(pci_dev_run_wake);

1592 1593 1594 1595 1596 1597 1598 1599
/**
 * pci_pm_init - Initialize PM functions of given PCI device
 * @dev: PCI device to handle.
 */
void pci_pm_init(struct pci_dev *dev)
{
	int pm;
	u16 pmc;
L
Linus Torvalds 已提交
1600

1601
	pm_runtime_forbid(&dev->dev);
1602
	device_enable_async_suspend(&dev->dev);
1603
	dev->wakeup_prepared = false;
1604

1605 1606
	dev->pm_cap = 0;

1607 1608 1609
	/* find PCI PM capability in list */
	pm = pci_find_capability(dev, PCI_CAP_ID_PM);
	if (!pm)
1610
		return;
1611 1612
	/* Check device's ability to generate PME# */
	pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1613

1614 1615 1616
	if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
		dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
			pmc & PCI_PM_CAP_VER_MASK);
1617
		return;
1618 1619
	}

1620
	dev->pm_cap = pm;
1621
	dev->d3_delay = PCI_PM_D3_WAIT;
1622 1623 1624 1625

	dev->d1_support = false;
	dev->d2_support = false;
	if (!pci_no_d1d2(dev)) {
B
Bjorn Helgaas 已提交
1626
		if (pmc & PCI_PM_CAP_D1)
1627
			dev->d1_support = true;
B
Bjorn Helgaas 已提交
1628
		if (pmc & PCI_PM_CAP_D2)
1629
			dev->d2_support = true;
B
Bjorn Helgaas 已提交
1630 1631 1632

		if (dev->d1_support || dev->d2_support)
			dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1633 1634
				   dev->d1_support ? " D1" : "",
				   dev->d2_support ? " D2" : "");
1635 1636 1637 1638
	}

	pmc &= PCI_PM_CAP_PME_MASK;
	if (pmc) {
B
Bjorn Helgaas 已提交
1639 1640
		dev_printk(KERN_DEBUG, &dev->dev,
			 "PME# supported from%s%s%s%s%s\n",
B
Bjorn Helgaas 已提交
1641 1642 1643 1644 1645
			 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
			 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
			 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
			 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
			 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1646
		dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1647 1648 1649 1650 1651 1652
		/*
		 * Make device's PM flags reflect the wake-up capability, but
		 * let the user space enable it to wake up the system as needed.
		 */
		device_set_wakeup_capable(&dev->dev, true);
		/* Disable the PME# generation functionality */
1653 1654 1655
		pci_pme_active(dev, false);
	} else {
		dev->pme_support = 0;
1656
	}
L
Linus Torvalds 已提交
1657 1658
}

1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677
/**
 * platform_pci_wakeup_init - init platform wakeup if present
 * @dev: PCI device
 *
 * Some devices don't have PCI PM caps but can still generate wakeup
 * events through platform methods (like ACPI events).  If @dev supports
 * platform wakeup events, set the device flag to indicate as much.  This
 * may be redundant if the device also supports PCI PM caps, but double
 * initialization should be safe in that case.
 */
void platform_pci_wakeup_init(struct pci_dev *dev)
{
	if (!platform_pci_can_wakeup(dev))
		return;

	device_set_wakeup_capable(&dev->dev, true);
	platform_pci_sleep_wake(dev, false);
}

1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711
/**
 * pci_add_save_buffer - allocate buffer for saving given capability registers
 * @dev: the PCI device
 * @cap: the capability to allocate the buffer for
 * @size: requested size of the buffer
 */
static int pci_add_cap_save_buffer(
	struct pci_dev *dev, char cap, unsigned int size)
{
	int pos;
	struct pci_cap_saved_state *save_state;

	pos = pci_find_capability(dev, cap);
	if (pos <= 0)
		return 0;

	save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
	if (!save_state)
		return -ENOMEM;

	save_state->cap_nr = cap;
	pci_add_saved_cap(dev, save_state);

	return 0;
}

/**
 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
 * @dev: the PCI device
 */
void pci_allocate_cap_save_buffers(struct pci_dev *dev)
{
	int error;

1712 1713
	error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
					PCI_EXP_SAVE_REGS * sizeof(u16));
1714 1715 1716 1717 1718 1719 1720 1721 1722 1723
	if (error)
		dev_err(&dev->dev,
			"unable to preallocate PCI Express save buffer\n");

	error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
	if (error)
		dev_err(&dev->dev,
			"unable to preallocate PCI-X save buffer\n");
}

Y
Yu Zhao 已提交
1724 1725 1726 1727 1728 1729 1730 1731 1732
/**
 * pci_enable_ari - enable ARI forwarding if hardware support it
 * @dev: the PCI device
 */
void pci_enable_ari(struct pci_dev *dev)
{
	int pos;
	u32 cap;
	u16 ctrl;
1733
	struct pci_dev *bridge;
Y
Yu Zhao 已提交
1734

1735
	if (!pci_is_pcie(dev) || dev->devfn)
Y
Yu Zhao 已提交
1736 1737
		return;

1738 1739
	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
	if (!pos)
Y
Yu Zhao 已提交
1740 1741
		return;

1742
	bridge = dev->bus->self;
1743
	if (!bridge || !pci_is_pcie(bridge))
1744 1745
		return;

1746
	pos = pci_pcie_cap(bridge);
Y
Yu Zhao 已提交
1747 1748 1749
	if (!pos)
		return;

1750
	pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
Y
Yu Zhao 已提交
1751 1752 1753
	if (!(cap & PCI_EXP_DEVCAP2_ARI))
		return;

1754
	pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
Y
Yu Zhao 已提交
1755
	ctrl |= PCI_EXP_DEVCTL2_ARI;
1756
	pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
Y
Yu Zhao 已提交
1757

1758
	bridge->ari_enabled = 1;
Y
Yu Zhao 已提交
1759 1760
}

C
Chris Wright 已提交
1761 1762 1763 1764 1765 1766 1767 1768 1769 1770
static int pci_acs_enable;

/**
 * pci_request_acs - ask for ACS to be enabled if supported
 */
void pci_request_acs(void)
{
	pci_acs_enable = 1;
}

1771 1772 1773 1774 1775 1776 1777 1778 1779 1780
/**
 * pci_enable_acs - enable ACS if hardware support it
 * @dev: the PCI device
 */
void pci_enable_acs(struct pci_dev *dev)
{
	int pos;
	u16 cap;
	u16 ctrl;

C
Chris Wright 已提交
1781 1782 1783
	if (!pci_acs_enable)
		return;

1784
	if (!pci_is_pcie(dev))
1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808
		return;

	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
	if (!pos)
		return;

	pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
	pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);

	/* Source Validation */
	ctrl |= (cap & PCI_ACS_SV);

	/* P2P Request Redirect */
	ctrl |= (cap & PCI_ACS_RR);

	/* P2P Completion Redirect */
	ctrl |= (cap & PCI_ACS_CR);

	/* Upstream Forwarding */
	ctrl |= (cap & PCI_ACS_UF);

	pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
}

1809 1810 1811 1812 1813 1814 1815
/**
 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
 * @dev: the PCI device
 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
 *
 * Perform INTx swizzling for a device behind one level of bridge.  This is
 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1816 1817 1818
 * behind bridges on add-in cards.  For devices with ARI enabled, the slot
 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
 * the PCI Express Base Specification, Revision 2.1)
1819 1820 1821
 */
u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
{
1822 1823 1824 1825 1826 1827 1828 1829
	int slot;

	if (pci_ari_enabled(dev->bus))
		slot = 0;
	else
		slot = PCI_SLOT(dev->devfn);

	return (((pin - 1) + slot) % 4) + 1;
1830 1831
}

L
Linus Torvalds 已提交
1832 1833 1834 1835 1836
int
pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
{
	u8 pin;

1837
	pin = dev->pin;
L
Linus Torvalds 已提交
1838 1839
	if (!pin)
		return -1;
1840

1841
	while (!pci_is_root_bus(dev->bus)) {
1842
		pin = pci_swizzle_interrupt_pin(dev, pin);
L
Linus Torvalds 已提交
1843 1844 1845 1846 1847 1848
		dev = dev->bus->self;
	}
	*bridge = dev;
	return pin;
}

1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860
/**
 * pci_common_swizzle - swizzle INTx all the way to root bridge
 * @dev: the PCI device
 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
 *
 * Perform INTx swizzling for a device.  This traverses through all PCI-to-PCI
 * bridges all the way up to a PCI root bus.
 */
u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
{
	u8 pin = *pinp;

1861
	while (!pci_is_root_bus(dev->bus)) {
1862 1863 1864 1865 1866 1867 1868
		pin = pci_swizzle_interrupt_pin(dev, pin);
		dev = dev->bus->self;
	}
	*pinp = pin;
	return PCI_SLOT(dev->devfn);
}

L
Linus Torvalds 已提交
1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879
/**
 *	pci_release_region - Release a PCI bar
 *	@pdev: PCI device whose resources were previously reserved by pci_request_region
 *	@bar: BAR to release
 *
 *	Releases the PCI I/O and memory resources previously reserved by a
 *	successful call to pci_request_region.  Call this function only
 *	after all use of the PCI regions has ceased.
 */
void pci_release_region(struct pci_dev *pdev, int bar)
{
T
Tejun Heo 已提交
1880 1881
	struct pci_devres *dr;

L
Linus Torvalds 已提交
1882 1883 1884 1885 1886 1887 1888 1889
	if (pci_resource_len(pdev, bar) == 0)
		return;
	if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
		release_region(pci_resource_start(pdev, bar),
				pci_resource_len(pdev, bar));
	else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
		release_mem_region(pci_resource_start(pdev, bar),
				pci_resource_len(pdev, bar));
T
Tejun Heo 已提交
1890 1891 1892 1893

	dr = find_pci_dr(pdev);
	if (dr)
		dr->region_mask &= ~(1 << bar);
L
Linus Torvalds 已提交
1894 1895 1896
}

/**
1897
 *	__pci_request_region - Reserved PCI I/O and memory resource
L
Linus Torvalds 已提交
1898 1899 1900
 *	@pdev: PCI device whose resources are to be reserved
 *	@bar: BAR to be reserved
 *	@res_name: Name to be associated with resource.
1901
 *	@exclusive: whether the region access is exclusive or not
L
Linus Torvalds 已提交
1902 1903 1904 1905 1906 1907
 *
 *	Mark the PCI region associated with PCI device @pdev BR @bar as
 *	being reserved by owner @res_name.  Do not access any
 *	address inside the PCI regions unless this call returns
 *	successfully.
 *
1908 1909 1910 1911
 *	If @exclusive is set, then the region is marked so that userspace
 *	is explicitly not allowed to map the resource via /dev/mem or
 * 	sysfs MMIO access.
 *
L
Linus Torvalds 已提交
1912 1913 1914
 *	Returns 0 on success, or %EBUSY on error.  A warning
 *	message is also printed on failure.
 */
1915 1916
static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
									int exclusive)
L
Linus Torvalds 已提交
1917
{
T
Tejun Heo 已提交
1918 1919
	struct pci_devres *dr;

L
Linus Torvalds 已提交
1920 1921 1922 1923 1924 1925 1926 1927 1928
	if (pci_resource_len(pdev, bar) == 0)
		return 0;
		
	if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
		if (!request_region(pci_resource_start(pdev, bar),
			    pci_resource_len(pdev, bar), res_name))
			goto err_out;
	}
	else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1929 1930 1931
		if (!__request_mem_region(pci_resource_start(pdev, bar),
					pci_resource_len(pdev, bar), res_name,
					exclusive))
L
Linus Torvalds 已提交
1932 1933
			goto err_out;
	}
T
Tejun Heo 已提交
1934 1935 1936 1937 1938

	dr = find_pci_dr(pdev);
	if (dr)
		dr->region_mask |= 1 << bar;

L
Linus Torvalds 已提交
1939 1940 1941
	return 0;

err_out:
1942
	dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
1943
		 &pdev->resource[bar]);
L
Linus Torvalds 已提交
1944 1945 1946
	return -EBUSY;
}

1947
/**
1948
 *	pci_request_region - Reserve PCI I/O and memory resource
1949 1950
 *	@pdev: PCI device whose resources are to be reserved
 *	@bar: BAR to be reserved
1951
 *	@res_name: Name to be associated with resource
1952
 *
1953
 *	Mark the PCI region associated with PCI device @pdev BAR @bar as
1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987
 *	being reserved by owner @res_name.  Do not access any
 *	address inside the PCI regions unless this call returns
 *	successfully.
 *
 *	Returns 0 on success, or %EBUSY on error.  A warning
 *	message is also printed on failure.
 */
int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
{
	return __pci_request_region(pdev, bar, res_name, 0);
}

/**
 *	pci_request_region_exclusive - Reserved PCI I/O and memory resource
 *	@pdev: PCI device whose resources are to be reserved
 *	@bar: BAR to be reserved
 *	@res_name: Name to be associated with resource.
 *
 *	Mark the PCI region associated with PCI device @pdev BR @bar as
 *	being reserved by owner @res_name.  Do not access any
 *	address inside the PCI regions unless this call returns
 *	successfully.
 *
 *	Returns 0 on success, or %EBUSY on error.  A warning
 *	message is also printed on failure.
 *
 *	The key difference that _exclusive makes it that userspace is
 *	explicitly not allowed to map the resource via /dev/mem or
 * 	sysfs.
 */
int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
{
	return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
}
1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004
/**
 * pci_release_selected_regions - Release selected PCI I/O and memory resources
 * @pdev: PCI device whose resources were previously reserved
 * @bars: Bitmask of BARs to be released
 *
 * Release selected PCI I/O and memory resources previously reserved.
 * Call this function only after all use of the PCI regions has ceased.
 */
void pci_release_selected_regions(struct pci_dev *pdev, int bars)
{
	int i;

	for (i = 0; i < 6; i++)
		if (bars & (1 << i))
			pci_release_region(pdev, i);
}

2005 2006
int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
				 const char *res_name, int excl)
2007 2008 2009 2010 2011
{
	int i;

	for (i = 0; i < 6; i++)
		if (bars & (1 << i))
2012
			if (__pci_request_region(pdev, i, res_name, excl))
2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
				goto err_out;
	return 0;

err_out:
	while(--i >= 0)
		if (bars & (1 << i))
			pci_release_region(pdev, i);

	return -EBUSY;
}
L
Linus Torvalds 已提交
2023

2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043

/**
 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
 * @pdev: PCI device whose resources are to be reserved
 * @bars: Bitmask of BARs to be requested
 * @res_name: Name to be associated with resource
 */
int pci_request_selected_regions(struct pci_dev *pdev, int bars,
				 const char *res_name)
{
	return __pci_request_selected_regions(pdev, bars, res_name, 0);
}

int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
				 int bars, const char *res_name)
{
	return __pci_request_selected_regions(pdev, bars, res_name,
			IORESOURCE_EXCLUSIVE);
}

L
Linus Torvalds 已提交
2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054
/**
 *	pci_release_regions - Release reserved PCI I/O and memory resources
 *	@pdev: PCI device whose resources were previously reserved by pci_request_regions
 *
 *	Releases all PCI I/O and memory resources previously reserved by a
 *	successful call to pci_request_regions.  Call this function only
 *	after all use of the PCI regions has ceased.
 */

void pci_release_regions(struct pci_dev *pdev)
{
2055
	pci_release_selected_regions(pdev, (1 << 6) - 1);
L
Linus Torvalds 已提交
2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070
}

/**
 *	pci_request_regions - Reserved PCI I/O and memory resources
 *	@pdev: PCI device whose resources are to be reserved
 *	@res_name: Name to be associated with resource.
 *
 *	Mark all PCI regions associated with PCI device @pdev as
 *	being reserved by owner @res_name.  Do not access any
 *	address inside the PCI regions unless this call returns
 *	successfully.
 *
 *	Returns 0 on success, or %EBUSY on error.  A warning
 *	message is also printed on failure.
 */
2071
int pci_request_regions(struct pci_dev *pdev, const char *res_name)
L
Linus Torvalds 已提交
2072
{
2073
	return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
L
Linus Torvalds 已提交
2074 2075
}

2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097
/**
 *	pci_request_regions_exclusive - Reserved PCI I/O and memory resources
 *	@pdev: PCI device whose resources are to be reserved
 *	@res_name: Name to be associated with resource.
 *
 *	Mark all PCI regions associated with PCI device @pdev as
 *	being reserved by owner @res_name.  Do not access any
 *	address inside the PCI regions unless this call returns
 *	successfully.
 *
 *	pci_request_regions_exclusive() will mark the region so that
 * 	/dev/mem and the sysfs MMIO access will not be allowed.
 *
 *	Returns 0 on success, or %EBUSY on error.  A warning
 *	message is also printed on failure.
 */
int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
{
	return pci_request_selected_regions_exclusive(pdev,
					((1 << 6) - 1), res_name);
}

2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113
static void __pci_set_master(struct pci_dev *dev, bool enable)
{
	u16 old_cmd, cmd;

	pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
	if (enable)
		cmd = old_cmd | PCI_COMMAND_MASTER;
	else
		cmd = old_cmd & ~PCI_COMMAND_MASTER;
	if (cmd != old_cmd) {
		dev_dbg(&dev->dev, "%s bus mastering\n",
			enable ? "enabling" : "disabling");
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	dev->is_busmaster = enable;
}
2114

L
Linus Torvalds 已提交
2115 2116 2117 2118 2119 2120 2121
/**
 * pci_set_master - enables bus-mastering for device dev
 * @dev: the PCI device to enable
 *
 * Enables bus-mastering on the device and calls pcibios_set_master()
 * to do the needed arch specific settings.
 */
2122
void pci_set_master(struct pci_dev *dev)
L
Linus Torvalds 已提交
2123
{
2124
	__pci_set_master(dev, true);
L
Linus Torvalds 已提交
2125 2126 2127
	pcibios_set_master(dev);
}

2128 2129 2130 2131 2132 2133 2134 2135 2136
/**
 * pci_clear_master - disables bus-mastering for device dev
 * @dev: the PCI device to disable
 */
void pci_clear_master(struct pci_dev *dev)
{
	__pci_set_master(dev, false);
}

L
Linus Torvalds 已提交
2137
/**
2138 2139
 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
 * @dev: the PCI device for which MWI is to be enabled
L
Linus Torvalds 已提交
2140
 *
2141 2142
 * Helper function for pci_set_mwi.
 * Originally copied from drivers/net/acenic.c.
L
Linus Torvalds 已提交
2143 2144 2145 2146
 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
 *
 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 */
T
Tejun Heo 已提交
2147
int pci_set_cacheline_size(struct pci_dev *dev)
L
Linus Torvalds 已提交
2148 2149 2150 2151
{
	u8 cacheline_size;

	if (!pci_cache_line_size)
T
Tejun Heo 已提交
2152
		return -EINVAL;
L
Linus Torvalds 已提交
2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167

	/* Validate current setting: the PCI_CACHE_LINE_SIZE must be
	   equal to or multiple of the right value. */
	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
	if (cacheline_size >= pci_cache_line_size &&
	    (cacheline_size % pci_cache_line_size) == 0)
		return 0;

	/* Write the correct value. */
	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
	/* Read it back. */
	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
	if (cacheline_size == pci_cache_line_size)
		return 0;

2168 2169
	dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
		   "supported\n", pci_cache_line_size << 2);
L
Linus Torvalds 已提交
2170 2171 2172

	return -EINVAL;
}
T
Tejun Heo 已提交
2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190
EXPORT_SYMBOL_GPL(pci_set_cacheline_size);

#ifdef PCI_DISABLE_MWI
int pci_set_mwi(struct pci_dev *dev)
{
	return 0;
}

int pci_try_set_mwi(struct pci_dev *dev)
{
	return 0;
}

void pci_clear_mwi(struct pci_dev *dev)
{
}

#else
L
Linus Torvalds 已提交
2191 2192 2193 2194 2195

/**
 * pci_set_mwi - enables memory-write-invalidate PCI transaction
 * @dev: the PCI device for which MWI is enabled
 *
R
Randy Dunlap 已提交
2196
 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
L
Linus Torvalds 已提交
2197 2198 2199 2200 2201 2202 2203 2204 2205
 *
 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 */
int
pci_set_mwi(struct pci_dev *dev)
{
	int rc;
	u16 cmd;

2206
	rc = pci_set_cacheline_size(dev);
L
Linus Torvalds 已提交
2207 2208 2209 2210 2211
	if (rc)
		return rc;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2212
		dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
L
Linus Torvalds 已提交
2213 2214 2215 2216 2217 2218 2219
		cmd |= PCI_COMMAND_INVALIDATE;
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	
	return 0;
}

R
Randy Dunlap 已提交
2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234
/**
 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
 * @dev: the PCI device for which MWI is enabled
 *
 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
 * Callers are not required to check the return value.
 *
 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
 */
int pci_try_set_mwi(struct pci_dev *dev)
{
	int rc = pci_set_mwi(dev);
	return rc;
}

L
Linus Torvalds 已提交
2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251
/**
 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
 * @dev: the PCI device to disable
 *
 * Disables PCI Memory-Write-Invalidate transaction on the device
 */
void
pci_clear_mwi(struct pci_dev *dev)
{
	u16 cmd;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (cmd & PCI_COMMAND_INVALIDATE) {
		cmd &= ~PCI_COMMAND_INVALIDATE;
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
}
2252
#endif /* ! PCI_DISABLE_MWI */
L
Linus Torvalds 已提交
2253

B
Brett M Russ 已提交
2254 2255
/**
 * pci_intx - enables/disables PCI INTx for device dev
R
Randy Dunlap 已提交
2256 2257
 * @pdev: the PCI device to operate on
 * @enable: boolean: whether to enable or disable PCI INTx
B
Brett M Russ 已提交
2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274
 *
 * Enables/disables PCI INTx for device dev
 */
void
pci_intx(struct pci_dev *pdev, int enable)
{
	u16 pci_command, new;

	pci_read_config_word(pdev, PCI_COMMAND, &pci_command);

	if (enable) {
		new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
	} else {
		new = pci_command | PCI_COMMAND_INTX_DISABLE;
	}

	if (new != pci_command) {
T
Tejun Heo 已提交
2275 2276
		struct pci_devres *dr;

2277
		pci_write_config_word(pdev, PCI_COMMAND, new);
T
Tejun Heo 已提交
2278 2279 2280 2281 2282 2283

		dr = find_pci_dr(pdev);
		if (dr && !dr->restore_intx) {
			dr->restore_intx = 1;
			dr->orig_intx = !enable;
		}
B
Brett M Russ 已提交
2284 2285 2286
	}
}

2287 2288
/**
 * pci_msi_off - disables any msi or msix capabilities
R
Randy Dunlap 已提交
2289
 * @dev: the PCI device to operate on
2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312
 *
 * If you want to use msi see pci_enable_msi and friends.
 * This is a lower level primitive that allows us to disable
 * msi operation at the device level.
 */
void pci_msi_off(struct pci_dev *dev)
{
	int pos;
	u16 control;

	pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
	if (pos) {
		pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
		control &= ~PCI_MSI_FLAGS_ENABLE;
		pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
	}
	pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
	if (pos) {
		pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
		control &= ~PCI_MSIX_FLAGS_ENABLE;
		pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
	}
}
2313
EXPORT_SYMBOL_GPL(pci_msi_off);
2314

2315 2316 2317 2318 2319 2320 2321 2322
#ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
{
	return dma_set_max_seg_size(&dev->dev, size);
}
EXPORT_SYMBOL(pci_set_dma_max_seg_size);
#endif

2323 2324 2325 2326 2327 2328 2329 2330
#ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
{
	return dma_set_seg_boundary(&dev->dev, mask);
}
EXPORT_SYMBOL(pci_set_dma_seg_boundary);
#endif

Y
Yu Zhao 已提交
2331
static int pcie_flr(struct pci_dev *dev, int probe)
2332
{
Y
Yu Zhao 已提交
2333 2334
	int i;
	int pos;
2335
	u32 cap;
2336
	u16 status, control;
2337

2338
	pos = pci_pcie_cap(dev);
Y
Yu Zhao 已提交
2339
	if (!pos)
2340
		return -ENOTTY;
Y
Yu Zhao 已提交
2341 2342

	pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2343 2344 2345
	if (!(cap & PCI_EXP_DEVCAP_FLR))
		return -ENOTTY;

S
Sheng Yang 已提交
2346 2347 2348
	if (probe)
		return 0;

2349
	/* Wait for Transaction Pending bit clean */
Y
Yu Zhao 已提交
2350 2351 2352
	for (i = 0; i < 4; i++) {
		if (i)
			msleep((1 << (i - 1)) * 100);
S
Sheng Yang 已提交
2353

Y
Yu Zhao 已提交
2354 2355 2356 2357 2358 2359 2360 2361 2362
		pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
		if (!(status & PCI_EXP_DEVSTA_TRPND))
			goto clear;
	}

	dev_err(&dev->dev, "transaction is not cleared; "
			"proceeding with reset anyway\n");

clear:
2363 2364 2365 2366
	pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
	control |= PCI_EXP_DEVCTL_BCR_FLR;
	pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);

Y
Yu Zhao 已提交
2367
	msleep(100);
2368 2369 2370

	return 0;
}
S
Sheng Yang 已提交
2371

Y
Yu Zhao 已提交
2372
static int pci_af_flr(struct pci_dev *dev, int probe)
2373
{
Y
Yu Zhao 已提交
2374 2375
	int i;
	int pos;
2376
	u8 cap;
Y
Yu Zhao 已提交
2377
	u8 status;
2378

Y
Yu Zhao 已提交
2379 2380
	pos = pci_find_capability(dev, PCI_CAP_ID_AF);
	if (!pos)
2381
		return -ENOTTY;
Y
Yu Zhao 已提交
2382 2383

	pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2384 2385 2386 2387 2388 2389 2390
	if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
		return -ENOTTY;

	if (probe)
		return 0;

	/* Wait for Transaction Pending bit clean */
Y
Yu Zhao 已提交
2391 2392 2393 2394 2395 2396 2397 2398
	for (i = 0; i < 4; i++) {
		if (i)
			msleep((1 << (i - 1)) * 100);

		pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
		if (!(status & PCI_AF_STATUS_TP))
			goto clear;
	}
S
Sheng Yang 已提交
2399

Y
Yu Zhao 已提交
2400 2401
	dev_err(&dev->dev, "transaction is not cleared; "
			"proceeding with reset anyway\n");
S
Sheng Yang 已提交
2402

Y
Yu Zhao 已提交
2403 2404
clear:
	pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2405
	msleep(100);
Y
Yu Zhao 已提交
2406

2407 2408 2409
	return 0;
}

2410
static int pci_pm_reset(struct pci_dev *dev, int probe)
S
Sheng Yang 已提交
2411
{
2412 2413 2414 2415
	u16 csr;

	if (!dev->pm_cap)
		return -ENOTTY;
S
Sheng Yang 已提交
2416

2417 2418 2419
	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
	if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
		return -ENOTTY;
S
Sheng Yang 已提交
2420

2421 2422
	if (probe)
		return 0;
2423

2424 2425 2426 2427 2428 2429
	if (dev->current_state != PCI_D0)
		return -EINVAL;

	csr &= ~PCI_PM_CTRL_STATE_MASK;
	csr |= PCI_D3hot;
	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2430
	pci_dev_d3_sleep(dev);
2431 2432 2433 2434

	csr &= ~PCI_PM_CTRL_STATE_MASK;
	csr |= PCI_D0;
	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2435
	pci_dev_d3_sleep(dev);
2436 2437 2438 2439

	return 0;
}

Y
Yu Zhao 已提交
2440 2441 2442 2443 2444
static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
{
	u16 ctrl;
	struct pci_dev *pdev;

2445
	if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
Y
Yu Zhao 已提交
2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466
		return -ENOTTY;

	list_for_each_entry(pdev, &dev->bus->devices, bus_list)
		if (pdev != dev)
			return -ENOTTY;

	if (probe)
		return 0;

	pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
	ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
	pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
	msleep(100);

	ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
	pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
	msleep(100);

	return 0;
}

Y
Yu Zhao 已提交
2467
static int pci_dev_reset(struct pci_dev *dev, int probe)
S
Sheng Yang 已提交
2468
{
Y
Yu Zhao 已提交
2469 2470 2471 2472 2473 2474 2475
	int rc;

	might_sleep();

	if (!probe) {
		pci_block_user_cfg_access(dev);
		/* block PM suspend, driver probe, etc. */
2476
		device_lock(&dev->dev);
Y
Yu Zhao 已提交
2477
	}
S
Sheng Yang 已提交
2478

2479 2480 2481 2482
	rc = pci_dev_specific_reset(dev, probe);
	if (rc != -ENOTTY)
		goto done;

Y
Yu Zhao 已提交
2483 2484 2485
	rc = pcie_flr(dev, probe);
	if (rc != -ENOTTY)
		goto done;
S
Sheng Yang 已提交
2486

Y
Yu Zhao 已提交
2487
	rc = pci_af_flr(dev, probe);
2488 2489 2490 2491
	if (rc != -ENOTTY)
		goto done;

	rc = pci_pm_reset(dev, probe);
Y
Yu Zhao 已提交
2492 2493 2494 2495
	if (rc != -ENOTTY)
		goto done;

	rc = pci_parent_bus_reset(dev, probe);
Y
Yu Zhao 已提交
2496 2497
done:
	if (!probe) {
2498
		device_unlock(&dev->dev);
Y
Yu Zhao 已提交
2499 2500
		pci_unblock_user_cfg_access(dev);
	}
2501

Y
Yu Zhao 已提交
2502
	return rc;
S
Sheng Yang 已提交
2503 2504 2505
}

/**
Y
Yu Zhao 已提交
2506 2507
 * __pci_reset_function - reset a PCI device function
 * @dev: PCI device to reset
S
Sheng Yang 已提交
2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518
 *
 * Some devices allow an individual function to be reset without affecting
 * other functions in the same device.  The PCI device must be responsive
 * to PCI config space in order to use this function.
 *
 * The device function is presumed to be unused when this function is called.
 * Resetting the device will make the contents of PCI configuration space
 * random, so any caller of this must be prepared to reinitialise the
 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
 * etc.
 *
Y
Yu Zhao 已提交
2519
 * Returns 0 if the device function was successfully reset or negative if the
S
Sheng Yang 已提交
2520 2521
 * device doesn't support resetting a single function.
 */
Y
Yu Zhao 已提交
2522
int __pci_reset_function(struct pci_dev *dev)
S
Sheng Yang 已提交
2523
{
Y
Yu Zhao 已提交
2524
	return pci_dev_reset(dev, 0);
S
Sheng Yang 已提交
2525
}
Y
Yu Zhao 已提交
2526
EXPORT_SYMBOL_GPL(__pci_reset_function);
2527

2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543
/**
 * pci_probe_reset_function - check whether the device can be safely reset
 * @dev: PCI device to reset
 *
 * Some devices allow an individual function to be reset without affecting
 * other functions in the same device.  The PCI device must be responsive
 * to PCI config space in order to use this function.
 *
 * Returns 0 if the device function can be reset or negative if the
 * device doesn't support resetting a single function.
 */
int pci_probe_reset_function(struct pci_dev *dev)
{
	return pci_dev_reset(dev, 1);
}

2544
/**
Y
Yu Zhao 已提交
2545 2546
 * pci_reset_function - quiesce and reset a PCI device function
 * @dev: PCI device to reset
2547 2548 2549 2550 2551 2552 2553
 *
 * Some devices allow an individual function to be reset without affecting
 * other functions in the same device.  The PCI device must be responsive
 * to PCI config space in order to use this function.
 *
 * This function does not just reset the PCI portion of a device, but
 * clears all the state associated with the device.  This function differs
Y
Yu Zhao 已提交
2554
 * from __pci_reset_function in that it saves and restores device state
2555 2556
 * over the reset.
 *
Y
Yu Zhao 已提交
2557
 * Returns 0 if the device function was successfully reset or negative if the
2558 2559 2560 2561
 * device doesn't support resetting a single function.
 */
int pci_reset_function(struct pci_dev *dev)
{
Y
Yu Zhao 已提交
2562
	int rc;
2563

Y
Yu Zhao 已提交
2564 2565 2566
	rc = pci_dev_reset(dev, 1);
	if (rc)
		return rc;
2567 2568 2569

	pci_save_state(dev);

Y
Yu Zhao 已提交
2570 2571 2572 2573
	/*
	 * both INTx and MSI are disabled after the Interrupt Disable bit
	 * is set and the Bus Master bit is cleared.
	 */
2574 2575
	pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);

Y
Yu Zhao 已提交
2576
	rc = pci_dev_reset(dev, 0);
2577 2578 2579

	pci_restore_state(dev);

Y
Yu Zhao 已提交
2580
	return rc;
2581 2582 2583
}
EXPORT_SYMBOL_GPL(pci_reset_function);

2584 2585 2586 2587 2588 2589 2590 2591 2592
/**
 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
 * @dev: PCI device to query
 *
 * Returns mmrbc: maximum designed memory read count in bytes
 *    or appropriate error value.
 */
int pcix_get_max_mmrbc(struct pci_dev *dev)
{
2593
	int cap;
2594 2595 2596 2597 2598 2599
	u32 stat;

	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
	if (!cap)
		return -EINVAL;

2600
	if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2601 2602
		return -EINVAL;

2603
	return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615
}
EXPORT_SYMBOL(pcix_get_max_mmrbc);

/**
 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
 * @dev: PCI device to query
 *
 * Returns mmrbc: maximum memory read count in bytes
 *    or appropriate error value.
 */
int pcix_get_mmrbc(struct pci_dev *dev)
{
2616
	int cap;
2617
	u16 cmd;
2618 2619 2620 2621 2622

	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
	if (!cap)
		return -EINVAL;

2623 2624
	if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
		return -EINVAL;
2625

2626
	return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640
}
EXPORT_SYMBOL(pcix_get_mmrbc);

/**
 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
 * @dev: PCI device to query
 * @mmrbc: maximum memory read count in bytes
 *    valid values are 512, 1024, 2048, 4096
 *
 * If possible sets maximum memory read byte count, some bridges have erratas
 * that prevent this.
 */
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
{
2641
	int cap;
2642 2643
	u32 stat, v, o;
	u16 cmd;
2644

2645
	if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2646
		return -EINVAL;
2647 2648 2649 2650 2651

	v = ffs(mmrbc) - 10;

	cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
	if (!cap)
2652
		return -EINVAL;
2653

2654 2655
	if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
		return -EINVAL;
2656 2657 2658 2659

	if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
		return -E2BIG;

2660 2661
	if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
		return -EINVAL;
2662 2663 2664 2665 2666 2667 2668 2669 2670

	o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
	if (o != v) {
		if (v > o && dev->bus &&
		   (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
			return -EIO;

		cmd &= ~PCI_X_CMD_MAX_READ;
		cmd |= v << 2;
2671 2672
		if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
			return -EIO;
2673
	}
2674
	return 0;
2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689
}
EXPORT_SYMBOL(pcix_set_mmrbc);

/**
 * pcie_get_readrq - get PCI Express read request size
 * @dev: PCI device to query
 *
 * Returns maximum memory read request in bytes
 *    or appropriate error value.
 */
int pcie_get_readrq(struct pci_dev *dev)
{
	int ret, cap;
	u16 ctl;

2690
	cap = pci_pcie_cap(dev);
2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704
	if (!cap)
		return -EINVAL;

	ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
	if (!ret)
	ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);

	return ret;
}
EXPORT_SYMBOL(pcie_get_readrq);

/**
 * pcie_set_readrq - set PCI Express maximum memory read request
 * @dev: PCI device to query
2705
 * @rq: maximum memory read count in bytes
2706 2707 2708 2709 2710 2711 2712 2713 2714
 *    valid values are 128, 256, 512, 1024, 2048, 4096
 *
 * If possible sets maximum read byte count
 */
int pcie_set_readrq(struct pci_dev *dev, int rq)
{
	int cap, err = -EINVAL;
	u16 ctl, v;

2715
	if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2716 2717 2718 2719
		goto out;

	v = (ffs(rq) - 8) << 12;

2720
	cap = pci_pcie_cap(dev);
2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738
	if (!cap)
		goto out;

	err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
	if (err)
		goto out;

	if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
		ctl &= ~PCI_EXP_DEVCTL_READRQ;
		ctl |= v;
		err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
	}

out:
	return err;
}
EXPORT_SYMBOL(pcie_set_readrq);

2739 2740
/**
 * pci_select_bars - Make BAR mask from the type of resource
2741
 * @dev: the PCI device for which BAR mask is made
2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754
 * @flags: resource type mask to be selected
 *
 * This helper routine makes bar mask from the type of resource.
 */
int pci_select_bars(struct pci_dev *dev, unsigned long flags)
{
	int i, bars = 0;
	for (i = 0; i < PCI_NUM_RESOURCES; i++)
		if (pci_resource_flags(dev, i) & flags)
			bars |= (1 << i);
	return bars;
}

2755 2756 2757 2758 2759 2760 2761 2762 2763 2764
/**
 * pci_resource_bar - get position of the BAR associated with a resource
 * @dev: the PCI device
 * @resno: the resource number
 * @type: the BAR type to be filled in
 *
 * Returns BAR position in config space, or 0 if the BAR is invalid.
 */
int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
{
2765 2766
	int reg;

2767 2768 2769 2770 2771 2772
	if (resno < PCI_ROM_RESOURCE) {
		*type = pci_bar_unknown;
		return PCI_BASE_ADDRESS_0 + 4 * resno;
	} else if (resno == PCI_ROM_RESOURCE) {
		*type = pci_bar_mem32;
		return dev->rom_base_reg;
2773 2774 2775 2776 2777
	} else if (resno < PCI_BRIDGE_RESOURCES) {
		/* device specific resource */
		reg = pci_iov_resource_bar(dev, resno, type);
		if (reg)
			return reg;
2778 2779
	}

2780
	dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
2781 2782 2783
	return 0;
}

2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800
/* Some architectures require additional programming to enable VGA */
static arch_set_vga_state_t arch_set_vga_state;

void __init pci_register_set_vga_state(arch_set_vga_state_t func)
{
	arch_set_vga_state = func;	/* NULL disables */
}

static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
		      unsigned int command_bits, bool change_bridge)
{
	if (arch_set_vga_state)
		return arch_set_vga_state(dev, decode, command_bits,
						change_bridge);
	return 0;
}

2801 2802
/**
 * pci_set_vga_state - set VGA decode state on device and parents if requested
R
Randy Dunlap 已提交
2803 2804 2805 2806
 * @dev: the PCI device
 * @decode: true = enable decoding, false = disable decoding
 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
 * @change_bridge: traverse ancestors and change bridges
2807 2808 2809 2810 2811 2812 2813
 */
int pci_set_vga_state(struct pci_dev *dev, bool decode,
		      unsigned int command_bits, bool change_bridge)
{
	struct pci_bus *bus;
	struct pci_dev *bridge;
	u16 cmd;
2814
	int rc;
2815 2816 2817

	WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));

2818 2819 2820 2821 2822
	/* ARCH specific VGA enables */
	rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
	if (rc)
		return rc;

2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850
	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (decode == true)
		cmd |= command_bits;
	else
		cmd &= ~command_bits;
	pci_write_config_word(dev, PCI_COMMAND, cmd);

	if (change_bridge == false)
		return 0;

	bus = dev->bus;
	while (bus) {
		bridge = bus->self;
		if (bridge) {
			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
					     &cmd);
			if (decode == true)
				cmd |= PCI_BRIDGE_CTL_VGA;
			else
				cmd &= ~PCI_BRIDGE_CTL_VGA;
			pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
					      cmd);
		}
		bus = bus->parent;
	}
	return 0;
}

2851 2852
#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2853
static DEFINE_SPINLOCK(resource_alignment_lock);
2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965

/**
 * pci_specified_resource_alignment - get resource alignment specified by user.
 * @dev: the PCI device to get
 *
 * RETURNS: Resource alignment if it is specified.
 *          Zero if it is not specified.
 */
resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
{
	int seg, bus, slot, func, align_order, count;
	resource_size_t align = 0;
	char *p;

	spin_lock(&resource_alignment_lock);
	p = resource_alignment_param;
	while (*p) {
		count = 0;
		if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
							p[count] == '@') {
			p += count + 1;
		} else {
			align_order = -1;
		}
		if (sscanf(p, "%x:%x:%x.%x%n",
			&seg, &bus, &slot, &func, &count) != 4) {
			seg = 0;
			if (sscanf(p, "%x:%x.%x%n",
					&bus, &slot, &func, &count) != 3) {
				/* Invalid format */
				printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
					p);
				break;
			}
		}
		p += count;
		if (seg == pci_domain_nr(dev->bus) &&
			bus == dev->bus->number &&
			slot == PCI_SLOT(dev->devfn) &&
			func == PCI_FUNC(dev->devfn)) {
			if (align_order == -1) {
				align = PAGE_SIZE;
			} else {
				align = 1 << align_order;
			}
			/* Found */
			break;
		}
		if (*p != ';' && *p != ',') {
			/* End of param or invalid format */
			break;
		}
		p++;
	}
	spin_unlock(&resource_alignment_lock);
	return align;
}

/**
 * pci_is_reassigndev - check if specified PCI is target device to reassign
 * @dev: the PCI device to check
 *
 * RETURNS: non-zero for PCI device is a target device to reassign,
 *          or zero is not.
 */
int pci_is_reassigndev(struct pci_dev *dev)
{
	return (pci_specified_resource_alignment(dev) != 0);
}

ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
{
	if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
		count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
	spin_lock(&resource_alignment_lock);
	strncpy(resource_alignment_param, buf, count);
	resource_alignment_param[count] = '\0';
	spin_unlock(&resource_alignment_lock);
	return count;
}

ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
{
	size_t count;
	spin_lock(&resource_alignment_lock);
	count = snprintf(buf, size, "%s", resource_alignment_param);
	spin_unlock(&resource_alignment_lock);
	return count;
}

static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
{
	return pci_get_resource_alignment_param(buf, PAGE_SIZE);
}

static ssize_t pci_resource_alignment_store(struct bus_type *bus,
					const char *buf, size_t count)
{
	return pci_set_resource_alignment_param(buf, count);
}

BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
					pci_resource_alignment_store);

static int __init pci_resource_alignment_sysfs_init(void)
{
	return bus_create_file(&pci_bus_type,
					&bus_attr_resource_alignment);
}

late_initcall(pci_resource_alignment_sysfs_init);

2966 2967 2968 2969 2970 2971 2972
static void __devinit pci_no_domains(void)
{
#ifdef CONFIG_PCI_DOMAINS
	pci_domains_supported = 0;
#endif
}

2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985
/**
 * pci_ext_cfg_enabled - can we access extended PCI config space?
 * @dev: The PCI device of the root bridge.
 *
 * Returns 1 if we can access PCI extended config space (offsets
 * greater than 0xff). This is the default implementation. Architecture
 * implementations can override this.
 */
int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
{
	return 1;
}

2986 2987 2988 2989 2990
void __weak pci_fixup_cardbus(struct pci_bus *bus)
{
}
EXPORT_SYMBOL(pci_fixup_cardbus);

A
Al Viro 已提交
2991
static int __init pci_setup(char *str)
L
Linus Torvalds 已提交
2992 2993 2994 2995 2996 2997
{
	while (str) {
		char *k = strchr(str, ',');
		if (k)
			*k++ = 0;
		if (*str && (str = pcibios_setup(str)) && *str) {
2998 2999
			if (!strcmp(str, "nomsi")) {
				pci_no_msi();
R
Randy Dunlap 已提交
3000 3001
			} else if (!strcmp(str, "noaer")) {
				pci_no_aer();
3002 3003
			} else if (!strcmp(str, "nodomains")) {
				pci_no_domains();
3004 3005 3006 3007
			} else if (!strncmp(str, "cbiosize=", 9)) {
				pci_cardbus_io_size = memparse(str + 9, &str);
			} else if (!strncmp(str, "cbmemsize=", 10)) {
				pci_cardbus_mem_size = memparse(str + 10, &str);
3008 3009 3010
			} else if (!strncmp(str, "resource_alignment=", 19)) {
				pci_set_resource_alignment_param(str + 19,
							strlen(str + 19));
3011 3012
			} else if (!strncmp(str, "ecrc=", 5)) {
				pcie_ecrc_get_policy(str + 5);
3013 3014 3015 3016
			} else if (!strncmp(str, "hpiosize=", 9)) {
				pci_hotplug_io_size = memparse(str + 9, &str);
			} else if (!strncmp(str, "hpmemsize=", 10)) {
				pci_hotplug_mem_size = memparse(str + 10, &str);
3017 3018 3019 3020
			} else {
				printk(KERN_ERR "PCI: Unknown option `%s'\n",
						str);
			}
L
Linus Torvalds 已提交
3021 3022 3023
		}
		str = k;
	}
3024
	return 0;
L
Linus Torvalds 已提交
3025
}
3026
early_param("pci", pci_setup);
L
Linus Torvalds 已提交
3027

3028
EXPORT_SYMBOL(pci_reenable_device);
3029 3030
EXPORT_SYMBOL(pci_enable_device_io);
EXPORT_SYMBOL(pci_enable_device_mem);
L
Linus Torvalds 已提交
3031
EXPORT_SYMBOL(pci_enable_device);
T
Tejun Heo 已提交
3032 3033
EXPORT_SYMBOL(pcim_enable_device);
EXPORT_SYMBOL(pcim_pin_device);
L
Linus Torvalds 已提交
3034 3035 3036 3037 3038
EXPORT_SYMBOL(pci_disable_device);
EXPORT_SYMBOL(pci_find_capability);
EXPORT_SYMBOL(pci_bus_find_capability);
EXPORT_SYMBOL(pci_release_regions);
EXPORT_SYMBOL(pci_request_regions);
3039
EXPORT_SYMBOL(pci_request_regions_exclusive);
L
Linus Torvalds 已提交
3040 3041
EXPORT_SYMBOL(pci_release_region);
EXPORT_SYMBOL(pci_request_region);
3042
EXPORT_SYMBOL(pci_request_region_exclusive);
3043 3044
EXPORT_SYMBOL(pci_release_selected_regions);
EXPORT_SYMBOL(pci_request_selected_regions);
3045
EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
L
Linus Torvalds 已提交
3046
EXPORT_SYMBOL(pci_set_master);
3047
EXPORT_SYMBOL(pci_clear_master);
L
Linus Torvalds 已提交
3048
EXPORT_SYMBOL(pci_set_mwi);
R
Randy Dunlap 已提交
3049
EXPORT_SYMBOL(pci_try_set_mwi);
L
Linus Torvalds 已提交
3050
EXPORT_SYMBOL(pci_clear_mwi);
B
Brett M Russ 已提交
3051
EXPORT_SYMBOL_GPL(pci_intx);
L
Linus Torvalds 已提交
3052 3053
EXPORT_SYMBOL(pci_assign_resource);
EXPORT_SYMBOL(pci_find_parent_resource);
3054
EXPORT_SYMBOL(pci_select_bars);
L
Linus Torvalds 已提交
3055 3056 3057 3058

EXPORT_SYMBOL(pci_set_power_state);
EXPORT_SYMBOL(pci_save_state);
EXPORT_SYMBOL(pci_restore_state);
3059
EXPORT_SYMBOL(pci_pme_capable);
3060
EXPORT_SYMBOL(pci_pme_active);
3061
EXPORT_SYMBOL(pci_wake_from_d3);
3062
EXPORT_SYMBOL(pci_target_state);
3063 3064
EXPORT_SYMBOL(pci_prepare_to_sleep);
EXPORT_SYMBOL(pci_back_from_sleep);
B
Brian King 已提交
3065
EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);