adv7604.c 103.6 KB
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// SPDX-License-Identifier: GPL-2.0-only
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/*
 * adv7604 - Analog Devices ADV7604 video decoder driver
 *
 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
 *
 */

/*
 * References (c = chapter, p = page):
 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
 *		Revision 2.5, June 2010
 * REF_02 - Analog devices, Register map documentation, Documentation of
 *		the register maps, Software manual, Rev. F, June 2010
 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
 */

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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/hdmi.h>
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#include <linux/i2c.h>
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#include <linux/kernel.h>
#include <linux/module.h>
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#include <linux/of_graph.h>
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#include <linux/slab.h>
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#include <linux/v4l2-dv-timings.h>
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#include <linux/videodev2.h>
#include <linux/workqueue.h>
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#include <linux/regmap.h>
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#include <media/i2c/adv7604.h>
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#include <media/cec.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-event.h>
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#include <media/v4l2-dv-timings.h>
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#include <media/v4l2-fwnode.h>
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static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "debug level (0-2)");

MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
MODULE_LICENSE("GPL");

/* ADV7604 system clock frequency */
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#define ADV76XX_FSC (28636360)
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#define ADV76XX_RGB_OUT					(1 << 1)
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#define ADV76XX_OP_FORMAT_SEL_8BIT			(0 << 0)
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#define ADV7604_OP_FORMAT_SEL_10BIT			(1 << 0)
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#define ADV76XX_OP_FORMAT_SEL_12BIT			(2 << 0)
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#define ADV76XX_OP_MODE_SEL_SDR_422			(0 << 5)
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#define ADV7604_OP_MODE_SEL_DDR_422			(1 << 5)
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#define ADV76XX_OP_MODE_SEL_SDR_444			(2 << 5)
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#define ADV7604_OP_MODE_SEL_DDR_444			(3 << 5)
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#define ADV76XX_OP_MODE_SEL_SDR_422_2X			(4 << 5)
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#define ADV7604_OP_MODE_SEL_ADI_CM			(5 << 5)

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#define ADV76XX_OP_CH_SEL_GBR				(0 << 5)
#define ADV76XX_OP_CH_SEL_GRB				(1 << 5)
#define ADV76XX_OP_CH_SEL_BGR				(2 << 5)
#define ADV76XX_OP_CH_SEL_RGB				(3 << 5)
#define ADV76XX_OP_CH_SEL_BRG				(4 << 5)
#define ADV76XX_OP_CH_SEL_RBG				(5 << 5)
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#define ADV76XX_OP_SWAP_CB_CR				(1 << 0)
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#define ADV76XX_MAX_ADDRS (3)

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enum adv76xx_type {
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	ADV7604,
	ADV7611,
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	ADV7612,
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};

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struct adv76xx_reg_seq {
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	unsigned int reg;
	u8 val;
};

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struct adv76xx_format_info {
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	u32 code;
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	u8 op_ch_sel;
	bool rgb_out;
	bool swap_cb_cr;
	u8 op_format_sel;
};

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struct adv76xx_cfg_read_infoframe {
	const char *desc;
	u8 present_mask;
	u8 head_addr;
	u8 payload_addr;
};

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struct adv76xx_chip_info {
	enum adv76xx_type type;
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	bool has_afe;
	unsigned int max_port;
	unsigned int num_dv_ports;

	unsigned int edid_enable_reg;
	unsigned int edid_status_reg;
	unsigned int lcf_reg;

	unsigned int cable_det_mask;
	unsigned int tdms_lock_mask;
	unsigned int fmt_change_digital_mask;
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	unsigned int cp_csc;
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	const struct adv76xx_format_info *formats;
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	unsigned int nformats;

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	void (*set_termination)(struct v4l2_subdev *sd, bool enable);
	void (*setup_irqs)(struct v4l2_subdev *sd);
	unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
	unsigned int (*read_cable_det)(struct v4l2_subdev *sd);

	/* 0 = AFE, 1 = HDMI */
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	const struct adv76xx_reg_seq *recommended_settings[2];
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	unsigned int num_recommended_settings[2];

	unsigned long page_mask;
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	/* Masks for timings */
	unsigned int linewidth_mask;
	unsigned int field0_height_mask;
	unsigned int field1_height_mask;
	unsigned int hfrontporch_mask;
	unsigned int hsync_mask;
	unsigned int hbackporch_mask;
	unsigned int field0_vfrontporch_mask;
	unsigned int field1_vfrontporch_mask;
	unsigned int field0_vsync_mask;
	unsigned int field1_vsync_mask;
	unsigned int field0_vbackporch_mask;
	unsigned int field1_vbackporch_mask;
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};

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/*
 **********************************************************************
 *
 *  Arrays with configuration parameters for the ADV7604
 *
 **********************************************************************
 */
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struct adv76xx_state {
	const struct adv76xx_chip_info *info;
	struct adv76xx_platform_data pdata;
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	struct gpio_desc *hpd_gpio[4];
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	struct gpio_desc *reset_gpio;
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	struct v4l2_subdev sd;
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	struct media_pad pads[ADV76XX_PAD_MAX];
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	unsigned int source_pad;
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	struct v4l2_ctrl_handler hdl;
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	enum adv76xx_pad selected_input;
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	struct v4l2_dv_timings timings;
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	const struct adv76xx_format_info *format;
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	struct {
		u8 edid[256];
		u32 present;
		unsigned blocks;
	} edid;
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	u16 spa_port_a[2];
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	struct v4l2_fract aspect_ratio;
	u32 rgb_quantization_range;
	struct delayed_work delayed_work_enable_hotplug;
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	bool restart_stdi_once;
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	/* CEC */
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	struct cec_adapter *cec_adap;
	u8   cec_addr[ADV76XX_MAX_ADDRS];
	u8   cec_valid_addrs;
	bool cec_enabled_adap;

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	/* i2c clients */
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	struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
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	/* Regmaps */
	struct regmap *regmap[ADV76XX_PAGE_MAX];

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	/* controls */
	struct v4l2_ctrl *detect_tx_5v_ctrl;
	struct v4l2_ctrl *analog_sampling_phase_ctrl;
	struct v4l2_ctrl *free_run_color_manual_ctrl;
	struct v4l2_ctrl *free_run_color_ctrl;
	struct v4l2_ctrl *rgb_quantization_range_ctrl;
};

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static bool adv76xx_has_afe(struct adv76xx_state *state)
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{
	return state->info->has_afe;
}

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/* Unsupported timings. This device cannot support 720p30. */
static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
	V4L2_DV_BT_CEA_1280X720P30,
	{ }
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};

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static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
{
	int i;

	for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
		if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
			return false;
	return true;
}

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struct adv76xx_video_standards {
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	struct v4l2_dv_timings timings;
	u8 vid_std;
	u8 v_freq;
};

/* sorted by number of lines */
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static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
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	/* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
	{ V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
	{ V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
	{ V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
	{ V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
	{ V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
	{ V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
	{ V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
	{ V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
	/* TODO add 1920x1080P60_RB (CVT timing) */
	{ },
};

/* sorted by number of lines */
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static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
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	{ V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
	{ V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
	{ V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
	{ V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
	{ V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
	{ V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
	{ V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
	{ V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
	/* TODO add 1600X1200P60_RB (not a DMT timing) */
	{ V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
	{ V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
	{ },
};

/* sorted by number of lines */
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static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
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	{ V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
	{ V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
	{ V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
	{ V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
	{ V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
	{ V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
	{ V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
	{ V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
	{ V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
	{ },
};

/* sorted by number of lines */
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static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
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	{ V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
	{ V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
	{ V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
	{ },
};

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static const struct v4l2_event adv76xx_ev_fmt = {
	.type = V4L2_EVENT_SOURCE_CHANGE,
	.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
};

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/* ----------------------------------------------------------------------- */

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static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
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{
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	return container_of(sd, struct adv76xx_state, sd);
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}

static inline unsigned htotal(const struct v4l2_bt_timings *t)
{
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	return V4L2_DV_BT_FRAME_WIDTH(t);
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}

static inline unsigned vtotal(const struct v4l2_bt_timings *t)
{
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	return V4L2_DV_BT_FRAME_HEIGHT(t);
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}

/* ----------------------------------------------------------------------- */

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static int adv76xx_read_check(struct adv76xx_state *state,
			     int client_page, u8 reg)
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{
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	struct i2c_client *client = state->i2c_clients[client_page];
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	int err;
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	unsigned int val;
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	err = regmap_read(state->regmap[client_page], reg, &val);

	if (err) {
		v4l_err(client, "error reading %02x, %02x\n",
				client->addr, reg);
		return err;
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	}
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	return val;
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}

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/* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
 * size to one or more registers.
 *
 * A value of zero will be returned on success, a negative errno will
 * be returned in error cases.
 */
static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
			      unsigned int init_reg, const void *val,
			      size_t val_len)
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{
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	struct regmap *regmap = state->regmap[client_page];

	if (val_len > I2C_SMBUS_BLOCK_MAX)
		val_len = I2C_SMBUS_BLOCK_MAX;
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	return regmap_raw_write(regmap, init_reg, val, val_len);
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}

/* ----------------------------------------------------------------------- */

static inline int io_read(struct v4l2_subdev *sd, u8 reg)
{
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	struct adv76xx_state *state = to_state(sd);
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	return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
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}

static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
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	struct adv76xx_state *state = to_state(sd);
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	return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
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}

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static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
				   u8 val)
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{
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	return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
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}

static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
{
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	struct adv76xx_state *state = to_state(sd);
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	return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
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}

static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
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	struct adv76xx_state *state = to_state(sd);
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	return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
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}

static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
{
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	struct adv76xx_state *state = to_state(sd);
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	return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
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}

static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
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	struct adv76xx_state *state = to_state(sd);
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	return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
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}

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static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
				   u8 val)
{
	return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
}

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static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
{
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	struct adv76xx_state *state = to_state(sd);
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	return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
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}

static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
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	struct adv76xx_state *state = to_state(sd);
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	return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
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}

static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
{
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	struct adv76xx_state *state = to_state(sd);
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	return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
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}

static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
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	struct adv76xx_state *state = to_state(sd);
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	return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
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}

static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
{
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	struct adv76xx_state *state = to_state(sd);
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	return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
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}

static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
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	struct adv76xx_state *state = to_state(sd);
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	return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
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}

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static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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{
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	return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
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}

static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
{
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	struct adv76xx_state *state = to_state(sd);
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	return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
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}

static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
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	struct adv76xx_state *state = to_state(sd);
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	return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
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}

static inline int edid_write_block(struct v4l2_subdev *sd,
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					unsigned int total_len, const u8 *val)
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{
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	struct adv76xx_state *state = to_state(sd);
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	int err = 0;
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	int i = 0;
	int len = 0;
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	v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
				__func__, total_len);

	while (!err && i < total_len) {
		len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
				I2C_SMBUS_BLOCK_MAX :
				(total_len - i);

		err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
				i, val + i, len);
		i += len;
	}
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	return err;
}
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static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
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{
	unsigned int i;

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	for (i = 0; i < state->info->num_dv_ports; ++i)
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		gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));

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	v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
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}

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static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
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{
	struct delayed_work *dwork = to_delayed_work(work);
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	struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
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						delayed_work_enable_hotplug);
	struct v4l2_subdev *sd = &state->sd;
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	v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
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	adv76xx_set_hpd(state, state->edid.present);
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}

static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
{
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	struct adv76xx_state *state = to_state(sd);
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	return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
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}

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static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
{
	return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
}

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static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
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	struct adv76xx_state *state = to_state(sd);
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	return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
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}

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static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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{
550
	return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
551 552
}

553 554
static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
555
	struct adv76xx_state *state = to_state(sd);
556

557
	return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
558 559 560 561
}

static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
{
562
	struct adv76xx_state *state = to_state(sd);
563

564
	return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
565 566
}

567 568 569 570 571
static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
{
	return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
}

572 573
static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
574
	struct adv76xx_state *state = to_state(sd);
575

576
	return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
577 578
}

579
static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
580
{
581
	return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
582 583 584 585
}

static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
{
586
	struct adv76xx_state *state = to_state(sd);
587

588
	return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
589 590 591 592
}

static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
593
	struct adv76xx_state *state = to_state(sd);
594

595
	return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
596
}
597

598 599
#define ADV76XX_REG(page, offset)	(((page) << 8) | (offset))
#define ADV76XX_REG_SEQ_TERM		0xffff
600 601

#ifdef CONFIG_VIDEO_ADV_DEBUG
602
static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
603
{
604
	struct adv76xx_state *state = to_state(sd);
605
	unsigned int page = reg >> 8;
606 607
	unsigned int val;
	int err;
608

609
	if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
610 611 612
		return -EINVAL;

	reg &= 0xff;
613
	err = regmap_read(state->regmap[page], reg, &val);
614

615
	return err ? err : val;
616 617 618
}
#endif

619
static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
620
{
621
	struct adv76xx_state *state = to_state(sd);
622 623
	unsigned int page = reg >> 8;

624
	if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
625 626 627 628
		return -EINVAL;

	reg &= 0xff;

629
	return regmap_write(state->regmap[page], reg, val);
630 631
}

632 633
static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
				  const struct adv76xx_reg_seq *reg_seq)
634 635 636
{
	unsigned int i;

637 638
	for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
		adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
639 640
}

641 642 643 644
/* -----------------------------------------------------------------------------
 * Format helpers
 */

645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683
static const struct adv76xx_format_info adv7604_formats[] = {
	{ MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
	  ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
	{ MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
	{ MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
	{ MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
	{ MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
	{ MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
	{ MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
	{ MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
	{ MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
	{ MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
	{ MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
	{ MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
684 685
};

686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712
static const struct adv76xx_format_info adv7611_formats[] = {
	{ MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
	  ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
	{ MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
	{ MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
	{ MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
	{ MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
	{ MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
713 714
};

715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731
static const struct adv76xx_format_info adv7612_formats[] = {
	{ MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
	  ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
	{ MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
	  ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
};

732 733
static const struct adv76xx_format_info *
adv76xx_format_info(struct adv76xx_state *state, u32 code)
734 735 736 737 738 739 740 741 742 743 744
{
	unsigned int i;

	for (i = 0; i < state->info->nformats; ++i) {
		if (state->info->formats[i].code == code)
			return &state->info->formats[i];
	}

	return NULL;
}

745 746
/* ----------------------------------------------------------------------- */

747 748
static inline bool is_analog_input(struct v4l2_subdev *sd)
{
749
	struct adv76xx_state *state = to_state(sd);
750

751 752
	return state->selected_input == ADV7604_PAD_VGA_RGB ||
	       state->selected_input == ADV7604_PAD_VGA_COMP;
753 754 755 756
}

static inline bool is_digital_input(struct v4l2_subdev *sd)
{
757
	struct adv76xx_state *state = to_state(sd);
758

759
	return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
760 761 762
	       state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
	       state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
	       state->selected_input == ADV7604_PAD_HDMI_PORT_D;
763 764
}

765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786
static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
	.type = V4L2_DV_BT_656_1120,
	/* keep this initialization for compatibility with GCC < 4.4.6 */
	.reserved = { 0 },
	V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
		V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
		V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
			V4L2_DV_BT_CAP_CUSTOM)
};

static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
	.type = V4L2_DV_BT_656_1120,
	/* keep this initialization for compatibility with GCC < 4.4.6 */
	.reserved = { 0 },
	V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
		V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
		V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
			V4L2_DV_BT_CAP_CUSTOM)
};

787 788 789 790 791 792
/*
 * Return the DV timings capabilities for the requested sink pad. As a special
 * case, pad value -1 returns the capabilities for the currently selected input.
 */
static const struct v4l2_dv_timings_cap *
adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
793
{
794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811
	if (pad == -1) {
		struct adv76xx_state *state = to_state(sd);

		pad = state->selected_input;
	}

	switch (pad) {
	case ADV76XX_PAD_HDMI_PORT_A:
	case ADV7604_PAD_HDMI_PORT_B:
	case ADV7604_PAD_HDMI_PORT_C:
	case ADV7604_PAD_HDMI_PORT_D:
		return &adv76xx_timings_cap_digital;

	case ADV7604_PAD_VGA_RGB:
	case ADV7604_PAD_VGA_COMP:
	default:
		return &adv7604_timings_cap_analog;
	}
812 813 814
}


815 816
/* ----------------------------------------------------------------------- */

817
#ifdef CONFIG_VIDEO_ADV_DEBUG
818
static void adv76xx_inv_register(struct v4l2_subdev *sd)
819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834
{
	v4l2_info(sd, "0x000-0x0ff: IO Map\n");
	v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
	v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
	v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
	v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
	v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
	v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
	v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
	v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
	v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
	v4l2_info(sd, "0xa00-0xaff: Test Map\n");
	v4l2_info(sd, "0xb00-0xbff: CP Map\n");
	v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
}

835
static int adv76xx_g_register(struct v4l2_subdev *sd,
836 837
					struct v4l2_dbg_register *reg)
{
838 839
	int ret;

840
	ret = adv76xx_read_reg(sd, reg->reg);
841
	if (ret < 0) {
842
		v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
843
		adv76xx_inv_register(sd);
844
		return ret;
845
	}
846 847 848 849

	reg->size = 1;
	reg->val = ret;

850 851 852
	return 0;
}

853
static int adv76xx_s_register(struct v4l2_subdev *sd,
854
					const struct v4l2_dbg_register *reg)
855
{
856
	int ret;
857

858
	ret = adv76xx_write_reg(sd, reg->reg, reg->val);
859
	if (ret < 0) {
860
		v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
861
		adv76xx_inv_register(sd);
862
		return ret;
863
	}
864

865 866 867 868
	return 0;
}
#endif

869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885
static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
{
	u8 value = io_read(sd, 0x6f);

	return ((value & 0x10) >> 4)
	     | ((value & 0x08) >> 2)
	     | ((value & 0x04) << 0)
	     | ((value & 0x02) << 2);
}

static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
{
	u8 value = io_read(sd, 0x6f);

	return value & 1;
}

886 887 888 889 890 891 892 893 894 895
static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
{
	/*  Reads CABLE_DET_A_RAW. For input B support, need to
	 *  account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
	 */
	u8 value = io_read(sd, 0x6f);

	return value & 1;
}

896
static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
897
{
898 899
	struct adv76xx_state *state = to_state(sd);
	const struct adv76xx_chip_info *info = state->info;
900
	u16 cable_det = info->read_cable_det(sd);
901

902
	return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
903 904
}

905 906
static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
		u8 prim_mode,
907
		const struct adv76xx_video_standards *predef_vid_timings,
908 909 910 911 912
		const struct v4l2_dv_timings *timings)
{
	int i;

	for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
913
		if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
914
				is_digital_input(sd) ? 250000 : 1000000, false))
915 916 917 918 919 920 921 922 923 924 925 926
			continue;
		io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
		io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
				prim_mode); /* v_freq and prim mode */
		return 0;
	}

	return -1;
}

static int configure_predefined_video_timings(struct v4l2_subdev *sd,
		struct v4l2_dv_timings *timings)
927
{
928
	struct adv76xx_state *state = to_state(sd);
929 930 931 932
	int err;

	v4l2_dbg(1, debug, sd, "%s", __func__);

933
	if (adv76xx_has_afe(state)) {
934 935 936 937
		/* reset to default values */
		io_write(sd, 0x16, 0x43);
		io_write(sd, 0x17, 0x5a);
	}
938
	/* disable embedded syncs for auto graphics mode */
939
	cp_write_clr_set(sd, 0x81, 0x10, 0x00);
940 941 942 943 944 945 946 947 948 949 950
	cp_write(sd, 0x8f, 0x00);
	cp_write(sd, 0x90, 0x00);
	cp_write(sd, 0xa2, 0x00);
	cp_write(sd, 0xa3, 0x00);
	cp_write(sd, 0xa4, 0x00);
	cp_write(sd, 0xa5, 0x00);
	cp_write(sd, 0xa6, 0x00);
	cp_write(sd, 0xa7, 0x00);
	cp_write(sd, 0xab, 0x00);
	cp_write(sd, 0xac, 0x00);

951
	if (is_analog_input(sd)) {
952 953 954 955 956
		err = find_and_set_predefined_video_timings(sd,
				0x01, adv7604_prim_mode_comp, timings);
		if (err)
			err = find_and_set_predefined_video_timings(sd,
					0x02, adv7604_prim_mode_gr, timings);
957
	} else if (is_digital_input(sd)) {
958
		err = find_and_set_predefined_video_timings(sd,
959
				0x05, adv76xx_prim_mode_hdmi_comp, timings);
960 961
		if (err)
			err = find_and_set_predefined_video_timings(sd,
962
					0x06, adv76xx_prim_mode_hdmi_gr, timings);
963 964 965
	} else {
		v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
				__func__, state->selected_input);
966 967 968 969 970 971 972 973 974 975
		err = -1;
	}


	return err;
}

static void configure_custom_video_timings(struct v4l2_subdev *sd,
		const struct v4l2_bt_timings *bt)
{
976
	struct adv76xx_state *state = to_state(sd);
977 978 979 980 981 982 983
	u32 width = htotal(bt);
	u32 height = vtotal(bt);
	u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
	u16 cp_start_eav = width - bt->hfrontporch;
	u16 cp_start_vbi = height - bt->vfrontporch;
	u16 cp_end_vbi = bt->vsync + bt->vbackporch;
	u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
984
		((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
985 986 987 988
	const u8 pll[2] = {
		0xc0 | ((width >> 8) & 0x1f),
		width & 0xff
	};
989 990 991

	v4l2_dbg(2, debug, sd, "%s\n", __func__);

992
	if (is_analog_input(sd)) {
993 994 995 996
		/* auto graphics */
		io_write(sd, 0x00, 0x07); /* video std */
		io_write(sd, 0x01, 0x02); /* prim mode */
		/* enable embedded syncs for auto graphics mode */
997
		cp_write_clr_set(sd, 0x81, 0x10, 0x10);
998

999
		/* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1000 1001
		/* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
		/* IO-map reg. 0x16 and 0x17 should be written in sequence */
1002 1003
		if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
					0x16, pll, 2))
1004 1005 1006 1007
			v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");

		/* active video - horizontal timing */
		cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1008
		cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1009
				   ((cp_start_eav >> 8) & 0x0f));
1010 1011 1012 1013
		cp_write(sd, 0xa4, cp_start_eav & 0xff);

		/* active video - vertical timing */
		cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1014
		cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1015
				   ((cp_end_vbi >> 8) & 0xf));
1016
		cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1017
	} else if (is_digital_input(sd)) {
1018
		/* set default prim_mode/vid_std for HDMI
1019
		   according to [REF_03, c. 4.2] */
1020 1021
		io_write(sd, 0x00, 0x02); /* video std */
		io_write(sd, 0x01, 0x06); /* prim mode */
1022 1023 1024
	} else {
		v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
				__func__, state->selected_input);
1025 1026
	}

1027 1028 1029 1030 1031
	cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
	cp_write(sd, 0x90, ch1_fr_ll & 0xff);
	cp_write(sd, 0xab, (height >> 4) & 0xff);
	cp_write(sd, 0xac, (height & 0x0f) << 4);
}
1032

1033
static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1034
{
1035
	struct adv76xx_state *state = to_state(sd);
1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053
	u8 offset_buf[4];

	if (auto_offset) {
		offset_a = 0x3ff;
		offset_b = 0x3ff;
		offset_c = 0x3ff;
	}

	v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
			__func__, auto_offset ? "Auto" : "Manual",
			offset_a, offset_b, offset_c);

	offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
	offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
	offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
	offset_buf[3] = offset_c & 0x0ff;

	/* Registers must be written in this order with no i2c access in between */
1054 1055
	if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
			0x77, offset_buf, 4))
1056 1057 1058
		v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
}

1059
static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1060
{
1061
	struct adv76xx_state *state = to_state(sd);
1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083
	u8 gain_buf[4];
	u8 gain_man = 1;
	u8 agc_mode_man = 1;

	if (auto_gain) {
		gain_man = 0;
		agc_mode_man = 0;
		gain_a = 0x100;
		gain_b = 0x100;
		gain_c = 0x100;
	}

	v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
			__func__, auto_gain ? "Auto" : "Manual",
			gain_a, gain_b, gain_c);

	gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
	gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
	gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
	gain_buf[3] = ((gain_c & 0x0ff));

	/* Registers must be written in this order with no i2c access in between */
1084 1085
	if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
			     0x73, gain_buf, 4))
1086 1087 1088
		v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
}

1089 1090
static void set_rgb_quantization_range(struct v4l2_subdev *sd)
{
1091
	struct adv76xx_state *state = to_state(sd);
1092 1093
	bool rgb_output = io_read(sd, 0x02) & 0x02;
	bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1094 1095 1096 1097
	u8 y = HDMI_COLORSPACE_RGB;

	if (hdmi_signal && (io_read(sd, 0x60) & 1))
		y = infoframe_read(sd, 0x01) >> 5;
1098 1099 1100 1101

	v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
			__func__, state->rgb_quantization_range,
			rgb_output, hdmi_signal);
1102

1103 1104
	adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
	adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1105
	io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1106

1107 1108
	switch (state->rgb_quantization_range) {
	case V4L2_DV_RGB_RANGE_AUTO:
1109
		if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1110 1111
			/* Receiving analog RGB signal
			 * Set RGB full range (0-255) */
1112
			io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1113 1114 1115
			break;
		}

1116
		if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1117 1118
			/* Receiving analog YPbPr signal
			 * Set automode */
1119
			io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1120 1121 1122
			break;
		}

1123
		if (hdmi_signal) {
1124 1125
			/* Receiving HDMI signal
			 * Set automode */
1126
			io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1127 1128 1129 1130 1131 1132
			break;
		}

		/* Receiving DVI-D signal
		 * ADV7604 selects RGB limited range regardless of
		 * input format (CE/IT) in automatic mode */
1133
		if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1134
			/* RGB limited range (16-235) */
1135
			io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1136 1137
		} else {
			/* RGB full range (0-255) */
1138
			io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1139 1140

			if (is_digital_input(sd) && rgb_output) {
1141
				adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1142
			} else {
1143 1144
				adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
				adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1145
			}
1146 1147 1148
		}
		break;
	case V4L2_DV_RGB_RANGE_LIMITED:
1149
		if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1150
			/* YCrCb limited range (16-235) */
1151
			io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1152
			break;
1153
		}
1154

1155 1156 1157
		if (y != HDMI_COLORSPACE_RGB)
			break;

1158
		/* RGB limited range (16-235) */
1159
		io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1160

1161 1162
		break;
	case V4L2_DV_RGB_RANGE_FULL:
1163
		if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1164
			/* YCrCb full range (0-255) */
1165
			io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1166 1167 1168
			break;
		}

1169 1170 1171
		if (y != HDMI_COLORSPACE_RGB)
			break;

1172
		/* RGB full range (0-255) */
1173
		io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1174 1175 1176 1177 1178 1179

		if (is_analog_input(sd) || hdmi_signal)
			break;

		/* Adjust gain/offset for DVI-D signals only */
		if (rgb_output) {
1180
			adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1181
		} else {
1182 1183
			adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
			adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1184
		}
1185 1186 1187 1188
		break;
	}
}

1189
static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1190
{
1191
	struct v4l2_subdev *sd =
1192
		&container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1193

1194
	struct adv76xx_state *state = to_state(sd);
1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213

	switch (ctrl->id) {
	case V4L2_CID_BRIGHTNESS:
		cp_write(sd, 0x3c, ctrl->val);
		return 0;
	case V4L2_CID_CONTRAST:
		cp_write(sd, 0x3a, ctrl->val);
		return 0;
	case V4L2_CID_SATURATION:
		cp_write(sd, 0x3b, ctrl->val);
		return 0;
	case V4L2_CID_HUE:
		cp_write(sd, 0x3d, ctrl->val);
		return 0;
	case  V4L2_CID_DV_RX_RGB_RANGE:
		state->rgb_quantization_range = ctrl->val;
		set_rgb_quantization_range(sd);
		return 0;
	case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1214
		if (!adv76xx_has_afe(state))
1215
			return -EINVAL;
1216 1217 1218 1219 1220 1221 1222 1223 1224
		/* Set the analog sampling phase. This is needed to find the
		   best sampling phase for analog video: an application or
		   driver has to try a number of phases and analyze the picture
		   quality before settling on the best performing phase. */
		afe_write(sd, 0xc8, ctrl->val);
		return 0;
	case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
		/* Use the default blue color for free running mode,
		   or supply your own. */
1225
		cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1226 1227 1228 1229 1230 1231 1232 1233 1234 1235
		return 0;
	case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
		cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
		cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
		cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
		return 0;
	}
	return -EINVAL;
}

1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249
static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
{
	struct v4l2_subdev *sd =
		&container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;

	if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
		ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
		if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
			ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
		return 0;
	}
	return -EINVAL;
}

1250 1251 1252 1253 1254 1255 1256 1257 1258 1259
/* ----------------------------------------------------------------------- */

static inline bool no_power(struct v4l2_subdev *sd)
{
	/* Entire chip or CP powered off */
	return io_read(sd, 0x0c) & 0x24;
}

static inline bool no_signal_tmds(struct v4l2_subdev *sd)
{
1260
	struct adv76xx_state *state = to_state(sd);
1261 1262

	return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1263 1264 1265 1266
}

static inline bool no_lock_tmds(struct v4l2_subdev *sd)
{
1267 1268
	struct adv76xx_state *state = to_state(sd);
	const struct adv76xx_chip_info *info = state->info;
1269 1270

	return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1271 1272
}

1273 1274 1275 1276 1277
static inline bool is_hdmi(struct v4l2_subdev *sd)
{
	return hdmi_read(sd, 0x05) & 0x80;
}

1278 1279
static inline bool no_lock_sspd(struct v4l2_subdev *sd)
{
1280
	struct adv76xx_state *state = to_state(sd);
1281 1282 1283 1284 1285

	/*
	 * Chips without a AFE don't expose registers for the SSPD, so just assume
	 * that we have a lock.
	 */
1286
	if (adv76xx_has_afe(state))
1287 1288
		return false;

1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307
	/* TODO channel 2 */
	return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
}

static inline bool no_lock_stdi(struct v4l2_subdev *sd)
{
	/* TODO channel 2 */
	return !(cp_read(sd, 0xb1) & 0x80);
}

static inline bool no_signal(struct v4l2_subdev *sd)
{
	bool ret;

	ret = no_power(sd);

	ret |= no_lock_stdi(sd);
	ret |= no_lock_sspd(sd);

1308
	if (is_digital_input(sd)) {
1309 1310 1311 1312 1313 1314 1315 1316 1317
		ret |= no_lock_tmds(sd);
		ret |= no_signal_tmds(sd);
	}

	return ret;
}

static inline bool no_lock_cp(struct v4l2_subdev *sd)
{
1318
	struct adv76xx_state *state = to_state(sd);
1319

1320
	if (!adv76xx_has_afe(state))
1321 1322
		return false;

1323 1324 1325 1326 1327
	/* CP has detected a non standard number of lines on the incoming
	   video compared to what it is configured to receive by s_dv_timings */
	return io_read(sd, 0x12) & 0x01;
}

1328 1329 1330 1331 1332
static inline bool in_free_run(struct v4l2_subdev *sd)
{
	return cp_read(sd, 0xff) & 0x10;
}

1333
static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1334 1335 1336 1337
{
	*status = 0;
	*status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
	*status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1338 1339 1340
	if (!in_free_run(sd) && no_lock_cp(sd))
		*status |= is_digital_input(sd) ?
			   V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358

	v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);

	return 0;
}

/* ----------------------------------------------------------------------- */

struct stdi_readback {
	u16 bl, lcf, lcvs;
	u8 hs_pol, vs_pol;
	bool interlaced;
};

static int stdi2dv_timings(struct v4l2_subdev *sd,
		struct stdi_readback *stdi,
		struct v4l2_dv_timings *timings)
{
1359 1360
	struct adv76xx_state *state = to_state(sd);
	u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1361 1362 1363
	u32 pix_clk;
	int i;

1364 1365 1366 1367
	for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
		const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;

		if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1368
					   adv76xx_get_dv_timings_cap(sd, -1),
1369
					   adv76xx_check_dv_timings, NULL))
1370
			continue;
1371 1372 1373
		if (vtotal(bt) != stdi->lcf + 1)
			continue;
		if (bt->vsync != stdi->lcvs)
1374 1375
			continue;

1376
		pix_clk = hfreq * htotal(bt);
1377

1378 1379 1380
		if ((pix_clk < bt->pixelclock + 1000000) &&
		    (pix_clk > bt->pixelclock - 1000000)) {
			*timings = v4l2_dv_timings_presets[i];
1381 1382 1383 1384
			return 0;
		}
	}

1385
	if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1386 1387
			(stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
			(stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1388
			false, timings))
1389 1390 1391 1392
		return 0;
	if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
			(stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
			(stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1393
			false, state->aspect_ratio, timings))
1394 1395
		return 0;

1396 1397 1398 1399
	v4l2_dbg(2, debug, sd,
		"%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
		__func__, stdi->lcvs, stdi->lcf, stdi->bl,
		stdi->hs_pol, stdi->vs_pol);
1400 1401 1402
	return -1;
}

1403

1404 1405
static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
{
1406 1407
	struct adv76xx_state *state = to_state(sd);
	const struct adv76xx_chip_info *info = state->info;
1408 1409
	u8 polarity;

1410 1411 1412 1413 1414 1415
	if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
		v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
		return -1;
	}

	/* read STDI */
1416
	stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1417
	stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1418 1419 1420
	stdi->lcvs = cp_read(sd, 0xb3) >> 3;
	stdi->interlaced = io_read(sd, 0x12) & 0x10;

1421
	if (adv76xx_has_afe(state)) {
1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432
		/* read SSPD */
		polarity = cp_read(sd, 0xb5);
		if ((polarity & 0x03) == 0x01) {
			stdi->hs_pol = polarity & 0x10
				     ? (polarity & 0x08 ? '+' : '-') : 'x';
			stdi->vs_pol = polarity & 0x40
				     ? (polarity & 0x20 ? '+' : '-') : 'x';
		} else {
			stdi->hs_pol = 'x';
			stdi->vs_pol = 'x';
		}
1433
	} else {
1434 1435 1436
		polarity = hdmi_read(sd, 0x05);
		stdi->hs_pol = polarity & 0x20 ? '+' : '-';
		stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459
	}

	if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
		v4l2_dbg(2, debug, sd,
			"%s: signal lost during readout of STDI/SSPD\n", __func__);
		return -1;
	}

	if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
		v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
		memset(stdi, 0, sizeof(struct stdi_readback));
		return -1;
	}

	v4l2_dbg(2, debug, sd,
		"%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
		__func__, stdi->lcf, stdi->bl, stdi->lcvs,
		stdi->hs_pol, stdi->vs_pol,
		stdi->interlaced ? "interlaced" : "progressive");

	return 0;
}

1460
static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1461 1462
			struct v4l2_enum_dv_timings *timings)
{
1463
	struct adv76xx_state *state = to_state(sd);
1464 1465 1466 1467

	if (timings->pad >= state->source_pad)
		return -EINVAL;

1468
	return v4l2_enum_dv_timings_cap(timings,
1469 1470
		adv76xx_get_dv_timings_cap(sd, timings->pad),
		adv76xx_check_dv_timings, NULL);
1471 1472
}

1473
static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1474
			struct v4l2_dv_timings_cap *cap)
1475
{
1476
	struct adv76xx_state *state = to_state(sd);
1477
	unsigned int pad = cap->pad;
1478 1479 1480 1481

	if (cap->pad >= state->source_pad)
		return -EINVAL;

1482 1483 1484
	*cap = *adv76xx_get_dv_timings_cap(sd, pad);
	cap->pad = pad;

1485 1486 1487 1488
	return 0;
}

/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1489 1490
   if the format is listed in adv76xx_timings[] */
static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1491 1492
		struct v4l2_dv_timings *timings)
{
1493 1494 1495
	v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
				 is_digital_input(sd) ? 250000 : 1000000,
				 adv76xx_check_dv_timings, NULL);
1496 1497
}

1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529
static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
{
	unsigned int freq;
	int a, b;

	a = hdmi_read(sd, 0x06);
	b = hdmi_read(sd, 0x3b);
	if (a < 0 || b < 0)
		return 0;
	freq =  a * 1000000 + ((b & 0x30) >> 4) * 250000;

	if (is_hdmi(sd)) {
		/* adjust for deep color mode */
		unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;

		freq = freq * 8 / bits_per_channel;
	}

	return freq;
}

static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
{
	int a, b;

	a = hdmi_read(sd, 0x51);
	b = hdmi_read(sd, 0x52);
	if (a < 0 || b < 0)
		return 0;
	return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
}

1530
static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1531 1532
			struct v4l2_dv_timings *timings)
{
1533 1534
	struct adv76xx_state *state = to_state(sd);
	const struct adv76xx_chip_info *info = state->info;
1535 1536 1537 1538 1539 1540 1541 1542 1543
	struct v4l2_bt_timings *bt = &timings->bt;
	struct stdi_readback stdi;

	if (!timings)
		return -EINVAL;

	memset(timings, 0, sizeof(struct v4l2_dv_timings));

	if (no_signal(sd)) {
1544
		state->restart_stdi_once = true;
1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
		v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
		return -ENOLINK;
	}

	/* read STDI */
	if (read_stdi(sd, &stdi)) {
		v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
		return -ENOLINK;
	}
	bt->interlaced = stdi.interlaced ?
		V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;

1557
	if (is_digital_input(sd)) {
1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571
		bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
		u8 vic = 0;
		u32 w, h;

		w = hdmi_read16(sd, 0x07, info->linewidth_mask);
		h = hdmi_read16(sd, 0x09, info->field0_height_mask);

		if (hdmi_signal && (io_read(sd, 0x60) & 1))
			vic = infoframe_read(sd, 0x04);

		if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) &&
		    bt->width == w && bt->height == h)
			goto found;

1572 1573
		timings->type = V4L2_DV_BT_656_1120;

1574 1575
		bt->width = w;
		bt->height = h;
1576
		bt->pixelclock = info->read_hdmi_pixelclock(sd);
1577 1578 1579 1580 1581 1582 1583 1584
		bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
		bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
		bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
		bt->vfrontporch = hdmi_read16(sd, 0x2a,
			info->field0_vfrontporch_mask) / 2;
		bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
		bt->vbackporch = hdmi_read16(sd, 0x32,
			info->field0_vbackporch_mask) / 2;
1585 1586 1587
		bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
			((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
		if (bt->interlaced == V4L2_DV_INTERLACED) {
1588 1589 1590 1591 1592 1593 1594 1595
			bt->height += hdmi_read16(sd, 0x0b,
				info->field1_height_mask);
			bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
				info->field1_vfrontporch_mask) / 2;
			bt->il_vsync = hdmi_read16(sd, 0x30,
				info->field1_vsync_mask) / 2;
			bt->il_vbackporch = hdmi_read16(sd, 0x34,
				info->field1_vbackporch_mask) / 2;
1596
		}
1597
		adv76xx_fill_optional_dv_timings_fields(sd, timings);
1598 1599
	} else {
		/* find format
1600
		 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611
		 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
		 */
		if (!stdi2dv_timings(sd, &stdi, timings))
			goto found;
		stdi.lcvs += 1;
		v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
		if (!stdi2dv_timings(sd, &stdi, timings))
			goto found;
		stdi.lcvs -= 2;
		v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
		if (stdi2dv_timings(sd, &stdi, timings)) {
1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624
			/*
			 * The STDI block may measure wrong values, especially
			 * for lcvs and lcf. If the driver can not find any
			 * valid timing, the STDI block is restarted to measure
			 * the video timings again. The function will return an
			 * error, but the restart of STDI will generate a new
			 * STDI interrupt and the format detection process will
			 * restart.
			 */
			if (state->restart_stdi_once) {
				v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
				/* TODO restart STDI for Sync Channel 2 */
				/* enter one-shot mode */
1625
				cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1626
				/* trigger STDI restart */
1627
				cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1628
				/* reset to continuous mode */
1629
				cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1630 1631 1632
				state->restart_stdi_once = false;
				return -ENOLINK;
			}
1633 1634 1635
			v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
			return -ERANGE;
		}
1636
		state->restart_stdi_once = true;
1637 1638 1639 1640 1641 1642 1643 1644 1645
	}
found:

	if (no_signal(sd)) {
		v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
		memset(timings, 0, sizeof(struct v4l2_dv_timings));
		return -ENOLINK;
	}

1646 1647
	if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
			(is_digital_input(sd) && bt->pixelclock > 225000000)) {
1648 1649 1650 1651 1652 1653
		v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
				__func__, (u32)bt->pixelclock);
		return -ERANGE;
	}

	if (debug > 1)
1654
		v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1655
				      timings, true);
1656 1657 1658 1659

	return 0;
}

1660
static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1661 1662
		struct v4l2_dv_timings *timings)
{
1663
	struct adv76xx_state *state = to_state(sd);
1664
	struct v4l2_bt_timings *bt;
1665
	int err;
1666 1667 1668 1669

	if (!timings)
		return -EINVAL;

1670
	if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1671 1672 1673 1674
		v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
		return 0;
	}

1675 1676
	bt = &timings->bt;

1677
	if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1678
				   adv76xx_check_dv_timings, NULL))
1679
		return -ERANGE;
1680

1681
	adv76xx_fill_optional_dv_timings_fields(sd, timings);
1682 1683 1684

	state->timings = *timings;

1685
	cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1686 1687 1688 1689 1690 1691 1692 1693

	/* Use prim_mode and vid_std when available */
	err = configure_predefined_video_timings(sd, timings);
	if (err) {
		/* custom settings when the video format
		 does not have prim_mode/vid_std */
		configure_custom_video_timings(sd, bt);
	}
1694 1695 1696 1697

	set_rgb_quantization_range(sd);

	if (debug > 1)
1698
		v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1699
				      timings, true);
1700 1701 1702
	return 0;
}

1703
static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1704 1705
		struct v4l2_dv_timings *timings)
{
1706
	struct adv76xx_state *state = to_state(sd);
1707 1708 1709 1710 1711

	*timings = state->timings;
	return 0;
}

1712 1713 1714 1715 1716 1717 1718 1719 1720 1721
static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
{
	hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
}

static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
{
	hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
}

1722
static void enable_input(struct v4l2_subdev *sd)
1723
{
1724
	struct adv76xx_state *state = to_state(sd);
1725

1726
	if (is_analog_input(sd)) {
1727
		io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1728
	} else if (is_digital_input(sd)) {
1729
		hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1730
		state->info->set_termination(sd, true);
1731
		io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1732
		hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1733 1734 1735
	} else {
		v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
				__func__, state->selected_input);
1736 1737 1738 1739 1740
	}
}

static void disable_input(struct v4l2_subdev *sd)
{
1741
	struct adv76xx_state *state = to_state(sd);
1742

1743
	hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1744
	msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1745
	io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1746
	state->info->set_termination(sd, false);
1747 1748
}

1749
static void select_input(struct v4l2_subdev *sd)
1750
{
1751 1752
	struct adv76xx_state *state = to_state(sd);
	const struct adv76xx_chip_info *info = state->info;
1753

1754
	if (is_analog_input(sd)) {
1755
		adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1756 1757 1758 1759

		afe_write(sd, 0x00, 0x08); /* power up ADC */
		afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
		afe_write(sd, 0xc8, 0x00); /* phase control */
1760 1761
	} else if (is_digital_input(sd)) {
		hdmi_write(sd, 0x00, state->selected_input & 0x03);
1762

1763
		adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1764

1765
		if (adv76xx_has_afe(state)) {
1766 1767 1768 1769 1770
			afe_write(sd, 0x00, 0xff); /* power down ADC */
			afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
			afe_write(sd, 0xc8, 0x40); /* phase control */
		}

1771 1772 1773
		cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
		cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
		cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1774 1775 1776
	} else {
		v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
				__func__, state->selected_input);
1777 1778 1779
	}
}

1780
static int adv76xx_s_routing(struct v4l2_subdev *sd,
1781 1782
		u32 input, u32 output, u32 config)
{
1783
	struct adv76xx_state *state = to_state(sd);
1784

1785 1786 1787 1788 1789
	v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
			__func__, input, state->selected_input);

	if (input == state->selected_input)
		return 0;
1790

1791 1792 1793
	if (input > state->info->max_port)
		return -EINVAL;

1794
	state->selected_input = input;
1795 1796

	disable_input(sd);
1797 1798
	select_input(sd);
	enable_input(sd);
1799

1800 1801
	v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);

1802 1803 1804
	return 0;
}

1805
static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1806
				  struct v4l2_subdev_pad_config *cfg,
1807
				  struct v4l2_subdev_mbus_code_enum *code)
1808
{
1809
	struct adv76xx_state *state = to_state(sd);
1810 1811

	if (code->index >= state->info->nformats)
1812
		return -EINVAL;
1813 1814 1815

	code->code = state->info->formats[code->index].code;

1816 1817 1818
	return 0;
}

1819
static void adv76xx_fill_format(struct adv76xx_state *state,
1820
				struct v4l2_mbus_framefmt *format)
1821
{
1822
	memset(format, 0, sizeof(*format));
1823

1824 1825 1826
	format->width = state->timings.bt.width;
	format->height = state->timings.bt.height;
	format->field = V4L2_FIELD_NONE;
1827
	format->colorspace = V4L2_COLORSPACE_SRGB;
1828

1829
	if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1830
		format->colorspace = (state->timings.bt.height <= 576) ?
1831
			V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1832 1833 1834 1835 1836 1837 1838 1839 1840
}

/*
 * Compute the op_ch_sel value required to obtain on the bus the component order
 * corresponding to the selected format taking into account bus reordering
 * applied by the board at the output of the device.
 *
 * The following table gives the op_ch_value from the format component order
 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1841
 * adv76xx_bus_order value in row).
1842 1843 1844 1845 1846 1847 1848 1849 1850 1851
 *
 *           |	GBR(0)	GRB(1)	BGR(2)	RGB(3)	BRG(4)	RBG(5)
 * ----------+-------------------------------------------------
 * RGB (NOP) |	GBR	GRB	BGR	RGB	BRG	RBG
 * GRB (1-2) |	BGR	RGB	GBR	GRB	RBG	BRG
 * RBG (2-3) |	GRB	GBR	BRG	RBG	BGR	RGB
 * BGR (1-3) |	RBG	BRG	RGB	BGR	GRB	GBR
 * BRG (ROR) |	BRG	RBG	GRB	GBR	RGB	BGR
 * GBR (ROL) |	RGB	BGR	RBG	BRG	GBR	GRB
 */
1852
static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1853 1854
{
#define _SEL(a,b,c,d,e,f)	{ \
1855 1856
	ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
	ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870
#define _BUS(x)			[ADV7604_BUS_ORDER_##x]

	static const unsigned int op_ch_sel[6][6] = {
		_BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
		_BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
		_BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
		_BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
		_BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
		_BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
	};

	return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
}

1871
static void adv76xx_setup_format(struct adv76xx_state *state)
1872 1873 1874
{
	struct v4l2_subdev *sd = &state->sd;

1875
	io_write_clr_set(sd, 0x02, 0x02,
1876
			state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1877 1878
	io_write(sd, 0x03, state->format->op_format_sel |
		 state->pdata.op_format_mode_sel);
1879
	io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1880
	io_write_clr_set(sd, 0x05, 0x01,
1881
			state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1882
	set_rgb_quantization_range(sd);
1883 1884
}

1885 1886
static int adv76xx_get_format(struct v4l2_subdev *sd,
			      struct v4l2_subdev_pad_config *cfg,
1887 1888
			      struct v4l2_subdev_format *format)
{
1889
	struct adv76xx_state *state = to_state(sd);
1890 1891 1892 1893

	if (format->pad != state->source_pad)
		return -EINVAL;

1894
	adv76xx_fill_format(state, &format->format);
1895 1896 1897 1898

	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
		struct v4l2_mbus_framefmt *fmt;

1899
		fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1900 1901 1902
		format->format.code = fmt->code;
	} else {
		format->format.code = state->format->code;
1903
	}
1904 1905 1906 1907

	return 0;
}

1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927
static int adv76xx_get_selection(struct v4l2_subdev *sd,
				 struct v4l2_subdev_pad_config *cfg,
				 struct v4l2_subdev_selection *sel)
{
	struct adv76xx_state *state = to_state(sd);

	if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
		return -EINVAL;
	/* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
	if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
		return -EINVAL;

	sel->r.left	= 0;
	sel->r.top	= 0;
	sel->r.width	= state->timings.bt.width;
	sel->r.height	= state->timings.bt.height;

	return 0;
}

1928 1929
static int adv76xx_set_format(struct v4l2_subdev *sd,
			      struct v4l2_subdev_pad_config *cfg,
1930 1931
			      struct v4l2_subdev_format *format)
{
1932 1933
	struct adv76xx_state *state = to_state(sd);
	const struct adv76xx_format_info *info;
1934 1935 1936 1937

	if (format->pad != state->source_pad)
		return -EINVAL;

1938
	info = adv76xx_format_info(state, format->format.code);
1939
	if (!info)
1940
		info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1941

1942
	adv76xx_fill_format(state, &format->format);
1943 1944 1945 1946 1947
	format->format.code = info->code;

	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
		struct v4l2_mbus_framefmt *fmt;

1948
		fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1949 1950 1951
		fmt->code = format->format.code;
	} else {
		state->format = info;
1952
		adv76xx_setup_format(state);
1953 1954
	}

1955 1956 1957
	return 0;
}

1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972
#if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
{
	struct adv76xx_state *state = to_state(sd);

	if ((cec_read(sd, 0x11) & 0x01) == 0) {
		v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
		return;
	}

	if (tx_raw_status & 0x02) {
		v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
			 __func__);
		cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
				  1, 0, 0, 0);
1973
		return;
1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042
	}
	if (tx_raw_status & 0x04) {
		u8 status;
		u8 nack_cnt;
		u8 low_drive_cnt;

		v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
		/*
		 * We set this status bit since this hardware performs
		 * retransmissions.
		 */
		status = CEC_TX_STATUS_MAX_RETRIES;
		nack_cnt = cec_read(sd, 0x14) & 0xf;
		if (nack_cnt)
			status |= CEC_TX_STATUS_NACK;
		low_drive_cnt = cec_read(sd, 0x14) >> 4;
		if (low_drive_cnt)
			status |= CEC_TX_STATUS_LOW_DRIVE;
		cec_transmit_done(state->cec_adap, status,
				  0, nack_cnt, low_drive_cnt, 0);
		return;
	}
	if (tx_raw_status & 0x01) {
		v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
		cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
		return;
	}
}

static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
{
	struct adv76xx_state *state = to_state(sd);
	u8 cec_irq;

	/* cec controller */
	cec_irq = io_read(sd, 0x4d) & 0x0f;
	if (!cec_irq)
		return;

	v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
	adv76xx_cec_tx_raw_status(sd, cec_irq);
	if (cec_irq & 0x08) {
		struct cec_msg msg;

		msg.len = cec_read(sd, 0x25) & 0x1f;
		if (msg.len > 16)
			msg.len = 16;

		if (msg.len) {
			u8 i;

			for (i = 0; i < msg.len; i++)
				msg.msg[i] = cec_read(sd, i + 0x15);
			cec_write(sd, 0x26, 0x01); /* re-enable rx */
			cec_received_msg(state->cec_adap, &msg);
		}
	}

	/* note: the bit order is swapped between 0x4d and 0x4e */
	cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) |
		  ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3);
	io_write(sd, 0x4e, cec_irq);

	if (handled)
		*handled = true;
}

static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable)
{
2043
	struct adv76xx_state *state = cec_get_drvdata(adap);
2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072
	struct v4l2_subdev *sd = &state->sd;

	if (!state->cec_enabled_adap && enable) {
		cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
		cec_write(sd, 0x2c, 0x01);	/* cec soft reset */
		cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
		/* enabled irqs: */
		/* tx: ready */
		/* tx: arbitration lost */
		/* tx: retry timeout */
		/* rx: ready */
		io_write_clr_set(sd, 0x50, 0x0f, 0x0f);
		cec_write(sd, 0x26, 0x01);            /* enable rx */
	} else if (state->cec_enabled_adap && !enable) {
		/* disable cec interrupts */
		io_write_clr_set(sd, 0x50, 0x0f, 0x00);
		/* disable address mask 1-3 */
		cec_write_clr_set(sd, 0x27, 0x70, 0x00);
		/* power down cec section */
		cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
		state->cec_valid_addrs = 0;
	}
	state->cec_enabled_adap = enable;
	adv76xx_s_detect_tx_5v_ctrl(sd);
	return 0;
}

static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
{
2073
	struct adv76xx_state *state = cec_get_drvdata(adap);
2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127
	struct v4l2_subdev *sd = &state->sd;
	unsigned int i, free_idx = ADV76XX_MAX_ADDRS;

	if (!state->cec_enabled_adap)
		return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;

	if (addr == CEC_LOG_ADDR_INVALID) {
		cec_write_clr_set(sd, 0x27, 0x70, 0);
		state->cec_valid_addrs = 0;
		return 0;
	}

	for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
		bool is_valid = state->cec_valid_addrs & (1 << i);

		if (free_idx == ADV76XX_MAX_ADDRS && !is_valid)
			free_idx = i;
		if (is_valid && state->cec_addr[i] == addr)
			return 0;
	}
	if (i == ADV76XX_MAX_ADDRS) {
		i = free_idx;
		if (i == ADV76XX_MAX_ADDRS)
			return -ENXIO;
	}
	state->cec_addr[i] = addr;
	state->cec_valid_addrs |= 1 << i;

	switch (i) {
	case 0:
		/* enable address mask 0 */
		cec_write_clr_set(sd, 0x27, 0x10, 0x10);
		/* set address for mask 0 */
		cec_write_clr_set(sd, 0x28, 0x0f, addr);
		break;
	case 1:
		/* enable address mask 1 */
		cec_write_clr_set(sd, 0x27, 0x20, 0x20);
		/* set address for mask 1 */
		cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
		break;
	case 2:
		/* enable address mask 2 */
		cec_write_clr_set(sd, 0x27, 0x40, 0x40);
		/* set address for mask 1 */
		cec_write_clr_set(sd, 0x29, 0x0f, addr);
		break;
	}
	return 0;
}

static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
				     u32 signal_free_time, struct cec_msg *msg)
{
2128
	struct adv76xx_state *state = cec_get_drvdata(adap);
2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162
	struct v4l2_subdev *sd = &state->sd;
	u8 len = msg->len;
	unsigned int i;

	/*
	 * The number of retries is the number of attempts - 1, but retry
	 * at least once. It's not clear if a value of 0 is allowed, so
	 * let's do at least one retry.
	 */
	cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);

	if (len > 16) {
		v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
		return -EINVAL;
	}

	/* write data */
	for (i = 0; i < len; i++)
		cec_write(sd, i, msg->msg[i]);

	/* set length (data + header) */
	cec_write(sd, 0x10, len);
	/* start transmit, enable tx */
	cec_write(sd, 0x11, 0x01);
	return 0;
}

static const struct cec_adap_ops adv76xx_cec_adap_ops = {
	.adap_enable = adv76xx_cec_adap_enable,
	.adap_log_addr = adv76xx_cec_adap_log_addr,
	.adap_transmit = adv76xx_cec_adap_transmit,
};
#endif

2163
static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2164
{
2165 2166
	struct adv76xx_state *state = to_state(sd);
	const struct adv76xx_chip_info *info = state->info;
2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179
	const u8 irq_reg_0x43 = io_read(sd, 0x43);
	const u8 irq_reg_0x6b = io_read(sd, 0x6b);
	const u8 irq_reg_0x70 = io_read(sd, 0x70);
	u8 fmt_change_digital;
	u8 fmt_change;
	u8 tx_5v;

	if (irq_reg_0x43)
		io_write(sd, 0x44, irq_reg_0x43);
	if (irq_reg_0x70)
		io_write(sd, 0x71, irq_reg_0x70);
	if (irq_reg_0x6b)
		io_write(sd, 0x6c, irq_reg_0x6b);
2180

2181 2182
	v4l2_dbg(2, debug, sd, "%s: ", __func__);

2183
	/* format change */
2184
	fmt_change = irq_reg_0x43 & 0x98;
2185 2186 2187
	fmt_change_digital = is_digital_input(sd)
			   ? irq_reg_0x6b & info->fmt_change_digital_mask
			   : 0;
2188

2189 2190
	if (fmt_change || fmt_change_digital) {
		v4l2_dbg(1, debug, sd,
2191
			"%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
2192
			__func__, fmt_change, fmt_change_digital);
2193

2194
		v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
2195

2196 2197 2198
		if (handled)
			*handled = true;
	}
2199 2200 2201 2202 2203 2204 2205 2206 2207
	/* HDMI/DVI mode */
	if (irq_reg_0x6b & 0x01) {
		v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
			(io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
		set_rgb_quantization_range(sd);
		if (handled)
			*handled = true;
	}

2208 2209 2210 2211 2212
#if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
	/* cec */
	adv76xx_cec_isr(sd, handled);
#endif

2213
	/* tx 5v detect */
2214
	tx_5v = irq_reg_0x70 & info->cable_det_mask;
2215 2216
	if (tx_5v) {
		v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2217
		adv76xx_s_detect_tx_5v_ctrl(sd);
2218 2219 2220 2221 2222 2223
		if (handled)
			*handled = true;
	}
	return 0;
}

2224
static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2225
{
2226
	struct adv76xx_state *state = to_state(sd);
2227
	u8 *data = NULL;
2228

2229
	memset(edid->reserved, 0, sizeof(edid->reserved));
2230 2231

	switch (edid->pad) {
2232
	case ADV76XX_PAD_HDMI_PORT_A:
2233 2234 2235
	case ADV7604_PAD_HDMI_PORT_B:
	case ADV7604_PAD_HDMI_PORT_C:
	case ADV7604_PAD_HDMI_PORT_D:
2236 2237 2238 2239 2240 2241
		if (state->edid.present & (1 << edid->pad))
			data = state->edid.edid;
		break;
	default:
		return -EINVAL;
	}
2242 2243 2244 2245 2246 2247

	if (edid->start_block == 0 && edid->blocks == 0) {
		edid->blocks = data ? state->edid.blocks : 0;
		return 0;
	}

2248
	if (!data)
2249 2250
		return -ENODATA;

2251 2252 2253 2254 2255 2256 2257 2258
	if (edid->start_block >= state->edid.blocks)
		return -EINVAL;

	if (edid->start_block + edid->blocks > state->edid.blocks)
		edid->blocks = state->edid.blocks - edid->start_block;

	memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);

2259 2260 2261
	return 0;
}

2262
static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2263
{
2264 2265
	struct adv76xx_state *state = to_state(sd);
	const struct adv76xx_chip_info *info = state->info;
2266 2267
	unsigned int spa_loc;
	u16 pa;
2268
	int err;
2269
	int i;
2270

2271 2272
	memset(edid->reserved, 0, sizeof(edid->reserved));

2273
	if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2274 2275 2276 2277
		return -EINVAL;
	if (edid->start_block != 0)
		return -EINVAL;
	if (edid->blocks == 0) {
2278
		/* Disable hotplug and I2C access to EDID RAM from DDC port */
2279
		state->edid.present &= ~(1 << edid->pad);
2280
		adv76xx_set_hpd(state, state->edid.present);
2281
		rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2282

2283 2284 2285
		/* Fall back to a 16:9 aspect ratio */
		state->aspect_ratio.numerator = 16;
		state->aspect_ratio.denominator = 9;
2286 2287 2288 2289 2290 2291

		if (!state->edid.present)
			state->edid.blocks = 0;

		v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
				__func__, edid->pad, state->edid.present);
2292 2293
		return 0;
	}
2294 2295
	if (edid->blocks > 2) {
		edid->blocks = 2;
2296
		return -E2BIG;
2297
	}
2298 2299 2300 2301
	pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc);
	err = cec_phys_addr_validate(pa, &pa, NULL);
	if (err)
		return err;
2302

2303 2304 2305
	v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
			__func__, edid->pad, state->edid.present);

2306
	/* Disable hotplug and I2C access to EDID RAM from DDC port */
2307
	cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2308
	adv76xx_set_hpd(state, 0);
2309
	rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2310

2311 2312 2313 2314 2315 2316
	/*
	 * Return an error if no location of the source physical address
	 * was found.
	 */
	if (spa_loc == 0)
		return -EINVAL;
2317

2318
	switch (edid->pad) {
2319
	case ADV76XX_PAD_HDMI_PORT_A:
2320 2321
		state->spa_port_a[0] = edid->edid[spa_loc];
		state->spa_port_a[1] = edid->edid[spa_loc + 1];
2322
		break;
2323
	case ADV7604_PAD_HDMI_PORT_B:
2324 2325
		rep_write(sd, 0x70, edid->edid[spa_loc]);
		rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2326
		break;
2327
	case ADV7604_PAD_HDMI_PORT_C:
2328 2329
		rep_write(sd, 0x72, edid->edid[spa_loc]);
		rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2330
		break;
2331
	case ADV7604_PAD_HDMI_PORT_D:
2332 2333
		rep_write(sd, 0x74, edid->edid[spa_loc]);
		rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2334
		break;
2335 2336
	default:
		return -EINVAL;
2337
	}
2338 2339 2340

	if (info->type == ADV7604) {
		rep_write(sd, 0x76, spa_loc & 0xff);
2341
		rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2342
	} else {
2343 2344
		/* ADV7612 Software Manual Rev. A, p. 15 */
		rep_write(sd, 0x70, spa_loc & 0xff);
2345
		rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2346
	}
2347

2348 2349
	edid->edid[spa_loc] = state->spa_port_a[0];
	edid->edid[spa_loc + 1] = state->spa_port_a[1];
2350 2351 2352

	memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
	state->edid.blocks = edid->blocks;
2353 2354
	state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
			edid->edid[0x16]);
2355
	state->edid.present |= 1 << edid->pad;
2356 2357 2358

	err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
	if (err < 0) {
2359
		v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2360 2361 2362
		return err;
	}

2363
	/* adv76xx calculates the checksums and enables I2C access to internal
2364
	   EDID RAM from DDC port. */
2365
	rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2366 2367

	for (i = 0; i < 1000; i++) {
2368
		if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2369 2370 2371 2372 2373 2374 2375
			break;
		mdelay(1);
	}
	if (i == 1000) {
		v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
		return -EIO;
	}
2376
	cec_s_phys_addr(state->cec_adap, pa, false);
2377

2378
	/* enable hotplug after 100 ms */
2379
	schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
2380
	return 0;
2381 2382 2383 2384
}

/*********** avi info frame CEA-861-E **************/

2385 2386 2387 2388 2389 2390 2391 2392 2393
static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
	{ "AVI", 0x01, 0xe0, 0x00 },
	{ "Audio", 0x02, 0xe3, 0x1c },
	{ "SDP", 0x04, 0xe6, 0x2a },
	{ "Vendor", 0x10, 0xec, 0x54 }
};

static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
				  union hdmi_infoframe *frame)
2394
{
2395 2396
	uint8_t buffer[32];
	u8 len;
2397 2398
	int i;

2399 2400 2401 2402
	if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
		v4l2_info(sd, "%s infoframe not received\n",
			  adv76xx_cri[index].desc);
		return -ENOENT;
2403
	}
2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414

	for (i = 0; i < 3; i++)
		buffer[i] = infoframe_read(sd,
					   adv76xx_cri[index].head_addr + i);

	len = buffer[2] + 1;

	if (len + 3 > sizeof(buffer)) {
		v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
			 adv76xx_cri[index].desc, len);
		return -ENOENT;
2415 2416
	}

2417 2418 2419 2420 2421 2422 2423 2424
	for (i = 0; i < len; i++)
		buffer[i + 3] = infoframe_read(sd,
				       adv76xx_cri[index].payload_addr + i);

	if (hdmi_infoframe_unpack(frame, buffer) < 0) {
		v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
			 adv76xx_cri[index].desc);
		return -ENOENT;
2425
	}
2426 2427
	return 0;
}
2428

2429 2430 2431
static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
{
	int i;
2432

2433 2434
	if (!is_hdmi(sd)) {
		v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2435
		return;
2436
	}
2437

2438 2439 2440
	for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
		union hdmi_infoframe frame;
		struct i2c_client *client = v4l2_get_subdevdata(sd);
2441

2442 2443 2444 2445
		if (adv76xx_read_infoframe(sd, i, &frame))
			return;
		hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
	}
2446 2447
}

2448
static int adv76xx_log_status(struct v4l2_subdev *sd)
2449
{
2450 2451
	struct adv76xx_state *state = to_state(sd);
	const struct adv76xx_chip_info *info = state->info;
2452 2453 2454
	struct v4l2_dv_timings timings;
	struct stdi_readback stdi;
	u8 reg_io_0x02 = io_read(sd, 0x02);
2455 2456
	u8 edid_enabled;
	u8 cable_det;
2457

2458
	static const char * const csc_coeff_sel_rb[16] = {
2459 2460 2461 2462 2463
		"bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
		"reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
		"reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
		"reserved", "reserved", "reserved", "reserved", "manual"
	};
2464
	static const char * const input_color_space_txt[16] = {
2465 2466
		"RGB limited range (16-235)", "RGB full range (0-255)",
		"YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2467
		"xvYCC Bt.601", "xvYCC Bt.709",
2468 2469 2470 2471
		"YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
		"invalid", "invalid", "invalid", "invalid", "invalid",
		"invalid", "invalid", "automatic"
	};
2472 2473 2474 2475 2476 2477 2478 2479
	static const char * const hdmi_color_space_txt[16] = {
		"RGB limited range (16-235)", "RGB full range (0-255)",
		"YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
		"xvYCC Bt.601", "xvYCC Bt.709",
		"YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
		"sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid",
		"invalid", "invalid", "invalid"
	};
2480
	static const char * const rgb_quantization_range_txt[] = {
2481 2482 2483 2484
		"Automatic",
		"RGB limited range (16-235)",
		"RGB full range (0-255)",
	};
2485
	static const char * const deep_color_mode_txt[4] = {
2486 2487 2488 2489 2490
		"8-bits per channel",
		"10-bits per channel",
		"12-bits per channel",
		"16-bits per channel (not supported)"
	};
2491 2492 2493

	v4l2_info(sd, "-----Chip status-----\n");
	v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2494
	edid_enabled = rep_read(sd, info->edid_status_reg);
2495
	v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2496 2497 2498 2499
			((edid_enabled & 0x01) ? "Yes" : "No"),
			((edid_enabled & 0x02) ? "Yes" : "No"),
			((edid_enabled & 0x04) ? "Yes" : "No"),
			((edid_enabled & 0x08) ? "Yes" : "No"));
2500
	v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2501
			"enabled" : "disabled");
2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512
	if (state->cec_enabled_adap) {
		int i;

		for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
			bool is_valid = state->cec_valid_addrs & (1 << i);

			if (is_valid)
				v4l2_info(sd, "CEC Logical Address: 0x%x\n",
					  state->cec_addr[i]);
		}
	}
2513 2514

	v4l2_info(sd, "-----Signal status-----\n");
2515
	cable_det = info->read_cable_det(sd);
2516
	v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2517 2518
			((cable_det & 0x01) ? "Yes" : "No"),
			((cable_det & 0x02) ? "Yes" : "No"),
2519
			((cable_det & 0x04) ? "Yes" : "No"),
2520
			((cable_det & 0x08) ? "Yes" : "No"));
2521 2522 2523 2524 2525 2526 2527 2528
	v4l2_info(sd, "TMDS signal detected: %s\n",
			no_signal_tmds(sd) ? "false" : "true");
	v4l2_info(sd, "TMDS signal locked: %s\n",
			no_lock_tmds(sd) ? "false" : "true");
	v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
	v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
	v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
	v4l2_info(sd, "CP free run: %s\n",
2529
			(in_free_run(sd)) ? "on" : "off");
2530 2531 2532
	v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
			io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
			(io_read(sd, 0x01) & 0x70) >> 4);
2533 2534 2535 2536 2537 2538 2539 2540 2541

	v4l2_info(sd, "-----Video Timings-----\n");
	if (read_stdi(sd, &stdi))
		v4l2_info(sd, "STDI: not locked\n");
	else
		v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
				stdi.lcf, stdi.bl, stdi.lcvs,
				stdi.interlaced ? "interlaced" : "progressive",
				stdi.hs_pol, stdi.vs_pol);
2542
	if (adv76xx_query_dv_timings(sd, &timings))
2543 2544
		v4l2_info(sd, "No video detected\n");
	else
2545 2546 2547 2548
		v4l2_print_dv_timings(sd->name, "Detected format: ",
				      &timings, true);
	v4l2_print_dv_timings(sd->name, "Configured format: ",
			      &state->timings, true);
2549

2550 2551 2552
	if (no_signal(sd))
		return 0;

2553 2554 2555 2556 2557
	v4l2_info(sd, "-----Color space-----\n");
	v4l2_info(sd, "RGB quantization range ctrl: %s\n",
			rgb_quantization_range_txt[state->rgb_quantization_range]);
	v4l2_info(sd, "Input color space: %s\n",
			input_color_space_txt[reg_io_0x02 >> 4]);
2558
	v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2559
			(reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2560
			(((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2561
				"(16-235)" : "(0-255)",
2562
			(reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2563
	v4l2_info(sd, "Color space conversion: %s\n",
2564
			csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2565

2566
	if (!is_digital_input(sd))
2567 2568 2569
		return 0;

	v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2570 2571 2572 2573
	v4l2_info(sd, "Digital video port selected: %c\n",
			(hdmi_read(sd, 0x00) & 0x03) + 'A');
	v4l2_info(sd, "HDCP encrypted content: %s\n",
			(hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2574 2575 2576
	v4l2_info(sd, "HDCP keys read: %s%s\n",
			(hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
			(hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2577
	if (is_hdmi(sd)) {
2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598
		bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
		bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
		bool audio_mute = io_read(sd, 0x65) & 0x40;

		v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
				audio_pll_locked ? "locked" : "not locked",
				audio_sample_packet_detect ? "detected" : "not detected",
				audio_mute ? "muted" : "enabled");
		if (audio_pll_locked && audio_sample_packet_detect) {
			v4l2_info(sd, "Audio format: %s\n",
					(hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
		}
		v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
				(hdmi_read(sd, 0x5c) << 8) +
				(hdmi_read(sd, 0x5d) & 0xf0));
		v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
				(hdmi_read(sd, 0x5e) << 8) +
				hdmi_read(sd, 0x5f));
		v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");

		v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2599
		v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2600

2601
		adv76xx_log_infoframes(sd);
2602 2603 2604 2605 2606
	}

	return 0;
}

2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620
static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
				   struct v4l2_fh *fh,
				   struct v4l2_event_subscription *sub)
{
	switch (sub->type) {
	case V4L2_EVENT_SOURCE_CHANGE:
		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
	case V4L2_EVENT_CTRL:
		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
	default:
		return -EINVAL;
	}
}

2621 2622 2623
static int adv76xx_registered(struct v4l2_subdev *sd)
{
	struct adv76xx_state *state = to_state(sd);
2624
	struct i2c_client *client = v4l2_get_subdevdata(sd);
2625 2626
	int err;

2627
	err = cec_register_adapter(state->cec_adap, &client->dev);
2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639
	if (err)
		cec_delete_adapter(state->cec_adap);
	return err;
}

static void adv76xx_unregistered(struct v4l2_subdev *sd)
{
	struct adv76xx_state *state = to_state(sd);

	cec_unregister_adapter(state->cec_adap);
}

2640 2641
/* ----------------------------------------------------------------------- */

2642 2643
static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
	.s_ctrl = adv76xx_s_ctrl,
2644
	.g_volatile_ctrl = adv76xx_g_volatile_ctrl,
2645 2646
};

2647 2648 2649
static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
	.log_status = adv76xx_log_status,
	.interrupt_service_routine = adv76xx_isr,
2650
	.subscribe_event = adv76xx_subscribe_event,
2651
	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
2652
#ifdef CONFIG_VIDEO_ADV_DEBUG
2653 2654
	.g_register = adv76xx_g_register,
	.s_register = adv76xx_s_register,
2655 2656 2657
#endif
};

2658 2659 2660 2661 2662 2663
static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
	.s_routing = adv76xx_s_routing,
	.g_input_status = adv76xx_g_input_status,
	.s_dv_timings = adv76xx_s_dv_timings,
	.g_dv_timings = adv76xx_g_dv_timings,
	.query_dv_timings = adv76xx_query_dv_timings,
2664 2665
};

2666 2667
static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
	.enum_mbus_code = adv76xx_enum_mbus_code,
2668
	.get_selection = adv76xx_get_selection,
2669 2670 2671 2672 2673 2674
	.get_fmt = adv76xx_get_format,
	.set_fmt = adv76xx_set_format,
	.get_edid = adv76xx_get_edid,
	.set_edid = adv76xx_set_edid,
	.dv_timings_cap = adv76xx_dv_timings_cap,
	.enum_dv_timings = adv76xx_enum_dv_timings,
2675 2676
};

2677 2678 2679 2680
static const struct v4l2_subdev_ops adv76xx_ops = {
	.core = &adv76xx_core_ops,
	.video = &adv76xx_video_ops,
	.pad = &adv76xx_pad_ops,
2681 2682
};

2683 2684 2685 2686 2687
static const struct v4l2_subdev_internal_ops adv76xx_int_ops = {
	.registered = adv76xx_registered,
	.unregistered = adv76xx_unregistered,
};

2688 2689 2690
/* -------------------------- custom ctrls ---------------------------------- */

static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2691
	.ops = &adv76xx_ctrl_ops,
2692 2693 2694 2695 2696 2697 2698 2699 2700
	.id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
	.name = "Analog Sampling Phase",
	.type = V4L2_CTRL_TYPE_INTEGER,
	.min = 0,
	.max = 0x1f,
	.step = 1,
	.def = 0,
};

2701 2702
static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
	.ops = &adv76xx_ctrl_ops,
2703 2704 2705 2706 2707 2708 2709 2710 2711
	.id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
	.name = "Free Running Color, Manual",
	.type = V4L2_CTRL_TYPE_BOOLEAN,
	.min = false,
	.max = true,
	.step = 1,
	.def = false,
};

2712 2713
static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
	.ops = &adv76xx_ctrl_ops,
2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724
	.id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
	.name = "Free Running Color",
	.type = V4L2_CTRL_TYPE_INTEGER,
	.min = 0x0,
	.max = 0xffffff,
	.step = 0x1,
	.def = 0x0,
};

/* ----------------------------------------------------------------------- */

2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745
struct adv76xx_register_map {
	const char *name;
	u8 default_addr;
};

static const struct adv76xx_register_map adv76xx_default_addresses[] = {
	[ADV76XX_PAGE_IO] = { "main", 0x4c },
	[ADV7604_PAGE_AVLINK] = { "avlink", 0x42 },
	[ADV76XX_PAGE_CEC] = { "cec", 0x40 },
	[ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e },
	[ADV7604_PAGE_ESDP] = { "esdp", 0x38 },
	[ADV7604_PAGE_DPP] = { "dpp", 0x3c },
	[ADV76XX_PAGE_AFE] = { "afe", 0x26 },
	[ADV76XX_PAGE_REP] = { "rep", 0x32 },
	[ADV76XX_PAGE_EDID] = { "edid", 0x36 },
	[ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 },
	[ADV76XX_PAGE_TEST] = { "test", 0x30 },
	[ADV76XX_PAGE_CP] = { "cp", 0x22 },
	[ADV7604_PAGE_VDP] = { "vdp", 0x24 },
};

2746
static int adv76xx_core_init(struct v4l2_subdev *sd)
2747
{
2748 2749 2750
	struct adv76xx_state *state = to_state(sd);
	const struct adv76xx_chip_info *info = state->info;
	struct adv76xx_platform_data *pdata = &state->pdata;
2751 2752 2753 2754 2755 2756 2757

	hdmi_write(sd, 0x48,
		(pdata->disable_pwrdnb ? 0x80 : 0) |
		(pdata->disable_cable_det_rst ? 0x40 : 0));

	disable_input(sd);

2758 2759 2760 2761 2762 2763 2764
	if (pdata->default_input >= 0 &&
	    pdata->default_input < state->source_pad) {
		state->selected_input = pdata->default_input;
		select_input(sd);
		enable_input(sd);
	}

2765 2766 2767 2768 2769 2770
	/* power */
	io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
	io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
	cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */

	/* video format */
2771
	io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
2772
	io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2773 2774
			pdata->insert_av_codes << 2 |
			pdata->replicate_av_codes << 1);
2775
	adv76xx_setup_format(state);
2776 2777

	cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2778 2779

	/* VS, HS polarities */
2780 2781
	io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
		 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2782 2783 2784 2785 2786 2787

	/* Adjust drive strength */
	io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
				pdata->dr_str_clk << 2 |
				pdata->dr_str_sync);

2788 2789 2790
	cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
	cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
	cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2791
				      ADI recommended setting [REF_01, c. 2.3.3] */
2792
	cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2793
				      ADI recommended setting [REF_01, c. 2.3.3] */
2794 2795 2796
	cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
				     for digital formats */

2797
	/* HDMI audio */
2798 2799 2800
	hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
	hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
	hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2801

2802 2803 2804
	/* TODO from platform data */
	afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */

2805
	if (adv76xx_has_afe(state)) {
2806
		afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2807
		io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2808
	}
2809 2810

	/* interrupts */
2811
	io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2812
	io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2813 2814 2815
	io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
	io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
	info->setup_irqs(sd);
2816 2817 2818 2819

	return v4l2_ctrl_handler_setup(sd->ctrl_handler);
}

2820 2821 2822 2823 2824 2825 2826 2827 2828 2829
static void adv7604_setup_irqs(struct v4l2_subdev *sd)
{
	io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
}

static void adv7611_setup_irqs(struct v4l2_subdev *sd)
{
	io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
}

2830 2831 2832 2833 2834
static void adv7612_setup_irqs(struct v4l2_subdev *sd)
{
	io_write(sd, 0x41, 0xd0); /* disable INT2 */
}

2835
static void adv76xx_unregister_clients(struct adv76xx_state *state)
2836
{
2837 2838 2839 2840 2841 2842
	unsigned int i;

	for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
		if (state->i2c_clients[i])
			i2c_unregister_device(state->i2c_clients[i]);
	}
2843 2844
}

2845
static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2846
					       unsigned int page)
2847 2848
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860
	struct adv76xx_state *state = to_state(sd);
	struct adv76xx_platform_data *pdata = &state->pdata;
	unsigned int io_reg = 0xf2 + page;
	struct i2c_client *new_client;

	if (pdata && pdata->i2c_addresses[page])
		new_client = i2c_new_dummy(client->adapter,
					   pdata->i2c_addresses[page]);
	else
		new_client = i2c_new_secondary_device(client,
				adv76xx_default_addresses[page].name,
				adv76xx_default_addresses[page].default_addr);
2861

2862 2863 2864 2865
	if (new_client)
		io_write(sd, io_reg, new_client->addr << 1);

	return new_client;
2866 2867
}

2868
static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2869 2870
	/* reset ADI recommended settings for HDMI: */
	/* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2883 2884 2885

	/* set ADI recommended settings for digitizer */
	/* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2886 2887 2888 2889 2890
	{ ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
	{ ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
	{ ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
	{ ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
	{ ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2891

2892
	{ ADV76XX_REG_SEQ_TERM, 0 },
2893 2894
};

2895
static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2896 2897
	/* set ADI recommended settings for HDMI: */
	/* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2909 2910 2911

	/* reset ADI recommended settings for digitizer */
	/* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2912 2913
	{ ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
	{ ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2914

2915
	{ ADV76XX_REG_SEQ_TERM, 0 },
2916 2917
};

2918
static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2919
	/* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932
	{ ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },

	{ ADV76XX_REG_SEQ_TERM, 0 },
2933 2934
};

2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947
static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
	{ ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
	{ ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
	{ ADV76XX_REG_SEQ_TERM, 0 },
};

2948
static const struct adv76xx_chip_info adv76xx_chip_info[] = {
2949 2950 2951
	[ADV7604] = {
		.type = ADV7604,
		.has_afe = true,
2952
		.max_port = ADV7604_PAD_VGA_COMP,
2953 2954 2955 2956 2957 2958 2959
		.num_dv_ports = 4,
		.edid_enable_reg = 0x77,
		.edid_status_reg = 0x7d,
		.lcf_reg = 0xb3,
		.tdms_lock_mask = 0xe0,
		.cable_det_mask = 0x1e,
		.fmt_change_digital_mask = 0xc1,
2960
		.cp_csc = 0xfc,
2961 2962
		.formats = adv7604_formats,
		.nformats = ARRAY_SIZE(adv7604_formats),
2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974
		.set_termination = adv7604_set_termination,
		.setup_irqs = adv7604_setup_irqs,
		.read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
		.read_cable_det = adv7604_read_cable_det,
		.recommended_settings = {
		    [0] = adv7604_recommended_settings_afe,
		    [1] = adv7604_recommended_settings_hdmi,
		},
		.num_recommended_settings = {
		    [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
		    [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
		},
2975 2976
		.page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
			BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
2977
			BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2978 2979 2980
			BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
			BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
			BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
2981
			BIT(ADV7604_PAGE_VDP),
2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993
		.linewidth_mask = 0xfff,
		.field0_height_mask = 0xfff,
		.field1_height_mask = 0xfff,
		.hfrontporch_mask = 0x3ff,
		.hsync_mask = 0x3ff,
		.hbackporch_mask = 0x3ff,
		.field0_vfrontporch_mask = 0x1fff,
		.field0_vsync_mask = 0x1fff,
		.field0_vbackporch_mask = 0x1fff,
		.field1_vfrontporch_mask = 0x1fff,
		.field1_vsync_mask = 0x1fff,
		.field1_vbackporch_mask = 0x1fff,
2994 2995 2996 2997
	},
	[ADV7611] = {
		.type = ADV7611,
		.has_afe = false,
2998
		.max_port = ADV76XX_PAD_HDMI_PORT_A,
2999 3000 3001 3002 3003 3004 3005
		.num_dv_ports = 1,
		.edid_enable_reg = 0x74,
		.edid_status_reg = 0x76,
		.lcf_reg = 0xa3,
		.tdms_lock_mask = 0x43,
		.cable_det_mask = 0x01,
		.fmt_change_digital_mask = 0x03,
3006
		.cp_csc = 0xf4,
3007 3008
		.formats = adv7611_formats,
		.nformats = ARRAY_SIZE(adv7611_formats),
3009 3010 3011 3012 3013 3014 3015 3016 3017 3018
		.set_termination = adv7611_set_termination,
		.setup_irqs = adv7611_setup_irqs,
		.read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
		.read_cable_det = adv7611_read_cable_det,
		.recommended_settings = {
		    [1] = adv7611_recommended_settings_hdmi,
		},
		.num_recommended_settings = {
		    [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
		},
3019 3020 3021 3022
		.page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
			BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
			BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
			BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034
		.linewidth_mask = 0x1fff,
		.field0_height_mask = 0x1fff,
		.field1_height_mask = 0x1fff,
		.hfrontporch_mask = 0x1fff,
		.hsync_mask = 0x1fff,
		.hbackporch_mask = 0x1fff,
		.field0_vfrontporch_mask = 0x3fff,
		.field0_vsync_mask = 0x3fff,
		.field0_vbackporch_mask = 0x3fff,
		.field1_vfrontporch_mask = 0x3fff,
		.field1_vsync_mask = 0x3fff,
		.field1_vbackporch_mask = 0x3fff,
3035
	},
3036 3037 3038
	[ADV7612] = {
		.type = ADV7612,
		.has_afe = false,
3039 3040
		.max_port = ADV76XX_PAD_HDMI_PORT_A,	/* B not supported */
		.num_dv_ports = 1,			/* normally 2 */
3041 3042 3043 3044 3045 3046
		.edid_enable_reg = 0x74,
		.edid_status_reg = 0x76,
		.lcf_reg = 0xa3,
		.tdms_lock_mask = 0x43,
		.cable_det_mask = 0x01,
		.fmt_change_digital_mask = 0x03,
3047
		.cp_csc = 0xf4,
3048 3049 3050 3051 3052
		.formats = adv7612_formats,
		.nformats = ARRAY_SIZE(adv7612_formats),
		.set_termination = adv7611_set_termination,
		.setup_irqs = adv7612_setup_irqs,
		.read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3053
		.read_cable_det = adv7612_read_cable_det,
3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076
		.recommended_settings = {
		    [1] = adv7612_recommended_settings_hdmi,
		},
		.num_recommended_settings = {
		    [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
		},
		.page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
			BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
			BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
			BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
		.linewidth_mask = 0x1fff,
		.field0_height_mask = 0x1fff,
		.field1_height_mask = 0x1fff,
		.hfrontporch_mask = 0x1fff,
		.hsync_mask = 0x1fff,
		.hbackporch_mask = 0x1fff,
		.field0_vfrontporch_mask = 0x3fff,
		.field0_vsync_mask = 0x3fff,
		.field0_vbackporch_mask = 0x3fff,
		.field1_vfrontporch_mask = 0x3fff,
		.field1_vsync_mask = 0x3fff,
		.field1_vbackporch_mask = 0x3fff,
	},
3077 3078
};

3079
static const struct i2c_device_id adv76xx_i2c_id[] = {
3080 3081
	{ "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
	{ "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3082
	{ "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
3083 3084
	{ }
};
3085
MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
3086

3087
static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
3088
	{ .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
3089
	{ .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
3090 3091
	{ }
};
3092
MODULE_DEVICE_TABLE(of, adv76xx_of_id);
3093

3094
static int adv76xx_parse_dt(struct adv76xx_state *state)
3095
{
3096
	struct v4l2_fwnode_endpoint bus_cfg;
3097 3098 3099
	struct device_node *endpoint;
	struct device_node *np;
	unsigned int flags;
3100
	int ret;
3101
	u32 v;
3102

3103
	np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
3104 3105 3106 3107 3108 3109

	/* Parse the endpoint. */
	endpoint = of_graph_get_next_endpoint(np, NULL);
	if (!endpoint)
		return -EINVAL;

3110
	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg);
3111 3112 3113 3114
	if (ret) {
		of_node_put(endpoint);
		return ret;
	}
3115

3116 3117 3118
	of_node_put(endpoint);

	if (!of_property_read_u32(np, "default-input", &v))
3119 3120 3121 3122
		state->pdata.default_input = v;
	else
		state->pdata.default_input = -1;

3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133
	flags = bus_cfg.bus.parallel.flags;

	if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
		state->pdata.inv_hs_pol = 1;

	if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
		state->pdata.inv_vs_pol = 1;

	if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
		state->pdata.inv_llc_pol = 1;

3134
	if (bus_cfg.bus_type == V4L2_MBUS_BT656)
3135 3136
		state->pdata.insert_av_codes = 1;

3137
	/* Disable the interrupt for now as no DT-based board uses it. */
3138
	state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
3139 3140 3141 3142 3143 3144 3145

	/* Hardcode the remaining platform data fields. */
	state->pdata.disable_pwrdnb = 0;
	state->pdata.disable_cable_det_rst = 0;
	state->pdata.blank_data = 1;
	state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
	state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
3146 3147 3148
	state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH;
	state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH;
	state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH;
3149 3150 3151 3152

	return 0;
}

3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294
static const struct regmap_config adv76xx_regmap_cnf[] = {
	{
		.name			= "io",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "avlink",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "cec",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "infoframe",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "esdp",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "epp",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "afe",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "rep",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "edid",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},

	{
		.name			= "hdmi",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "test",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "cp",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
	{
		.name			= "vdp",
		.reg_bits		= 8,
		.val_bits		= 8,

		.max_register		= 0xff,
		.cache_type		= REGCACHE_NONE,
	},
};

static int configure_regmap(struct adv76xx_state *state, int region)
{
	int err;

	if (!state->i2c_clients[region])
		return -ENODEV;

	state->regmap[region] =
		devm_regmap_init_i2c(state->i2c_clients[region],
				     &adv76xx_regmap_cnf[region]);

	if (IS_ERR(state->regmap[region])) {
		err = PTR_ERR(state->regmap[region]);
		v4l_err(state->i2c_clients[region],
			"Error initializing regmap %d with error %d\n",
			region, err);
		return -EINVAL;
	}

	return 0;
}

static int configure_regmaps(struct adv76xx_state *state)
{
	int i, err;

	for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
		err = configure_regmap(state, i);
		if (err && (err != -ENODEV))
			return err;
	}
	return 0;
}

3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307
static void adv76xx_reset(struct adv76xx_state *state)
{
	if (state->reset_gpio) {
		/* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */
		gpiod_set_value_cansleep(state->reset_gpio, 0);
		usleep_range(5000, 10000);
		gpiod_set_value_cansleep(state->reset_gpio, 1);
		/* It is recommended to wait 5 ms after the low pulse before */
		/* an I2C write is performed to the ADV76XX. */
		usleep_range(5000, 10000);
	}
}

3308
static int adv76xx_probe(struct i2c_client *client,
3309 3310
			 const struct i2c_device_id *id)
{
3311 3312
	static const struct v4l2_dv_timings cea640x480 =
		V4L2_DV_BT_CEA_640X480P59_94;
3313
	struct adv76xx_state *state;
3314
	struct v4l2_ctrl_handler *hdl;
3315
	struct v4l2_ctrl *ctrl;
3316
	struct v4l2_subdev *sd;
3317
	unsigned int i;
3318
	unsigned int val, val2;
3319 3320 3321 3322 3323
	int err;

	/* Check if the adapter supports the needed features */
	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
		return -EIO;
3324
	v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
3325 3326
			client->addr << 1);

3327
	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3328
	if (!state)
3329 3330
		return -ENOMEM;

3331
	state->i2c_clients[ADV76XX_PAGE_IO] = client;
3332

3333 3334
	/* initialize variables */
	state->restart_stdi_once = true;
3335
	state->selected_input = ~0;
3336

3337 3338 3339
	if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
		const struct of_device_id *oid;

3340
		oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3341 3342
		state->info = oid->data;

3343
		err = adv76xx_parse_dt(state);
3344 3345 3346 3347 3348
		if (err < 0) {
			v4l_err(client, "DT parsing error\n");
			return err;
		}
	} else if (client->dev.platform_data) {
3349
		struct adv76xx_platform_data *pdata = client->dev.platform_data;
3350

3351
		state->info = (const struct adv76xx_chip_info *)id->driver_data;
3352 3353
		state->pdata = *pdata;
	} else {
3354
		v4l_err(client, "No platform data!\n");
3355
		return -ENODEV;
3356
	}
3357 3358 3359 3360

	/* Request GPIOs. */
	for (i = 0; i < state->info->num_dv_ports; ++i) {
		state->hpd_gpio[i] =
3361 3362
			devm_gpiod_get_index_optional(&client->dev, "hpd", i,
						      GPIOD_OUT_LOW);
3363
		if (IS_ERR(state->hpd_gpio[i]))
3364
			return PTR_ERR(state->hpd_gpio[i]);
3365

3366 3367
		if (state->hpd_gpio[i])
			v4l_info(client, "Handling HPD %u GPIO\n", i);
3368
	}
3369 3370 3371 3372 3373 3374
	state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
								GPIOD_OUT_HIGH);
	if (IS_ERR(state->reset_gpio))
		return PTR_ERR(state->reset_gpio);

	adv76xx_reset(state);
3375

3376
	state->timings = cea640x480;
3377
	state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3378 3379

	sd = &state->sd;
3380
	v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3381 3382 3383
	snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
		id->name, i2c_adapter_id(client->adapter),
		client->addr);
3384
	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3385
	sd->internal_ops = &adv76xx_int_ops;
3386

3387 3388 3389 3390 3391 3392 3393 3394
	/* Configure IO Regmap region */
	err = configure_regmap(state, ADV76XX_PAGE_IO);

	if (err) {
		v4l2_err(sd, "Error configuring IO regmap region\n");
		return -ENODEV;
	}

3395 3396 3397 3398 3399
	/*
	 * Verify that the chip is present. On ADV7604 the RD_INFO register only
	 * identifies the revision, while on ADV7611 it identifies the model as
	 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
	 */
3400 3401
	switch (state->info->type) {
	case ADV7604:
3402 3403 3404 3405 3406
		err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
		if (err) {
			v4l2_err(sd, "Error %d reading IO Regmap\n", err);
			return -ENODEV;
		}
3407
		if (val != 0x68) {
3408
			v4l2_err(sd, "not an adv7604 on address 0x%x\n",
3409 3410 3411
					client->addr << 1);
			return -ENODEV;
		}
3412 3413 3414
		break;
	case ADV7611:
	case ADV7612:
3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429
		err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
				0xea,
				&val);
		if (err) {
			v4l2_err(sd, "Error %d reading IO Regmap\n", err);
			return -ENODEV;
		}
		val2 = val << 8;
		err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
			    0xeb,
			    &val);
		if (err) {
			v4l2_err(sd, "Error %d reading IO Regmap\n", err);
			return -ENODEV;
		}
3430
		val |= val2;
3431 3432 3433
		if ((state->info->type == ADV7611 && val != 0x2051) ||
			(state->info->type == ADV7612 && val != 0x2041)) {
			v4l2_err(sd, "not an adv761x on address 0x%x\n",
3434 3435 3436
					client->addr << 1);
			return -ENODEV;
		}
3437
		break;
3438 3439 3440 3441
	}

	/* control handlers */
	hdl = &state->hdl;
3442
	v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
3443

3444
	v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3445
			V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3446
	v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3447
			V4L2_CID_CONTRAST, 0, 255, 1, 128);
3448
	v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3449
			V4L2_CID_SATURATION, 0, 255, 1, 128);
3450
	v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3451
			V4L2_CID_HUE, 0, 128, 1, 0);
3452 3453 3454 3455 3456
	ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
			V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
			0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
	if (ctrl)
		ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3457 3458

	state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3459 3460
			V4L2_CID_DV_RX_POWER_PRESENT, 0,
			(1 << state->info->num_dv_ports) - 1, 0, 0);
3461
	state->rgb_quantization_range_ctrl =
3462
		v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3463 3464 3465 3466
			V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
			0, V4L2_DV_RGB_RANGE_AUTO);

	/* custom controls */
3467
	if (adv76xx_has_afe(state))
3468 3469
		state->analog_sampling_phase_ctrl =
			v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
3470
	state->free_run_color_manual_ctrl =
3471
		v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
3472
	state->free_run_color_ctrl =
3473
		v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
3474 3475 3476 3477 3478 3479

	sd->ctrl_handler = hdl;
	if (hdl->error) {
		err = hdl->error;
		goto err_hdl;
	}
3480
	if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3481 3482 3483 3484
		err = -ENODEV;
		goto err_hdl;
	}

3485
	for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3486 3487
		if (!(BIT(i) & state->info->page_mask))
			continue;
3488

3489
		state->i2c_clients[i] = adv76xx_dummy_client(sd, i);
3490
		if (!state->i2c_clients[i]) {
3491
			err = -EINVAL;
3492
			v4l2_err(sd, "failed to create i2c client %u\n", i);
3493 3494 3495
			goto err_i2c;
		}
	}
3496

3497
	INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3498
			adv76xx_delayed_work_enable_hotplug);
3499

3500 3501 3502 3503 3504 3505
	state->source_pad = state->info->num_dv_ports
			  + (state->info->has_afe ? 2 : 0);
	for (i = 0; i < state->source_pad; ++i)
		state->pads[i].flags = MEDIA_PAD_FL_SINK;
	state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;

3506
	err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3507
				state->pads);
3508 3509 3510
	if (err)
		goto err_work_queues;

3511 3512 3513 3514 3515
	/* Configure regmaps */
	err = configure_regmaps(state);
	if (err)
		goto err_entity;

3516
	err = adv76xx_core_init(sd);
3517 3518
	if (err)
		goto err_entity;
3519 3520 3521 3522

#if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
	state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops,
		state, dev_name(&client->dev),
3523
		CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS);
3524 3525 3526 3527 3528
	err = PTR_ERR_OR_ZERO(state->cec_adap);
	if (err)
		goto err_entity;
#endif

3529 3530
	v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
			client->addr << 1, client->adapter->name);
3531 3532 3533 3534 3535

	err = v4l2_async_register_subdev(sd);
	if (err)
		goto err_entity;

3536 3537 3538 3539 3540 3541 3542
	return 0;

err_entity:
	media_entity_cleanup(&sd->entity);
err_work_queues:
	cancel_delayed_work(&state->delayed_work_enable_hotplug);
err_i2c:
3543
	adv76xx_unregister_clients(state);
3544 3545 3546 3547 3548 3549 3550
err_hdl:
	v4l2_ctrl_handler_free(hdl);
	return err;
}

/* ----------------------------------------------------------------------- */

3551
static int adv76xx_remove(struct i2c_client *client)
3552 3553
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
3554
	struct adv76xx_state *state = to_state(sd);
3555

3556 3557 3558 3559 3560 3561 3562
	/* disable interrupts */
	io_write(sd, 0x40, 0);
	io_write(sd, 0x41, 0);
	io_write(sd, 0x46, 0);
	io_write(sd, 0x6e, 0);
	io_write(sd, 0x73, 0);

3563
	cancel_delayed_work(&state->delayed_work_enable_hotplug);
3564
	v4l2_async_unregister_subdev(sd);
3565
	media_entity_cleanup(&sd->entity);
3566
	adv76xx_unregister_clients(to_state(sd));
3567 3568 3569 3570 3571 3572
	v4l2_ctrl_handler_free(sd->ctrl_handler);
	return 0;
}

/* ----------------------------------------------------------------------- */

3573
static struct i2c_driver adv76xx_driver = {
3574 3575
	.driver = {
		.name = "adv7604",
3576
		.of_match_table = of_match_ptr(adv76xx_of_id),
3577
	},
3578 3579 3580
	.probe = adv76xx_probe,
	.remove = adv76xx_remove,
	.id_table = adv76xx_i2c_id,
3581 3582
};

3583
module_i2c_driver(adv76xx_driver);
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